Integrated circuit, integrated device and method of forming the same

Abstract

Some embodiments relate to an integrated device, including: a substrate including a top surface; a semiconductor device on the substrate; an interconnect structure covering the substrate and coupled to the semiconductor device; and a first conductive pad coupled to the interconnect structure, wherein the first conductive pad has a first upper surface located at a first height above the top surface of the substrate, and a second upper surface located at a second height above the top surface of the substrate, wherein the first height is greater than the second height.

Description

Prior Technology

[0001] The semiconductor industry is constantly improving the processing power and power consumption of integrated circuits by shrinking the smallest feature size. Functional integrated circuits can have widths of less than 10 micrometers. However, due to the shrinking feature size and the increased possibility of damaging smaller features, testing integrated circuits has become more difficult. Simple Explanation of the Diagram

[0002] The best understanding of all aspects of this disclosure can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1A, 1B, 1C, 1D and 1E illustrate cross-sectional views of some embodiments of an integrated circuit with conductive pads having upper surfaces of different heights. Figures 2A, 2B, 2C, and 2D illustrate top views of the redistribution layer in an intermediate step of the known-good-die (KGD) method for testing multiple integrated circuits at once. Figure 3 illustrates a top view of the conductive pads of the multiple integrated circuits shown in Figure 2A after testing. Figure 4 illustrates a cross-sectional view of some embodiments of an integrated circuit coupled to a second integrated circuit via a conductive pad. Figure 5 illustrates a cross-sectional view of some embodiments of through-holes coupled to conductive pads of integrated devices. Figure 6 is a top view illustrating some embodiments of the trenches introduced during the patterning of the conductive pads and redistribution layers of the integrated device. Figures 7-9, 10A-10B, and 11-21 illustrate a series of cross-sectional views of some embodiments of a method for forming an integrated device using the known-good-die (KGD) method. Figure 22 illustrates flowcharts of some embodiments of a method for forming an integrated device using the known-good-die (KGD) method. Implementation

[0003] This disclosure provides numerous different embodiments or examples to implement various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0004] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0005] It should be understood that the terms "first," "second," "third," etc., used in this written description and in the following claims are merely general identifiers for ease of explanation, used to distinguish different elements in a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the elements, and are not intended to describe corresponding elements in different illustrated examples and / or examples not shown. For example, "first dielectric layer" illustrated in conjunction with the first figure may not necessarily correspond to "first dielectric layer" illustrated in conjunction with another figure, and may not necessarily correspond to "first dielectric layer" in examples not shown.

[0006] With the development of integrated circuit technology, the compactness of circuits and features has been improved in various ways. The reduction in the size of circuit components leads to a reduction in the size of the formed circuits and semiconductor dies. The reduction in semiconductor die size increases the yield per wafer and improves the efficiency of the manufacturing process. However, testing a larger number of semiconductor dies becomes more time-consuming. Testing individual semiconductor dies produced from a single wafer can take several days, significantly reducing manufacturing throughput. There is a need for methods to test multiple semiconductor dies simultaneously to reduce the time required to test the formed integrated circuits, thereby improving the efficiency of the manufacturing process.

[0007] This disclosure provides a method for simultaneously testing multiple semiconductor dies. In a manufacturing process, circuit elements and interconnect structures for multiple semiconductor dies are formed on a substrate. The interconnect structures include multiple vias on the top surface of an interlayer dielectric layer. After forming the interconnect structures (and the surrounding interlayer dielectric layer), a redistribution layer is formed and patterned to couple the vias to multiple metal pads. The redistribution layer includes multiple conductors that couple corresponding vias (e.g., vias coupled to the same elements on the semiconductor dies) together, allowing that portion of the semiconductor dies to be tested in parallel. Electrical tests (e.g., circuit probing tests) are then performed on the semiconductor dies using the metal pads and the conductors of the redistribution layer to determine if any coupled semiconductor dies have damaged or missing connections. If the tests show damaged connections or voltage or current higher than expected, that portion of the semiconductor die is not used to form the final circuit. In this way, hundreds of semiconductor dies can be coupled together and tested simultaneously, reducing the time to test a single semiconductor die wafer from days to hours, greatly increasing the throughput of the manufacturing process. The cost is that additional semiconductor dies are discarded when tests fail.

[0008] Figures 1A, 1B, 1C, 1D and 1E illustrate cross-sectional views 100a, 100b, 100c, 100d and 100e of some embodiments of an integrated circuit with conductive pads having upper surfaces of different heights.

[0009] Multiple semiconductor devices 104 are located on a substrate 102. The multiple semiconductor devices 104 include one or more transistors (e.g., planar field-effect transistors, fin field-effect transistors, gate-all-loop (GAA) devices, etc.), circuit elements (e.g., resistors, capacitors, diodes, etc.), or similar elements. The multiple semiconductor devices 104 are coupled to an interconnect structure 106. The interconnect structure 106 includes multiple line layers 108 and multiple via layers 110. In some embodiments, multiple contacts 112 couple the multiple semiconductor devices 104 to the interconnect structure 106. The interconnect structure is surrounded by an interlayer dielectric layer 114. In some embodiments, the multiple semiconductor devices 104 and the interconnect structure 106 are configured to form a light-emitting diode (LED) driving circuit.

[0010] Multiple conductive pads 116 are coupled to the interconnect structure through the uppermost via layer of multiple via layers 110. In some embodiments, some of the multiple conductive pads 116 are coupled to the interconnect structure through four or more vias. The multiple conductive pads 116 have a first upper surface 118 located at a first height 119 above the top surface 102a of the substrate 102, a second upper surface 120 located at a second height 121 above the top surface 102a of the substrate 102, and a third upper surface 122 located at a third height 123 above the top surface 102a of the substrate 102. In some embodiments, the first height 119 and the third height 123 are substantially the same. The second height 121 is smaller than the first height 119 and the third height 123. In some embodiments, the conductive pads 116 are coupled to the interconnect structure 106 at a first lower surface directly below the first upper surface 118 and a second lower surface directly below the third upper surface 122.

[0011] Multiple conductive pads 116 conform to the upper surface of the interlayer dielectric layer 114. Electrical testing (e.g., probing) of the integrated device (before the conductive pads are formed) using a known-good-die (KGD) method results in multiple trenches 124 extending between the uppermost vias 110a, and multiple protrusions 126 through which the uppermost vias 110a extend. The multiple conductive pads 116 extend to cover and conform to portions of the trenches 124, resulting in multiple conductive pads 116 having multiple upper surfaces of different heights (e.g., a first upper surface 118, a second upper surface 120, and a third upper surface 122).

[0012] As shown in the cross-sectional view 100b of Figure 1B, in some embodiments, a first conductive pad 116a of a plurality of conductive pads 116 may conform to the upper surface of a first trench 124a of a plurality of trenches 124, while a second conductive pad 116b of a plurality of conductive pads 116 may conform to the upper surfaces of a second trench 124b and a third trench 124c of a plurality of trenches 124. The conductive pads of the plurality of conductive pads 116 extend to cover and conform to the upper surfaces of any number of trenches 124 and protrusions 126 based on the design of the underlying semiconductor die. In some embodiments, the trenches 124 in the interlayer dielectric layer 114 depict a plurality of protrusions 126 extending from the interlayer dielectric layer 114 and including one or more uppermost vias 110a. For example, a single through-hole 110b in the uppermost through-hole 110a may couple a first conductive pad 116a to the interconnect structure 106 in a first protrusion 126a, while multiple through-holes may couple a second conductive pad 116b to the interconnect structure 106 in a second protrusion 126b. In some embodiments, the uppermost through-hole 110a has a rectangular outline when viewed from a top view. In other embodiments, the uppermost through-hole 110a has a square or circular outline when viewed from a top view.

[0013] In some embodiments, vias coupled to the plurality of conductive pads 116 couple individual conductive pads to multiple conductive paths within the interconnect structure 106. Thus, the plurality of conductive pads 116 can function as additional line layers, extending horizontally across the interconnect structure to couple conductive paths that would otherwise be separated by the interlayer dielectric layer 114. Furthermore, in some embodiments, certain protrusions 126 are not covered by the conductive pads among the plurality of conductive pads 116 and do not include vias.

[0014] As shown in the cross-sectional view 100c of FIG1C, in some embodiments, a first portion 128 of the plurality of trenches 124 has a wider width than a second portion 130 of the plurality of trenches 124. In some embodiments, portions of the plurality of trenches 124 extend from a first outer sidewall of the interlayer dielectric layer 114 to a second outer sidewall of the interlayer dielectric layer. That is, portions of the plurality of trenches 124 extend across a semiconductor die. In a further embodiment, portions of the plurality of trenches partially extend across a semiconductor die and extend to one outer sidewall of the semiconductor die without extending to the second outer sidewall of the semiconductor die. In some embodiments, the first portion 128 of the plurality of trenches 124 has a bottom surface at a fourth height 129 above the substrate 102, while the second portion 130 of the plurality of trenches 124 has a bottom surface at a fifth height 131 above the substrate 102, wherein the fourth height 129 is smaller than the fifth height 131.

[0015] In some embodiments, the interlayer dielectric layer 114 surrounding the interconnect structure 106 includes a first surface 115a at a sixth height 115b above the substrate, a second surface 117a at a seventh height 117b above the substrate, and a third surface 125a at an eighth height 125b above the substrate 102, wherein the seventh height 117b is smaller than the sixth height 115b and the eighth height 125b.

[0016] As shown in the cross-sectional view 100d of Figure 1D, in some embodiments, a plurality of protrusions 126 extend between the conductive pads of a plurality of conductive pads 116. In a further embodiment, a first portion of the plurality of protrusions 126 is a line segment extending along a first direction 132, while a second portion of the plurality of protrusions 126 is a line segment extending along a second direction 134 perpendicular to the first direction 132. The second line segment extends between the first line segments based on a redistribution layer pattern for probing tests using known good grain methods (see Figures 2A, 2B, 2C, and 2D). For example, a first protrusion 126a and a second protrusion 126b extend parallel to a third protrusion 126c and are intersected by a fourth protrusion 126d (shown in dashed lines) extending perpendicular to the first protrusion 126a, the second protrusion 126b, and the third protrusion 126c.

[0017] As shown in the cross-sectional view 100e of FIG1E, in some embodiments, in an intermediate step prior to semiconductor die cutting (see FIG21), additional protrusions 136 extend between semiconductor dies. In some embodiments, the additional protrusions 136 extend across a plurality of semiconductor dies in a first direction 132, and vertical protrusions 138 (shown in dashed lines) extend from the additional protrusions 136 to the semiconductor dies in a second direction 134.

[0018] Figures 2A, 2B, 2C, and 2D illustrate top views of the redistribution layers 200a, 200b, 200c, and 200d of an intermediate step in a known-good-die (KGD) method for testing multiple integrated circuits at once.

[0019] As shown in the top view 200a of Figure 2A, in some embodiments, a redistribution layer (RDL) 202 is formed on the interlayer dielectric layer 114 before forming a plurality of conductive pads 116 (shown in dashed lines). The RDL 202 couples vias of a plurality of semiconductor dies to each other and to a plurality of metal pads 204. In some embodiments, the plurality of metal pads are arranged on one or more sides of the wafer, and each metal pad is coupled to more than 100 semiconductor dies. The repeating pattern of the semiconductor dies allows more than 100 semiconductor dies to be tested simultaneously in subsequent probing tests. If a probing test of a set of interconnected semiconductor dies fails (e.g., the voltage or current between two metal pads is higher or lower than expected), the semiconductor die coupled to the metal pad 204 is discarded.

[0020] For example, the first semiconductor die 140a, the second semiconductor die 140b, and the third semiconductor die 140c are located directly below two conductors of RDL 202, and their uppermost via 110a is coupled to the first conductor 202a and the second conductor 202b of RDL 202. When the first metal pad 204a coupled to the first conductor 202a and the second metal pad 204b coupled to the second conductor are probed, the voltage measured between the two pads is unexpectedly low. Therefore, the first semiconductor die 140a, the second semiconductor die 140b, the third semiconductor die 140c, or another semiconductor die 140 coupled to the first conductor 202a and the second conductor 202b may have faulty circuit elements or improper connections, causing the semiconductor die coupled to the first conductor 202a and the second conductor 202b to be discarded. While this does reduce the yield of the wafer being tested, testing hundreds of semiconductor dies simultaneously reduces wafer testing time and increases the speed of the final wafer manufacturing process.

[0021] RDL 202 is formed by depositing a conformal metal layer on the interlayer dielectric layer 114, and then patterning the conformal metal layer into RDL 202 and multiple metal pads 204 (see Figures 9, 10A, and 10B). When the conformal metal layer is patterned, the material of the interlayer dielectric layer 114 beneath it is also removed, resulting in trenches 124 forming around RDL 202. Therefore, the multiple trenches 124 surrounding the vias in the uppermost layer of the multiple via layers 110 indicate that the KGD method has been performed.

[0022] As shown in the top view 200b of Figure 2B, in some embodiments, the number of conductive pads 116 (not yet formed in this figure) in each semiconductor die 140 may be more or less than six, depending on the function and design of the semiconductor die 140. For example, as shown, the number of conductive pads 116 in each semiconductor die 140 may be four. As shown in the top view 200c of Figure 2C, the conductors of RDL 202 may follow different patterns to more effectively utilize the limited space on the semiconductor die and increase the spacing between conductors, further isolating the conductors from each other. As shown in the top view 200d of Figure 2D, the conductors of RDL 202 may cross the semiconductor die 140 in a direction perpendicular to the uppermost via 110a. For example, the conductors of RDL 202 extend in a first direction 132, while the uppermost via 110a has the longest dimension extending in a second direction 134. It is understood that other conductor patterns can be used to couple corresponding vias of different semiconductor dies to a conductor of RDL 202 and one of the multiple metal pads 204.

[0023] Figure 3 illustrates the top view 300 of the conductive pads of the multiple integrated circuits shown in Figure 2A after testing.

[0024] After performing electrical tests, the RDL (see 202 in FIG. 2A) is removed, and a conductive pad 116 is formed on the uppermost via 110a (shown in dashed lines). The trenches 124 and protrusions 126 resulting from the formation of RDL 202 remain on the upper surface of the interlayer dielectric layer 114, such that the conductive pad 116 has multiple upper surfaces of different heights. The protrusions 126 extend along the same path as the RDL (see 202 in FIG. 2A), and the trenches 124 extend between the protrusions 126. For example, the first set of vias 110a and the second set of vias 110b are located directly below the first conductive pad 116a. The first protrusion 126a extends along the first set of vias 110a, and the second protrusion 126b extends along the second set of vias 110b in the first direction 132. The third protrusion 126c extends in the second direction 134 between the first protrusion 126a and the second protrusion 126b, resulting in the first, second, and third protrusions 126a, 126b, 126c forming a "U" shape. One of the plurality of trenches 124 extends between the first protrusion 126a and the second protrusion 126b, filling the "U" shape. Based on the pattern of the RDL (see 202 in FIG. 2A), the conductive pad 116 has protrusions that uniquely extend into a "U" shape. In other embodiments with different RDL (see 202 in FIG. 2A) patterns or patterns of the uppermost via 110a, the protrusions extend on the semiconductor die 140 in different patterns.

[0025] Figure 4 illustrates a cross-sectional view 400 of an integrated circuit coupled to a second integrated circuit via a conductive pad in some embodiments.

[0026] In some embodiments, a plurality of conductive pads 116 couple the interconnect structure 106 to a second interconnect structure 402. In some embodiments, the second interconnect structure 402 is coupled to a plurality of micro-LEDs 404 disposed on the second interconnect structure 402, other suitable light-emitting devices, or any combination thereof. The second interconnect structure 402 is or includes a redistribution layer 403 that contacts the plurality of conductive pads 116. In some embodiments, one or more via layers extend between the redistribution layer 403 and the plurality of conductive pads 116. In other embodiments, the one or more via layers are omitted, and the redistribution layer 403 directly contacts the plurality of conductive pads 116.

[0027] In some embodiments, the plurality of micro light-emitting diodes 404 are or include a first electrode 406, a second electrode 408, and a semiconductor layer 410 extending between the first electrode 406 and the second electrode 408. In some embodiments, the first electrode 406 and the second electrode 408 are formed separately from the redistribution layer 403. In other embodiments, the first electrode 406 and the second electrode 408 are part of the redistribution layer 403.

[0028] In some embodiments, the first electrode 406 is or comprises a reflective conductive material, extends beneath the semiconductor layer 410, and acts as a reflector. In other embodiments, the first electrode 406 is or comprises a conductive material and / or does not act as a reflector. In some embodiments, the second electrode 408 covers the semiconductor layer 410. In a further embodiment, the second electrode 408 is or comprises a transparent conductive material, such as a transparent conducting oxide (TCO) (e.g., indium tin oxide (ITO)). In other embodiments, the second electrode 408 does not cover the semiconductor layer 410 and / or comprises a conductive material, such as gold (Au), copper (Cu), titanium (Ti), titanium nitride (TiN), aluminum (Al), or similar materials. In some embodiments, the semiconductor layer 410 covers the first electrode 406 and the second electrode 408. In other embodiments, the first electrode 406 is on a first side of the semiconductor layer 410, and the second electrode 408 is on a second side of the semiconductor layer 410 opposite to the first side. The semiconductor layer 410 is configured to emit light when current passes between the first electrode 406 and the second electrode 408.

[0029] Figure 5 illustrates a through-hole cross-sectional view 500 of a conductive pad coupled to an integrated device in some embodiments.

[0030] In some embodiments, the uppermost via 110a is surrounded by a first barrier layer 502. The first barrier layer 502 extends around the bottom and sidewalls of the via. In some embodiments, the first barrier layer 502 has an uppermost surface substantially flush with the uppermost surface of the via. In some embodiments, the first barrier layer 502 is or comprises one or more tantalum nitride (TaN), titanium nitride (TiN), nickel (Ni), or other similar materials. The first barrier layer 502 is configured to separate the via from the interlayer dielectric layer 114, preventing via material from diffusing into the interlayer dielectric layer 114 material.

[0031] In some embodiments, a plurality of conductive pads 116 are separated from the interlayer dielectric layer 114 by a second barrier layer 504. The second barrier layer 504 covers the bottom surface of the conductive pads 116. In some embodiments, the second barrier layer 504 is or comprises one or more tantalum nitride (TaN), titanium nitride (TiN), nickel (Ni), or other similar materials. In some embodiments, the second barrier layer 504 is configured to attach the plurality of conductive pads 116 to the interlayer dielectric layer 114 and the uppermost via 110a.

[0032] In some embodiments, during an intermediate step, a third barrier layer 506 is formed on the conductive pad 116 and the interlayer dielectric layer to prevent damage to them during processes related to dicing semiconductor dies, transporting semiconductor dies, and attaching carrier wafers to the substrate (see 102 in FIG. 1A) to transport semiconductor dies. In some embodiments, the third barrier layer 506 is or comprises one or more aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), titanium oxide (TiO₂), silicon nitride (Si₃N₄), titanium nitride (TiN), other similar materials, or combinations thereof.

[0033] Figure 6 illustrates a top view 600 of the conductive pads of the integrated device and the trenches 124 introduced during the patterning of the redistribution layer in some embodiments. In some embodiments, the width of the protrusion 126 is greater than the width of the trench 124. In a further embodiment, the protrusion 126 extends to a plurality of adjacent conductive pads 116. For example, the protrusion 126 shown in Figure 6 extends from a first conductive pad 116a to a second conductive pad 116b. In some embodiments, a second upper surface 120 of the first conductive pad 116a extends from a first outer sidewall of the first conductive pad 116a to a second outer sidewall of the first conductive pad 116a.

[0034] Figures 7-9, 10A-10B, and 11-21 illustrate a series of cross-sectional views of some embodiments of forming integrated devices using the Known Good Grain Deposition (KGD) method. While Figures 7-9, 10A-10B, and 11-21 are described as a series of actions, it should be understood that these actions are not limiting, as the order of actions may change in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some illustrated and / or described actions may be omitted in whole or in part. Cross-sectional view 1000a of Figure 10A is taken along line A-A' in the top view 1000b of Figure 10B.

[0035] As shown in the cross-sectional view 700 of Figure 7, a plurality of semiconductor devices 104 are formed on a substrate 102. The plurality of semiconductor devices 104 include one or more transistors (e.g., planar field-effect transistors, fin field-effect transistors (FinFETs), gate-all-around (GAA) devices, etc.), circuit elements (e.g., resistors, capacitors, diodes, etc.), or the like. Forming the plurality of semiconductor devices 104 includes forming the transistors and circuit elements using one or more physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etching and implantation processes, or similar processes.

[0036] As shown in the cross-sectional view 800 of FIG8, in some embodiments, an interconnect structure 106 is formed on a plurality of semiconductor devices 104. The interconnect structure 106 includes a plurality of line layers 108, a plurality of via layers 110, and a plurality of contacts 112 coupling the interconnect structure 106 to the plurality of semiconductor devices 104. An interlayer dielectric layer 114 surrounds the plurality of line layers 108 and the plurality of via layers 110. In some embodiments, the plurality of line layers 108, the plurality of via layers 110, and the plurality of contacts 112 are or comprise one or more of aluminum (Al), copper (Cu), aluminum-copper alloys, tungsten (W), tantalum nitride (TaN), or the like. In some embodiments, the interlayer dielectric layer 114 is or comprises an insulating material, such as one or more of silicon dioxide (SiO2), silicon nitride (Si3N4), or the like.

[0037] In some embodiments, the interconnect structure 106 is formed by depositing a portion 114a of an interlayer dielectric layer 114, etching openings corresponding to the wire layers and via layers in the interlayer dielectric layer 114, forming a metal layer to fill the openings using one or more PVD, ALD, CVD, or similar methods, and then removing the portion of the metal layer above the upper surface of the portion of the interlayer dielectric layer 114. This method is repeated to form additional portions of the interlayer dielectric layers 114b and 114c until the interconnect structure 106 is completed. In some embodiments, multiple semiconductor devices 104 and the interconnect structure 106 are configured to form an LED driving circuit. In some embodiments, the uppermost via layer of multiple via layers 110 is formed using a single damascene process.

[0038] As shown in the cross-sectional view 900 of Figure 9, a first conformal metal layer 902 is formed on the interconnect structure 106. The first conformal metal layer 902 is or contains one or more aluminum (Al), gold (Au), titanium (Ti), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), or the like. In some embodiments, the first conformal metal layer 902 is formed using one or more PVD, ALD, CVD, or similar methods.

[0039] As shown in the cross-sectional view 1000a of FIG. 10A and the top view 1000b of FIG. 10B, a first mask 1004 is formed on a substrate 102 and subsequently patterned. In some embodiments, the first mask 1004 comprises a photoresist and is patterned using a photolithography process. After the first mask 1004 is patterned, a first conformal metal layer (see 902 in FIG. 9) is patterned to form an RDL layer 202 and a plurality of metal pads 204. The pattern of the RDL layer 202 is configured to couple the corresponding uppermost vias 110a in the discrete semiconductor die to each other and to one of the plurality of metal pads 204.

[0040] In some embodiments, patterning is performed using a dry etching process 1002. The dry etching process 1002 removes portions of the first conformal metal layer (see 902 in FIG. 9) not covered by the first mask 1004. Furthermore, the interlayer dielectric layer 114 is partially etched away by the dry etching process 1002, resulting in trenches 124 and protrusions 126 formed on the upper surface of the interlayer dielectric layer 114. The first mask 1004 is then removed.

[0041] After the first mask 1004 is removed, electrical tests are performed on the plurality of semiconductor dies 140. In some embodiments, the electrical tests are performed by probing the individual metal pads 204 coupled to the plurality of semiconductor dies 140 and measuring the voltage and current between the probed metal pads 204. The resulting measurements are used to determine the semiconductor dies to be retained after the dicing process and used in the final product.

[0042] As shown in the cross-sectional view 1100 of Figure 11, the RDL (see 202 in Figure 2A) and multiple metal pads (see 204 in Figure 2B) are removed. In some embodiments, the removal is performed using a combination of etching (e.g., dry or wet etching) and planarization processes (e.g., chemical mechanical planarization (CMP)). The removal process results in the exposure of the uppermost via 110a, while the protrusion 126 and trench 124 remain on the uppermost surface of the interlayer dielectric layer 114.

[0043] As shown in the cross-sectional view 1200 of FIG12, a second conformal metal layer 1202 is formed on the uppermost surface of the interlayer dielectric layer 114. In some embodiments, the second conformal metal layer 1202 is or comprises aluminum (Al), gold (Au), titanium (Ti), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), the like, or combinations thereof. The second conformal metal layer 1202 conforms to the protrusions 126 and trenches 124 on the uppermost surface of the interlayer dielectric layer 114, resulting in the second conformal metal layer 1202 having multiple upper surfaces at different heights above the substrate 102. In some embodiments, the second conformal metal layer 1202 is formed using a deposition process such as PVD, ALD, CVD, or similar.

[0044] As shown in the cross-sectional view 1300 of FIG13, a second mask 1304 is formed over the interconnect structure 106 and subsequently patterned. In some embodiments, the second mask 1304 comprises a photoresist and is patterned using photolithography. After the second mask 1304 is patterned, a second conformal metal layer (see 1202 in FIG12) is patterned to form a plurality of conductive pads 116. The pattern configured to couple the plurality of conductive pads 116 together to the uppermost via 110a is based on an integrated circuit layout.

[0045] In some embodiments, patterning is performed using a dry etching process 1302. The dry etching process 1302 removes portions of the second conformal metal layer (see 1202 in FIG. 12) not covered by the second mask 1304. In some embodiments, the interlayer dielectric layer 114 is partially etched away by the dry etching process 1302, causing the trench 124 to extend further into the interlayer dielectric layer 114, and resulting in a first portion 128 of the trench 124 having a height above the upper surface of the substrate 102 that is less than the height of the bottom upper surface of the second portion 130 of the trench 124 below the conductive pad 116. The second mask 1304 is then removed.

[0046] As shown in the cross-sectional view 1400 of Figure 14, a third barrier layer 506 is formed over a plurality of conductive pads 116 and an interlayer dielectric layer 114. In some embodiments, the third barrier layer 506 is or is composed of the following materials: alumina (Al₂O₃), hafnium oxide (HfO₂), titanium oxide (TiO₂), silicon nitride (Si₃N₄), titanium nitride (TiN), another similar material or combination thereof. In some embodiments, the third barrier layer 506 is formed using deposition processes such as PVD, ALD, CVD, etc.

[0047] As shown in the cross-sectional view 1500 of Figure 15, an insulating layer 1502 is formed above the third barrier layer 506. In some embodiments, the insulating layer 1502 is or contains an insulating material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or the like. In some embodiments, the insulating layer 1502 is formed using a deposition process such as PVD, ALD, CVD, or similar, and then subsequently planarized using CMP or similar methods.

[0048] As shown in the cross-sectional view 1600 of FIG16, the first carrier wafer 1602 is bonded to the insulating layer 1502. In some embodiments, the first carrier wafer 1602 is or contains silicon, silicon germanium (SiGe) or the like, or contains a silicon on insulator (SOI) substrate. In some embodiments, the first carrier wafer 1602 is bonded to the insulating layer 1502 using a direct bonding method.

[0049] As shown in the cross-sectional view 1700 of Figure 17, a portion of the substrate 102 is removed to achieve a specified thickness. In some embodiments, this portion of the substrate 102 is removed using a polishing process. In some embodiments, the specified thickness is approximately between 3 and 10 micrometers, between 2 and 7 micrometers, between 4 and 13 micrometers, or in another similar range.

[0050] As shown in the cross-sectional view 1800 of FIG18, the second carrier wafer 1802 is bonded to the substrate 102. In some embodiments, the second carrier wafer 1802 is or comprises silicon, silicon germanium (SiGe) or the like, or comprises a silicon on insulator (SOI) substrate. The second carrier wafer 1802 is bonded to the substrate 102 by an adhesive layer 1804. The adhesive layer 1804 and the second carrier wafer 1802 are configured to hold a semiconductor die (see 140 in FIG2A) in the method steps shown in FIG19 and FIG20.

[0051] As shown in cross-sectional view 1900 of FIG. 19, the first carrier wafer (see 1602 in FIG. 16) is removed from the insulating layer 1502. In some embodiments, the first carrier wafer (see 1602 in FIG. 16) is removed using a grinding or thinning process. As shown in cross-sectional view 2000 of FIG. 20, in some embodiments, the insulating layer (see 1502 in FIG. 19) is removed from the substrate 102. Removing the insulating layer (see 1502 in FIG. 19) exposes the third barrier layer 506. In some embodiments, a portion of the insulating layer (see 1502 in FIG. 19) is removed in the same grinding or thinning process used to remove the first carrier wafer (see 1602 in FIG. 16). In some embodiments, a portion of the insulating layer (see 1502 in FIG. 19) is removed using an etching process that is selective to the material of the insulating layer (see 1502 in FIG. 19). In some embodiments, the insulating layer (see 1502 in FIG. 19) is not removed but instead serves as a dielectric layer surrounding the via layer to be formed subsequently.

[0052] As shown in the cross-sectional view 2100 of FIG21, openings are etched in the third barrier layer 506, and a second interconnect structure 402 is formed on a plurality of conductive pads 116. Subsequently, a micro-light-emitting diode 404 is formed on the second interconnect structure 402. In some embodiments, a plurality of semiconductor dies 140 are diced before the formation of the second interconnect structure 402 and the micro-light-emitting diode 404, separating the semiconductor dies 140 from each other. In some embodiments, the plurality of semiconductor dies 140 are diced using a selective etching process. The semiconductor dies 140 are then transferred from the adhesive layer (see 1804 in FIG18) (e.g., using a batch transfer technique) to form the second interconnect structure 402 and the micro-light-emitting diode 404. In some embodiments, portions of semiconductor dies 140 that fail electrical testing (or electrically coupled to semiconductor dies 140 that fail electrical testing via a redistribution layer (see 202 in FIG2C)) do not form micro-light-emitting diodes on the plurality of conductive pads 116. In other embodiments, semiconductor dies 140 that fail electrical tests are partially formed into miniature light-emitting diodes 404 on a plurality of conductive pads 116, and then the defective dies are discarded. In some embodiments, the plurality of miniature light-emitting diodes 404 are omitted, and other suitable light-emitting devices are formed on the plurality of conductive pads 116 instead.

[0053] Figure 22 illustrates a flowchart 2200 of some embodiments of forming an integrated device using the Known Good Grain Deposition (KGD) method. While this method and other methods illustrated and / or described herein are illustrated as a series of actions or events, it should be understood that this disclosure is not limited to the illustrated sequence or actions. Therefore, in some embodiments, actions may be performed in a different order than illustrated, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other unillustrated actions or events may be included. [, , ]

[0054] In block 2202, a semiconductor device is formed on the substrate. An example illustrating this step can be seen in Figure 7.

[0055] In block 2204, an interconnect structure coupled to a semiconductor device and surrounded by an interlayer dielectric layer is formed on the substrate. The interconnect structure includes multiple vias located on the top surface of the interlayer dielectric layer. An example illustrating this step can be seen in Figure 8.

[0056] In block 2206, a first conformal metal layer is formed on the interlayer dielectric layer. A diagram illustrating this step can be seen in Figure 9.

[0057] In block 2208, the first conformal metal layer is patterned into a plurality of metal pads and a redistribution layer covering a plurality of vias. The patterning results in the formation of a first trench between the first vias and the second vias of the plurality of vias. An illustrated example of this step can be seen in Figure 10A.

[0058] In block 2210, electrical tests are performed on the redistribution layer and interconnect structure by probing the metal pads. A diagram illustrating this step can be seen in Figure 10B.

[0059] In block 2212, remove the redistribution layer. A graphical example illustrating this step can be seen in Figure 11.

[0060] In block 2214, a conductive pad is formed that couples to the first and second vias, wherein the conductive pad extends into the first trench. An illustrated example of this step can be seen in Figures 12-13.

[0061] Some embodiments relate to an integrated circuit including: a substrate having a top surface; a semiconductor device on the substrate; an interconnect structure covering the substrate and coupled to the semiconductor device; and a first conductive pad coupled to the interconnect structure, wherein the first conductive pad has a first upper surface at a first height above the top surface of the substrate and a second upper surface at a second height above the top surface of the substrate, wherein the first height is greater than the second height.

[0062] Other embodiments relate to an integrated device, including: a substrate; a plurality of semiconductor devices above the substrate; an interconnect structure coupled to the plurality of semiconductor devices; an interlayer dielectric layer surrounding the interconnect structure, the interlayer dielectric layer including a first surface at a first height above the substrate, a second surface at a second height above the substrate, and a third surface at a third height above the substrate, the second height being smaller than the first and third heights; and a first conductive pad including a lower surface conforming to the first, second, and third surfaces of the interlayer dielectric layer and coupled to the interconnect structure through the first surface of the interlayer dielectric layer.

[0063] Other embodiments relate to a method of forming an integrated device, the method comprising: forming a semiconductor device on a substrate; forming an interconnect structure on the substrate coupled to the semiconductor device and surrounded by an interlayer dielectric layer, the interconnect structure including a plurality of uppermost vias located on the top surface of the interlayer dielectric layer; forming a first conformal metal layer on the interlayer dielectric layer; patterning the first conformal metal layer into a plurality of metal pads and a redistribution layer covering the plurality of uppermost vias, the patterning causing a first trench to be formed between a first via and a second via of the plurality of uppermost vias; performing an electrical test on the redistribution layer and the interconnect structure by probing the metal pads; removing the redistribution layer; and forming conductive pads coupled to the first and second vias, wherein the conductive pads extend into the first trench.

[0064] It should be understood that the terms "first," "second," "third," etc., used in this written description and in the following claims are merely general identifiers for ease of explanation, used to distinguish different elements in a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the elements, and are not intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, "first dielectric layer" illustrated in connection with the first figure may not necessarily correspond to "first dielectric layer" illustrated in connection with another figure, and may not necessarily correspond to "first dielectric layer" in embodiments not shown.

[0065] The features of the above embodiments are intended to facilitate understanding of various aspects of this disclosure by those skilled in the art. Those skilled in the art should understand that this disclosure can be used as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the above embodiments. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

[0066] 100a, 100b, 100c, 100d, 100e, 1000a, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 400, 500, 700, 800, 900: Sectional Views 102: Base 102a: Top surface 104: Semiconductor Devices 106: Internal Wiring Structure 108: Linear Layer 110: Through-hole layer 110a, 110b: Through holes 112: Contact element 114, 114b, 114c: Interlayer dielectric layers 114a: Part 115a: First surface 115b: Sixth Altitude 116: Conductive pad 116a: First conductive pad 116b: Second conductive pad 117a: Second surface 117b: Seventh Altitude 118: First upper surface 119: First Height 120: Second upper surface 121: Second Altitude 122: Third upper surface 123: Third Altitude 124: Trench 124a: First trench 124b: Second trench 124c: Third groove 125a: Third surface 125b: Eighth Altitude 126: Protrusion 126a: First protrusion 126b: Second protrusion 126c: Third protrusion 126d: Fourth protrusion 128: Part One 129: Fourth Altitude 130: Part Two 131: Fifth Altitude 132: First Direction 134: Second Direction 136: Extra protrusion 138: Vertical protrusion 140: Semiconductor die 140a: First semiconductor die 140b: Second semiconductor wafer 140c: Third semiconductor die 202, 403: Redistribution layers 202a: First conductor 202b: Second conductor 204: Metal Pad 204a: First metal pad 204b: Second metal pad 402: Second internal connection structure 404: Miniature Light Emitting Diode 406: First electrode 408: Second electrode 410: Semiconductor layer 502: First Barrier Layer 504: Second Barrier Layer 506: Third Barrier Layer 902: First conformal metal layer 1000b, 200a, 200b, 200c, 200d, 300, 600: Top View 1002, 1302: Dry etching process 1004: The First Curtain 1202: Second conformal metal layer 1304: The Second Curtain 1502: Insulation layer 1602: First carrier wafer 1802: Second carrier wafer 1804: Adhesive layer 2200: Flowchart 2202, 2204, 2206, 2208, 2210, 2212, 2214: Squares

Claims

1. An integrated circuit, comprising: The substrate, including the top surface; A semiconductor device is located on the substrate; An interconnect structure covering the substrate and coupled to the semiconductor device includes a topmost via; a first conductive pad coupled to the interconnect structure, wherein the first conductive pad has a first upper surface at a first height above the top surface of the substrate, and a second upper surface at a second height above the top surface of the substrate, wherein the first height is greater than the second height, wherein the first conductive pad is coupled to the interconnect structure via the topmost via; a trench extending between the topmost via; and a second conductive pad coupled to the interconnect structure, wherein the trench separates the first conductive pad from the second conductive pad.

2. The integrated circuit of claim 1, wherein the first conductive pad has a third upper surface at a third height greater than the second height, and wherein the second upper surface is located between the first upper surface and the third upper surface.

3. The integrated circuit as claimed in claim 2, wherein the first conductive pad is coupled to the interconnect structure at a first lower surface directly below the first upper surface and at a second lower surface directly below the third upper surface.

4. The integrated circuit as claimed in claim 1, wherein the bottom surface of the first conductive pad extends below the upper surface of the uppermost through-hole.

5. An integrated device, comprising: Base; Multiple semiconductor devices are located above the substrate; An interconnect structure is coupled to the plurality of semiconductor devices; An interlayer dielectric layer surrounds the interconnect structure and includes a first surface at a first height above the substrate, a second surface at a second height above the substrate, and a third surface at a third height above the substrate, wherein the second height is smaller than the first height and the third height; a first conductive pad includes a lower surface conforming to the first surface, the second surface, and the third surface of the interlayer dielectric layer, and is coupled to the interconnect structure through the first surface of the interlayer dielectric layer; And a second conductive pad, located on the interlayer dielectric layer, wherein trenches in the interlayer dielectric layer separate the first conductive pad from the second conductive pad.

6. The integrated device as claimed in claim 5, wherein the interlayer dielectric layer includes a fourth surface located at the bottom of the trench at a fourth height above the substrate, the fourth height not exceeding the second height.

7. A method of forming an integrated device, the method comprising: Forming semiconductor devices on a substrate; An interconnect structure is formed on the substrate, coupled to the semiconductor device and surrounded by an interlayer dielectric layer, the interconnect structure including a plurality of uppermost vias located on the top surface of the interlayer dielectric layer; a first conformal metal layer is formed on the interlayer dielectric layer; the first conformal metal layer is patterned into a plurality of metal pads and a redistribution layer covering the plurality of uppermost vias, the patterning causing a first trench to be formed between a first via and a second via of the plurality of uppermost vias; an electrical test is performed on the redistribution layer and the interconnect structure by probing the metal pads; the redistribution layer is removed; and a conductive pad is formed, coupled to the first via and the second via, wherein the conductive pad extends into the first trench.

8. The method of claim 7 further includes dicing the substrate and the interconnect structure to separate the plurality of semiconductor dies from the integrated device.

9. The method of claim 8, wherein forming the conductive pad further comprises: A second conformal metal layer is formed on the plurality of uppermost through-holes; A mask is formed and patterned on the second conformal metal layer, wherein the mask is patterned to expose a portion of the conformal metal layer located within a second trench formed during the patterning of the first conformal metal layer; and the conformal metal layer is patterned to leave the conductive pad on the interlayer dielectric layer.

10. The method as described in claim 7, further comprising: A barrier layer is formed on the conductive pad and the interlayer dielectric layer; An insulating layer is formed on the barrier layer; The first carrier wafer is bonded to the insulating layer; Remove a portion of the substrate to expose the lower surface of the substrate; The second carrier wafer is bonded to the lower surface of the substrate; And remove the first carrier wafer, the insulating layer and the barrier layer, exposing the conductive pad and the interlayer dielectric layer.

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