P-type dipole for p-fet

Abstract

Methods for forming and processing semiconductor devices are described. Some embodiments relate to electronic devices that include a dipole region having an interlayer dielectric, a high-k dielectric material, and a dipole layer. The dipole layer includes one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of electronic component manufacturing, and more particularly, to transistors. More specifically, embodiments of the present disclosure are directed to FinFET components and methods of manufacturing FinFET components. Prior Art

[0002] Integrated circuits have evolved into complex components that can include millions of transistors, capacitors, and resistors on a single wafer. In the process of integrated circuit development, the functional density (i.e., the number of interconnected components per wafer area) has generally increased, while the geometric size (i.e., the smallest components (or lines) that can be produced using the manufacturing process) has decreased.

[0003] A transistor is a circuit component or element that is typically formed on a semiconductor component. Many transistors can be formed on a semiconductor component, which depends not only on capacitors, inductors, resistors, diodes, wires, or other components, but also on the circuit design. An integrated circuit includes planar field-effect transistors (FETs), where current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004] As component sizes shrink, the geometric shapes and materials of components face difficulties in maintaining switching speeds without causing failures. Some new technologies have emerged that enable chip designers to continue to shrink the gate length. Control of component structure dimensions is a key challenge for current and future technology generations. Since 1970, the number of components per wafer has doubled every two years. Due to this trend, miniaturization of circuits by shrinking transistor sizes has been the main driving force in the semiconductor technology roadmap.

[0005] There will be challenges related to the development of new p-type dipole materials with Vt shift and no equivalent oxide thickness (EOT) loss. The migration of transistor technology from planar to FinFET requires conformal work function layers and solutions for multiple threshold voltages. The Vt adjustment range will be limited by thickness variations and will further shrink component sizes. The dipole layer will serve as an effective treatment for transferring the work functions of PMOS and NMOS and will simplify the material requirements for the energy band edges. Summary of the Invention

[0006] One or more embodiments relate to an electronic component and a method of manufacturing an electronic component, the component including a source region, a drain region, and a channel separating the source region and the drain region; having a dipole region on a top surface of the channel, the dipole region including an interlayer dielectric, a high-k dielectric material, and a dipole layer.

[0007] In one or more embodiments, a method of manufacturing an electronic component includes: depositing an interlayer dielectric on a top surface of a channel between a source and a drain located on a substrate; depositing a high-k dielectric material on the interlayer dielectric; and depositing a dipole layer on the high-k dielectric material.

[0008] One or more embodiments relate to a non-transitory computer-readable medium including instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the following operations: depositing an interlayer dielectric on a top surface of a channel between a source and a drain located on a substrate; depositing a high-k dielectric material on the interlayer dielectric; and depositing a dipole layer on the high-k dielectric material. Brief Description of the Drawings

[0009] Accordingly, in order to understand in detail the manner in which the above-described features of the present disclosure can be obtained, the present disclosure may be described in more detail by reference to the embodiments, which are briefly summarized above, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of the present disclosure and should not be considered as limiting its scope, since the present disclosure may admit other equivalent embodiments. The embodiments described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals indicate like elements.

[0010] FIG. 1 depicts a process flowchart of an embodiment of a method according to an embodiment described herein;

[0011] FIG. 2 shows a cross-sectional view of a substrate according to one or more embodiments;

[0012] FIG. 3A shows a cross-sectional view of a substrate according to one or more embodiments;

[0013] FIG. 3B shows a cross-sectional view of a substrate according to one or more embodiments; and

[0014] FIG. 4 shows a cluster tool according to one or more embodiments of the present disclosure. Embodiments

[0015] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or processing steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0016] As used herein, the term "about" means approximate or close and, in the context of the numerical value or range set forth, means a variation of ±15% or less of the numerical value. For example, values that differ by ±14%, ±10%, ±5%, ±2%, or ±1% will satisfy the definition of about.

[0017] As used in this specification and the appended claims, the term "substrate" or "wafer" refers to the surface or a portion of the surface on which processing is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, a reference to a substrate may only refer to a portion of the substrate. Additionally, a reference to depositing on a substrate may refer to a bare substrate and a substrate on which one or more films or features have been deposited or formed.

[0018] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials, such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate can be exposed to a pre-treatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing thin film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed thin film processing steps can also be performed on an underlying layer formed on the substrate. As disclosed in more detail below, the term "substrate surface" is intended to include the underlying layer as indicated by the context. Thus, for example, in the case where a film / layer or a portion of a film / layer has been deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0019] As used in this specification and the appended claims, the terms "precursor", "reactant", "reaction gas", etc. are used interchangeably and refer to any gaseous substance that can react with a substrate surface.

[0020] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate is separately exposed to two or more reactive compounds, which are introduced into the reaction zone of a processing chamber. In time-domain ALD processing, there is a time interval between the exposures to each reactive compound to allow each compound to adhere and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In spatial ALD processing, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to two or more reactive compounds such that any given point on the substrate is not substantially simultaneously exposed to more than one reactive compound. As used in this specification and the appended claims, in this regard, the term "substantially" means that, as would be understood by one of ordinary skill in the art, due to diffusion, a small portion of the substrate may be simultaneously exposed to multiple reactive gases and that such simultaneous exposure is unintentional.

[0021] In one aspect of time-domain ALD processing, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay period, a purge gas such as argon is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process such that only the purge gas flows during the time delay periods between the pulses of the reactive compounds. Alternatively, the reactive compounds are pulsed until a desired film or film thickness is formed on the substrate surface. In either case, the ALD process of pulsing compound A, the purge gas, compound B, and the purge gas is one cycle. The cycle can start with compound A or compound B and then continue through the various sequences of the cycle until a film of a predetermined thickness is obtained.

[0022] In an embodiment of spatial ALD processing, a first reactive gas and a second reactive gas (e.g., nitrogen) are simultaneously delivered to the reaction zone but are separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery elements such that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0023] A transistor is a circuit component or element typically formed on a semiconductor device. In accordance with the circuit design, in addition to capacitors, inductors, resistors, diodes, wires, or other elements, transistors are also formed on the semiconductor device. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0024] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. A field effect transistor is a voltage-controlled device in which its current-carrying capacity is changed by applying an electric field. Field effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain terminal and the source terminal is controlled by an electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of an FET are the source (S) through which carriers enter the channel, the drain (D) through which carriers leave the channel, and the gate (G), the terminal used to modulate the channel conductivity. Generally, the current entering the channel at the source (S) is labeled I S, and the current entering the channel at the drain (D) is labeled I D. The drain-to-source voltage is called V DS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D) can be controlled.

[0025] A metal-oxide-semiconductor field effect transistor (MOSFET) is a type of field effect transistor (FET) used in integrated circuits and high-speed switching applications. A MOSFET has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitor between a body electrode and a gate electrode located above the body, where the gate electrode is insulated from all other device regions by a gate dielectric layer. Compared with a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a respective highly doped region separated by the body region. These regions can be either p-type or n-type, but they are both of the same type as the body region and of the opposite type to the body region. The source and drain (different from the body) are highly doped and are denoted by a "+" sign after the doping type.

[0026] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions, while the body is a p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions, while the body is an n-type substrate region. The source is so named because it is the source of the charge carriers (n-channel electrons, p-channel holes) flowing through the channel; similarly, the drain is where the charge carriers leave the channel.

[0027] An nMOS FET consists of an n-type source and drain and a p-type substrate. When a voltage is applied to the gate, the holes in the body (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain, and current is transferred from the source to the drain by electrons through the induced n-type channel. Logic gates and other digital components implemented using several NMOS are said to have NMOS logic. There are three operating modes in NMOS, called cutoff, triode, and saturation. Circuits with NMOS logic gates consume static power when idling because a direct current flows through the logic gates when the output is low.

[0028] A pMOS FET consists of a p-type source and drain and an n-type substrate. When a positive voltage (negative voltage between the gate and source) is applied between the source and the gate, a p-type channel of opposite polarity is formed between the source and the drain. Holes transfer current from the source to the drain through the induced p-type channel. A high voltage on the gate will cause the PMOS to be non-conductive, while a low voltage on the gate will cause it to be conductive. Logic gates and other digital components implemented using PMOS are said to have PMOS logic. PMOS technology is inexpensive and has good noise immunity.

[0029] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS will conduct, while PMOS will not. Additionally, when a low voltage is applied to the gate, NMOS will not conduct, while PMOS will conduct. NMOS is considered faster than PMOS because the propagation speed of the carriers (electrons) in NMOS is twice that of holes (the carriers in PMOS). However, PMOS components are more noise-resistant than NMOS components. Also, since NMOS can provide half the impedance of what PMOS can provide (with the same geometry and operating conditions), NMOS ICs will be smaller than PMOS ICs providing the same functionality.

[0030] As used herein, the term "FinFET" refers to a MOSFET transistor built on a substrate, where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double-gate structure. The common name for FinFET components is FinFETs because the source / drain regions form "fins" on the substrate. FinFET components have fast switching times and high current densities.

[0031] One or more embodiments advantageously target materials that can serve as effective dipoles for p-FETs, which improve Vt and do not affect the equivalent oxide thickness (EOT). Embodiments of the novel materials can be used for dipoles without increasing the EOT. Embodiments of the present disclosure significantly improve Vt without EOT loss due to a new integration scheme.

[0032] In one or more embodiments, materials exhibiting p-metal behavior are advantageously provided. Materials of one or more embodiments include, but are not limited to, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium aluminum carbide (TiAlC), or tantalum oxide (TaO). Other embodiments relate to a method of integrating dipole materials for p-FETs.

[0033] In one or more embodiments, a film containing a p-metal material is provided. The thin film that can be deposited by atomic layer deposition shows the ability to tune the PMOS work function. The growth of the dipole material is carried out in an ALD chamber at a temperature of 150°C to 500°C. In-situ capping layers (such as TiN or TiAl) can be used to control the oxidation of the film after deposition.

[0034] In some embodiments, the growth of TiAlN / TiTaN is carried out in an ALD chamber at a temperature of 200°C to 500°C. In some embodiments, the amounts of aluminum (Al) and tantalum (Ta) are adjusted by changing the pulse periods of the titanium (Ti) precursor and the aluminum (Al) and tantalum (Ta) precursor pulse periods.

[0035] Some embodiments provide tantalum oxide (TaO) films. In certain embodiments, the growth of TaO is carried out by ALD in the temperature range of 150°C to 500°C.

[0036] Embodiments of the present disclosure include a dipole material that provides a Vfb shift of more than 100 mV and has a minimal EOT increase. Embodiments alleviate the need to develop extreme p-type work function materials. TiAlN / TiTaN is p-type and can be capped in-situ with TiN (e.g., in a cluster tool) to prevent oxidation and EOT increase. In some embodiments, the Al or Ta content in TiAlN / TiTaN is adjustable to adjust the work function shift. Some embodiments allow for multiple Vt adjustments. In one or more embodiments, multiple Vt adjustments can be achieved through both composition and dipole film thickness.

[0037] Some embodiments of the present disclosure relate to an atomic layer deposition method for depositing a titanium aluminum nitride (TiAlN) film. According to some embodiments, an ALD cycle includes exposing a substrate to a titanium precursor pulse to form a titanium-containing layer on the surface of the substrate. Then the titanium precursor is purged from the processing chamber or removed from the reaction region adjacent to the substrate surface. The substrate with the titanium-containing layer is exposed to a pulse of a nitrogen reactant (e.g., ammonia) to form a titanium nitride-containing layer on the substrate surface. Then the nitrogen reactant is purged from the processing chamber or removed from the reaction region adjacent to the substrate surface. The substrate with the titanium nitride-containing layer is exposed to an aluminum reactant pulse to form a titanium aluminum nitride film. Then the aluminum reactant is purged from the processing chamber or removed from the reaction region adjacent to the substrate surface.

[0038] In some embodiments, the titanium precursor includes titanium halide TiX4. In some embodiments, the titanium halide includes TiCl4. In other embodiments, the precursor is any suitable titanium metal organic precursor.

[0039] In some embodiments, the precursor includes tantalum halide TaX4. In some embodiments, the tantalum halide includes TaCl4. In other embodiments, the precursor is any suitable tantalum metal organic precursor.

[0040] In some embodiments, the aluminum precursor includes aluminum amide. In some embodiments, the aluminum precursor includes triethylaluminum, trimethylaluminum,三叔丁基鋁 etc.

[0041] In some embodiments, the reactant includes a nitriding agent. In some embodiments, the nitriding agent includes ammonia. In some embodiments, the nitriding agent includes plasma.

[0042] In some embodiments, the reactants include an oxidizing agent. In some embodiments, the oxidizing agent comprises O2 or water. In some embodiments, the oxidizing agent includes plasma.

[0043] In some embodiments, the reaction pressure ranges from about 0 Torr to about 100 Torr, or from about 100 Torr to about 50 Torr, or from about 1 Torr to about 40 Torr, or from about 10 Torr to about 35 Torr, or from about 20 Torr to about 30 Torr.

[0044] In some examples, the growth rate of the TiAlN film grown using trimethylaluminum as a reactant ranges from about 0.2 Å / cycle to about 2 Å / cycle, or from about 0.5 Å / cycle to about 1.5 Å / cycle, or from about 0.8 Å / cycle to about 1.2 Å / cycle, or about 1 Å / cycle.

[0045] In some embodiments, based on atoms and measured by XPS, the surface of the TiAlN film has about 5% to about 20% titanium and about 1% to about 20% aluminum. In some embodiments, based on atoms and measured by XPS, the surface of the TiAlN film has about 8% to about 17% titanium and about 1% to about 9% aluminum. In some examples, based on atoms, the surface of the TiAlN film has about 10% to about 15% titanium and about 1% to about 7% aluminum.

[0046] Some embodiments of the present disclosure relate to a method of forming a metal-oxide semiconductor capacitor (MOSCAP). A substrate including a high-k dielectric layer and an optional high-k capping layer is exposed to one or more treatments to form a dipole modulation layer and an optional dipole capping layer (e.g., TiN) on the dipole modulation layer. In some embodiments, an amorphous silicon (a-Si) film is formed on the dipole modulation layer or the dipole capping layer. In some embodiments, the a-Si layer and the stack of films on which the a-Si layer is formed are annealed to modulate the dipole of the high-k dielectric layer and form a modulated high-k dielectric layer. In some embodiments, one or more suitable etching or stripping treatments are used to remove the amorphous silicon layer, the optional dipole capping layer, and the dipole modulation layer. In some embodiments, a work function metal layer is deposited on the dipole-modulated high-k dielectric layer. In some embodiments, a fill metal layer is formed on the work function metal layer.

[0047] In some embodiments, the flat-band voltage increase of the resulting MOSCAP is greater than or equal to about 20 mV, 30 mV, 40 mV, 50 mV, 60 mV, 70 mV, 80 mV, 90 mV, or 100 mV. In some embodiments, the amount of increase in the equivalent oxide thickness (EOT) of the high-k dielectric layer ranges from about 0 angstroms to about 1.0 angstroms.

[0048] Embodiments of the present disclosure are described by way of the accompanying drawings, which illustrate elements (e.g., transistors) according to one or more embodiments of the present disclosure and processes for forming the transistors. The processes shown are merely exemplary possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0049] FIG. 1 depicts a flowchart of method 100 according to one or more embodiments of the present disclosure. Referring to FIG. 1, method 100 begins at operation 102 by depositing an interlayer dielectric on a top surface of a channel between a source and a drain located on a substrate. At operation 104, a high-K dielectric material is deposited on the interlayer dielectric. At operation 106, a dipole layer is deposited on the high-K dielectric material. At operation 108, a capping layer is optionally deposited on the dipole layer.

[0050] FIGS. 2 and 3A and 3B are cross-sectional views of an electronic component (e.g., a transistor) 200 according to one or more embodiments. Referring to FIGS. 2 and 3A, electronic component 200 includes a semiconductor substrate 202 having a top surface 203. The semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 202 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), copper indium gallium selenide (CIGS), other semiconductor materials, or any combination thereof. In one or more embodiments, the semiconductor substrate 202 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), copper (Cu), or selenium (Se). Although some examples of materials from which substrate 202 can be formed are described herein, materials that can be used as a basis for constructing passive and active electronic components (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic components, or any other electronic component) fall within the spirit and scope of the present disclosure.

[0051] In one or more embodiments, the semiconductor substrate 202 is a p-type or n-type substrate. As used herein, the term "n-type" refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during a manufacturing process. The term n-type comes from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of holes (or electron holes). In contrast to an n-type semiconductor, a p-type semiconductor has a hole concentration greater than the electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0052] As shown in reference to FIGS. 2 and 3A, the source region 204a is located on the top surface 203 of the semiconductor substrate 202. In one or more embodiments, the source region 204a has a source and a source contact (not shown). The drain region 204b is located on the top surface 203 of the semiconductor substrate 202 opposite the source region 204a. In one or more embodiments, the drain region 204b has a drain and a drain contact (not shown).

[0053] In one or more embodiments, the source region 204a and / or the drain region 204b can be any suitable material known to those skilled in the art. In one or more embodiments, the source region 204a and / or the drain region 204b can have more than one layer. For example, the source region 204a and / or the drain region 204b can independently include three layers. In one or more embodiments, the source region 204a and the drain region 204b can independently include one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source region 204a and the drain region 204b can independently include a bottom layer of silicon with doped epi (e.g., SiGe, SiP, etc.), a second silicide layer that can contain nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third or top layer that can be a metal (e.g., but not limited to cobalt, tungsten, ruthenium, etc.).

[0054] In some embodiments, the source region 204a and the drain region 204b can be elevated source / drain regions formed by epitaxial growth.

[0055] In one or more embodiments, the source contact and / or the drain contact can be independently selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the source contact and / or the drain contact is formed by any suitable process known to those skilled in the art, including but not limited to ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to the technician.

[0056] In one or more embodiments, the channel 206 is located between the source region 204a and the drain region 204b.

[0057] In one or more embodiments, the dipole region 208 covers the channel 206 and contacts one or more of the channel 206, the source region 204a, and the drain region 204b. In one or more embodiments, the thickness of the dipole layer is less than about 50 angstroms.

[0058] In one or more embodiments, the dipole region 208 includes one or more of an interlayer dielectric (ILD) 210, a high-k dielectric material 212, and a dipole layer 214. In some embodiments, the dipole region 208 includes an interlayer dielectric (ILD) 210, a high-k dielectric material 212, and a dipole layer 214.

[0059] In one or more embodiments, an interlayer dielectric (ILD) 210 is deposited on the top surface 205 of the channel 206. In one or more embodiments, the interlayer dielectric 210 can be any suitable material known to those skilled in the art. For example, in one or more embodiments, the interlayer dielectric 210 includes a low-k dielectric. In one or more embodiments, the low-k dielectric is selected from one or more of silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon oxynitride, SiCONH, doped silicon, doped silicon oxide, doped silicon nitride, doped silicon oxynitride, spin-on dielectric, or growth of a diffused species. In one or more embodiments, the interlayer dielectric 210 includes silicon oxide. One or more deposition techniques known to one of ordinary skill in the field of microelectronic device manufacturing can be used to deposit the interlayer dielectric (ILD) 210. In one or more embodiments, those skilled in the art use a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or one of the other known insulating layer deposition techniques to deposit the interlayer dielectric (ILD) 210. In one or more embodiments, the interlayer dielectric (ILD) 210 can be formed by etching and forming an oxide on the surface.

[0060] In one or more embodiments, a high-k dielectric material 212 is deposited on the top surface 211 of the interlayer dielectric (ILD) 210. The high-k dielectric material can be any suitable high-k dielectric material known to those skilled in the art. In one or more embodiments, the high-k dielectric material 212 includes hafnium oxide or a high-k dielectric doped with lanthanum (La). In one or more embodiments, those skilled in the art use one of the deposition techniques to deposit the high-k dielectric material 212, such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or one of the other known insulating layer deposition techniques.

[0061] Typically, a high-k capping layer such as titanium nitride (TiN) is deposited on the top surface of the high-k dielectric material. However, in one or more embodiments, a deposition dipole layer 214 is deposited instead of the high-k dielectric material.

[0062] In one or more embodiments, the dipole layer 214 is deposited on the top surface 213 of the high-K dielectric material 212. In one or more embodiments, a person skilled in the art uses one of the deposition techniques to deposit the dipole layer 214, such as but not limited to ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art. In one or more specific embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD). In one or more embodiments, the dipole layer 214 is deposited by atomic layer deposition at a temperature of about 150 °C to about 500 °C.

[0063] In one or more embodiments, the channel 206 comprises a p-type material, and the dipole layer 214 comprises one or more of aluminum nitride (Al3N), titanium aluminum nitride (TiAlN), tantalum titanium nitride (TiTaN), titanium oxide (TiO), and tantalum oxide (TaO).

[0064] Referring to FIGS. 3A and 3B, in one or more embodiments, the dipole layer 214 comprises a p-dipole material film deposited by atomic layer deposition between about 150 °C and about 500 °C. In one or more embodiments, the p-dipole material film is deposited in alternating cycles of TiN and, for example, aluminum nitride (Al3N). In one or more embodiments, the aluminum content in the composite dipole layer 214 can be adjusted by adjusting the cycle ratio between TiN and TiAlN. Referring to FIG. 3B, in one or more embodiments, the dipole layer 214 on the PFET side 250 is removed by patterning.

[0065] In one or more embodiments, the channel 206 comprises a p-type material, and the dipole layer 214 comprises one or more of titanium aluminum nitride (TiAlN), tantalum titanium nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

[0066] In one or more embodiments, high-temperature thermal annealing is performed to drive the metal in the high-K material 212 to form n and p dipoles. The remaining TiN is directly used as a high-K capping layer.

[0067] Not bound by theory, it is believed that including one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC) in the dipole layer simplifies the existing integration process and reduces the integration cost. Additionally, it is believed that when one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), or titanium oxide (TiO) are embedded in the titanium nitride layer, oxidation can be reduced, which will potentially lower the required annealing temperature. Furthermore, the above-described composite dipole layer 214 method provides excellent control over the amount of one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC) that allows for the multi-voltage persistence of electronic components.

[0068] In one or more embodiments, an in-situ capping layer (such as titanium nitride (TiN) or titanium aluminum (TiAl)) can be used to control post-deposition film oxidation.

[0069] In one or more embodiments, a gate including one or more of a gate metal (not shown) or a gate contact (not shown) can optionally be formed or deposited on the exposed surface of the dipole region 208. The gate metal can be any material known to those skilled in the art. In one or more embodiments, the gate metal includes one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), aluminum (Al), or platinum (Pt). In one or more specific embodiments, the gate metal includes one or more metals selected from nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), iridium (Ir), aluminum (Al), or platinum (Pt). In other specific embodiments, the gate metal includes one or more metals selected from nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), or ruthenium (Ru). In one or more embodiments, the gate contact can be any suitable material known to those skilled in the art. In one or more embodiments, the gate contact is selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), aluminum (Al), or platinum (Pt).

[0070] In one or more embodiments, a capping layer may be deposited on the exposed surface of the dipole region 208. In one or more embodiments, the capping layer may include one or more of titanium nitride (TiN) or titanium aluminum (TiAl).

[0071] One or more embodiments relate to an electronic component that includes a source region having a source and a source contact, the source region being located on a top surface of a substrate; a drain region having a drain and a drain contact, the drain region being on the top surface of the substrate; a channel located between the source and the drain; a dipole region on a top surface of the channel, the dipole region including an interlayer dielectric, a high-k dielectric material, and a dipole layer including one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

[0072] Further embodiments of the present disclosure relate to a cluster tool 900 for forming the described logic / memory elements and methods, as shown in FIG. 4.

[0073] Cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are located within central transfer stations 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0074] Cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918 connected to the central transfer station, also referred to as processing stations. Each processing chamber provides an independent processing area isolated from adjacent processing stations. The processing chamber can be any suitable chamber, including but not limited to a pre-cleaning chamber, a buffer chamber, a transfer space, a wafer orienter / degassing chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, a rapid thermal processing (RTP) chamber, a plasma oxidation chamber, a plasma nitridation chamber, and an atomic layer deposition (ALD) chamber. The specific arrangement of the processing chambers and components can vary depending on the cluster tool and should not be considered as limiting the scope of the present disclosure.

[0075] In one or more embodiments, cluster tool 900 includes a silicon oxide (SiO2) chamber to deposit silicon oxide (SiO2). The silicon oxide (SiO2) deposition chamber of some embodiments includes an atomic layer deposition chamber, a plasma enhanced atomic layer deposition chamber, or a spatial atomic layer deposition chamber. In one or more embodiments, cluster tool 900 includes a pre-cleaning chamber connected to the central transfer station.

[0076] In the embodiment shown in FIG. 4, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a load chamber 954 and an unload chamber 956 on the front portion 951 of the factory interface 950. Although the load chamber 954 is shown on the left side and the unload chamber 956 is shown on the right side, those skilled in the art will understand that this is only representative of one possible configuration.

[0077] The sizes and shapes of the load chamber 954 and the unload chamber 956 can vary depending on, for example, the substrates processed in the cluster tool 900. In the embodiment shown, the sizes of the load chamber 954 and the unload chamber 956 are adjusted to hold a wafer cassette in which a plurality of wafers are located.

[0078] The robot 952 is within the factory interface 950 and can move between the load chamber 954 and the unload chamber 956. The robot 952 is capable of transferring wafers from a cassette in the load chamber 954 through the factory interface 950 to the load lock chamber 960. The robot 952 is also capable of transferring wafers from the load lock chamber 962 to a cassette in the unload chamber 956 through the factory interface 950. As those skilled in the art will understand, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the load chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock chamber 962 and the unload chamber 956.

[0079] The illustrated cluster tool 900 has a first portion 920 and a second portion 930. The first portion 920 is connected to the factory interface 950 through the load lock chambers 960, 962. The first portion 920 includes a central transfer station 921 in which at least one robot 925 is positioned. The robot 925 is also referred to as a robot wafer transfer mechanism. The central transfer station 921 is located centrally with respect to the load lock chambers 960, 962, the process chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 in some embodiments is a multi-arm robot capable of independently moving more than one wafer at a time. In one or more embodiments, the central transfer station 921 includes more than one automatic wafer transfer mechanism. The robot 925 in the central transfer station 921 is configured to move wafers between the chambers around the central transfer station 921. Each wafer is carried on a wafer transfer blade located at the distal end of the first robot mechanism.

[0080] After processing the wafer in the first section 920, the wafer can be transferred to the second section 930 through a pass-through chamber. For example, chambers 922, 924 can be one-way or two-way pass-through chambers. The pass-through chambers 922, 924 can be used to (for example) perform cryogenic cooling of the wafer before processing in the second section 930, or to perform wafer cooling or post-processing before returning to the first section 920.

[0081] The system controller 990 communicates with the first robot 925, the second robot 935, the plurality of first processing chambers 902, 904, 916, 918, and the plurality of second processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component that can control the processing chambers and the robots. For example, the system controller 990 can be a computer including a central processing unit, memory, suitable circuitry, and storage.

[0082] The processing can generally be stored as a software routine in the memory of the system controller 990, and when executed by the processor, the processing causes the processing chambers to perform the processing of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown) located remote from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. Thus, the processing can be implemented in software and can use a computer system, implemented in hardware (e.g., an application specific integrated circuit or other type of hardware implementation), or performed in a combination of software and hardware. When executed by the processor, the software routine transforms a general-purpose computer into a dedicated computer (controller) that controls the operation of the chambers to perform the processing.

[0083] In one or more embodiments, cluster tool 900 includes central transfer stations 921, 931, which include at least one robotic arm 925, 935 configured to move wafers; one or more of a rapid thermal processing (RTP) station, a decoupled plasma oxidation (DPO) or decoupled plasma nitridation (DPN) station connected to the central transfer station; an atomic layer deposition (ALD) station connected to the central transfer station; an optional pre-cleaning station connected to the central transfer station; and at least one controller connected to one or more of the central transfer station, the RTP station, the DPO station, the DPN station, the ALD station, or the optional pre-cleaning station. In one or more embodiments, the at least one controller has at least one configuration selected from the following: a configuration for moving wafers between stations using a robotic arm; a configuration for causing a robotic arm to move between stations; a configuration for performing rapid thermal processing; a configuration for performing decoupled plasma processing; a configuration for controlling the flow of oxidation gas into the RTP station or the DPO station; a configuration for controlling the flow of nitridation gas into the RTP station or the DPN station; a configuration for depositing a silicon oxide film by atomic layer deposition; and a configuration for pre-cleaning wafers.

[0084] For ease of description, spatial relative terms, such as "beneath", "below", "lower", "above", "upper", etc., may be used herein to describe the relationship of one element or feature to another element, as shown in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "below" can include both an orientation of above and below. The element may be otherwise oriented (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0085] In the context of describing the materials and methods discussed herein (especially in the context of the appended claims), the use of the terms "a", "an", and "the" and similar referents should be construed to cover both the singular and the plural, unless otherwise specified herein or clearly contradicted by the context. Unless otherwise indicated herein, the recitation of numerical ranges herein is merely intended to be a shorthand method of referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were recited herein individually. Unless otherwise indicated herein or clearly contradicted by the context, all methods described herein can be performed in any suitable order. Unless otherwise required, the use of any and all examples or exemplary language (e.g., "such as") provided herein is merely intended to better illustrate the materials and methods and is not a limitation on the scope. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0086] Throughout the specification, references to "one embodiment", "certain embodiments", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosed invention. Thus, the appearances of phrases such as "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in an embodiment" throughout the specification are not necessarily referring to the same embodiment disclosed herein. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0087] Although the present invention has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and elements of the present invention without departing from the spirit and scope of the present invention. Accordingly, it is intended that the present invention cover modifications and variations within the scope of the appended claims and their equivalents.

[0088] 100: Method 102: Operation 104: Operation 106: Operation 108: Operation 200: Electronic Component 203: Top Surface 202: Semiconductor Substrate 204a: Source Region 204b: Drain region 208: Dipole region 206: Channel 210: Interlayer dielectric (ILD) 212: High-K dielectric material 214: Dipole layer 205: Top surface 211: Top surface 213: Top surface 250: PFET side 208: Dipole region 900: Cluster tool 921, 931: Central transfer station 925, 935: Robot arm 902, 904, 906, 908, 910, 912, 914, 916, 918: Processing chamber 950: Factory interface 951: Front part 954: Load chamber 956: Unload chamber 952: Robot arm 960, 962: Loading lock chamber 920: First part 930: Second part 922, 924: Buffer chamber 990: System controller

[0089] Domestic registration information (Please note in the order of registration institution, date, number) None Overseas registration information (Please note in the order of registration country, institution, date, number) None

Claims

1. A method for manufacturing a p-type FET, the method comprising the steps of: depositing an interlayer dielectric on a top surface of a channel located between a source and a drain on a substrate; depositing a high-k dielectric material on the interlayer dielectric; depositing a p-type dipole layer on the high-k dielectric material, the p-type dipole layer comprising one or more of aluminum nitride, titanium oxide (TiO), and tantalum oxide (TaO); depositing a capping layer in situ, the capping layer comprising one or more of titanium nitride and titanium aluminum; and performing a thermal annealing.

2. The method according to claim 1, wherein the p-type dipole layer comprises aluminum nitride and has a thickness of less than about 50 angstroms (Å).

3. The method according to claim 1 further includes depositing a gate metal on a p-type dipole region, wherein the p-type dipole region includes the interlayer dielectric, the high-k dielectric material, and the p-type dipole layer.

4. The method according to claim 3, wherein the gate metal comprises one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), aluminum (Al), and platinum (Pt).

5. The method according to claim 1, wherein the source and the drain independently comprise one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), and zirconium (Zr).

6. The method according to claim 1, wherein the interlayer dielectric comprises a low-k dielectric.

7. The method according to claim 6, wherein the low-k dielectric is selected from one or more of silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, doped silicon, doped silicon oxide, and spin-coated dielectrics.

8. The method according to claim 1, wherein the high-k dielectric material comprises one or more of hafnium oxide and lanthanum (La) doped high-k dielectrics.

9. The method according to claim 1, wherein the p-type dipole layer is formed by exposing a substrate to alternating cycles of ammonia (NH3) and a p-type dipole precursor at a temperature ranging from about 150°C to about 500°C, wherein the p-type dipole precursor includes one or more of titanium halide, aluminum amine, aluminum nitride, tantalum nitride, triethylaluminum, trimethylaluminum, tri-tert-butylaluminum, tantalum halide, titanium organometallic precursor, and tantalum organometallic precursor.

10. A non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the following operations: depositing an interlayer dielectric on a top surface of a channel located between a source and a drain on a substrate; depositing a high-k dielectric material on the interlayer dielectric; depositing a p-type dipole layer on the high-k dielectric material, the p-type dipole layer comprising one or more of aluminum nitride, titanium oxide (TiO), and tantalum oxide (TaO), wherein the p-type dipole layer is formed by exposing the substrate to alternating cycles of ammonia (NH3) and a p-type dipole precursor at a temperature in the range of about 150°C to about 500°C; in situ depositing a capping layer comprising one or more of titanium nitride and titanium aluminum; and performing a thermal annealing.

11. The non-transitory computer-readable medium according to claim 10, including instructions that, when executed by a controller of a processing chamber, cause the processing chamber to further perform the following operations: depositing a gate metal on a p-type dipole region, wherein the p-type dipole region includes the interlayer dielectric, the high-k dielectric material, and the p-type dipole layer.

12. A method of manufacturing a p-type FET, the method comprising the steps of: depositing an interlayer dielectric on a top surface of a channel located between a source and a drain on a substrate; depositing a high-k dielectric material on the interlayer dielectric; depositing a p-type dipole layer on the high-k dielectric material by alternating cycles of exposing the substrate to ammonia (NH3) and a p-type dipole precursor at a temperature in the range of about 150°C to about 500°C, the p-type dipole precursor comprising one or more of aluminum nitride, aluminumamine, tantalum nitride, triethylaluminum, tantalum halide, and tantalum organometallic precursors, the p-type dipole layer comprising one or more of aluminum nitride, titanium oxide (TiO), and tantalum oxide (TaO); and in situ depositing a capping layer comprising one or more of titanium nitride and titanium aluminum.

13. The method according to claim 12, wherein the dipole layer has a thickness of less than about 50 angstroms (Å).

14. The method according to claim 12 further includes depositing a gate metal on a dipole region, wherein the dipole region includes the interlayer dielectric, the high-k dielectric material, and the dipole layer.

15. The method according to claim 12, wherein the interlayer dielectric comprises a low-k dielectric.

16. The method according to claim 12, wherein the high-k dielectric material comprises one or more of hafnium oxide and lanthanum (La) doped high-k dielectrics.

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