NAND flash memory and manufacturing method thereof

Abstract

This invention provides a NAND flash memory capable of reducing capacitive coupling between adjacent memory cells and a method for manufacturing the same. The NAND flash memory of this invention includes: an active region extending along the bit line direction within a silicon substrate; a trench isolation region defining the active region; a charge storage layer formed on the active region corresponding to each memory cell, and having a SiN layer sandwiched between insulating layers stacked thereon; a first control gate formed on the charge storage layer corresponding to each memory cell; and a second control gate extending along the word line direction on the first control gate. The second control gate is electrically connected to a plurality of first control gates in the corresponding column direction, and the trench isolation region is aligned with the sidewalls of the first control gates and the charge storage layer.

Description

[Technical Field]

[0001] The present invention relates to a non-volatile semiconductor memory device, and more particularly to a two-dimensional (2D) NAND flash memory. [Previous Technology]

[0002] The cell structure of NAND flash memory employs a floating gate structure. The floating gate, for example, contains polysilicon and has excellent charge retention characteristics. In addition, a highly reliable NAND flash memory that suppresses the effects caused by floating gate coupling between memory cells has also been disclosed (e.g., Japanese Patent Application Publication No. 2017-097927).

[0003] In existing FG-type two-dimensional NAND flash memory, due to size reduction, the coupling effect of parasitic capacitance between the floating gates of adjacent memory cells or between the floating gate and the control gate increases. For example, the charge of the floating gates of adjacent memory cells can sometimes cause changes in the threshold (Vth) of the programmed memory cells. As a result, there are problems such as an increased threshold distribution of memory cells and reduced reliability of NAND flash memory.

[0004] The purpose of this invention is to solve the existing problems and provide a NAND flash memory that can reduce capacitive coupling between adjacent storage memory cells and a method for manufacturing the same. [Summary of the Invention]

[0005] The NAND flash memory of the present invention includes: an active region formed extending along a bit line direction within a semiconductor substrate; a trench isolation region for defining the active region; a charge storage layer formed on the active region corresponding to each memory cell and including a nitride layer sandwiched between insulating layers; a first conductive layer formed on the charge storage layer corresponding to each memory cell; and a second conductive layer formed on the first conductive layer extending along a word line direction, the second conductive layer being electrically connected to a plurality of first conductive layers in a corresponding column direction, the trench isolation region being aligned with the sidewalls of the first conductive layer and the charge storage layer.

[0006] In one embodiment, the charge storage layer comprises an oxide-nitride-oxide (ONO) structure, or a stacked structure comprising multiple insulating films other than oxides between the silicon substrate and the nitride layer, or a stacked structure comprising multiple insulating films other than oxides between the nitride and the first conductive layer. In one embodiment, the first conductive layer comprises a polycrystalline silicon layer, the semiconductor substrate comprises a silicon region, and the charge storage layer comprises a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In one embodiment, the trench isolation region is formed in a self-aligned manner during etching of the first conductive layer, the charge storage layer, and the semiconductor substrate. In one embodiment, the peripheral region of the NAND flash memory comprises a gate insulating film and a gate material separate from the charge storage layer and the first conductive layer.

[0007] The method for manufacturing a NAND flash memory according to the present invention includes: forming a stack of a charge storage layer and a first conductive layer comprising a nitride layer sandwiched between insulating layers on a semiconductor substrate; simultaneously etching the first conductive layer, the charge storage layer and the semiconductor substrate; patterning the first conductive layer and the charge storage layer along the bit line direction; and forming a trench defining an active region on the semiconductor substrate; filling the trench with an insulating material; conformally forming a second conductive layer on the semiconductor substrate comprising the first conductive layer; simultaneously etching the second conductive layer, the first conductive layer and the charge storage layer; patterning the second conductive layer, the first conductive layer and the charge storage layer along the word line direction; and forming a source / drain doped region in the active region after removing the second conductive layer, the first conductive layer and the charge storage layer.

[0008] In one embodiment, the manufacturing method further includes: forming a mask pattern covering the cell array region, removing the charge accumulation layer and the first conductive layer on the peripheral region; and forming the gate insulating film and the gate material on the peripheral region, which are separate from the charge accumulation layer and the first conductive layer. In one embodiment, the manufacturing method further includes: conformally forming the gate insulating film and the gate material on a semiconductor substrate; and planarizing the gate insulating film and the gate material until the first conductive layer on the cell array region is exposed.

[0009] According to the present invention, a charge storage layer comprising a nitride layer is formed for each memory cell. Therefore, compared with FG-type memory cells, the capacitive coupling between adjacent memory cells can be reduced, and the threshold distribution of the memory cells can be narrowed. In addition, by using a trench isolation region that defines the active region to align with the charge storage layer and the first conductive layer, the capacitive coupling between adjacent memory cells can be reduced while achieving high integration of the cell array.

Implementation Method

[0011] The two-dimensional NAND flash memory of the present invention uses silicon nitride (SiN) as a charge storage layer. For example, a SONOS-type (Si / oxide / nitride / oxide / Si) charge storage layer is used to achieve narrowing of the threshold distribution (Vth) of the memory cell. Furthermore, the NAND flash memory of the present invention is used as a storage medium in various semiconductor devices (e.g., microcontrollers, microprocessors, logic, etc., in which such flash memory is embedded).

[0012] Figure 1 shows a cross-sectional view of the cell array of a conventional two-dimensional NAND flash memory in the direction of intersection with the NAND string, i.e., the word line direction. As shown in Figure 1, the conventional NAND flash memory 10 forms active regions 30 extending along the bit line direction on a P-type semiconductor substrate or a P-type well 20, wherein each active region 30 is isolated by a trench 40.

[0013] The active region 30 provides a channel region or an N-type source / drain (S / D) diffusion region for the memory cell. On the active region 30, a patterned floating gate 60 corresponding to each memory cell is formed across a gate oxide film (or tunneling oxide film) 50. A control gate 70 extending along the word line direction is formed on the floating gate 60. The floating gate 60, for example, comprises doped conductive polysilicon, and the control gate 70, for example, comprises conductive polysilicon and a metal material such as tungsten. The floating gate 60 is capacitively coupled to the control gate 70 via an upper dielectric layer.

[0014] When the memory cell is programmed, the charge tunneling through the gate oxide film 50 in the channel region of the active region 30 is stored in the floating gate 60. When the memory cell is erased, the charge stored in the floating gate 60 tunnels through the gate oxide film 50 and is released to the channel region.

[0015] As the manufacturing process shrinks, the distance between the floating gates 60 of adjacent memory cells becomes smaller, and the capacitive coupling between adjacent floating gates 60 becomes larger. For example, the charge accumulated in the floating gates 60 of the programmed memory cells will affect the threshold of adjacent memory cells.

[0016] Figures 2A and 2B are diagrams of a two-dimensional NAND flash memory according to an embodiment of the present invention. In the NAND flash memory 100 of this embodiment, a charge storage layer 110, in place of a floating gate 60, is formed on the active region 30, with multiple insulating layers sandwiching a SiN layer in between. The patterned charge storage layer is formed on the active region 30 of each memory cell. The charge storage layer 110 may have an ONO structure of oxide / nitride / oxide, or multiple insulating films may be stacked between the silicon substrate and the nitride layer instead of a single layer of oxide. Alternatively, multiple insulating films may be stacked between the nitride and the gate instead of a single layer of oxide. A first control gate (CG1) 120 is formed on the charge storage layer 110 and is patterned to correspond to the charge storage layer 110. The first control gate 120 may contain, for example, doped conductive polysilicon, or multiple low-resistance materials (e.g., TaN) and other metal layers may be stacked. A patterned second control gate (CG2) 130 extending along the character line direction (column direction) is formed on the first control gate 120. The second control gate 130 is electrically connected to the first control gate 120. Ideally, the second control gate 130 has low resistance and may contain a metallic material such as Al or Cu. Furthermore, the first control gate 120 may contain the same or different material as the second control gate 130.

[0017] As described above, the charge storage layer 110 has, for example, an ONO structure of oxide / nitride / oxide, and the ONO structure together forms a SONOS structure between the silicon substrate (or silicon well) and the first control gate 120 containing polysilicon. During programming, the charge storage layer 110 stores the charge obtained from Fowler-Nordheim (FN) tunneling of the oxide through the channel region at the interface of the nitride layer. During erasing, the charge stored in the charge storage layer 110 is released to the channel region through FN tunneling of the oxide layer.

[0018] In this embodiment, the thickness of the nitride layer (SiN layer) of the charge storage layer 110 is relatively smaller than the thickness of the floating gate of the FG structure, and the nitride layer is an insulating film. Therefore, compared with the FG structure, the capacitive coupling between adjacent memory cells can be reduced, resulting in a narrower threshold distribution of the memory cells. Furthermore, when the nitride layer of the charge storage layer 110 is continuously formed along the word line direction (without being separated for each memory cell), if electrons held in the nitride layer are attracted to holes and move, or holes are attracted to electrons and move, there are problems such as changes in the threshold of the memory cells. However, by separating the charge storage layer according to each memory cell as in this embodiment, the aforementioned problems can be eliminated.

[0019] Next, the fabrication process of the cell array region of the NAND flash memory in this embodiment will be described with reference to FIGS. 3A to 5B. As shown in FIG. 3A, a charge storage layer 210 with a three-layer structure is formed on the surface of a P-type silicon substrate or a P-type well 200 (hereinafter referred to as substrate for convenience) by means of a chemical vapor deposition (CVD), such as including an oxide film such as SiO2, a nitride film such as Si3N4, and an oxide film such as SiO2. In addition, a first control gate 220 made of, for example, polycrystalline silicon is formed on the charge storage layer 210.

[0020] Next, as shown in FIG3B, a masking material 230 for resist can be formed. Next, the masking material 230 is patterned by a photolithography process, as shown in FIG3C, to form a masking pattern M1 that is spaced at a certain interval and extends along the bit line direction.

[0021] Next, as shown in FIG4A, through the mask pattern M1, the exposed first control gate 220, charge storage layer 210 and substrate 200 are simultaneously anisotropically etched to form a patterned stack of charge storage layer 210 and first control gate 220 on substrate 200, and at the same time, a groove 240 for defining active region 202 is formed in substrate 200. FIG5A is a plan view of the substrate when the first control gate 220, charge storage layer 210 and substrate 200 are etched through mask pattern M1, and FIG4A corresponds to the BB line cross section of FIG5A.

[0022] The stack of charge storage layer 210 and first control gate 220 extends along the bit line direction, and the trench 240 is self-aligned with the sidewalls of the stack of charge storage layer 210 and first control gate 220. Therefore, the trench 240 is formed with good precision between the stack of charge storage layer 210 and first control gate 220 without positional error. In addition, since the charge storage layer 210 is covered by the first control gate 220, it is protected from etching.

[0023] Next, as shown in FIG4B, an insulating film 250 is conformally formed on the substrate 200 including the trench 240, and then the insulating film 250 is etched to the vicinity of the surface of the substrate 200 so that the insulator 250A is retained in the trench 240. At this time, the mask pattern M1 protects the first control gate 220 from etching.

[0024] Next, as shown in FIG4C, the trench insulator 250A is planarized by surface polishing to expose the surface of the masking pattern M1. Next, as shown in FIG4D, the masking pattern M1 is removed, and the trench insulator 250A is surface polished so that the height of the trench insulator 250A is approximately the same as the height of the first control gate 220. Thus, the active region 202 extending along the bit line direction is isolated by the trench insulator 250A, and a stack of charge accumulation layer 210 and first control gate 220 is formed on the active region 202. FIG5B is a plan view of the substrate when the height of the first control gate 220 and the trench insulator 250A is approximately the same, and FIG4D corresponds to the CC line cross-section of FIG5B. In addition, in some embodiments, the process shown in FIG4D may not be required.

[0025] Next, the fabrication process of the cell array region and peripheral region in the flash memory of this embodiment will be described with reference to FIGS. 6A-6F and 7A-7C. As shown in FIG. 6A, a charge storage layer 310 and a first control gate (CG1) 320 are conformally formed on a P-type silicon substrate 300, and then a mask pattern M2 covering the cell array region is formed. Next, as shown in FIG. 6B, the mask pattern M2 is used as an etching mask, and the charge storage layer 310 and the first control gate 320 on the peripheral region are removed by etching.

[0026] Next, after removing the mask pattern M2, as shown in FIG6C, a gate insulating film 330 is conformally formed on the substrate 200 including the peripheral region. The gate insulating film 330 is, for example, a silicon oxide film. Page buffers / readout amplifiers or decoders, etc., are formed in the peripheral region. These circuits include transistors driven by high voltage or transistors driven by low voltage. Therefore, the gate insulating film 330 is formed in various thicknesses, such as thick films suitable for high voltage and thin films suitable for low voltage. After the gate insulating film 330 is formed, a gate material 340 for the transistors in the peripheral region is conformally formed on the substrate 200. The gate material 340 is, for example, polycrystalline silicon.

[0027] Next, the gate insulating film 330 and the gate material 340 are etched back or planarized, as shown in FIG6D, so that the first control gate 320 is exposed on the cell array region and the gate material 340 is exposed on the peripheral region. Through these processes, the charge accumulation layer 310 and the first control gate 320 of the cell array region can be formed separately from the gate insulating film 330 and the gate material 340 of the peripheral region. It should be noted that in the existing FG type flash memory, the floating gate of the cell array region is connected to the floating gate of the peripheral region (the floating gate is electrically connected to the control gate and serves as the gate of the transistor).

[0028] In the aforementioned process, after removing the masking pattern M2, a gate insulating film 330 and a gate material 340 are formed. However, this is only one example, and the masking pattern M2 may also be retained. As shown in FIG6E, a gate insulating film 330A and a gate material 340A are conformally formed on a substrate including the masking pattern M2. In this case, when the gate insulating film 330A in the peripheral region is a high-voltage-resistant thick insulating film, the height of the masking pattern M2 in the cell array region is set to be approximately the same as the height of the gate material 340A. In addition, the gate insulating film 330 at the boundary between the cell array region and the peripheral region is set to a high-voltage-resistant thick insulating film.

[0029] Subsequently, as shown in FIG6F, after planarization is performed to expose the masking pattern M2 of the cell array region and the gate material 340A of the peripheral region, the masking pattern M2 is removed. Through these processes, the charge storage layer 310 and the first control gate 320 of the cell array region can be formed separately from the gate insulating film 330A and the gate material 340A of the peripheral region.

[0030] After forming the first control gate 320 of the unit array region and the gate material 340 of the peripheral region, a mask pattern M3 as shown in FIG7A is formed. The gate material, gate insulating film and silicon of the unit array region and the peripheral region are simultaneously etched to form trenches 350 and 352 on the substrate 300. The trench 350 of the unit array region may have different sizes and / or different depths than the trench 352 of the peripheral region.

[0031] After removing the masking pattern M3, as shown in Figure 7B, insulating material 360 is filled into grooves 350 and 352. The insulating material 360 is, for example, a silicon oxide film. Subsequently, the insulating material 360 is planarized to expose the surfaces of the first control gate 320 and the gate material 340.

[0032] Next, as shown in FIG7B, a conductive material 370 serving as a precursor for the second control gate is conformally formed on the substrate 300 including the first control gate 320 and the gate material 340. The conductive material 370 is not particularly limited and may be, for example, a metallic material such as Al or Cu. The conductive material 370 is electrically connected to the first control gate 320 and the gate material 340. Alternatively, a silicon metal may be formed between the conductive material 370 and the first control gate 320 and the gate material 340.

[0033] Next, as shown in FIG7C, the conductive material 370 in the region where the charge storage layer 310 and the first control gate 320 are formed in the cell array is patterned in a manner extending along the word line direction using a mask pattern (not shown) to form a second control gate 370A. The second control gate 370A is electrically connected to a plurality of first control gates 320 in the corresponding column direction and provides word lines. In addition, by patterning the conductive material 370, the first control gate 320 and the charge storage layer 310 beneath it are simultaneously etched to expose the active region. On the other hand, by patterning the conductive material 370, a wiring layer 370B electrically connected to the gate material 340 is formed on the peripheral region.

[0034] After patterning the second control gate 370A, ion implantation is performed in the exposed active region 202 to form N-type dopant for the source / drain. Moreover, similar to existing NAND flash memory, bit lines BL and source lines SL are formed in the cell array region.

[0035] Figure 8 is a cross-section of the bit line direction in the cell array region, that is, a cross-section of the direction orthogonal to line AA in Figure 2A. As shown in Figure 8, an N-well 410 is formed on the P-type silicon substrate 400, and a P-well 420 is formed within the N-well 410. An N-type diffusion region 430 for the source / drain of the memory cell, bit line-side select transistor, and source line-side select transistor for constituting the NAND string is formed on the surface of the P-well 420. A charge accumulation layer 440 is formed on the P-well 420, and a first control gate 450 and a second control gate 460 are formed on the charge accumulation layer 440. The diffusion region 430A of the bit line-side select transistor is electrically connected to the bit line BL via contact CT1, and the diffusion region 430B of the source line-side select transistor is electrically connected to the source line SL via contact CT2.

[0036] The two-dimensional NAND flash memory of this embodiment has an insulator stack (charge accumulation layer) between silicon and the control gate, which includes an insulating layer such as a SiN layer for accumulating charge. The control gate consists of two layers: a first control gate CG1 formed on the insulator stack and a second control gate CG2 formed on the first control gate CG1. The insulator stack and the first control gate CG1 are sequentially deposited on silicon, and the first control gate CG1, the insulator stack, and silicon are simultaneously etched to fill trenches with insulating material, thereby forming a shallow trench isolation region in a self-aligned manner. After planarizing the trench-filled insulating material, the second control gate CG2 is deposited on the first control gate CG1, so that the first control gate CG1 and the second control gate CG2 are electrically connected to each other.

[0037] The second control gate, the first control gate, and the charge accumulation layer are simultaneously etched to form multiple rectangular character lines WL. In this way, the charge accumulation layer is isolated from adjacent cells. The ends of the character lines in the cell array region are connected to the column decoder, which applies a bias voltage for read / write (programming) / erase operations to the character lines WL.

[0038] In this embodiment, a charge storage layer consisting of a three-layer structure of oxide / nitride / oxide is shown, but it is not limited to this and may also be a charge storage layer containing four or more nitrides. In addition, the memory cell may be a single-level cell (SLC) type that stores 1 bit (binary data) or a type that stores multiple bits.

[0039] The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to a specific embodiment and can be modified and altered in various ways within the scope of the spirit of the invention as described in the claims. [Simplified Explanation of the Diagram]

[0010] Figure 1 is a schematic cross-sectional view of the cell array region of a conventional two-dimensional NAND flash memory in a direction orthogonal to the bit lines. Figures 2A and 2B are diagrams of a two-dimensional NAND flash memory according to an embodiment of the present invention, where Figure 2A is a plan view of a portion of the cell array, and Figure 2B is a schematic cross-sectional view along line AA of Figure 2A. Figures 3A to 3C are schematic diagrams of the fabrication process of the cell array region of the NAND flash memory according to an embodiment of the present invention. Figures 4A to 4D are schematic diagrams of the fabrication process of the cell array region of the NAND flash memory according to an embodiment of the present invention. Figure 5A is a plan view of the substrate when the first control gate, charge storage layer, and substrate are etched through a mask pattern, and Figure 5B is a plan view of the substrate when the height of the first control gate and the trench insulator are the same. Figures 6A to 6D are schematic diagrams showing the fabrication process of the cell array region and the peripheral region of the NAND flash memory according to this embodiment. Figures 6E and 6F are schematic diagrams showing another fabrication process of the cell array region and the peripheral region of the NAND flash memory according to this embodiment. Figures 7A to 7C are schematic diagrams showing the manufacturing process of the cell array region and peripheral region of the NAND flash memory in this embodiment. Figure 8 is a schematic cross-sectional view of the cell array region of the NAND flash memory in this embodiment along the bit line direction.

Claims

1. A reverse-intercept type flash memory, comprising: an active region extending along a bit line direction within a semiconductor substrate; a trench isolation region defining the active region; a charge storage layer formed on the semiconductor substrate of the active region for each memory cell, and comprising a nitride layer sandwiched between insulating layers; a first conductive layer formed on the charge storage layer for each memory cell; a second conductive layer extending along a word line direction on the first conductive layer, the second conductive layer being electrically connected to a plurality of first conductive layers in a corresponding column direction, the trench isolation region being aligned with the sidewalls of the first conductive layer and the charge storage layer, and the height of the trench insulator of the trench isolation region being the same as the height of the first conductive layer; and a peripheral region including a gate insulating film and a gate material, wherein the gate insulating film is formed on the semiconductor substrate, and the gate material is formed on the gate insulating film, wherein the gate insulating film and the gate material are separated from the charge storage layer and the first conductive layer through the trench insulator. The height of the slot insulator is the same as the height of the gate material, and the thickness of the gate material is different from the thickness of the first conductive layer.

2. The reverse-type flash memory as described in claim 1, wherein, The charge storage layer includes an oxide-nitride-oxide structure, or a structure in which multiple insulating films other than oxides are stacked between the silicon substrate and the nitride layer, or a structure in which multiple insulating films other than oxides are stacked between the nitride and the first conductive layer.

3. The reverse-type flash memory as described in claim 2, wherein, The first conductive layer includes a polycrystalline silicon layer, the semiconductor substrate includes a silicon region, and the charge storage layer includes a silicon-oxide-nitride-oxide-silicon structure.

4. The reverse-type flash memory as described in claim 1, wherein, The trench isolation region is formed in a self-aligned manner during the etching of the first conductive layer, the charge storage layer, and the semiconductor substrate.

5. A method for manufacturing an inverse-mode flash memory, comprising: forming a stack of a charge storage layer and a first conductive layer sandwiched between an insulating layer on a semiconductor substrate; forming a mask pattern covering a cell array region, and removing the charge storage layer and the first conductive layer on a peripheral region; forming a stacked gate insulating film and a gate material on the peripheral region, separated from the charge storage layer and the first conductive layer by a filling insulating material, wherein the thickness of the gate material is different from the thickness of the first conductive layer; simultaneously etching the first conductive layer, the charge storage layer, the gate insulating film, the gate material, and the semiconductor substrate, patterning the first conductive layer and the charge storage layer along a bit line direction, and forming a trench defining an active region on the semiconductor substrate; filling the trench with an insulating material to form a trench insulator, wherein the height of the trench insulator is the same as the height of the first conductive layer and the height of the gate material; and conformally forming a second conductive layer on the semiconductor substrate containing the first conductive layer. The second conductive layer, the first conductive layer, and the charge storage layer are simultaneously etched, and the second conductive layer, the first conductive layer, and the charge storage layer are patterned along the character line direction; and a source / drain doped region is formed in the active region after the second conductive layer, the first conductive layer, and the charge storage layer are removed.

6. The manufacturing method as claimed in claim 5, further comprising: conformally forming the gate insulating film and the gate material on the semiconductor substrate; and planarizing the gate insulating film and the gate material until the first conductive layer on the cell array region is exposed.

7. The manufacturing method as described in claim 5, wherein, The charge storage layer includes an oxide-nitride-oxide structure of oxide / nitride / oxide, or a structure in which multiple insulating films other than oxides are stacked between the silicon substrate and the nitride layer, or a structure in which multiple insulating films other than oxides are stacked between the nitride and the first conductive layer.

8. The manufacturing method as described in claim 5, wherein, The first conductive layer includes a polycrystalline silicon layer, the semiconductor substrate includes a silicon region, and the charge storage layer includes a silicon-oxide-nitride-oxide-silicon structure.

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