Increased mut coupling efficiency and bandwidth via edge groove, virtual pivots, and free boundaries

Abstract

This invention presents a method for improving the electromechanical coupling coefficient and bandwidth of microfabricated ultrasonic sensors or MUTs, and a method for manufacturing such MUTs improved by the presented method.

Description

Technical Field

[0001] The present invention presents a method for improving the electromechanical coupling coefficient and bandwidth of a micromachined ultrasonic transducer or MUT, and a manufacturing method of such MUTs improved by the presented methods. Prior Art

[0002] A micromachined ultrasonic transducer (MUT) is a device that converts energy between the electrical domain and the acoustic domain. They generally present two variants: capacitive MUT (cMUT) and piezoelectric MUT (pMUT). cMUT utilizes the capacitance between two plates for electromechanical conversion, while pMUT utilizes the piezoelectric property of a piezoelectric film to accomplish electromechanical conversion. Summary of the Invention

[0003] Examples of a conventional circular diaphragm pMUT and cMUT are illustrated in FIGS. 1a - 1b and FIGS. 2a - 2b, respectively. The diaphragm 101 is formed by a substrate 100 - 1 or a device layer 100 - 2. In the case of the pMUT, a piezoelectric stack composed of a first electrode 200 (also referred to as "bottom electrode", "M1", "metal 1", "first metal layer" or "conductor"), a piezoelectric layer 201, and a second electrode 202 (also referred to as "top electrode", "M2", "metal 2", "second metal layer" or "conductor") is placed on or near the diaphragm 101 on top of the dielectric layer 102. In the case of the cMUT, the device layer 100 - 2 is attached to the dielectric layer 102 on top of a handle substrate 103. It is assumed that the diaphragm 101 is conductive, and the bottom electrode 200 is placed below the diaphragm 101 to form a capacitor between the diaphragm 101 and the bottom electrode 200.

[0004] In some embodiments, the dielectric layer 102 may be referred to as an "insulating layer". In some embodiments, the handle substrate 103 may be referred to as a "handle layer".

[0005] Although many metrics describe a MUT, the two most important metrics are the effective electromechanical coupling (keff2) of the MUT and its electrical and mechanical quality factors (Qe and Qm, respectively). The keff2 of a device determines how effectively it converts electrical energy into acoustic energy. Thus, keff2 is a key driver of the power specifications of products using that MUT. Keff2 typically varies between 0 and 1, with 1 being better. The mechanical and electrical quality factors drive the bandwidth of the sensor (the frequency at which the sensor is most effective). For most applications (especially imaging), a larger bandwidth is better, meaning a lower quality factor is better.

[0006] Advantageously, the electromechanical coupling and the quality factor are related: This means that maximizing keff2 will maximize both the conversion efficiency and minimize the quality factor of the system.

[0007] Although there are multiple ways to affect keff2, the present invention will focus on the clamping conditions of the MUT diaphragm. From [2], for a circular pMUT oscillating in its nth axisymmetric mode, we have: where k312 is the coupling coefficient of the material (material constant), λ0n is the natural frequency parameter of the nth mode (highly dependent on the edge clamping conditions), J0 is the Bessel function of the first kind of order 0, and Cn is a constant depending on the specific pMUT design (electrode coupling constant, flexural rigidity, and ratio of electrode area to diaphragm area; see [2] for the complete equation). For a given k312 coupling coefficient and design constant Cn, keff,n2 can be maximized by driving λ0n towards 0.

[0008] The natural frequency parameter is highly dependent on the boundary conditions under consideration, as shown in the comparison bar chart of Figure 3. Conventional MUT designs utilize clamped edges. The "free edge" in Figure 3 is equivalent to ideal piston motion and represents the best coupling. Between these two extreme cases, multiple edge conditions are considered to improve electromechanical coupling and bandwidth.

[0009] Although multiple factors affect k eff 2, intuitively, the enhanced coupling factor can be inversely related to the normalized volume displacement. For example, the comparison chart in Figure 4 shows the normalized displacement curves of three standard circular diaphragm MUTs: clamped edges (similar to Figures 1a to 1b and 2a to 2d), simply supported edges (i.e., edges that allow rotation but not displacement), and free edges clamped at the center. By integrating the surface area over the displacement, we can calculate the displacement volume of each MUT relative to an ideal piston:

[0010] Clamped edge = 31% of the piston displacement volume.

[0011] Simply supported edge MUT = 45% of the piston displacement volume.

[0012] Free edge MUT clamped at the center = 54% of the piston displacement volume.

[0013] Higher displacement volume indicates better coupling.

[0014] In one aspect, a micromachined ultrasonic transducer (MUT) is disclosed herein that includes: a diaphragm having a substantially free edge; one or more electrodes; and one or more anchors that clamp the diaphragm to a substrate at positions within, along, or both within and along the perimeter of the diaphragm. The diaphragm, the one or more electrodes, and the one or more anchors can have any shape. In some embodiments, the edges are free and the anchors reside entirely within the diaphragm. In some embodiments, the MUT is a pMUT that includes a piezoelectric film. In a further embodiment, the one or more electrodes are electrically coupled to the piezoelectric film. In a further embodiment, the piezoelectric film is positioned opposite the one or more anchors. In other embodiments, the piezoelectric film is positioned on the same side as the one or more anchors. In some embodiments, the piezoelectric film is between the one or more anchors and the diaphragm. In some embodiments, the diaphragm includes grooves. In some embodiments, the MUT includes a plurality of anchors, where a subset of the plurality of anchors is attached to one or more vertical cantilever shells. In some embodiments, the MUT includes a plurality of anchors, where a subset of the plurality of anchors is attached to one or more vertical cantilever shells, and where the diaphragm includes grooves. In some embodiments, the MUT is a cMUT. In a further embodiment, the one or more electrodes are electrically coupled to the diaphragm between gaps. In a further embodiment, the diaphragm includes grooves. In still a further embodiment, the MUT includes a plurality of anchors, where a subset of the plurality of anchors is attached to one or more vertical cantilever shells. In still a further embodiment, the MUT includes a plurality of anchors, where a subset of the plurality of anchors is attached to one or more vertical cantilever shells, and where the diaphragm includes grooves.

[0015] In another aspect, micromachined ultrasonic transducers (MUTs) are disclosed herein that include a clamped diaphragm that includes a vertical cantilever shell attached to an edge of the diaphragm. The diaphragm can have any shape. In some embodiments, the vertical cantilever shell forms a virtual pivot that substantially prevents out-of-plane motion but allows rotation of the diaphragm edge while imparting a counter-torque. In various embodiments, the vertical cantilever shell has a thickness between 0.1 µm and 50 µm, and where the vertical cantilever shell has a height that is between 1 and 100 times greater than its thickness. In still a further embodiment, the vertical cantilever shell is not continuous around the diaphragm edge but has regions that do not have a virtual pivot. In still a further embodiment, the MUT is multimode.

[0016] In another aspect, microfabricated ultrasonic transducers (MUTs) are disclosed herein, which include clamped diaphragms that include grooves. The clamped diaphragms can have any shape. In some embodiments, the MUT is a pMUT. In various embodiments, the grooves are within 20 diaphragm thicknesses of the diaphragm boundary, and wherein the grooves have a width of no greater than 10 diaphragm thicknesses, and wherein the grooves have a depth between 1% and 100% of the diaphragm thickness. In some embodiments, the grooves have a constant width. In other embodiments, the grooves have a variable width. In some embodiments, the grooves are interrupted at one or more locations to allow for electrical wiring. In some embodiments, the MUT is multimode. In some embodiments, the MUT is a cMUT. In various embodiments, the grooves are within 20 diaphragm thicknesses of the diaphragm boundary, and wherein the grooves have a width of no greater than 10 diaphragm thicknesses, and wherein the grooves have a depth between 1% and 100% of the diaphragm thickness. In some embodiments, the grooves have a constant width. In other embodiments, the grooves have a variable width. In some embodiments, the grooves are interrupted at one or more locations to allow for electrical wiring. In some embodiments, the MUT is multimode.

[0017] In yet another aspect, an array of MUTs configured for ultrasonic imaging is disclosed herein, wherein the array includes a plurality of such MUTs described herein. In some embodiments, each MUT of the plurality of such MUTs is a pMUT. In other embodiments, each MUT of the plurality of such MUTs is a cMUT. In some embodiments, each MUT of the plurality of such MUTs includes a vertical cantilever shell formed by multiple etchings.

[0018] In yet another aspect, a method of manufacturing the MUTs and MUT arrays described herein is disclosed.

[0019] In one aspect, microfabricated ultrasonic transducers (MUTs) are disclosed herein, which include: a piezoelectric stack including a substrate, an insulating layer, a top electrode, a piezoelectric layer, and a bottom electrode, wherein the piezoelectric stack has an edge portion and a central portion, wherein the piezoelectric stack has one or more grooves extending through at least the top electrode, the piezoelectric layer, the bottom electrode, and the insulating layer and into at least a portion of the substrate, and wherein the one or more grooves are disposed between the edge portion and the central portion of the piezoelectric stack; a base; one or more anchors that couple the central portion of the piezoelectric stack to the base such that the edge portions of the piezoelectric stack are free and the central portion of the piezoelectric stack is clamped to the base, the one or more anchors providing electrical coupling between the base and the piezoelectric stack; and a plurality of conductors including (i) a first conductor that electrically couples the top electrode of the piezoelectric stack to the base through a first via hole extending through the thickness of the piezoelectric stack; and (ii) a second conductor that electrically couples the bottom electrode of the piezoelectric stack to the base through a second via hole extending through the thickness of the piezoelectric stack, wherein the first via hole and the second via hole are disposed between the edge portion and the central portion of the piezoelectric stack. Brief Description of the Drawings

[0020] A better understanding of the features and advantages of the subject matter will be obtained from the following detailed description which refers to illustrative embodiments and the accompanying drawings, in which:

[0021] FIGS. 1a and 1b show a conventional circular diaphragm pMUT in the following forms respectively: (a) in a layout form, and (b) in a cross section.

[0022] FIGS. 2a and 2b show a conventional circular diaphragm cMUT in the following forms respectively: (a) in a layout form, and (b) in a cross section.

[0023] FIGS. 2c and 2d show a conventional circular diaphragm cMUT having a conductive portion at the top of the processing substrate instead of the bottom electrode in the cMUT of FIGS. 2a and 2b in the following forms respectively: (c) in a layout form, and (d) in a cross section. For the bottom electrode, the conductor 200 is replaced by a conductive or semiconductive processing layer 103.

[0024] FIG. 3 is a bar graph showing the fundamental mode natural frequency parameter λ01 varying according to boundary conditions. Interpreted from [2] from [1]. Blue indicates the most common MUT edge condition: clamped. Red indicates the boundary condition that [2] assumes to be "physically realizable".

[0025] Figure 4 shows a graph of the normalized displacement curves for different edge conditions of a circular diaphragm with radius a.

[0026] Figures 5a and 5b show an exemplary circular diaphragm pMUT with top-side grooves in the following forms respectively: (a) in a layout form, and (b) in a cross-section.

[0027] Figures 5c and 5d show an exemplary circular diaphragm pMUT with top-side grooves and using a silicon-on-insulator (SOI) wafer (including a buried oxide (BOX) layer 104 between the device layer 100-2 and the disposal layer 103) in the following forms respectively: (c) in a layout form, and (d) in a cross-section. This design includes edge grooves 300 and diaphragm edge 101a. The BOX layer 104 facilitates the cavity etching in the disposal layer 103.

[0028] Figures 6a and 6b show an exemplary circular diaphragm cMUT with top-side grooves in the following forms respectively: (a) in a layout form, and (b) in a cross-section.

[0029] Figures 6c and 6d show an exemplary circular diaphragm cMUT with top-side grooves and having a conductive portion at the top of the disposal substrate instead of the bottom electrode in the cMUT of Figures 6a and 6b in the following forms respectively: (c) in a layout form, and (d) in a cross-section. For the bottom electrode, the conductor 200 is replaced by a conductive or semiconductive disposal layer 103.

[0030] Figures 7a and 7b show an exemplary circular diaphragm pMUT with top-side virtual pivot etching in the following forms respectively: (a) in a layout form, and (b) in a cross-section.

[0031] Figures 7c and 7d show an exemplary circular diaphragm pMUT with top-side virtual pivot etching and using a silicon-on-insulator (SOI) wafer (including a buried oxide layer 104 between the device layer 100-2 and the disposal layer 103) in the following forms respectively: (c) in a layout form, and (d) in a cross-section. This design includes virtual pivot trenches 301a, diaphragm edge 101a, and cantilever shell 101b. The BOX layer 104 facilitates the cavity etching in the disposal layer 103.

[0032] Figures 8a and 8b show an exemplary circular diaphragm cMUT with top-side virtual pivot etching in the following forms respectively: (a) in a layout form, and (b) in a cross-section.

[0033] Figures 8c and 8d respectively show an exemplary circular diaphragm cMUT having top-side virtual pivot etching and having a conductive portion at the top of the disposed substrate in place of the bottom electrode in the cMUTs of FIGS. 8a and 8b: (c) in layout form, and (d) in cross-section. For the bottom electrode, the conductor is replaced by a conductive or semiconductive disposed layer 103. This design includes virtual pivot trenches 301a and 301b, diaphragm edges 101a and cantilever shells 101b.

[0034] Figures 9a through 9d respectively show the following exemplary variations on the edge trench: (a) arbitrary diaphragm shape; (b) multiple trenches; (c) trenches with variable width; and (d) a selected area without trenches. For simplicity, only the diaphragm edge (dashed line) and the trenches (solid line) are shown.

[0035] Figures 10a through 10d respectively show the following exemplary variations on the virtual pivot: (a) arbitrary diaphragm shape; (b) multiple virtual pivot trenches; (c) virtual pivot trenches with variable width; and (d) a selected area without virtual pivot trenches. For simplicity, only the diaphragm edge (dashed line) and the first virtual pivot trench etch and the second virtual pivot trench etch (solid lines, black and gray respectively) are shown.

[0036] Figures 11a and 11b respectively show an exemplary pMUT having a free edge and a clamped center, and with the piezoelectric stack opposite the anchor: (a) in layout form, and (b) in cross-section.

[0037] Figures 12a and 12b respectively show an exemplary pMUT having a free edge and a clamped center, and with the piezoelectric stack on the same side as the anchor: (a) in layout form, and (b) in cross-section.

[0038] Figures 13a and 13b respectively show an exemplary cMUT having a free edge and a clamped center and with the opposing electrode positioned between the substrate and the diaphragm (assumed to be conductive in this exemplary embodiment): (a) in layout form, and (b) in cross-section.

[0039] Figures 14a through 14d respectively show the following exemplary variations on a free edge having a fixed internal region and / or a fixed edge region: (a) an arbitrary diaphragm shape; (b) multiple anchor regions; (c) multiple anchor regions of arbitrary shape; and (d) a selected region having a fixed edge where the anchor overlaps the edge. For simplicity, only the diaphragm 101 and the anchor 105 are shown (the dashed lines are the dark gray interior).

[0040] Figures 15a and 15b respectively show an exemplary circular diaphragm pMUT having both an edge groove and a virtual pivot etch in the following forms: (a) in layout form, and (b) in cross-section.

[0041] Figures 15c and 15d respectively show an exemplary circular diaphragm pMUT having both an edge groove and a virtual pivot etch and using a silicon-on-insulator (SOI) wafer (including a buried oxide layer 104 between the device layer 100-2 and the disposal layer 103) in the following forms: (c) in layout form, and (d) in cross-section. This design includes an edge groove 300, a virtual pivot trench 301a, a diaphragm edge 101a, and a cantilever shell 101b. The BOX layer 104 facilitates the cavity etch in the disposal layer 103.

[0042] Figures 16a and 16b respectively show an exemplary circular diaphragm cMUT having both an edge groove and a virtual pivot etch in the following forms: (a) in layout form, and (b) in cross-section (the edge groove 300 is beige and the virtual pivot trench 301b is gray).

[0043] Figures 16c and 16d respectively show an exemplary circular diaphragm cMUT having both an edge groove and a virtual pivot etch and having a conductive portion at the top of the disposal substrate instead of a bottom electrode in the cMUT of Figures 16a and 16b in the following forms: (c) in layout form, and (d) in cross-section (the edge groove 300 is beige and the virtual pivot trench 301b is gray). For the bottom electrode, the conductor 200 is replaced by a conductive or semiconductive disposal substrate 103.

[0044] Figures 16e and 16f respectively show an exemplary circular diaphragm cMUT having both an edge groove and a virtual pivot etch and in which a gap defining the diaphragm is formed in the disposal substrate 103 (rather than in the device layer 100-2) in the following forms: (e) in layout form, and (f) in cross-section (the edge groove 300 is beige and the virtual pivot trench 301b is gray).

[0045] Figures 16g and 16h respectively show an exemplary circular diaphragm cMUT with edge grooves and virtual pivot etching and in which a gap between diaphragms is defined in the processing substrate 103 (rather than in the device layer 100-2): (g) in layout form, and (h) in cross-section (the edge groove 300 is beige and the virtual pivot channel 301b is gray).

[0046] Figures 17a and 17b respectively show an exemplary pMUT with a free edge and a clamped center, and with the piezoelectric stack opposite the anchor: (a) in layout form, and (b) in cross-section (for clarity, the virtual pivot channel 301b is not shown in the layout form).

[0047] Figures 18a and 18b respectively show an exemplary pMUT with a free edge and a clamped center, and with the piezoelectric stack on the same side as the anchor: (a) in layout form, and (b) in cross-section (for clarity, the virtual pivot channel 301b is not shown in the layout form).

[0048] Figures 19a and 19b respectively show an exemplary cMUT with a free edge and a clamped center and with the opposing electrodes positioned between the substrate and the diaphragm (assumed to be conductive in this exemplary embodiment): (a) in layout form, and (b) in cross-section (for clarity, the virtual pivot channel 301b is not shown in the layout form).

[0049] Figures 20a and 20b show an exemplary pMUT with a free edge and a clamped center and two side-by-side independent electrodes and a redistribution layer for contacting the top and bottom electrodes of the piezoelectric stack: (a) in layout form, and (b) in cross-section. Embodiments

[0050] Cross References This patent application claims the benefit of U.S. Provisional Application No. 62 / 899,602, filed on September 12, 2019, the entire content of which is incorporated herein by reference.

[0051] In some embodiments, microfabricated ultrasonic transducers (MUTs) are disclosed herein that include: a diaphragm having a substantially free edge; one or more electrodes; and one or more anchors that clamp the diaphragm to a substrate at a location within, along, or both within and along the perimeter of the diaphragm. The diaphragm, the one or more electrodes, and the one or more anchors can have any shape. In some embodiments, the edges are free and the anchors reside entirely within the diaphragm. In some embodiments, the MUT is a pMUT that includes a piezoelectric film. In a further embodiment, the one or more electrodes are electrically coupled to the piezoelectric film. In a further embodiment, the piezoelectric film is positioned opposite the one or more anchors. In other embodiments, the piezoelectric film is positioned on the same side as the one or more anchors. In some embodiments, the piezoelectric film is between the one or more anchors and the diaphragm. In some embodiments, the diaphragm includes grooves. In some embodiments, the MUT includes a plurality of anchors, where a subset of the plurality of anchors is attached to one or more vertical cantilever shells. In some embodiments, the MUT includes a plurality of anchors, where a subset of the plurality of anchors is attached to one or more vertical cantilever shells, and where the diaphragm includes grooves. In some embodiments, the MUT is a cMUT. In a further embodiment, the one or more electrodes are electrically coupled to the diaphragm between gaps. In a further embodiment, the diaphragm includes grooves. In yet a further embodiment, the MUT includes a plurality of anchors, where a subset of the plurality of anchors is attached to one or more vertical cantilever shells. In yet a further embodiment, the MUT includes a plurality of anchors, where a subset of the plurality of anchors is attached to one or more vertical cantilever shells, and where the diaphragm includes grooves.

[0052] In some embodiments, microfabricated ultrasonic transducers (MUTs) are disclosed herein that include a clamped diaphragm that includes a vertical cantilever shell attached to an edge of the diaphragm. The diaphragm can have any shape. In some embodiments, the vertical cantilever shell forms a virtual pivot that substantially prevents out-of-plane motion but allows rotation of the diaphragm edge while imparting a counter-torque. In various embodiments, the vertical cantilever shell has a thickness between 0.1 µm and 50 µm, and where the vertical cantilever shell has a height that is between 1 and 100 times greater than its thickness. In yet a further embodiment, the vertical cantilever shell is not continuous around the diaphragm edge but has regions that do not have a virtual pivot. In yet a further embodiment, the MUT is multimode.

[0053] In some embodiments, microfabricated ultrasonic transducers (MUTs) are disclosed herein, which include clamped diaphragms that include grooves. The clamped diaphragms can have any shape. In some embodiments, the MUT is a pMUT. In various embodiments, the grooves are within 20 diaphragm thicknesses of the diaphragm boundary, and wherein the grooves have a width no greater than 10 diaphragm thicknesses, and wherein the grooves have a depth between 1% and 100% of the diaphragm thickness. In some embodiments, the grooves have a constant width. In other embodiments, the grooves have a variable width. In some embodiments, the grooves are interrupted at one or more locations to allow for electrical wiring. In some embodiments, the MUT is multimode. In some embodiments, the MUT is a cMUT. In various embodiments, the grooves are within 20 diaphragm thicknesses of the diaphragm boundary, and wherein the grooves have a width no greater than 10 diaphragm thicknesses, and wherein the grooves have a depth between 1% and 100% of the diaphragm thickness. In some embodiments, the grooves have a constant width. In other embodiments, the grooves have a variable width. In some embodiments, the grooves are interrupted at one or more locations to allow for electrical wiring. In some embodiments, the MUT is multimode.

[0054] In various embodiments, an MUT array configured for ultrasonic imaging is disclosed herein, wherein the array includes a plurality of such MUTs described herein. In some embodiments, each MUT of the plurality of such MUTs is a pMUT. In other embodiments, each MUT of the plurality of such MUTs is a cMUT. In some embodiments, each MUT of the plurality of such MUTs includes a vertical cantilever shell formed by multiple etchings.

[0055] In various embodiments, methods of manufacturing the MUTs and MUT arrays described herein are disclosed.

[0056] In certain embodiments, microfabricated ultrasonic transducers (MUTs) are disclosed herein that include: a piezoelectric stack including a substrate, an insulating layer, a top electrode, a piezoelectric layer, and a bottom electrode, wherein the piezoelectric stack has an edge portion and a central portion, wherein the piezoelectric stack has one or more grooves extending through at least the top electrode, piezoelectric layer, bottom electrode, and insulating layer and into at least a portion of the substrate, and wherein the one or more grooves are disposed between the edge portion and the central portion of the piezoelectric stack; a base; one or more anchors that couple the central portion of the piezoelectric stack to the base such that the edge portions of the piezoelectric stack are free and the central portion of the piezoelectric stack is clamped to the base, the one or more anchors providing electrical coupling between the base and the piezoelectric stack; and a plurality of conductors including (i) a first conductor that electrically couples the top electrode of the piezoelectric stack to the base through a first via that passes through the thickness of the piezoelectric stack; and (ii) a second conductor that electrically couples the bottom electrode of the piezoelectric stack to the base through a second via that passes through the thickness of the piezoelectric stack, wherein the first via and the second via are disposed between the edge portion and the central portion of the piezoelectric stack. [Certain Definitions] []

[0057] Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Any reference to "or" herein is intended to cover "and / or" unless otherwise stated. [Overview of the Method] []

[0058] Three methods are presented for improving the electromechanical coupling coefficient and bandwidth of microfabricated ultrasonic transducers or MUTs:

[0059] 1) Forming grooves along the edges of the clamped diaphragm to locally enhance the flexibility of the diaphragm at its edges;

[0060] 2) Forming a virtual pivot via a vertical cantilever shell that restricts out-of-plane motion but permits rotation relative to the counter-torque, thus creating boundary conditions similar to a simply supported edge constrained by a torsion spring; and

[0061] 3) Form diaphragms that have largely free edges and are clamped at one or more locations within or around the diaphragms. [Diaphragm with Edge Grooves] []

[0062] Herein, we disclose a method for reducing the stiffness of a diaphragm near the diaphragm edge by etching a groove near the diaphragm edge. This results in a diaphragm having a boundary that acts between the clamped edge and an edge simply supported using a torsion spring. This “edge groove” promotes piston-like motion, better coupling, and a wider bandwidth.

[0063] As shown in FIGS. 5a - 5b and FIGS. 6a - 6b, this edge groove 300 can be applied to both pMUT and cMUT embodiments. For effectiveness, it should be within approximately five diaphragm thicknesses of the diaphragm edge 101a. The width of the groove affects the stiffness, where a wider groove promotes simply supported behavior while, at the same time, reducing the flexural stiffness of the plate and thus shifting its frequency more. [Diaphragm with Virtual Pivot] []

[0064] We further disclose a method for forming a “virtual pivot” that acts similar to a simply supported edge constrained by a torsion spring. This is accomplished by forming a vertical cantilever shell at the diaphragm edge. This cantilever shell is very stiff for vertical displacement, thus effectively preventing displacement in the z - direction. The cantilever shell is relatively flexible with respect to torsion at the diaphragm edge, thus allowing rotation but imparting a counter - moment based on the size of the shell. The cantilever shell is also susceptible to lateral displacement in the x and y directions via external lateral forces. Thus, in the absence of such lateral forces, the cantilever shell prevents displacement of the diaphragm edge while allowing rotation and imparting a counter - moment.

[0065] The formation of the cantilever shell can be accomplished in many ways. One example of a pMUT is depicted in FIGS. 7a and 7b, where a virtual pivot trench 301a is etched outside the diaphragm edge 101a and deeper than the diaphragm thickness. The cantilever shell is formed from the remaining material between the virtual pivot trench 301a and the cavity in the substrate 100 - 1 that forms the diaphragm 101. The nature of the virtual pivot (e.g., the stiffness of the torsion spring, its resistance to lateral forces, etc.) is specified by the size of the cantilever shell. The longer and thinner the shell, the more flexible the virtual pivot.

[0066] A similar method can be used for the cMUT shown in FIGS. 8a and 8b. A virtual pivot trench 301a is etched around the periphery of the diaphragm 101. For most common cMUT configurations, the cavity formed between the diaphragm 101 and the bottom electrode 200 is very narrow. Using a single virtual pivot trench 301a, the resulting cantilever shell 101b will be short and wide, resulting in a very stiff torsion spring. To produce a more flexible cantilever shell 101b, a second virtual pivot trench 301b can be etched inside the first virtual pivot trench 301a, where both trenches extend through the dielectric layer 102 and into the disposal substrate 103. This will provide a more flexible virtual pivot. [Diaphragm of any shape with edge grooves] []

[0067] In view of the disclosure herein, those skilled in the art will appreciate that the basic design features of the edge grooves can be applied to diaphragms of any shape, as depicted in FIG. 9a. The number and location of the grooves (FIG. 9b), as well as the width of the grooves (FIG. 9c), can also be varied. Indeed, the edge grooves do not need to be of uniform width to provide a beneficial effect. For the practical purpose of routing electrical signals, it may be necessary to break the grooves in the selected area without losing the overall benefit of the grooves (FIG. 9d). [Diaphragm of any shape with virtual pivot] []

[0068] Similarly, in view of the disclosure herein, those skilled in the art will appreciate that the basic design features of the virtual pivot can be applied to diaphragms of any shape, as depicted in FIG. 10a. The number and location of the virtual pivot etchings (FIG. 10b), as well as the width of the etchings (FIG. 10c), can also be varied. Even more so than the grooves, the virtual pivot etchings do not need to be of uniform width to perform their intended functions. Like the grooves, the virtual pivot trenches can be broken in the selected area to allow tasks such as electrical wiring (FIG. 10d). [Diaphragm with free edge and clamped central region] []

[0069] To further enhance the electromechanical coupling coefficient and broaden the bandwidth, we disclose a design method in which the diaphragm has largely free edges and is clamped at the center by one or more anchors. This design has the benefits similar to the centrally clamped free-edge design mentioned in FIG. 3.

[0070] Figures 11a and 11b depict a representative embodiment in the form of a pMUT having a circular diaphragm 101 and a central anchor 105 on top of a processing substrate 103. In this case, the piezoelectric stack (bottom electrode 200, piezoelectric layer 201, and top electrode 202) sits on top of the dielectric layer 102 on the diaphragm 101. Figures 12a and 12b depict another pMUT configuration where the piezoelectric stack sits between the diaphragm 101 and the anchor 105.

[0071] Figures 13a and 13b depict a similar configuration cMUT where the electrodes 200 and 202 sit on top of the dielectric layer 102 on the processing substrate 103. The anchor 105 attaches the electrode 202 to the diaphragm 101. Many configurations can produce a diaphragm of a capacitor having two electrodes separated from each other fixed at one or more anchors with a free edge. [Any shape with a free edge clamped at one or more arbitrary regions inside or attached to the free edge, a diaphragm with electrodes of any shape] []

[0072] In view of the disclosure herein, those skilled in the art will appreciate that the concept of a free-edge MUT can be applied to diaphragms of any shape having one or more arbitrarily shaped clamped regions, and top and bottom electrodes of any shape. Figures 14a through 14c provide several examples of such variations. Importantly, the anchor can be overlapped with the edge of the diaphragm to produce a diaphragm with different free and clamped boundaries, as illustrated in Figure 14d. [] [Combining edge grooves and virtual pivots] []

[0073] In view of the disclosure herein, those skilled in the art will appreciate that the concepts of edge grooves and virtual pivots can be combined to produce even more flexible edge conditions than either concept applied alone. Examples of pMUT and cMUT using two method configurations are respectively illustrated in Figures 15a through 15d and Figures 16a through 16d. [Combining free edges, edge grooves, and virtual pivots] []

[0074] In view of the disclosure herein, those skilled in the art will similarly appreciate that the concepts of edge grooves and virtual pivots can be applied to the free-edge MUT invention either together or separately. FIGS. 17a-17b, 18a-18b, and 19a-19b illustrate this concept for pMUTs having a piezoelectric stack on top of diaphragm 101, pMUTs where the piezoelectric stack sits between diaphragm 101 and anchor 105, and cMUTs, respectively. [Method of manufacturing a] [pMUT] [having grooves and virtual pivots] []

[0075] An exemplary method of manufacturing a pMUT having grooves and (a plurality of) virtual pivots, such as the pMUTs shown in FIGS. 15a-15b and 15c-15d, is now described.

[0076] (a) First, a substrate 100-1 or a device layer 100-2 is provided, which is typically single-crystalline silicon.

[0077] (b) Next, a dielectric layer 102 can be deposited over the substrate 100-1 or the device layer 100-2. The dielectric layer 102 is typically some form of SiO2, which is about 0.1 µm to 3 µm thick. It is typically deposited via thermal oxidation, plasma enhanced chemical vapor deposition (PECVD), or other techniques.

[0078] (c) Next, a first metal layer 200 (also referred to as the bottom electrode, M1, or metal 1) can be deposited. Generally speaking, this is a combination of a film that adheres to the substrate, prevents the diffusion of the piezoelectric, aids in the structured deposition / growth of the piezoelectric, and is conductive. Strontium ruthenate (SRO (SrRuO3)) can be used on top of platinum (Pt) for diffusion barrier and conduction, and as a structured film growth on top of titanium (Ti) as an adhesion layer (for Pt to silicon dioxide (SiO2)). Generally, these layers are thin, less than 200 nm, with some films being 10 nm to 40 nm. Stress, manufacturing, and cost issues will generally limit this stack to less than 1 µm. The conductor (Pt) is usually thicker than the structured layer (SRO) and the adhesion layer (Ti). Other common structured layers (instead of SRO) include (La0.5Sr0.5)CoO3, (La0.5Sr0.5)MnO3, LaNiO3, RuO2, IrO2, BaPbO3, and so on. Pt can be replaced with other conductive materials such as copper (Cu), chromium (Cr), nickel (Ni), silver (Ag), aluminum (Al), molybdenum (Mo), tungsten (W), and NiCr. These other materials usually have drawbacks such as poor diffusion barriers, brittleness, or unfavorable adhesion, and Pt is the most common conductor used. The adhesion layer Ti can be replaced with any common adhesion layer such as TiW, TiN, Cr, Ni, Cr, etc.

[0079] (d) Next, the piezoelectric material of the piezoelectric layer 201 can be deposited. Some common examples of suitable piezoelectric materials include: lead zirconate titanate (PZT), potassium sodium niobate (KNN), niobium doped PZT (PZT-N), lead magnesium niobate-lead titanate (PMN-Pt), aluminum nitride (AlN), scandium doped aluminum nitride (Sc-AlN), zinc oxide (ZnO), polyvinylidene difluoride (PVDF), and lithium niobate (LiNiO3). The thickness of the piezoelectric layer can vary between 100 nm and 5 µm or may be greater.

[0080] (e) Next, a second metal layer 202 (also referred to as the top electrode, M2, or metal 2) can be deposited. This second metal layer 202 can be similar to the first metal layer 200 and can be used for similar purposes. For M2, the same stack as for M1 can be used, but conversely: Ti is used for adhesion on top of Pt to prevent diffusion on top of the SRO used as the structure.

[0081] (f) Next, the second metal layer or M2 202 can be patterned and etched, stopping on the piezoelectric layer. Etching can be performed in many ways herein, for example, via reactive ion etching (RIE), ion milling, wet chemical etching, isotropic gas etching, etc. After patterning and etching, the photoresist used for patterning M2 can be stripped via wet and / or dry etching. In many embodiments for manufacturing the cMUTs and pMUTs described herein, any number of etching methods can be used, and the photoresist is typically stripped after most patterning and etching steps.

[0082] (g) Next, the piezoelectric layer can be similarly patterned and etched, stopping at the first metal layer or M1 200. Generally speaking, wet, RIE, and / or ion milling etching is used.

[0083] (h) Next, the first metal layer or M1 200 can be similarly patterned and etched, stopping on the dielectric layer 102.

[0084] (i) If desired, one or both of the following can be added: (1) H2 barrier. Diffusion of H2 into the piezoelectric layer can limit its lifespan. To prevent this, an H2 barrier can be used. This can be accomplished using 40 nm of atomic layer deposition (ALD) aluminum oxide (Al2O3). Other suitable materials can include silicon carbide (SiC), diamond-like carbon, etc. (2) Redistribution layer (RDL). This layer can provide connection capabilities between M1 and M2 and other connections (e.g., wire bonding, bump bonding, etc.). The RDL can be formed by: first, adding a dielectric (such as an oxide); etching vias in the dielectric; depositing a conductor (usually Al); and finally patterning the conductor. Additionally, we can add a passivation layer (usually, oxide + nitride) to prevent physical scratches, accidental short circuits, and / or moisture ingress.

[0085] (j) Next, the edge grooves 300 can be patterned. The dielectric layer 102 can be etched via RIE or wet etching. The substrate 100-1 or the device layer 100-2 can be etched, and since the substrate 100-1 or the device layer 100-2 is typically silicon, the etching is typically deep reactive ion etching (DRIE). These edge grooves 300 can have a lateral dimension between 100 nm and 1000 µm, but typically between 2 µm and 10 µm. The edge grooves 300 can have a depth ranging from 0.1% to 100% of the thickness of the device 100-1 or the device layer 100-2, but typically in the range of 25% to 75% of the thickness of the device 100-1 or the device layer 100-2.

[0086] (k) The virtual pivot channels 301a can be patterned and etched. The dielectric layer 102 can be etched via RIE or wet etching. The substrate 100-1 or the device layer 100-2 is typically silicon and can typically be etched via deep reactive ion etching (DRIE). These virtual pivot channels 301a can have a lateral dimension between 100 nm and 1000 µm, but typically between 2 µm and 10 µm. The virtual pivot channels 301a can have a depth ranging from 0.1% to 99.9% of the thickness of the disposal layer 103, but typically in the range of 10% to 50% of the thickness of the disposal layer 103 (approximately 10 µm to 100 µm).

[0087] (l) Frequently, an SOI substrate is used, as shown in FIGS. 15c to 15d. In this case, there is a buried insulator layer or buried oxide (BOX) layer 104 directly below the diaphragm 101. The diaphragm 101 then consists of a "device" layer 100-2 (the layer above the BOX layer 104) and a "handle" layer 103 below the BOX layer 104. The cavity in the handle layer 103 can stop on the BOX layer 104 and can be etched out from the handle layer 103. In this case, manufacturing the virtual pivot trench 301a can include two additional steps: (1) etching the BOX layer 104 after etching the device layer 100-2 via DRIE (usually via dry RIE etching or in some cases, via wet etching); and (2) etching the handle layer 103 to the desired depth via DRIE. Most SOI wafers are silicon, meaning the device layer 100-2 and the handle layer 103 will typically be single-crystalline silicon. In this case, the insulator BOX layer 104 is usually thermally grown silicon dioxide, which is called the "buried oxide", the source of the term "BOX". Silicon SOI wafers with a single-crystalline silicon handle layer and device layer with an oxide BOX can usually be used. The device layer 100-2 can be 5 µm, but typically varies between 100 nm and 100 µm, while the handle layer 103 thickness typically varies between 100 µm and 1000 µm. The BOX layer 104 is usually between 100 nm and 5 µm, but in many cases, 1 µm can be used.

[0088] (m) If desired, the back side of the wafer or the handle layer 103 can be thinned by grinding and optionally polishing at this point. In many embodiments, the handle layer 103 is thinned from 500 µm to 300 µm thick. Common thicknesses typically vary between 50 µm and 1000 µm.

[0089] (n) A cavity can be patterned and etched on the back side of the wafer or the handle layer 103. Generally speaking, the wafer / handle layer 103 is made of silicon, and the etching is done using DRIE. In the case of FIGS. 15a to 15b, the etching can be timed. In FIGS. 15c to 15d, the etching can optionally stop on the BOX layer 104. The cavity can be etched via other techniques such as potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), hydrofluoric acid / nitric acid / acetic acid (HNA), and reactive ion etching (RIE). After photoresist stripping, the wafer can be considered complete. [Method of manufacturing a] [pMUT] [with grooves] []

[0090] An exemplary method of manufacturing a pMUT with grooves (such as the pMUTs shown in FIGS. 5a - 5d) is also provided. This method can be similar to the above-described method of manufacturing a pMUT with grooves and (a) virtual pivot(s) (FIGS. 15a - 15b and FIGS. 15c - 15d), except that step (k) (patterning and etching the virtual pivot) is typically skipped. [Method of manufacturing a] [pMUT] [with a virtual pivot] []

[0091] An exemplary method of manufacturing a pMUT with a cantilever shell (such as the pMUTs shown in FIGS. 7a - 7d) is also provided. This method can be similar to the above-described method of manufacturing a pMUT with grooves and (a) virtual pivot(s) (FIGS. 15a - 15b and FIGS. 15c - 15d), except that step (j) (patterning and etching the grooves) is typically skipped. [Method of manufacturing a] [cMUT] [with grooves and a virtual pivot] []

[0092] An exemplary method of manufacturing a cMUT with grooves and (a) virtual pivot(s) (such as the cMUTs shown in FIGS. 16e and 16f) is now described.

[0093] (a) The method generally begins with a substrate that will become the processing substrate 103. Generally speaking, this substrate is single crystal silicon.

[0094] (b) Next, the shallow cavity can be patterned and etched. This cavity is typically 10 nm to 5 µm, most commonly between 100 nm and 1 µm. For a common single crystal silicon substrate, this cavity is etched using DRIE, RIE, HNA, or timed oxidation.

[0095] (c) Next, the dielectric layer 102 can be deposited. Generally speaking, this dielectric layer 102 is a form of SiO 2, which is about 0.1 µm to 3 µm thick. It is usually deposited via thermal oxidation, and in some cases, via PECVD or Low Pressure Chemical Vapor Deposition (LPCVD) or some other technique.

[0096] (d) Next, a metal layer or conductor 200 can be deposited. Examples of such conductors include Al, Au, Cr, Cu, Pt, etc. This conductor can be on an adhesion layer and / or a diffusion barrier layer (such as Ti, TiW, TiN, Cr, etc.).

[0097] (e) The metal layer or conductor 200 (and the adhesion layer and / or the diffusion barrier layer) can be patterned and etched, stopping on the dielectric layer 102.

[0098] (f) The bottom portions of the virtual pivot trenches 301b and the virtual pivot trenches 301a can be patterned and etched. First, the dielectric layer 102 can be etched via RIE, wet etching, or another technique. Next, the treated substrate 103 can be etched. Generally speaking, the treated substrate 103 is silicon, and this etching is carried out via DRIE and timed. As in the procedures described above with reference to FIGS. 15a to 15b and FIGS. 15c to 15d, the depth of the virtual pivot trenches 301a and 301b can range from 1 µm to 1000 µm, but is usually between 10 µm and 100 µm, or about 10% to 50% of the treated substrate 103.

[0099] (g) The device layer 100-2 can be bonded to the dielectric layer 102 on the treated substrate 103. This can be accomplished via many techniques, including (but not limited to) fusion, Al-Ge, Au-Si, anodic, solid liquid interdiffusion (SLID), adhesives, Au-Au, Au-Sn, Cu-Cu, Cu-Sn, etc. The selection of the bonding can depend on the allowable thermal budget and the available procedures and integration requirements. The bonds shown in FIGS. 16e and 16f are fusion bonds of the oxide material of the dielectric layer 102 to the silicon material of the device layer 100-2.

[0100] (h) The edge grooves 300 can be patterned and etched into the device layer 100-2. This is typically done using timed DRIE. As in the procedures of FIGS. 15a to 15b and FIGS. 15c to 15d, these edge grooves 300 can have a lateral dimension between 100 nm and 1000 µm, but typically between 2 µm and 10 µm. The edge grooves 300 can have any depth ranging from 0.1% to 100% of the thickness of the device layer 100-2, but typically in the range of 25% to 75% of the thickness of the device layer 100-2.

[0101] (i) The top portion of the virtual pivot trench 301a can be patterned and etched. This is typically done using timed DRIE. The lateral dimension of the top portion of the virtual pivot trench 301a is typically smaller or larger laterally than the bottom portion of the virtual pivot trench 301a to overcome alignment issues.

[0102] This method can be varied in many ways. In some embodiments, steps (d) and (e) can be skipped to fabricate the cMUTs shown in FIGS. 16g and 16h. In some embodiments, step (b) can alternatively be performed on the bottom of the device layer 100-2 to fabricate the cMUTs shown in FIGS. 16a and 16b. In some embodiments, steps (d) and (e) can be skipped and step (b) can alternatively be performed on the bottom of the device layer 100-2 to fabricate the cMUTs shown in FIGS. 16c and 16d. [Nominal Free-Edge Design and Fabrication Method] []

[0103] The nominal free-edge design of a pMUT will typically require two independent contacts to the substrate. This is because a pMUT typically requires a voltage difference across its piezoelectric material and thus requires at least two voltages. There are many ways to apply at least two voltages. FIGS. 20a and 20b show an exemplary pMUT free-edge design and its procedure or fabrication method is described below.

[0104] (a) The method can start with an SOI wafer. Generally speaking, this is a device layer 100-2 of single-crystalline silicon on top of a BOX (oxide) layer on top of the handling layer. This device layer 100-2 of this wafer is shown inverted in FIGS. 20a and 20b.

[0105] (b) Next, a dielectric layer 102 can be deposited. Generally speaking, this deposition is some form of SiO 2, which is about 0.1 µm to 3 µm thick. It is typically deposited via thermal oxidation, PECVD deposition, or other techniques.

[0106] (c) The first metal layer or M1 (Metal 1) 200 can be deposited. Generally speaking, this deposition is a combination of a film that adheres to the substrate, prevents the diffusion of piezoelectricity, aids in the structured deposition / growth of piezoelectricity, and is conductive. SRO (SrRuO3) can be used on top of Pt for diffusion barrier and conduction, and as a structured film growth on top of Ti as an adhesion layer (for Pt to SiO2). Generally, these layers are thin, less than 200 nm, and some of the films are 10 nm to 40 nm. Stress, manufacturing, and cost issues will generally limit this stack to less than 1 µm. The conductor (Pt) is usually thicker than the structured layer (SRO) and the adhesion layer (Ti). Other common structured layers (instead of SRO) include (La0.5Sr0.5)CoO3, (La0.5Sr0.5)MnO3, LaNiO3, RuO2, IrO2, BaPbO3, etc. Pt can be replaced with other conductive materials such as Cu, Cr, Ni, Ag, Al, Mo, W, and NiCr. These other materials usually have disadvantages such as poor diffusion barriers, brittleness, or unfavorable adhesion, and Pt is the most common conductor used. The adhesion layer Ti can be replaced with any common adhesion layer such as TiW, TiN, Cr, Ni, Cr, etc.

[0107] (d) Next, the piezoelectric material of the piezoelectric layer 201 can be deposited. Common examples of piezoelectric materials include: PZT, KNN, PZT-N, PMN-Pt, AlN, Sc-AlN, ZnO, PVDF, and LiNiO3. The thickness of the piezoelectric material can vary between 100 nm and 5 µm (possibly larger).

[0108] (e) The second metal layer or M2 (Metal 2) 202 can be deposited. M2 202 can be similar to M1 200 and can be used for similar purposes. For M2 202, the same stack as M1 200 can be used, but conversely: Ti is used for adhesion on top of Pt to prevent diffusion on top of SRO used as a structure.

[0109] (f) The M2 202 can be patterned and etched, stopping on the piezoelectric layer 201. Etching can be performed in many ways herein, for example, via RIE (reactive ion etching), ion milling, wet chemical etching, isotropic gas etching, etc. After patterning and etching, the photoresist used to pattern the M2 202 can be wet and / or dry stripped. In many embodiments for manufacturing the cMUTs and pMUTs described herein, any number of etching methods can be used, and the photoresist is typically stripped after most patterning and etching steps.

[0110] (g) Next, the piezoelectric layer 201 can be similarly patterned and etched, stopping at the first metal layer or M1 200. Generally speaking, wet, RIE, and / or ion milling etching are used.

[0111] (h) Next, the first metal layer or M1 200 can be similarly patterned and etched, stopping on the dielectric layer 102.

[0112] (i) If desired, an H2 barrier can be added. H2 diffusion into the piezoelectric layer 201 can limit its lifespan. To prevent this, an H2 barrier can be used. This can be accomplished using 40 nm atomic layer deposition (ALD) aluminum oxide (Al2O3). Other suitable materials can include SiC, diamond-like carbon, etc.

[0113] (j) An additional dielectric layer 106 can be deposited. This additional dielectric layer 106 is typically an oxide and / or nitride layer (usually PECVD), which is typically between 100 nm and 2 µm thick.

[0114] (k) Through-holes (or vias) 108 can be patterned and etched in the additional dielectric layer 106. This is typically accomplished via RIE etching or some form of wet etching. The etching can stop on the M1 200 or M2 202.

[0115] (l) The redistribution conductor 107 can be deposited, patterned, and etched. Typical conductors are metals (Al, Cu, Au, Ti, Cr, etc.) and / or semiconductors, such as poly-Si, poly-Ge, or poly-SiGe. The layer containing the redistribution conductor 107 is typically relatively thick (between 100 nm and 5 µm, but usually between 0.5 µm and 2 µm) to overcome topography and lower resistance. In an example, 1 µm of Au on top of 100 nm of Ti on top of 1.6 µm of Al is used. The Au is for the integration bonding in step s described further below.

[0116] (m) Next, the edge grooves 300 can be patterned. The dielectric layer 102 can be etched via RIE or wet etching. The device layer 100-2 can be etched, and since the device layer 100-2 is typically silicon, the etching is usually deep reactive ion etching (DRIE). These edge grooves 300 can have a lateral dimension between 100 nm and 1000 µm, but typically between 2 µm and 10 µm. The edge grooves 300 can have any depth ranging from 0.1% to 99.9% of the thickness of the device layer 100-2, but typically in the range of 25% to 75% of the thickness of the device layer 100-2.

[0117] (n) The device layer 100-2 can be patterned and etched. The dielectric layer 102 can be etched via RIE or wet etching. The device layer 100-2 (which is typically silicon) can be etched, so the etching is usually deep reactive ion etching (DRIE). This etching can proceed through the entire device layer 100-2 until it stops on the BOX layer. These etchings can have a lateral dimension between 100 nm and several cm, but typically between 5 µm and 1000 µm.

[0118] (o) Optionally, a passivation layer can be deposited, patterned, and etched to prevent physical scratches, accidental short circuits, and / or moisture ingress. This passivation layer is typically an oxide and / or nitride, and its thickness is typically in the range of 300 nm to 2 µm.

[0119] (p) If desired, the back side of the wafer or the handling layer can be thinned by grinding and optionally polishing at this point. In many embodiments, the handling layer is thinned from 500 µm to 300 µm thick. The common thickness typically varies between 50 µm and 1000 µm.

[0120] (q) Now, the microelectromechanical systems (MEMS) wafer (101 to 102, 106 to 109, 200 to 202, 300, 101a, and the handling layer) is cut in preparation for bonding.

[0121] (r) A conductive bonding material 110 can be deposited, patterned, and etched on the base substrate 111. For example, the base substrate 111 can be a planarized application specific integrated circuit (ASIC) wafer. The conductive bonding material 110 can be 1 µm Au to achieve the bonding in step (s).

[0122] (s) The MEMS dies (101 to 102, 106 to 109, 200 to 202, 300, 101a and the disposal layer) can be aligned with the base substrate 111 and bonded thereto, thereby forming an electrical connection 109 between the redistribution conductor 107 and the conductive bonding material 110. Optionally, only good MEMS dies are selected. The MEMS dies can be bonded only to the proven good ASIC dies to maintain the yield. The bad ASIC dies are bonded to dummy MEMS dies for etch loading (in step t). The bonding can be any electrical connection, including Au-Au thermocompression, SLID, Al-Ge, Au-Sn, Cu-Cu, etc. For example, Au-Au thermocompression can be used.

[0123] (t) The base substrate 111 can be filled with MEMS dies. The backside of the MEMS dies can be etched in a DRIE tool to remove the disposal layer (not shown), thereby stopping on the BOX layer.

[0124] (u) The backside of the MEMS dies can be etched in an oxide RIE to remove the BOX layer, thereby stopping on the device layer 100-2. Once completed, the layout and cross-section of FIGS. 20a and 20b can be considered achieved.

[0125] It should be noted that for the pMUT of FIGS. 20a and 20b:

[0126] (a) The electrical connection 109 can allow the telecom signal from the base substrate 111 to be transmitted through the conductive bonding material 110 to the MEMS die to the redistribution conductor 107.

[0127] (b) There can be at least two independent signals, one independent signal connected to M1 or the first metal layer 200 through a via 108, and another independent signal connected to M2 or the second metal layer 202 through a similar via 108. This can allow the designer to apply a known voltage difference across the piezoelectric layer 201, thereby enabling the actuation of the pMUT.

[0128] (c) The edge trench 300 can provide an enhanced k eff 2.

[0129] (d) A virtual pivot can be formed optionally to further enhance k eff 2. If the conductive bonding material 110 has a height much greater than its lateral dimension, the bonding can form a cantilever shell.

[0130] (e) The above process can produce pMUTs with free edges, grooves, and cantilever shells, and can enhance the yield by only combining known good die.

[0131] (f) Those skilled in the art can use this manufacturing method, combining the design concepts of grooves, free edges, and virtual pivots to produce a wide range of novel pMUTs.

[0132] Although the above describes various methods for manufacturing pMUTs and cMUTs according to many embodiments, those of ordinary skill in the art will recognize many variations based on the teachings described herein. The steps can be completed in a different order. Steps can be added or deleted. Some steps may include sub-steps. Manufacturing techniques known in the art can be applied to one or more steps. Whenever advantageous, many steps can be repeated. [References] []

[0133] [1] Formulas for natural frequency and mode shape by R.D. Blevins, Kreiger, 1979.

[0134] [2] Piezoelectric Micro-machined Ultrasonic Transducers for Medical Imaging by K.M. Smyth, Massachusetts Institute of Technology, 2017.

[0135] Although the preferred embodiments of the present invention have been shown and described herein, those skilled in the art will understand that these embodiments are provided by way of example only. Many variations, changes, and substitutions will now occur to those skilled in the art without departing from the present invention. It should be understood that various alternatives to the embodiments of the present invention described herein can be employed in practicing the present invention.

[0136] 100: Substrate 100 - 1: Substrate 100 - 2: Device layer 101: Diaphragm / Circular diaphragm 101a: Diaphragm edge 101b: Cantilever shell 102: Dielectric layer / Insulating layer 103: Disposal substrate / Disposal layer 104: Buried oxide (BOX) layer 105: Anchor 106: Dielectric layer 107: Redistribution conductor 108: Through hole / Hole 109: Conductive joint 110: Conductive joint material 111: Base substrate 200: Bottom electrode / First electrode / M1 / Metal 1 / First metal layer / Conductor 201: Piezoelectric layer 202: Top electrode / Second electrode / M2 / Metal 2 / Second metal layer / Conductor 300: Edge groove 301a: Virtual pivot trench 301b: Second virtual pivot trench

Claims

1. A microfabricated ultrasonic sensor (MUT) comprising (i) a piezoelectric stack including a top electrode, a bottom electrode and a piezoelectric layer disposed therebetween, and (ii) a diaphragm disposed below the piezoelectric stack and including a trench disposed within the diaphragm and at least partially surrounding the piezoelectric stack.

2. The micromachined ultrasonic sensor (MUT) as claimed in claim 1, wherein the micromachined ultrasonic sensor (MUT) is a piezoelectric micromachined ultrasonic sensor (pMUT).

3. The micromachined ultrasonic sensor (MUT) of claim 2, wherein the groove is within 20 diaphragm thicknesses of the diaphragm boundary, and wherein the groove has a width of no more than 10 diaphragm thicknesses, and wherein the groove has a depth between 1% and 100% of the diaphragm thickness.

4. The micromachined ultrasonic sensor (MUT) as described in claim 3, wherein the groove has a constant width.

5. The micromachined ultrasonic sensor (MUT) as described in claim 3, wherein the groove has a variable width.

6. The micromachined ultrasonic sensor (MUT) as claimed in claim 3, wherein the trench is interrupted at one or more locations to allow electrical wiring.

7. The micro-machined ultrasonic sensor (MUT) as described in claim 6, wherein the micro-machined ultrasonic sensor (MUT) is multi-mode.

8. A micromachining ultrasound sensor (MUT) array configured for ultrasound imaging, the array comprising a plurality of micromachining ultrasound sensors (MUTs) as claimed in claim 7.

9. The micromachined ultrasonic sensor (MUT) of claim 1, wherein the groove is within 20 diaphragm thicknesses of the diaphragm boundary, and wherein the groove has a width of no more than 10 diaphragm thicknesses, and wherein the groove has a depth between 1% and 100% of the diaphragm thickness.

10. The micromachined ultrasonic sensor (MUT) as claimed in claim 9, wherein the groove has a constant width.

11. The micromachined ultrasonic sensor (MUT) of claim 9, wherein the groove has a variable width.

12. The micromachined ultrasonic sensor (MUT) of claim 9, wherein the trench is interrupted at one or more locations to allow electrical wiring.

13. The micro-machined ultrasonic sensor (MUT) of claim 12, wherein the micro-machined ultrasonic sensor (MUT) is multi-mode.

14. A microfabricated ultrasound sensor (MUT) array configured for ultrasound imaging, the array comprising a plurality of microfabricated ultrasound sensors (MUTs) as claimed in claim 13.

15. The micromachined ultrasonic sensor (MUT) of claim 1, wherein the groove comprises one or more grooves.

16. The micromachined ultrasonic sensor (MUT) of claim 15, wherein the one or more grooves are all located within the diaphragm boundary.

17. The micromachined ultrasonic sensor (MUT) of claim 15, wherein the one or more grooves are all located outside the diaphragm boundary.

18. The micromachined ultrasonic sensor (MUT) of claim 15, wherein the one or more grooves include at least one first groove disposed within the diaphragm boundary and at least one second groove disposed outside the diaphragm boundary.

19. The microfabricated ultrasonic sensor (MUT) of claim 1 further includes a substrate and an insulating layer, wherein the substrate is located below the insulating layer and the insulating layer is located below the piezoelectric stack.

20. The micromachined ultrasonic sensor (MUT) of claim 19, wherein the diaphragm is supported by the substrate.

21. The micromachined ultrasonic sensor (MUT) of claim 19, wherein the diaphragm is formed as part of the substrate.

22. The microfabricated ultrasonic sensor (MUT) of claim 19, wherein the substrate includes a cavity and the diaphragm is supported by the substrate above the cavity.

23. The microfabricated ultrasonic sensor (MUT) of claim 1 further includes an insulating layer disposed between the diaphragm and the piezoelectric stack.

24. The micromachined ultrasonic sensor (MUT) of claim 23, wherein the insulating layer includes a dielectric layer.

25. The micromachined ultrasonic sensor (MUT) of claim 1, wherein the piezoelectric stack is completely housed within a cylinder, the cylindrical system being defined as the vertical projection of the groove upward from the diaphragm.

26. The micromachined ultrasonic sensor (MUT) of claim 1, wherein, when viewed from a top view, the piezoelectric stack defines a perimeter bounded by the trench.

27. The microfabricated ultrasonic sensor (MUT) of claim 26, wherein, when viewed from a top view, at least one of the top electrode, the bottom electrode, or the piezoelectric layer comprises a circular outline.

28. The micro-machined ultrasonic sensor (MUT) of claim 27, wherein, when viewed from a top view, the top electrode, the bottom electrode, and the piezoelectric layer have different circular profiles relative to each other.

29. The micromachined ultrasonic sensor (MUT) of claim 1, wherein the top electrode, the bottom electrode and the piezoelectric layer each define their respective perimeters, the perimeter of the top electrode is connected outside the perimeter of the piezoelectric layer, the perimeter of the piezoelectric layer is connected outside the perimeter of the bottom electrode, and the perimeter of the bottom electrode is connected outside the trench.

30. The micromachined ultrasonic sensor (MUT) of claim 1, wherein the groove has a depth that does not completely cut through the vertical thickness of the diaphragm.

31. The micromachined ultrasonic sensor (MUT) of claim 1, wherein the trench has a depth of about 0.01% to about 100% of the vertical thickness of the diaphragm.

32. The microfabricated ultrasonic sensor (MUT) of claim 1 further includes a trench extending into the substrate, wherein, when viewed from a side view, the trench is disposed between the trench and the piezoelectric stack.

33. The micromachining ultrasonic sensor (MUT) of claim 1, wherein the trench completely surrounds the piezoelectric stack without interruption within the trench.

34. The micromachined ultrasonic sensor (MUT) of claim 1, wherein the trench is broken to discontinuously surround the piezoelectric stack.

35. A microfabricated ultrasonic sensor (MUT), comprising: A substrate having a diaphragm having a vertical thickness; one or more electrodes located on or near the diaphragm; and a trench that cuts into the diaphragm and at least partially surrounds the one or more electrodes, the trench having a depth that does not completely cut through the vertical thickness of the diaphragm.

36. The micromachined ultrasonic sensor (MUT) of claim 35, wherein the micromachined ultrasonic sensor (MUT) is a piezoelectric micromachined ultrasonic sensor (pMUT) comprising a piezoelectric film.

37. The micromachined ultrasonic sensor (MUT) of claim 36, wherein the one or more electrodes are electrically coupled to the piezoelectric film.

38. The micromachined ultrasonic sensor (MUT) of claim 36 further includes clamping one or more anchors of the diaphragm.

39. The micromachined ultrasonic sensor (MUT) of claim 38, wherein the piezoelectric film is positioned relative to the one or more anchors.

40. The micromachined ultrasonic sensor (MUT) of claim 38, wherein the piezoelectric film is positioned on the same side as the one or more anchors.

41. The micromachined ultrasonic sensor (MUT) of claim 38, wherein the piezoelectric film is between the one or more anchors and the diaphragm.

42. The micromachined ultrasonic sensor (MUT) of claim 35, wherein the micromachined ultrasonic sensor (MUT) is a capacitive micromachined ultrasonic sensor (cMUT).

43. The micromachined ultrasonic sensor (MUT) of claim 42, wherein one or more electrodes are electrically coupled to the diaphragm between gaps.

44. The micromachined ultrasonic sensor (MUT) of claim 35 further includes a plurality of anchors, wherein a subset of the plurality of anchors is attached to one or more vertical cantilever shells.

45. The micromachined ultrasonic sensor (MUT) of claim 35, wherein the trench completely surrounds the one or more electrodes without interruption in the trench.

46. ​​The micromachined ultrasonic sensor (MUT) of claim 35, wherein the trench is broken to discontinuously surround the one or more electrodes.

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