Electronic package and substrate structure thereof

Abstract

This invention provides an electronic package and its substrate structure. The substrate structure includes an insulating layer, a wiring layer, conductive blind vias, and an insulating protective layer. The conductive blind vias are positioned not to overlap with the edge of the opening of the insulating protective layer, in order to avoid stress concentration in the insulating protective layer during probe testing and to prevent the insulating protective layer from cracking.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging technology, and more particularly to an electronic package and its substrate structure that can improve reliability. Prior Technology

[0002] Currently, the electrical testing equipment used by packaging and testing plants in the packaging and testing stage is standardized testing equipment for testing semiconductor packages and their end products.

[0003] As shown in Figure 1A, in conventional testing operations, a semiconductor package 1 of the Ball Grid Array (BGA) specification is placed on a probe card 9 so that the probes 90 of the probe card can contact the solder balls 19 on the underside of the semiconductor package 1. The probe card 9 transmits the test signal to the testing machine (not shown) via an external line. Therefore, during testing, the upper side of the semiconductor package 1 needs to be pressed down so that each probe 90 can contact the solder ball 19.

[0004] However, in a conventional semiconductor package 1, if the conductive blind via 102 of its substrate structure 10 and the edge of the opening 170 of the exposed electrical contact pad 103 of the solder resist layer 17 overlap each other, as shown in FIG1B, then when the semiconductor package 1 is subjected to probe testing (probe ball insertion), the solder resist layer 17 is prone to stress concentration, which causes the solder resist layer 17 to crack. In particular, when the conductive blind via 102 of the substrate structure 10 has a stacked via design, stress concentration is more likely to occur.

[0005] Therefore, overcoming the deficiencies of the aforementioned conventional technologies has become an urgent issue that needs to be addressed. Summary of the Invention

[0006] In view of the various deficiencies of the prior art, the present invention provides a substrate structure comprising: an insulating layer; a wiring layer formed on the insulating layer and having an electrical contact pad; a conductive blind via formed in the insulating layer; and an insulating protective layer formed on the insulating layer and having an opening, through which the electrical contact pad is exposed, wherein the position of the conductive blind via is not overlapping with the edge of the opening.

[0007] In the aforementioned substrate structure, the conductive blind via is located entirely within the edge of the opening.

[0008] In the aforementioned substrate structure, the conductive blind via is located entirely outside the edge of the opening. For example, the conductive blind via is aligned with the edge of the electrical contact pad, the conductive blind via is located entirely outside the edge of the electrical contact pad, or the conductive blind via is aligned with the edge of the opening.

[0009] In the aforementioned substrate structure, the insulating layer is multilayered, and a plurality of conductive blind vias are formed in the insulating layer using a stacked via design.

[0010] The present invention also provides an electronic package comprising: a substrate structure as described above; and electronic components disposed on the substrate structure and electrically connected to the wiring layer.

[0011] The aforementioned electronic package further includes conductive elements bonded to the electrical contact pad.

[0012] The aforementioned electronic package further includes a covering layer bonded to the substrate structure to cover the electronic component. For example, conductive pillars electrically connected to the wiring layer are formed on the substrate structure, so that the covering layer covers the conductive pillars. Furthermore, a circuit structure electrically connected to the conductive pillars is formed on the covering layer.

[0013] As can be seen from the above, the electronic package and its substrate structure of the present invention mainly avoid stress concentration in the insulating protective layer during probe testing by ensuring that the position of the conductive blind hole is not superimposed on the edge of the opening of the insulating protective layer. Therefore, compared with the prior art, the insulating protective layer of the present invention will not crack during testing, thus effectively improving the reliability of the electronic package. Simple Explanation of the Diagram

[0014] Figure 1A is a cross-sectional schematic diagram of a conventional semiconductor package during testing.

[0015] Figure 1B is a partial top view of Figure 1A.

[0016] Figure 2A is a cross-sectional view of the electronic package and its substrate structure of the present invention during testing.

[0017] Figure 2B is a partial top view of Figure 2A.

[0018] Figure 3 is a partial cross-sectional schematic diagram of another embodiment of the electronic package and its substrate structure of the present invention.

[0019] Figures 4A, 4B, and 4C are partial top views of other embodiments of the electronic package and its substrate structure of the present invention. Implementation

[0020] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0021] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0022] Figure 2A is a cross-sectional schematic diagram of the electronic package 2 of the present invention. As shown in Figure 2A, the electronic package 2 includes: a substrate structure 20, at least one electronic component 21, a plurality of conductive pillars 23, a covering layer 25, a circuit structure 24, and a plurality of conductive elements 29.

[0023] The substrate structure 20 is, for example, a package substrate with a core layer or without a core layer, which adopts the redistribution layer (RDL) specification, and the substrate structure 20 includes an insulating layer 200, a wiring layer 201 disposed on the insulating layer 200, and a plurality of conductive blind vias 202 disposed in the insulating layer 200 and electrically connected to the wiring layer 201.

[0024] In this embodiment, the substrate structure 20 defines a first side 20a and a second side 20b, and the wiring layer 201 of the first side 20a and the second side 20b has a plurality of contacts 204 and a plurality of electrical contact pads 203.

[0025] Furthermore, an insulating protective layer 27 is formed on the insulating layer 200 of the second side 20b, such that the insulating protective layer 27 has a plurality of openings 270, through which each of the plurality of electrical contact pads 203 is exposed. It should be understood that the outermost insulating layer 200 of the first side 20a can serve as a solder resist layer, exposing the plurality of contacts 204.

[0026] Please refer to Figure 2B for further details. In one embodiment, the conductive blind hole 202 is located entirely within the edge of the opening 270 and does not overlap with the edge of the opening 270.

[0027] Furthermore, the material forming the wiring layer 201 is copper, and the material forming the insulation layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP), while the material forming the insulating protective layer 27 is a solder resist such as green paint or ink.

[0028] The electronic component 21 is an active component, a passive component, or a combination thereof, and is disposed on the first side 20a of the substrate structure 20. The active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0029] In this embodiment, the electronic component 21 is disposed on the contact 204 and electrically connected to the wiring layer 201 by means of a plurality of conductive bumps 210 made of solder material in a flip-chip manner; or, the electronic component 21 may be electrically connected to the contact 204 by means of a plurality of bonding wires (not shown); or, the electronic component 21 may be in direct contact with the contact 204. However, the manner in which the electronic component 21 is electrically connected to the substrate structure 20 is not limited to the above.

[0030] The conductive post 23 is disposed on the contact 204 on the first side 20a of the substrate structure 20 to electrically connect to the wiring layer 201.

[0031] In this embodiment, the conductive post 23 is a metal post, such as a copper post. It should be understood that solder balls can also be used as conductive posts 23, but are not limited to the above.

[0032] The covering layer 25 is an insulating material, which is formed on the first side 20a of the substrate structure 20 to cover the electronic component 21 and the plurality of conductive pillars 23.

[0033] In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, or an encapsulating compound such as epoxy resin. For example, the coating layer 25 can be formed by methods such as liquid compounding, injection, lamination, or compression molding.

[0034] The circuit structure 24 is disposed on the cladding layer 25 and electrically connected to the plurality of conductive pillars 23.

[0035] In this embodiment, the circuit structure 24 includes multiple dielectric layers 240 and multiple circuit layers 241 disposed on the multiple dielectric layers 240, such as a redistribution layer (RDL) specification. The outermost dielectric layer 240 can serve as a solder resist layer, and the outermost circuit layer 241 is exposed on the solder resist layer for bonding electronic devices (not shown). Alternatively, the circuit structure 24 may also include only a single dielectric layer 240 and a single circuit layer 241.

[0036] Furthermore, the material forming the circuit layer 241 is copper, and the material forming the dielectric layer 240 is a dielectric material such as poly(p-diazolebenzene) (PBO), polyimide (PI), prepreg (PP), or a solder resist such as green paint or ink.

[0037] The conductive element 29 is a solder ball or a metal bump such as a copper bump, which is disposed on the electrical contact pad 203 of the substrate structure 20 and electrically connected to the wiring layer 201.

[0038] During testing, the electronic package 2 is placed on a probe card 9 with its conductive element 29, so that the probe 90 of the probe card can contact the conductive element 29, and the probe card 9 transmits the test signal to the test machine (not shown) through an external line.

[0039] Therefore, the electronic package 2 of the present invention mainly utilizes the fact that the conductive blind vias 202 of the substrate structure 20 are completely located within the edge of the opening 270 and do not overlap on the edge of the opening 270. When the electronic package 2 is pressed down during probe testing (probe ball insertion) operations, each probe 90 can correspondingly contact the conductive element 29, and stress concentration of the insulating protective layer 27 can be avoided. Therefore, compared with the prior art, the insulating protective layer 27 will not crack during testing operations, thus effectively improving the reliability of the electronic package 2.

[0040] Please refer to Figure 3. In another embodiment, when the substrate structure 30 adopts a stacked via design to form conductive blind vias 202, 302 in each layer, stress concentration in the insulating protective layer 27 can also be effectively avoided.

[0041] Furthermore, the electronic package 2 of the present invention not only improves the reliability of the electronic package 2, but also does not require changes to the appearance of the substrate structure, and can be manufactured using existing semiconductor packaging processes without the need to develop special processes or purchase special equipment, thus helping to reduce the production cost of the product.

[0042] In other embodiments, the conductive blind hole 402 may also be located completely outside the edge of the opening 270 without overlapping the edge of the opening 270, as shown in FIG4A, which is aligned with the edge of the electrical contact pad 203, or as shown in FIG4B, which is completely outside the edge of the electrical contact pad 203, or as shown in FIG4C, which is aligned with the edge of the opening 270.

[0043] Therefore, the position of the conductive blind hole can be set as needed, as long as it does not overlap with the edge of the opening 270 of the insulating protective layer 27, and is not limited to the above.

[0044] In summary, the electronic package and its substrate structure of the present invention avoid stress concentration in the insulating protective layer during probe testing by ensuring that the position of the conductive blind via is not superimposed on the edge of the opening of the insulating protective layer. Therefore, the insulating protective layer of the present invention will not crack during testing, thus effectively improving the reliability of the electronic package.

[0045] The above embodiments are illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent claims.

[0046] 1: Semiconductor package 10, 20, 30: Substrate structure 102, 202, 302, 402: Conductive blind vias 103, 203: Electrical contact pads 17: Solder resist layer 170, 270: Opening 19: Solder ball 2: Electronic packaging components 20a: First side 20b: Second side 200: Insulation layer 201: Wiring Layer 204:Contact 21: Electronic Components 210: Conductive bump 23: Conductive column 24: Line Structure 240: Dielectric layer 241: Line Layer 25: Covering layer 27: Insulation protective layer 29: Conductive elements 9: Probe Card 90: Probe

Claims

1. A substrate structure comprising: Insulating layer; The wiring layer is disposed on the insulating layer and has electrical contact pads; The conductive blind via is disposed within the insulating layer; An insulating protective layer is provided on the insulating layer and has an opening that penetrates both the upper and lower surfaces of the insulating protective layer, so that the lower surface of the electrical contact pad is exposed to the opening and directly contacts the upper surface of the insulating protective layer. The position of the conductive blind hole directly contacted by the electrical contact pad at the opening is completely outside the edge of the opening of the insulating protective layer and does not overlap with the edge of the opening.

2. The substrate structure as described in claim 1, wherein, The wiring layer has contacts.

3. The substrate structure as described in claim 1, wherein, The wiring system is multi-layered.

4. The substrate structure as described in claim 1, wherein, The conductive blind via is aligned with the edge of the electrical contact pad.

5. The substrate structure as described in claim 1, wherein, The conductive blind hole is located completely outside the edge of the electrical contact pad.

6. The substrate structure as described in claim 1, wherein, The conductive blind via is aligned with the edge of the opening.

7. The substrate structure as described in claim 1, wherein, The insulating layer is multi-layered, and a plurality of conductive blind vias are formed in the insulating layer by using a stacked via design.

8. An electronic package, comprising: The substrate structure as described in any of claims 1 to 7; And electronic components are disposed on the substrate structure and electrically connected to the wiring layer.

9. The electronic package as described in claim 8 further includes a conductive element bonded to the electrical contact pad.

10. The electronic package as claimed in claim 8 further includes a covering layer formed on the substrate structure to cover the electronic component.

11. The electronic package as claimed in claim 10 further includes conductive pillars formed on the substrate structure to electrically connect the wiring layer, and the covering layer covers the conductive pillars.

12. The electronic package as described in claim 11 further includes a circuit structure formed on the cover layer and electrically connected to the conductive post.

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