Semiconductor devices

Abstract

The present invention provides a semiconductor device capable of achieving high integration. The semiconductor device of the present invention includes a plurality of first resistive elements, an insulating layer, and a plurality of second resistive elements. The plurality of first resistive elements includes: a plurality of diffusion layers disposed on the main surface side of a semiconductor substrate, extending in a first direction parallel to the main surface of the semiconductor substrate, and arranged in a second direction parallel to the main surface of the semiconductor substrate and intersecting the first direction, each having a first connection terminal portion at its end in the first direction. An insulating layer is disposed on the main surface side of the semiconductor substrate between each of the plurality of first resistive elements, and has an electrode mounting surface in contact with an electrode layer. The plurality of second resistive elements includes: a plurality of conductive layers disposed on the electrode mounting surface of the insulating layer between the plurality of first resistive elements, extending in a first direction, arranged in the second direction, and each having a second connection terminal portion at its end in the first direction.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor device. [Previous Technology]

[0002] A semiconductor device is known, wherein a first resistive element comprising a diffusion layer and a second resistive element comprising a conductive layer are disposed on a substrate. [Summary of the Invention]

[0003] The semiconductor device of the embodiment provides a semiconductor device capable of achieving high integration.

[0004] A semiconductor device according to one embodiment includes: a semiconductor substrate having a main surface including a first direction and a second direction intersecting the first direction; an electrode layer disposed on the main surface side; a plurality of first resistive elements, each including: a plurality of diffusion layers disposed on the main surface side of the semiconductor substrate, extending in the first direction and arranged in the second direction, and each having a first connection terminal portion at an end in the first direction; and an insulating layer disposed on the main surface side of the semiconductor substrate between each of the plurality of first resistive elements, having an electrode mounting surface in contact with the electrode layer. The electrode layer includes: a plurality of second resistive elements, each including: a plurality of conductive layers disposed on the electrode mounting surface of the insulating layer between the plurality of first resistive elements, extending in the first direction and arranged in the second direction, and each having a second connection terminal portion at an end in the first direction.

Implementation Method

[0006] Next, the semiconductor device of the embodiment will be described in detail with reference to the drawings.

[0007] Furthermore, in the following embodiments, a "semiconductor memory device" is described as an example of a semiconductor device. However, the following embodiments are merely examples and are not intended to limit the present invention. Also, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, for common parts in the plurality of embodiments, the same symbols are sometimes used and the description is omitted.

[0008] Furthermore, in this specification, when referring to "semiconductor memory device," it sometimes means memory chip, and sometimes it also means memory system including controller chip, memory card, SSD (Solid State Drive), etc. Furthermore, it sometimes also means the composition of smartphones, tablet terminals, personal computers, etc., including a main computer.

[0009] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected" to the second component, it may mean that the first component is directly connected to the second component, or it may mean that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is still "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is mentioned that the first component is "connected" "between" the second and third components, it sometimes means that the first, second and third components are connected in series, and the second component is connected to the third component via the first component.

[0011] Furthermore, in this specification, when it is mentioned that a circuit or the like "conducts" two wirings, for example, it sometimes means that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and that the transistor or the like is in an ON state.

[0012] Furthermore, in this specification, a specified direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0013] Furthermore, in this specification, the direction along the specified surface is sometimes referred to as the first direction, the direction along the specified surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specified surface is referred to as the third direction. The aforementioned first direction, second direction, and third direction may correspond to any one of the X direction, Y direction, and Z direction, or they may not correspond to each other.

[0014] Furthermore, in this specification, the terms "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Also, when referring to a component as a lower surface or lower end, it means the surface or end of that component on the substrate side; when referring to an upper surface or upper end, it means the surface or end of that component on the side opposite to the substrate. Also, the surface intersecting the X or Y direction is called a side surface, etc.

[0015] Furthermore, in this specification, when referring to "width", "length" or "thickness" in a specified direction regarding the structure, components, etc., it sometimes means the width, length or thickness in a cross section observed using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0016] Furthermore, in this specification, when "wiring" is mentioned, it sometimes includes wiring, through-hole contact electrodes, connecting parts for connecting wiring to through-hole contact electrodes, and bonding electrodes, etc.

[0017] [First Embodiment] [Circuit Configuration of Memory Diode MD] Figure 1 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figure 2 is a schematic circuit diagram showing a portion of the configuration of the memory die MD.

[0018] As shown in Figure 1, the memory chip MD includes a memory cell array MCA and peripheral circuitry PC. The peripheral circuitry PC includes a voltage generation circuit VG, a column decoder RD, a sense amplifier module SAM, and a sequencer SQC. Furthermore, the peripheral circuitry PC includes cache memory CM, address register ADR, instruction register CMR, and status register STR. Additionally, the peripheral circuitry PC includes input / output control circuitry I / O and logic circuitry CTR.

[0019] [Circuit Configuration of Memory Cell Array MCA] As shown in Figure 2, the memory cell array MCA has the aforementioned plurality of memory blocks BLK. Each of the plurality of memory blocks BLK has a plurality of string cells SU. Each of the plurality of string cells SU has a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to the peripheral circuit PC via a bit line BL. Furthermore, the other end of each of the plurality of memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0020] The memory string (MS) comprises a drain-side select transistor (STD), a plurality of memory cells (MCs) (memory transistors), and a source-side select transistor (STS). The drain-side select transistor (STD), the plurality of memory cells (MCs), and the source-side select transistor (STS) are connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side select transistor (STD) and the source-side select transistor (STS) are sometimes referred to simply as select transistors (STD, STS).

[0021] The memory cell MC is a field-effect transistor. The memory cell MC has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores one or more bits of data. Furthermore, word lines WL are connected to the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS. These word lines WL are commonly connected to all memory strings MS in one memory block BLK.

[0022] The select transistor (STD, STS) is a field-effect transistor. The select transistor (STD, STS) has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may also contain a charge storage layer. Select gate lines (SGD, SGS) are connected to the gate electrodes of the select transistor (STD, STS). One drain-side select gate line SGD is connected to all memory strings MS in one string cell SU. One source-side select gate line SGS is connected to all memory strings MS in one memory block BLK. Furthermore, sometimes the drain-side select gate line SGD and the source-side select gate line SGS are referred to as select gate lines SG.

[0023] [Structure of Memory Chip MD] FIG3 is a schematic exploded perspective view showing an example of the configuration of the semiconductor memory device according to the first embodiment. As shown in FIG3, the memory chip MD includes a chip CM on the memory cell array MCA side and a chip CP on the peripheral circuit PC side.

[0024] A plurality of external bonding pad electrodes PX, capable of connecting to bonding wires (not shown), are provided on the upper surface of the wafer CM. A plurality of bonding electrodes PI1 are provided on the lower surface of the wafer CM. A plurality of bonding electrodes PI2 are provided on the upper surface of the wafer CP. Hereinafter, regarding the wafer CM, the surface where the plurality of bonding electrodes PI1 are provided is referred to as the front side, and the surface where the plurality of external bonding pad electrodes PX are provided is referred to as the back side. Regarding the wafer CP, the surface where the plurality of bonding electrodes PI2 are provided is referred to as the front side, and the surface opposite to the front side is referred to as the back side. In the illustrated example, the front side of the wafer CP is positioned higher than the back side of the wafer CP, and the back side of the wafer CM is positioned higher than the front side of the wafer CM.

[0025] The wafer CM and the wafer CP are arranged with the front sides of the wafer CM and the wafer CP facing each other. A plurality of bonding electrodes PI1 are respectively provided corresponding to a plurality of bonding electrodes PI2, and are arranged at positions that can bond with the plurality of bonding electrodes PI2. The bonding electrodes PI1 and PI2 function as bonding electrodes for bonding the wafer CM and the wafer CP and making them electrically conductive.

[0026] Furthermore, in the example of Figure 3, the corners a1, a2, a3, and a4 of the wafer CM correspond to the corners b1, b2, b3, and b4 of the wafer CP, respectively.

[0027] Figure 4 is a schematic bottom view showing an example of the configuration of a chip CM. In Figure 4, the bonding electrode PI1 and other components are omitted. Figures 5 and 6 are schematic cross-sectional views showing a portion of the configuration of a memory die MD. Figure 7 is a schematic top view showing an example of the configuration of a chip CP. In Figure 7, the bonding electrode PI2 and other components are omitted.

[0028] [Structure of the Chip CM] In the example of Figure 4, the chip CM has four memory surfaces MP0 to MP3 arranged in the X direction. Furthermore, the four memory surfaces MP0 to MP3 are sometimes simply referred to as memory surfaces MP. Each of the four memory surfaces MP0 to MP3 has a plurality of memory blocks BLK arranged in the Y direction. In the example of Figure 4, each of the four memory surfaces MP0 to MP3 has a wiring area R HU located at both ends in the X direction, and a memory via area R MH (memory area) located between the wiring areas R HU. In the example of Figure 4, the memory via area R MH is divided into four regions R MHU in the X direction. The widths of these four regions R MHU in the X direction may all be the same or different. The chip CM also has a peripheral area RP located at one end further in the Y direction than the four memory surfaces MP0 to MP3.

[0029] Furthermore, in the illustrated example, the wiring area R HU is located at both ends of the memory surface MP in the X direction. However, this configuration is only an example, and the specific configuration can be adjusted appropriately. For example, the wiring area R HU may also be located at one end in the X direction, instead of at both ends of the memory surface MP in the X direction. Also, the wiring area R HU may be located at the center or near the center of the memory surface MP in the X direction.

[0030] For example, as shown in FIG5, the wafer CM includes a substrate layer L SB, a memory cell array layer L MCA disposed below the substrate layer L SB, a via contact electrode layer CH disposed below the memory cell array layer L MCA, a plurality of wiring layers M0, M1 disposed below the via contact electrode layer CH, and a wafer bonding electrode layer MB disposed below the wiring layers M0, M1.

[0031] [Structure of substrate layer L SB of chip CM] For example, as shown in FIG5, the substrate layer L SB includes a conductive layer 100 disposed on the upper surface of the memory cell array layer L MCA, an insulating layer 101 disposed on the upper surface of the conductive layer 100, a back wiring layer MA disposed on the upper surface of the insulating layer 101, and an insulating layer 102 disposed on the upper surface of the back wiring layer MA.

[0032] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) with implanted N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or may include metals such as tungsten (W), or may include silicon compounds such as tungsten silicon (WSi).

[0033] The conductive layer 100 functions as part of the source line SL (Fig. 2). Four conductive layers 100 are provided corresponding to the four memory surfaces MP0 to MP3 (Fig. 4). At the ends of the memory surfaces MP in the X and Y directions, regions VZ that do not contain the conductive layer 100 are provided.

[0034] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0035] The back wiring layer MA includes a plurality of wiring layers MA. These plurality of wiring layers MA may also include, for example, aluminum (Al).

[0036] A portion of the plurality of wiring ma functions as part of the source line SL (Figure 2). For example, four such wiring ma are provided corresponding to four memory surfaces. Each of these wiring ma is electrically connected to the conductive layer 100.

[0037] Furthermore, a portion of the plurality of wiring ma functions as an external bonding pad electrode PX. This wiring ma is disposed in the peripheral region RP. This wiring ma is connected to the via contact electrode CC in the memory cell array layer L MCA in the region VZ excluding the conductive layer 100. Furthermore, a portion of the wiring ma is exposed to the outside of the memory die MD through an opening TV disposed in the insulating layer 102.

[0038] The insulating layer 102 is, for example, a passivation layer containing insulating materials such as polyimide.

[0039] [Structure of the memory cell array layer L MCA of the chip CM in the wiring area R HU] As shown in Figure 6, a plurality of through-hole contact electrodes CC are provided in the wiring area R HU. The plurality of through-hole contact electrodes CC extend along the Z direction and are connected to the conductive layer 110 (WL, SGD, SGS) at their upper ends.

[0040] [Construction of the memory cell array layer L MCA in the peripheral region RP of the wafer CM] For example, as shown in Figure 5, a plurality of via contact electrodes CC are provided in the peripheral region RP, corresponding to the external pad electrode PX. The plurality of via contact electrodes CC are connected to the external pad electrode PX at their upper ends.

[0041] [Construction of via contact electrode layer CH] The via contact electrode layer CH contains a plurality of via contact electrodes ch, for example, in a configuration that is electrically connected to at least one of a memory cell array layer L MCA and a wafer CP.

[0042] The via contact electrode layer CH includes a plurality of via contact electrodes ch serving as a plurality of wirings. These plurality of via contact electrodes ch may, for example, comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes ch are disposed corresponding to a plurality of semiconductor layers 120 and are connected to the lower end of the plurality of semiconductor layers 120.

[0043] [Construction of wiring layers M0 and M1 of chip CM] The plurality of wirings contained in wiring layers M0 and M1 are, for example, electrically connected to at least one of the configurations in memory cell array layer L MCA and chip CP.

[0044] The wiring layer M0 comprises a plurality of wirings m0. These plurality of wirings m0 may, for example, comprise barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), a multilayer film of tantalum nitride (TaN) and tantalum (Ta), or a multilayer film of metal films such as copper (Cu). Furthermore, a portion of the plurality of wirings m0 functions as bit lines BL. The bit lines BL are, for example, arranged in the X direction and extending along the Y direction.

[0045] For example, as shown in Figure 5, the wiring layer M1 includes a plurality of wirings m1. These plurality of wirings m1 may also include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0046] [Construction of wafer bonding electrode layer MB] The wafer bonding electrode layer MB includes at least one of the following: a plurality of wirings electrically connected to the memory cell array layer L MCA and the wafer CP.

[0047] The wafer bonding electrode layer MB includes a plurality of bonding electrodes P I1 (bonding pads). These plurality of bonding electrodes P I1 may also include, for example, a stacked film of titanium nitride (TiN), tantalum nitride (TaN), tantalum nitride (TaN) and tantalum (Ta) as a barrier conductive film p I1B, and a stacked film of metal film p I1M such as copper (Cu).

[0048] [Structure of Chip CP] For example, as shown in FIG7, the chip CP has regions MP0' to MP3' that overlap with four memory surfaces MP0 to MP3 arranged in the X direction. Column control circuit regions R RC are respectively provided at both ends of these four regions MP0' to MP3' in the X direction. Furthermore, two block decoder regions R BD arranged in the X direction are provided between the two column control circuit regions R RC. Furthermore, a peripheral circuit region R PC is provided between the two block decoder regions R BD. Four row control circuit regions R CC arranged in the X and Y directions are provided in the peripheral circuit region R PC. Although not shown in the figure, circuits are also arranged in other areas of the peripheral circuit region R PC. Furthermore, a circuit region RC is provided in the area of ​​the chip CP opposite to the peripheral region RP (FIG. 4) of the chip CM.

[0049] For example, as shown in FIG5, the chip CP includes a semiconductor substrate 200, an electrode layer GC disposed above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, D4 disposed above the electrode layer GC, and a chip bonding electrode layer DB disposed above the wiring layers D0, D1, D2, D3, D4.

[0050] [Structure of Semiconductor Substrate 200 of Wafer CP] The semiconductor substrate 200 includes, for example, P-type silicon (Si) containing P-type impurities such as boron (B). The semiconductor substrate 200 has a main surface SM on the electrode layer GC and wiring layers D0, D1, D2, D3, and D4 sides. On the surface of the main surface SM of the semiconductor substrate 200, for example, an N-type diffusion layer 200N containing N-type impurities such as phosphorus (P), a P-type diffusion layer 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S without the N-type diffusion layer 200N and the P-type diffusion layer 200P, and an insulating layer STI are provided. A portion of the P-type diffusion layer 200P is provided in the semiconductor substrate region 200S, and a portion of the P-type diffusion layer 200P is provided in the N-type diffusion layer 200N. The N-type diffusion layer 200N, the P-type diffusion layer 200P disposed on the N-type diffusion layer 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S respectively function as a portion of a plurality of transistors Tr and a plurality of capacitors constituting the peripheral circuit PC. Furthermore, a portion of the plurality of transistors Tr functions as a word line switch WLSW and a gate selection line switch SGSW.

[0051] [Construction of Electrode Layer GC of Wafer CP] An electrode layer GC is disposed on the upper surface of semiconductor substrate 200, separated by an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc. Furthermore, each region of semiconductor substrate 200 and the plurality of electrodes gc included in electrode layer GC are respectively connected to via contact electrodes CS.

[0052] The N-type diffusion layer 200N of the semiconductor substrate 200, the P-type diffusion layer 200P disposed on the N-type diffusion layer 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S respectively function as channel regions for a plurality of transistors Tr constituting the peripheral circuit PC, and as electrodes of a plurality of capacitors. Furthermore, as shown in FIG6, a portion of the P-type diffusion layer 200P of the semiconductor substrate 200 functions as a first resistive element, namely a diffusion resistor R DIFF.

[0053] The plurality of electrodes gc contained in the electrode layer GC function as gate electrodes of the plurality of transistors Tr constituting the peripheral circuit PC, and as the other electrode of the plurality of capacitors. Furthermore, as shown in Figure 6, a portion of the plurality of electrodes gc contained in the electrode layer GC functions as a second resistive element, namely the GC resistor R GC.

[0054] The through-hole contact electrode CS extends along the Z direction and is connected at its lower end to the upper surface of the semiconductor substrate 200 or the electrode gc. The through-hole contact electrode CS may also include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0055] [Construction of wiring layers D0, D1, D2, D3, D4 of chip CP] For example, as shown in Figure 7, D0, D1, D2, D3, D4 contain at least one of the following: a plurality of connection portions and a plurality of wirings electrically connected to the memory cell array layer L MCA and the chip CP.

[0056] Wiring layers D0, D1, and D2 each include a plurality of connection portions d0, d1, d2 and a plurality of wirings. These plurality of connection portions d0, d1, d2 and wirings may also include, for example, stacked films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W).

[0057] Wiring layers D3 and D4 each include a plurality of connection portions d3 and d4 and a plurality of wirings. These plurality of connection portions d3 and d4 and wirings may, for example, include barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), a multilayer film of tantalum nitride (TaN) and tantalum (Ta), and multilayer films of metal films such as copper (Cu).

[0058] [Construction of wafer bonding electrode layer DB] The wafer bonding electrode layer DB contains at least one of the following: a plurality of wirings electrically connected to the memory cell array layer L MCA and the wafer CP.

[0059] The wafer bonding electrode layer DB includes a plurality of bonding electrodes P I2. These plurality of bonding electrodes P I2 may also include, for example, a stacked film of titanium nitride (TiN), tantalum nitride (TaN), tantalum nitride (TaN) and tantalum (Ta) as a barrier conductive film p I2B, and a stacked film of metal film p I2M such as copper (Cu).

[0060] Furthermore, if metal films such as copper (Cu) pI1M and pI2M are used for bonding electrodes PI1 and PI2, the metal films pI1M and pI2M will become integrated, making it difficult to determine their boundaries. However, the bonding structure can be determined by the deformation of the shape of the bonding electrodes PI1 and PI2 after bonding due to the positional shift of the bonding, and the positional shift of the blocking conductive films pI1B and pI2B (creating discontinuous parts on the side). Also, when bonding electrodes PI1 and PI2 are formed by the inlay method, their respective side surfaces have an inclined shape. Therefore, regarding the cross-sectional shape along the Z direction of the portion after bonding electrodes PI1 and PI2 are bonded, the sidewalls are not straight, but non-rectangular. Furthermore, when bonding electrodes PI1 and PI2 are bonded together, the bottom, side, and top surfaces of each Cu electrode are covered by a barrier metal. In contrast, in conventional Cu wiring layers, an insulating layer (SiN or SiCN, etc.) that prevents Cu oxidation is provided on the top surface of the Cu electrode, but no barrier metal is provided. Therefore, even if no positional shift occurs during bonding, it can be distinguished from conventional wiring layers.

[0061] [Patterns of diffusion resistor R DIFF and GC resistor R GC] Figure 8 is a top view of circuit region A in the peripheral circuit region R PC shown in Figure 7, after being enlarged. Furthermore, this circuit region A can also be set in other regions such as the peripheral region RP.

[0062] Circuit region A includes three circuit modules MDA, MDB, and MDC, and a resistor element region RES disposed around them. In the resistor element region RES, a diffusion resistor R DIFF is formed as a first resistor element, and a GC resistor R GC is formed as a second resistor element. The diffusion resistor R DIFF and the GC resistor R GC are connected to the three circuit modules MDA, MDB, and MDC as part of the circuit elements. Furthermore, the number and configuration of the circuit modules are not limited to the number and configuration illustrated.

[0063] Figures 9 and 10 are diagrams showing the patterns of the diffusion resistor R DIFF and the GC resistor R GC of the first embodiment. Figure 9 is an enlarged top view of the circuit region B in the resistor element region RES of Figure 8. Figure 10 is a cross-sectional view taken along line C-C' of Figure 9 and viewed from the direction of the arrow.

[0064] The resistor circuit of this embodiment includes a semiconductor substrate 200 and an electrode layer GC disposed on the main surface SM side of the semiconductor substrate 200. A plurality of diffusion resistors R DIFF are provided on the main surface SM side of the semiconductor substrate 200. In this example, the plurality of diffusion resistors R DIFF includes a plurality of P-type diffusion layers 200P formed in an N-type diffusion layer 200N (N-type well). The plurality of diffusion resistors R DIFF extend along a Y direction parallel to the main surface SM of the semiconductor substrate 200, and are arranged at a predetermined distance P1 along an X direction parallel to the main surface SM of the semiconductor substrate 200 and intersecting the Y direction. Each diffusion resistor R DIFF has a first connection terminal T DIFF at its end side in the Y direction, for example, at both ends.

[0065] An insulating layer STI is provided between a plurality of diffusion resistors R DIFF on the semiconductor substrate 200. The insulating layer STI surrounds the side surfaces of each of the plurality of diffusion resistors R DIFF along the X and Y directions, insulating the plurality of diffusion resistors R DIFF from each other. The electrode layer GC side of the insulating layer STI functions as an electrode mounting surface SG. The electrode mounting surface SG protrudes from the upper surface (main surface SM) of the diffusion resistor R DIFF to a position where it contacts the lower surface of the electrode layer GC.

[0066] The electrode layer GC has a plurality of GC resistors R GC on the electrode setting surface SG of the insulating layer STI between the plurality of diffusion resistors R DIFF. Furthermore, in FIG9, the GC resistors R GC are shown with additional shading to distinguish them from the diffusion resistors R DIFF. The same applies to FIG18, FIG20, FIG22, FIG24 and FIG25. The plurality of GC resistors R GC extend along the Y direction on the electrode setting surface SG of the insulating layer STI and are arranged along the X direction at a predetermined distance P1 that is substantially equal to that between the plurality of diffusion resistors R DIFF. Each GC resistor R GC has a second connection terminal T GC at its end side in the Y direction, for example at both ends.

[0067] In this embodiment, a plurality of diffusion resistors R DIFF and a plurality of GC resistors R GC are arranged alternately in the X direction.

[0068] Furthermore, in this embodiment, the width W1 of the diffusion resistor R DIFF in the X direction is greater than the width W2 of the GC resistor R GC in the X direction. Also, the width W3 of the insulating layer STI in the X direction is greater than the width W2 of the GC resistor R GC in the X direction. However, the widths W1 and W2 can also be substantially equal.

[0069] [Effects of this embodiment] On the surface of the semiconductor substrate 200, the area covered by the electrode gc (hereinafter referred to as "GC coverage") and the area not covered by the electrode gc (hereinafter referred to as "AA coverage") of the aforementioned certain area must be ensured to be 15% to 30% or more respectively to prevent unevenness in planarization processing. Assuming that only a pattern of diffusion resistor R DIFF is formed in the resistor element region RES, a filling pattern of electrode gc must be formed around the diffusion resistor R DIFF to ensure the required GC coverage. Similarly, assuming that only a pattern of GC resistor R GC is formed in the resistor element region RES, a filling pattern of the area without electrode gc must be formed around the GC resistor R GC to ensure the required AA coverage. In this case, in any instance, an additional filling area other than the resistor element is required, and correspondingly, there is a problem of increased cell size.

[0070] In contrast, in this embodiment, the diffusion resistor R DIFF and the GC resistor R GC are configured alternately, so that the GC coverage rate and AA coverage rate can be satisfied simultaneously without setting a filling area. Therefore, the area of ​​the resistor element region RES can be reduced.

[0071] [Variation of the First Embodiment] FIG11 is a cross-sectional view corresponding to FIG10 of a variation of the first embodiment. In this variation, the width W2 of the electrode setting surface SG of the insulating layer STI in the X direction is substantially equal to the width W2 of the GC resistor R GC in the X direction. In this case, since the electrode setting surface SG of the insulating layer STI protrudes a distance D further towards the electrode layer GC than the upper surface (main surface SM) of the diffusion resistor R DIFF, the GC resistor R GC and the diffusion resistor R DIFF can also be arranged spaced apart from each other. Therefore, mutual insulation is ensured. According to this variation, the distance P1' between the GC resistor R GC and the diffusion resistor R DIFF in the X direction can be made smaller than the distance P1 in the first embodiment, and the wafer area can be further reduced.

[0072] [Manufacturing Method of Diffusion Resistor R DIFF and GC Resistor R GC] Figures 12 to 17 are cross-sectional views illustrating the manufacturing method of diffusion resistor R DIFF and GC resistor R GC according to this embodiment. Figures 12 to 17 show the resistive element region RES in the peripheral circuit region R PC, and other regions, such as the memory via region R MH, which are regions for forming transistor Tr.

[0073] When manufacturing the diffusion resistor R DIFF and the GC resistor R GC, for example as shown in FIG12, an insulating layer 200G is formed on the surface of a semiconductor substrate 200 on which an N-type diffusion layer 200N (N-type well) is selectively formed in advance. This step is performed, for example, by thermal oxidation.

[0074] Next, as shown in FIG13, for example, an opening 200A is formed at a position corresponding to the insulating layer STI described with reference to FIG10. The opening 200A extends along the Z and Y directions, and extends along the X direction at both ends of the Y direction. The opening 200A penetrates the insulating layer 200G and the N-type diffusion layer 200N in the Z direction, dividing a portion of the surface of the semiconductor substrate 200. This step is performed, for example, by a method such as RIE.

[0075] Next, for example, as shown in FIG14, an insulating layer 200H is formed on the semiconductor substrate 200. This step is performed, for example, by CVD. Here, the opening 200A is embedded in the insulating layer 200H.

[0076] Next, for example as shown in FIG15, a portion of the insulating layer 200H is removed until the surface of the insulating layer 200G is exposed, forming an insulating layer STI having an electrode mounting surface SG. This step is performed, for example, by a method such as CMP.

[0077] Next, as shown in FIG16, a conductive layer gcA comprising polycrystalline silicon or tungsten (W), or a two-layer conductive layer gcA comprising polycrystalline silicon and tungsten (W), is formed on the surface of the insulating layer STI and the insulating layer 200G. This step is performed, for example, by CVD, thermal oxidation, or sputtering.

[0078] Next, for example as shown in FIG17, a portion of the conductive layer gcA is removed to expose the surface of the semiconductor substrate 200, thereby forming a plurality of electrodes gc. This step is performed, for example, by means of a RIE (Radio Interchange Electrode).

[0079] Accordingly, in the resistive element region RES, on the electrode setting surface SG of the insulating layer STI, a GC resistor R GC containing an electrode gc is formed. Also, in the memory hole region R MH, in the region where the transistor Tr is formed, a gate containing an electrode gc is formed on the insulating layer 200G.

[0080] Next, boron (B) and other P-type impurities are implanted onto the surface of the N-type diffusion layer 200N of the exposed semiconductor substrate 200. This step is performed, for example, by ion implantation.

[0081] Accordingly, in the resistive element region RES, an N-type diffusion layer 200N formed of a P-type diffusion layer is formed in the insulating layer STI, and a diffusion resistor R DIFF is formed therein. Also, in the region of the memory hole region R MH where the transistor Tr is formed, P-type diffusion layers serving as drain and source electrodes are formed on both sides of the gate electrode gc in the Y direction.

[0082] [Second Embodiment] Figures 18 and 19 are diagrams showing the patterns of the diffusion resistor R DIFF and the GC resistor R GC in the second embodiment. Figure 18 is an enlarged top view of the region corresponding to the region shown in Figure 9. Figure 19 is a cross-sectional view taken from the direction of the arrow, cut along line D-D' in Figure 18.

[0083] In this embodiment, the diffusion resistors R DIFF and GC resistors R GC are arranged alternately in a plurality of units (in this example, in units of 6) in the X direction. The width W4 of the insulating layer STI between adjacent diffusion resistors R DIFF in the X direction is set to be smaller than the width W2 of the GC resistor R GC in the X direction and to be the minimum width that can insulate the diffusion resistors R DIFF. The insulating layer STI for arranging the GC resistors R GC is set to be larger than the width W4 and to be able to accommodate 6 GC resistors R GC.

[0084] Diffusion resistors R DIFF are arranged in the X direction with a predetermined spacing P2, and GC resistors R GC are arranged in the X direction with a predetermined spacing P3. When the width W2 of the GC resistors R GC in the X direction is smaller than the width W1 of the diffusion resistors R DIFF in the X direction, as long as the spacing between the diffusion resistors R DIFF and the GC resistors R GC in the X direction is a certain width, the spacing P3 can be made smaller than the spacing P2. Furthermore, the spacing P2 between the diffusion resistors R DIFF and the spacing P3 between the GC resistors R GC can also be the same. Regarding other configurations, since they are the same as in the first embodiment, detailed descriptions of repeated parts are omitted.

[0085] In this embodiment, in addition to the same effects as in the first embodiment, since a plurality of diffusion resistors R DIFF and a plurality of GC resistors R GC are alternately arranged in units of a plurality, the connection pattern can be simplified according to the shape of the connection wiring pattern for the circuit unit to be connected. Furthermore, the number of diffusion resistors R DIFF and GC resistors R GC arranged in units of a plurality is not limited to 6, and can be arbitrarily determined within the range of satisfying the AA coverage rate and GC coverage rate.

[0086] [Third Embodiment] Figures 20 and 21 are diagrams showing the patterns of the diffusion resistor R DIFF and the GC resistor R GC according to the third embodiment. Figure 20 is an enlarged top view of the region corresponding to the region shown in Figure 9. Figure 21 is a cross-sectional view taken from the direction of the arrow, cut along line E-E' of Figure 20.

[0087] In this embodiment, three diffusion resistors R DIFF and one GC resistor R GC are alternately arranged in the X direction. The width W4 of the insulating layer STI between adjacent diffusion resistors R DIFF in the X direction is set to be smaller than the width W2 of the GC resistor R GC in the X direction and to be the minimum width that can insulate the diffusion resistors R DIFF. The insulating layer STI for arranging the GC resistor R GC is set to be larger than the width W4 and to be able to accommodate the width W3 of one GC resistor R GC. Regarding other configurations, since they are the same as in the first embodiment, detailed descriptions of repeated parts are omitted.

[0088] Alternatively, as in this embodiment, different numbers of diffusion resistors R DIFF and GC resistors R GC can be alternately configured. In this embodiment, when more diffusion resistors R DIFF are used than GC resistors R GC, it can be used as a pattern. In this case, there is no need to provide a fill area, thus reducing the area of ​​the resistor element region RES.

[0089] [Fourth Embodiment] Figures 22 and 23 are diagrams showing the patterns of the diffusion resistor R DIFF and the GC resistor R GC according to the fourth embodiment. Figure 22 is an enlarged top view of the region corresponding to the region shown in Figure 9. Figure 23 is a cross-sectional view taken from the direction of the arrow, cut along line F-F' of Figure 22.

[0090] In this embodiment, one diffusion resistor R DIFF and three GC resistors R GC are alternately arranged in the X direction. The insulating layer STI for arranging the GC resistors R GC is set to a width W6 that allows the three GC resistors R GC to be arranged. Regarding other configurations, since they are the same as in the first embodiment, detailed descriptions of repeated parts are omitted.

[0091] As in this embodiment, different numbers of diffusion resistors R DIFF and GC resistors R GC can also be alternately configured. In this embodiment, when more GC resistors R GC are used than diffusion resistors R DIFF, it can be used as a pattern. In this case, there is no need to provide a fill area, thus reducing the area of ​​the resistor element region RES.

[0092] [Fifth Embodiment] FIG24 is a diagram showing the patterns of the diffusion resistor R DIFF and the GC resistor R GC in the fifth embodiment. FIG24 is an enlarged top view of the area corresponding to the area shown in FIG9.

[0093] In this embodiment, a plurality of diffusion resistors R DIFF and a plurality of GC resistors R GC are arranged alternately in the X direction. The length L1 of the diffusion resistor R DIFF in the Y direction is less than the length L2 of the GC resistor R GC in the Y direction. At one end of the plurality of diffusion resistors R DIFF in the Y direction, they are connected in series via a wiring W DIFF extending in the X direction that connects the odd-numbered first connection terminal T DIFF and the first connection terminal T DIFF adjacent to it on one side in the X direction. At the other end of the Y direction, they are connected in series via a wiring W DIFF extending in the X direction that connects the even-numbered first connection terminal T DIFF and the first connection terminal T DIFF adjacent to it on one side in the X direction. A plurality of GC resistors R GC are connected in series at one end in the Y direction via a wiring W GC extending in the X direction that connects the odd-numbered second connection terminal T GC to the adjacent second connection terminal T GC on the X direction side. At the other end in the Y direction, they are connected in series via a wiring W GC extending in the X direction that connects the even-numbered second connection terminal T GC to the adjacent second connection terminal T GC on the X direction side. Regarding other configurations, since they are the same as in the first embodiment, detailed descriptions of repeated parts are omitted.

[0094] As in this embodiment, the diffusion resistor R DIFF and the GC resistor R GC may not be of the same length. For example, the length L1 of the diffusion resistor R DIFF in the Y direction may be longer than the length L2 of the GC resistor R GC in the Y direction. Furthermore, by connecting the diffusion resistor R DIFF and the GC resistor R GC in series with each other, a resistive element with the desired resistance value can be provided.

[0095] [Sixth Embodiment] FIG25 is a diagram showing the patterns of the diffusion resistor R DIFF and the GC resistor R GC in the sixth embodiment. FIG25 is an enlarged top view of the area corresponding to the area shown in FIG9.

[0096] In this embodiment, when viewed from the Z direction, a plurality of diffusion resistors R DIFF and a plurality of GC resistors R GC are alternately arranged in the X direction. At one end in the Y direction, the plurality of diffusion resistors R DIFF and the plurality of GC resistors R GC are connected in series alternately via a wiring WDG extending in the X direction, which is adjacent to each other and connects the second connection terminal T GC located in one direction to the first connection terminal T DIFF located in the other direction. At the other end in the Y direction, they are connected in series alternately via a wiring WDG extending in the X direction, which is adjacent to each other and connects the first connection terminal T DIFF located in one direction to the second connection terminal T GC located in the other direction. Regarding other configurations, since they are the same as in the first embodiment, detailed descriptions of repeated parts are omitted.

[0097] According to this embodiment, by alternately connecting the diffusion resistor R DIFF and the GC resistor R GC in series, a resistive element having a desired resistance value can be provided.

[0098] [Other Embodiments] The semiconductor memory devices of the first to sixth embodiments have been described above. However, the configurations described above are merely examples, and the specific configurations can be adjusted appropriately.

[0099] For example, in the above embodiments, a P-type diffusion layer 200P formed in an N-type diffusion layer 200N (N-type well) is used as the diffusion resistor R DIFF. However, an N-type diffusion layer 200N formed in a P-type diffusion layer 200P (P-type well) may also be used as the diffusion resistor R DIFF.

[0100] Furthermore, the diffusion resistor R DIFF and GC resistor R GC shown in the above embodiments can also be used as a part of the dummy resistors not connected to any circuit.

[0101] Furthermore, in the above embodiments, an example applied to NAND flash memory has been described. However, the technology described in this specification can also be applied to configurations other than NAND flash memory, such as three-dimensional NOR flash memory. Furthermore, the technology described in this specification can also be applied to semiconductor memory devices other than flash memory, such as three-dimensional DRAM, and semiconductor devices other than semiconductor memory devices.

[0102] [Other] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents. [Simplified Explanation of the Diagram]

[0005] Figure 1 is a schematic block diagram showing the structure of the memory chip MD according to the first embodiment. Figure 2 is a schematic circuit diagram showing a partial structure of the memory chip MD. Figure 3 is a schematic exploded perspective view showing an example of the structure of the memory chip MD. Figure 4 is a schematic bottom view showing an example of the structure of the chip CM. Figure 5 is a schematic cross-sectional view showing a partial structure of the memory chip MD. Figure 6 is a schematic cross-sectional view showing a partial structure of the memory chip MD. Figure 7 is a schematic top view showing an example of the structure of the chip CP. Figure 8 is a schematic top view showing an enlarged view of circuit region A in the peripheral circuit region RPC shown in Figure 7. Figure 9 is a top view showing the diffusion resistor R DIFF and GC resistor R GC according to the first embodiment. Figure 10 is a cross-sectional view showing the diffusion resistor R DIFF and GC resistor R GC according to the first embodiment. Figure 11 is a cross-sectional view corresponding to Figure 10 of a variation of the first embodiment. Figure 12 is a cross-sectional view illustrating the manufacturing method of the diffusion resistor R DIFF and GC resistor R GC according to this embodiment. Figure 13 is a cross-sectional view illustrating the manufacturing method of the diffusion resistor R DIFF and GC resistor R GC according to this embodiment. Figure 14 is a cross-sectional view illustrating the manufacturing method of the diffusion resistor R DIFF and GC resistor R GC according to this embodiment. Figure 15 is a cross-sectional view illustrating the manufacturing method of the diffusion resistor R DIFF and GC resistor R GC according to this embodiment. Figure 16 is a cross-sectional view illustrating the manufacturing method of the diffusion resistor R DIFF and GC resistor R GC according to this embodiment. Figure 17 is a cross-sectional view illustrating the manufacturing method of the diffusion resistor R DIFF and GC resistor R GC according to this embodiment. Figure 18 is a top view showing the diffusion resistor R DIFF and GC resistor R GC according to the second embodiment. Figure 19 is a cross-sectional view showing the diffusion resistor R DIFF and GC resistor R GC according to the second embodiment. Figure 20 is a top view of the diffusion resistor R DIFF and the GC resistor R GC according to the third embodiment. Figure 21 is a cross-sectional view of the diffusion resistor R DIFF and the GC resistor R GC according to the third embodiment. Figure 22 is a top view of the diffusion resistor R DIFF and the GC resistor R GC according to the fourth embodiment. Figure 23 is a cross-sectional view of the diffusion resistor R DIFF and the GC resistor R GC according to the fourth embodiment. Figure 24 is a top view of the diffusion resistor R DIFF and the GC resistor R GC according to the fifth embodiment. Figure 25 is a top view of the diffusion resistor R DIFF and the GC resistor R GC according to the sixth embodiment.

Claims

1. A semiconductor device comprising: a semiconductor substrate having a main surface including a first direction and a second direction intersecting the first direction; an electrode layer disposed on the main surface side; a plurality of first resistive elements, each comprising: a plurality of diffusion layers disposed on the main surface side of the semiconductor substrate, extending in the first direction and arranged in the second direction, and each having a first connection terminal portion at an end side in the first direction; and an insulating layer disposed on the main surface side of the semiconductor substrate between each of the plurality of first resistive elements, having an electrode mounting surface in contact with the electrode layer; and the electrode layer comprising: a plurality of second resistive elements, each comprising: a plurality of conductive layers disposed on the electrode mounting surface of the insulating layer between the plurality of first resistive elements, extending in the first direction and arranged in the second direction, and each having a second connection terminal portion at an end side in the first direction.

2. The semiconductor device of claim 1, wherein the plurality of first resistive elements and the plurality of second resistive elements are arranged alternately in the second direction.

3. The semiconductor device of claim 1, wherein the plurality of first resistive elements and the plurality of second resistive elements are alternately arranged in a plurality of units in the second direction.

4. The semiconductor device of claim 1, wherein one of the plurality of second resistive elements is disposed between a portion of the plurality of first resistive elements and another portion of the plurality of first resistive elements.

5. The semiconductor device of claim 1, wherein one of the plurality of first resistive elements is disposed between a portion of the plurality of second resistive elements and another portion of the plurality of second resistive elements.

6. The semiconductor device of claim 1, wherein the plurality of diffusion layers are P-type diffusion layers.

7. The semiconductor device of claim 1, wherein the plurality of diffusion layers are N-type diffusion layers.

8. The semiconductor device of claim 1, wherein at least two of the plurality of first resistive elements are electrically connected in series via the first connection terminal portion, and at least two of the plurality of second resistive elements are electrically connected in series via the second connection terminal portion.

9. The semiconductor device of claim 1, wherein at least two of the plurality of first resistive elements and at least two of the plurality of second resistive elements are alternately connected in series via the first connection terminal portion and the second connection terminal portion.

10. The semiconductor device of claim 1, further comprising: a transistor having a gate electrode, wherein the electrode layer further comprises the gate electrode.

11. The semiconductor device of claim 1, wherein the electrode mounting surface of the insulating layer protrudes further toward the electrode layer than the main surface of the semiconductor substrate.

12. The semiconductor device of claim 11, wherein the width of the electrode mounting surface of the insulating layer in the second direction is equal to the width of the second resistive element in the second direction.

13. The semiconductor device of claim 1, wherein the width of the first resistive element in the second direction is greater than the width of the second resistive element in the second direction.

14. The semiconductor device of claim 3, wherein the distance between the plurality of first resistive elements in the second direction is greater than the distance between the plurality of second resistive elements in the second direction.

15. The semiconductor device of claim 1, wherein the length of the first resistive element in the first direction is different from the length of the second resistive element in the first direction.

16. A semiconductor device comprising: a memory cell array layer; a semiconductor substrate having a main surface facing the memory cell array layer, the main surface extending in a first direction and a second direction intersecting the first direction, and having formed at least a portion of a peripheral circuit for controlling the memory cell array layer; and an electrode layer disposed between the main surface of the memory cell array layer and the semiconductor substrate; wherein the peripheral circuit has a resistive element region, the resistive element region comprising: a plurality of first resistive elements, each comprising: a plurality of diffusion layers disposed on the main surface side of the semiconductor substrate, extending in the first direction and arranged in the second direction, and each having a first connection terminal portion at an end side in the first direction; and an insulating layer disposed on the main surface side of the semiconductor substrate between each of the plurality of first resistive elements, having an electrode placement surface connected to the electrode layer; and the electrode layer comprising: A plurality of second resistive elements, each comprising: a plurality of conductive layers, an electrode mounting surface of the insulating layer disposed between the plurality of first resistive elements, extending in the first direction and arranged in the second direction, and each having a second connection terminal portion at its end in the first direction.

17. The semiconductor device of claim 16, wherein the peripheral circuitry further comprises: a transistor having a gate electrode, and the electrode layer further comprising the gate electrode.

18. The semiconductor device of claim 16, wherein the electrode mounting surface of the insulating layer protrudes further toward the electrode layer than the main surface of the semiconductor substrate.

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