Semiconductor structure and method of forming the same

Abstract

The method includes providing a structure. The structure includes a substrate; a first stack of staggered first channel layers and a first sacrificial layer on the substrate; a first source / drain trench exposing the sidewalls of the first sacrificial layer; a second stack of staggered second channel layers and a second sacrificial layer on the substrate; and a second source / drain trench exposing the sidewalls of the second sacrificial layer. The method further includes performing a first etching process to selectively remove the first and second sacrificial layers; performing a second etching process on the first channel layer but not the second channel layer; forming a first source / drain structure in the first source / drain trench and forming a second source / drain structure in the second source / drain trench; and forming a first gate structure to cover the first channel layer and forming a second gate structure to cover the second channel layer.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to semiconductor structures in which the thickness of the channel components in different regions varies. Prior Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per unit wafer area) typically increases as the geometry (i.e., the smallest component (or line) that the manufacturing process can produce) shrinks. Shrinking processes generally facilitate increased production capacity and reduced associated costs.

[0003] The shrinking size of integrated circuits also increases the complexity of handling and manufacturing them. Integrated circuits include various circuit components such as transistors. Transistors with different configurations have different performance characteristics and are suitable for different circuit functions. Although existing transistors and their fabrication methods are generally suitable for the intended purpose, they cannot meet all the requirements. Summary of the Invention

[0004] An embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes providing a structure. The structure includes a substrate; a first stack of staggered first channel layers and a first sacrificial layer is located on the substrate; a first source / drain trench exposes the sidewalls of the first sacrificial layer; a second stack of staggered second channel layers and a second sacrificial layer is located on the substrate; and a second source / drain trench exposes the sidewalls of the second sacrificial layer. The method further includes performing a first etching process to selectively remove the first and second sacrificial layers; performing a second etching process on the first channel layers but not the second channel layers; forming a first source / drain structure in the first source / drain trench and forming a second source / drain structure in the second source / drain trench; and forming a first gate structure to cover the first channel layer and forming a second gate structure to cover the second channel layer.

[0005] Another exemplary embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes forming a first region and a second region on a substrate. The first region includes a first stack of interleaved first channel layers and a first sacrificial layer, and the second region includes a second stack of interleaved second channel layers and a second sacrificial layer. The method further includes forming a first dummy gate structure on the first stack of interleaved first channel layers and first sacrificial layers, and forming a second dummy gate structure on the second stack of interleaved second channel layers and second sacrificial layers; forming a first source / drain recess in the first stack of interleaved first channel layers and first sacrificial layers adjacent to the first dummy gate structure; forming a second source / drain recess in the second stack of interleaved second channel layers and second sacrificial layers adjacent to the second dummy gate structure; selectively removing the first and second sacrificial layers to release the first channel layers and second sacrificial layers. A second channel layer; forming a masking layer on the second region instead of the first region; removing a portion of the first channel layer to reduce the thickness of the first channel layer; removing the masking layer; depositing a first dummy layer around the first channel layer, and depositing a second dummy layer around the second channel layer; forming a first source / drain structure in the first source / drain recess, and forming a second source / drain structure in the second source / drain recess; and replacing the first dummy gate structure and the first dummy layer to form a first metal gate structure, and replacing the second dummy gate structure and the second dummy layer to form a second metal gate structure.

[0006] Another exemplary embodiment of the present invention relates to a semiconductor structure. The semiconductor structure includes a substrate; a first stack of a plurality of first channel layers located on the substrate; a first source / drain structure connected to the first stack of the first channel layers; a second stack of a plurality of second channel layers located on the substrate; a second source / drain structure connected to the second stack of the second channel layers; and a metal gate structure covering the first channel layers and extending along a direction in its length direction. At least one of the first channel layers has a first thickness and a first width along the direction, and at least one of the second channel layers has a second thickness and a second width along the direction, the second thickness being greater than the first thickness and the second width being less than or equal to the first width. Simple Explanation of the Diagram

[0007] Figure 1 is a flowchart of a method for forming a semiconductor structure in one or more embodiments of the present invention. Figures 2A and 2B are simplified block diagrams of semiconductor structures containing structures fabricated according to the method of Figure 1 in various embodiments of the present invention. Figures 3, 4, 5, 6, 7, 8, 9, 10A, 10B, 11A, 11B, 12A, 12B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A, and 21B are partial cross-sectional views of an exemplary semiconductor structure at various fabrication stages in the method of Figure 1, according to one or more embodiments of the present invention. Figures 13A and 13B are further enlarged views of portions of the exemplary semiconductor structure in Figure 12A in one or more embodiments of the present invention. Figure 22 is an exemplary circuit diagram of a static random access memory unit in various embodiments of the present invention. Figure 23 is a partial layout diagram of the static random access memory unit in various embodiments of the present invention. Figures 24A and 24B are partial top views of other semiconductor structures at various fabrication stages in the method of Figure 1 in one or more embodiments of the present invention. Figure 25 is a partial cross-sectional view of other semiconductor structures along section line C-C' in Figure 24A in one or more embodiments of the present invention. Figures 26 and 27 are partial top views of other semiconductor structures at various fabrication stages in the method of Figure 1 in one or more embodiments of the present invention. Figures 28 and 29 are partial cross-sectional views of other semiconductor structures along the sections C-C' and D-D' in Figure 26, respectively, in one or more embodiments of the present invention. Figures 30A and 30B are partial top views of other semiconductor structures at various fabrication stages in the method of Figure 1 in one or more embodiments of the present invention. Figure 31 is a partial cross-sectional view of other semiconductor structures along section line C-C' in Figure 30A in one or more embodiments of the present invention. Figure 32 is another exemplary circuit diagram of a static random access memory unit in various embodiments of the present invention. Implementation

[0008] The following detailed description, accompanied by accompanying drawings, will aid in understanding various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity of explanation.

[0009] The different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The specific components and arrangements described are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes situations where the two are in direct contact, or where there are additional components between them that are not in direct contact.

[0010] Furthermore, while the same reference numerals may be used repeatedly in various embodiments of the present invention for brevity, elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence. Additionally, embodiments forming a structure on another structure, connecting a structure to another structure, and / or coupling a structure to another structure may include structures in direct contact, or structures may be spaced apart by other structures without direct contact. Furthermore, spatial relative terms such as "below," "lower," "above," "higher," or similar terms are used to describe the relationship between some elements or structures in the drawings and another element or structure. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. Furthermore, when numerical values ​​or ranges are described with terms such as "about," "approximately," or similar terms, it is intended to cover values ​​within a reasonable range, such as inherent variations arising during the manufacturing process, as considered by those skilled in the art. For example, based on known manufacturing tolerances related to the numerical value, the numerical value or range covers a reasonable range including the number, for example, within + / - 10% of the number. For example, when the thickness of the material layer is about 5 nm and those skilled in the art know that the permissible range for the fabrication of the deposited material layer is 15%, the size range it contains is 4.25 nm to 5.75 nm.

[0011] Static Random Access Memory (SRAM) is a type of semiconductor memory that retains data statically when powered on. Unlike Dynamic Random Access Memory (DRAM), SRAM is faster, more reliable, and does not require continuous updates. Semiconductor devices such as SRAM macros can include memory cells in memory cell areas and logic cells in logic cell areas. Memory cells can also be considered bit cells and can be configured to store memory bits. Memory cells can be configured in columns and rows to form an array. Logic cells can be standard cells such as inverters, AND, OR, NAND, NOR, flip-flops, SCAN, and similar cells. Logic cell areas are adjacent to memory cell areas and are configured to implement various logic functions. As integrated circuit technology moves towards smaller technology nodes, multi-gate structures such as fin field-effect transistors (FETs) or fully wound gate transistors (WWTs) are integrated into SRAM cells to improve performance.

[0012] Fully wound gate transistors can also be considered as nanosheet transistors or nanowire transistors, and can be n-type or p-type. The channel region of a fully wound gate transistor is located in a nanowire channel assembly, a rod-shaped channel assembly, a nanosheet channel assembly, a nanostructure channel assembly, a bridge-shaped channel assembly, and / or other suitable channel configurations.

[0013] In some existing technologies, methods for forming fully wound gate transistors include forming several interleaved channel layers and several sacrificial layers, and performing a channel release process to selectively remove the sacrificial layers and release the channel layers as channel components. However, the high uniformity of the sheet-like structure of the channel layers limits further reduction in the size of fully wound gate transistors. While existing technologies generally meet their intended purpose, they cannot satisfy all requirements.

[0014] This invention provides a method for forming a semiconductor structure. The semiconductor structure includes a first region and a second region. In some embodiments, the first region includes a memory region, and the second region includes a peripheral region. In an example of the process, a fin structure having a channel layer and a sacrificial layer is formed in each of the first and second regions. After forming a dummy gate stack on the channel region of the fin structure, at least one gate spacer is formed on the dummy gate stack. The source / drain regions of the fin structure are recessed. The sacrificial layer is selectively removed to release the channel layer as a channel component. In some embodiments, a mask layer is then formed in the second region, exposing the first region. The channel component in the area covered by the mask layer (such as the first region) is etched to reduce the channel thickness. The mask layer is then removed from the second region. A dummy layer may be deposited around the channel component. After forming the inner spacer structure and the source / drain structure, the dummy gate stack and the dummy layer are selectively removed to release the channel component again. Additional processes are then performed to complete the fabrication of the semiconductor structure. In some other embodiments, the first region includes a sub-region in which a p-type transistor is formed, and a masking layer is formed in the sub-region and the second region. In some other embodiments, the first region includes a sub-region in which a pull-down transistor for static random access memory and a p-type transistor are formed, and a masking layer is formed in the sub-region and the second region. In some other embodiments, the first region includes a sub-region in which an n-type transistor is formed, and a masking layer is formed in the sub-region and the second region. By forming a masking layer on a specific region and performing an etching process on the channel components in the uncovered region, the thickness of the channel components in different regions of the semiconductor structure can be different, and the performance of different regions can be improved, thereby improving the overall performance of the semiconductor structure.

[0015] Various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this regard, FIG1 is a flowchart of a method 100 for forming a semiconductor structure according to an embodiment of the present invention. Method 100 will be described below with reference to FIGS. 2A to 21B. FIGS. 2A and 2B are simplified block diagrams of a structure 10 containing a semiconductor structure fabricated according to method 100 of FIG1 in the embodiments. FIGS. 3 to 21B are partial cross-sectional views of structure 10 at different fabrication stages of method 100 in FIG1 in the embodiments. FIG. 22 is an exemplary circuit diagram of a static random access memory cell in various embodiments of the present invention. FIG. 23 is a partial layout diagram of a static random access memory cell in various embodiments of the present invention. FIGS. 24A to 25 are partial top views or cross-sectional views of other structures 20 at different fabrication stages of method 100 in FIG.1 in the embodiments. FIGS. 26 to 29 are partial top views or cross-sectional views of another structure 30 at different fabrication stages of method 100 in FIG.1. FIGS. 30 and 31 are partial top views or cross-sectional views of another structure 40 at different fabrication stages of method 100 in FIG.1. Figure 32 shows another exemplary circuit diagram of a static random access memory cell used in various embodiments of the present invention. Method 100 is for illustrative purposes only and is not intended to limit the embodiments of the present invention to the actual description of method 100. Additional steps may be provided before, during, and after method 100, and additional embodiments of method 100 may substitute, omit, or interchange some of the steps described. All steps are not detailed here for simplicity. Since structures 10, 20, 30, or 40 will be fabricated as semiconductor structures or semiconductor devices, they may be considered as semiconductor structures or semiconductor devices as required by the content. For the avoidance of doubt, the X, Y, and Z directions in Figures 2A to 21B and Figures 23 to 31 are perpendicular to each other and are consistent in direction in the description of the present invention. In the following description, similar reference numerals are used to indicate similar structures unless otherwise stated. This refers to the material properties and comparisons of various reference numerals related to the method or diagram, which may be used for the same reference numerals related to different methods or different diagrams.

[0016] As shown in Figures 1, 2A, and 2B, method 100 can be used to form an integrated circuit structure (such as structure 10). Semiconductor structure 10 may include a microchip, microprocessor, special-purpose integrated circuit, field-programmable gate array, digital signal processor, or a portion thereof, and various passive and active microelectronic devices (such as resistors, capacitors, inductors, diodes, p-type field-effect transistors, n-type field-effect transistors, fin field-effect transistors, fully wound gate transistors such as nanosheet field-effect transistors or nanowire field-effect transistors, other types of multi-gate field-effect transistors, metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor transistors, bipolar junction transistors, laterally diffused metal-oxide-semiconductor transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof). The exact function of the semiconductor device such as structure 10 is not limited to the above.

[0017] As shown in Figures 2A and 2B, structure 10 may include a first region 200 and a second region 300. In the embodiment shown in Figure 2A, the second region 300 surrounds the first region 200. In the embodiment shown in Figure 2B, the first region 200 and the second region 300 are separated from each other. In some embodiments (not shown), the first region 200 and the second region 300 are adjacent to each other. In some embodiments, semiconductor structure 10 includes more than one first region 200 and more than one second region 300. Figures 2A and 2B have been simplified for clarity of illustration to facilitate understanding of the inventive concept of embodiments of the present invention. Additional structures may be added to the structure, and other embodiments of the structure may replace, adjust, or omit some of the following structures.

[0018] In some embodiments, the first region 200 includes a memory region. The memory region, such as the first region 200, may include at least one array of memory cells configured in columns and rows. The array may include static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, non-volatile random access memory (NRAM) cells, flash memory cells, other suitable memory cells, or combinations thereof. In one embodiment, the array includes a plurality of SRAM cells that are typically capable of retaining or storing data when powered on. In some embodiments, the SRAM cells include one or more transistors described below.

[0019] In some embodiments, the second region 300 includes a peripheral region. The peripheral region, such as the second region 300, may include a logic region, which includes logic units. The logic units are configured to implement various logic functions. In some embodiments, the logic units are configured to implement various logic functions to memory cells in a memory region, such as the first region 200. For example, the logic functions of the logic units include write and / or read decoding, select word lines, select bit lines, data driving, and memory self-test. The logic functions of the logic units described above are for illustrative purposes only. The various logic functions of the logic units are within the scope of the embodiments of this invention.

[0020] The following description uses one or more fully wound gate transistors as examples to illustrate various embodiments of the present invention. However, it should be understood that embodiments of the present invention are not limited to a particular type of device unless specifically defined in the claims. For example, embodiments of the present invention can be used to implement fork-plate devices, complementary field-effect transistor (FET) devices, or the like. A complementary FET comprises a first transistor of a first conductivity type (such as n-type or p-type) stacked vertically on a second transistor of the opposite conductivity type. In some examples, fully wound gate transistors can be used to implement complementary FET devices. Those skilled in the art will understand that embodiments of the present invention are also advantageous for other embodiments of semiconductor devices.

[0021] As shown in Figures 1 and 3, step 102 of method 100 provides structure 10. As shown in Figure 3, structure 10 includes a substrate 202 and a stack 204 of interleaved semiconductor layers formed on the substrate 202. A first region 200 and a second region 300 may include portions of the same substrate 202. In some embodiments, the first region 200 and the second region 300 include portions of the same stack 204. In some embodiments, the substrate 202 may be a semiconductor substrate such as a silicon substrate. The substrate 202 may include various doping profiles, depending on design requirements known in the art. In embodiments where the semiconductor device is p-type, an n-type doped profile (i.e., an n-type well) may be formed on the substrate 202. In some embodiments, the n-type dopant required to form the n-type well may include phosphorus, arsenic, or antimony. In embodiments where the semiconductor device is n-type, a p-type doped profile (i.e., a p-type well) may be formed on the substrate 202. In some embodiments, the p-type dopant used to form the p-type well may include boron or gallium. Suitable doping may include ion-implanted dopant and / or diffusion processes. The substrate 202 may also include other semiconductors such as germanium, silicon carbide, silicon-germanium, germanium-tin, or diamond. The substrate 202 may be modified to include semiconductor compounds and / or semiconductor alloys. Furthermore, the substrate 202 may, where appropriate, include an epitaxial layer, may have stress to improve performance, may include silicon-on-insulator or germanium-on-insulator structures, and / or may have other suitable enhancing structures.

[0022] In some embodiments, the stack 204 on substrate 202 includes staggered channel layers 208 composed of a first semiconductor and sacrificial layers 206 composed of a second semiconductor. In other words, the sacrificial layers 206 and channel layers 208 are staggered. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layer 206 comprises silicon germanium or germanium tin, while the channel layers 208 comprise silicon. It is worth noting that FIG3 shows three sacrificial layers 206 and three channel layers 208 in an staggered configuration, which is for illustrative purposes only and is not intended to limit the embodiments of the invention to the places not specifically described in the claims. It should be understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the number of channel components required for the semiconductor structure 10. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0023] The deposition method for the sacrificial layer 206 and the channel layer 208 in stack 204 can employ molecular beam epitaxy, vapor phase epitaxy, and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium layer, and the channel layer 208 comprises an epitaxially grown silicon layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially undoped (i.e., the added dopant concentration is from about 0 atoms / cm³ to about 1 x 10¹⁷ atoms / cm³). For example, no deliberate doping is performed during the epitaxial growth process used in stack 204.

[0024] In some embodiments, Figures 4 to 9 show examples of structures in the first region 200 or the second region 300 at different fabrication stages. As shown in Figures 1 and 4, step 104 of method 100 forms a fin structure 212 (which can also be considered as an active region) from the stack 204 and the substrate 202. The fin structure 212 may be formed in each of the first region 200 and the second region 300. To pattern the stack 204, a hard mask layer may be deposited on the stack 204 to form an etch mask. The hard mask layer may be a single layer or multiple layers. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer on the pad oxide layer. The fin structure 212 may be patterned from the stack 204 and the substrate 202 using lithography and etching processes. The lithography process may include photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (reactive ion etching), wet etching, and / or other etching methods. As shown in FIG4, the etching process in step 104 forms trenches that extend vertically through a portion of the stack 204 and the substrate 202. The trenches define a fin structure 212. In some embodiments, the fin structure may be defined using dual or multiple patterning with a spacing smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a material layer is formed on the substrate and patterned using a photolithography process. A self-aligned process is used to form spacers along the sides of the patterned material layer. The material layer is then removed, and the remaining spacers or cores can then be used to etch portions of the stack 204 and the substrate 202 to pattern the fin structure 212. As shown in FIG4, the fin structure 212 includes a sacrificial layer 206 and a channel layer 208 that extend vertically along the Z direction and whose length direction extends along the X direction. As shown in FIG4, the fin structure 212 includes a base fin structure 212B formed by patterning the substrate 202. The patterned stack 204 includes a sacrificial layer 206 and a channel layer 208, and is deposited on the substrate fin structure 212B.

[0025] An isolation structure 214 is formed adjacent to the fin structure 212. In some embodiments shown in FIG. 4, the isolation structure 214 is located on the sidewall of the substrate fin structure 212B. In some embodiments, the isolation structure 214 may be formed in a trench to isolate the adjacent fin structure 212. The isolation structure 214 may also be considered as a shallow trench isolation structure. For example, in some embodiments, a dielectric layer is first deposited on the substrate 202 to fill the trench. In some embodiments, the dielectric layer may include silicon oxide, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric layer, a combination of the above, and / or other suitable materials. In many examples, the dielectric layer deposition method may be a chemical vapor deposition process, a sub-pressure chemical vapor deposition process, a flowable chemical vapor deposition process, a spin coating process, and / or other suitable processes. For example, the deposited dielectric material may then be thinned and planarized by a chemical mechanical polishing process. The planarized dielectric layer can be further recessed or pulled back by dry etching, wet etching, and / or a combination thereof to form the shallow trench isolation structure 214 shown in FIG4. After the dielectric layer is recessed, the fin structure 212 protrudes above the shallow trench isolation structure 214, while the base fin structure 212B is embedded in the isolation structure 214.

[0026] As shown in Figures 1, 5, and 6, step 106 of method 100 forms a dummy gate stack 220 on the channel region 212C of the fin structure 212. Figure 6 is a partial cross-sectional view of the silicon structure 10 along section line A-A' in Figure 5. In some embodiments, a gate replacement process (or gate post-processing) is employed, wherein the dummy gate stack 220 (as shown in Figures 5 and 6) serves as a placeholder for various processes, after which the dummy gate stack 220 is removed and replaced to form a functional gate and structure. Other processes and setups are also possible. In some embodiments shown in Figure 6, the dummy gate stack 220 is formed on the fin structure 212, and the fin structure 212 can be divided into a channel region 212C below the dummy gate stack 220 and a source / drain region 212SD not below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. As shown in Figure 6, the channel region 212C is located between the two source / drain regions 212SD along the X direction.

[0027] A method for forming a dummy gate stack 220 may include depositing and patterning layers in the dummy gate stack 220. As shown in FIG5, a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 may be deposited blanket-like over the first region 200 and the second region 300. In some embodiments, the dummy dielectric layer 216 may be formed on the fin structure 212, and the formation method may employ a chemical vapor deposition process, an atomic layer deposition process, an oxygen plasma oxidation process, or other suitable processes. In some examples, the dummy dielectric layer 216 may include silicon oxide. A dummy electrode layer 218 may then be deposited on the dummy dielectric layer 216, and the deposition method may employ a chemical vapor deposition process, an atomic layer deposition process, or other suitable processes. In some examples, the dummy electrode layer 218 may include polycrystalline silicon. For patterning purposes, a gate-top hard mask layer 222 can be deposited on the dummy electrode layer 218, and the deposition method can employ chemical vapor deposition, atomic layer deposition, or other suitable processes. The gate-top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, as shown in FIG6. For example, the patterning process may include lithography processes (such as photolithography or electron beam lithography) and etching processes. The lithography process may further include photoresist coating (such as spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (such as spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The photolithography process forms a patterned photoresist layer. A patterned photoresist layer can then be used as an etching mask to pattern the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 during the etching process. In some embodiments, the etching process may include dry etching (such as reactive ion etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 located on the silicon oxide layer 223. As shown in FIG6, the patterned dummy gate stack 220 is located only on the channel region 212C and not on the source / drain region 212SD.

[0028] As shown in Figures 1 and 7, step 108 of method 100 deposits a gate spacer layer 226 on structure 10, including on the dummy gate stack 220. In some embodiments, the gate spacer layer 226 is compliantly deposited on first region 200 and second region 300, including on the upper surface and sidewalls of the dummy gate stack 220. The term "compliant" is used herein to conveniently describe a layer having a substantially uniform thickness in multiple regions. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon oxide, silicon carbonitride, or silicon nitride. The process of depositing the gate spacer layer 226 on the dummy gate stack 220 may employ chemical vapor deposition, sub-pressure chemical vapor deposition, atomic layer deposition, or other suitable processes.

[0029] As shown in Figures 1 and 8, in step 110 of method 100, the source / drain region 212SD of the fin structure 212 is anisotropically recessed to form a source / drain trench 228. The anisotropic etching may include dry etching or a suitable etching process that etches the gate spacer layer 226, the source / drain region 212SD, and a portion of the substrate 202 beneath the source / drain region 212SD. The final source / drain trench 228 extends vertically through the depth of the stack 204 and partially extends into the substrate 202. Examples of the dry etching process in step 110 may be implemented using oxygen-containing gases, fluorine-containing gases (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, trifluoromethane, tetrafluorocyclobutane, and / or hexafluoroethane), fluorine-containing gases (such as chlorine, chloroform, carbon tetrachloride, and / or boron trichloride), bromine-containing gases (such as hydrogen bromide and / or bromoform), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. As shown in FIG8, the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain trench 228 extends below the stack 204 and into the substrate 202, the lower surface and lower sidewalls of the source / drain trench 228 are defined in the substrate 202.

[0030] As shown in Figures 1 and 9, step 112 of method 100 releases the channel layer 208 in the channel region 212C to form a channel assembly 2080. After forming the source / drain trench 228, a sacrificial layer 206 intersects with the channel layer 208 in the channel region 212C. Selectively removing the sacrificial layer 206 releases the channel layer 208 (as shown in Figure 8) to form the channel assembly 2080 (as shown in Figure 9). In embodiments where the channel assembly 2080 comprises silicon and the sacrificial layer 206 comprises silicon-germanium, the step of selectively removing the sacrificial layer 206 removes at least a portion of the germanium impurities diffused from the sacrificial layer 206 into the channel assembly 2080. Selectively removing the sacrificial layer 206 may form an opening 229 between adjacent channel assemblies 2080. In some embodiments, the channel assembly 2080 has a thickness T1 (or sheet height) along the Z direction, and the opening 229 has a height S1 along the Z direction. The method for selectively removing the sacrificial layer 206 can be selective dry etching, selective wet etching, or other selective etching processes. Examples of selective dry etching processes include using one or more fluorine-based etchants, such as fluorine gas or hydrocarbons. Examples of selective wet etching processes include using a mixture of ammonium hydroxide, hydrogen peroxide, and water. Depending on the design, the channel assembly 2080 can take the form of nanowires, nanosheets, or other nanostructures. Performing step 112 can increase the thickness uniformity of the channel assembly 2080.

[0031] In some embodiments, Figures 10A to 12A and Figures 14A to 21A are embodiments of the structure in the first region 200 at different manufacturing stages, while Figures 10B to 12B and Figures 14B to 21B are embodiments of the structure in the second region 300 at different manufacturing stages.

[0032] As shown in Figures 1, 10A, and 10B, step 114 of method 100 forms a mask layer on a second region (e.g., second region 300) of structure 10, but not on a first region (e.g., first region 200) of structure 10. Step 114 may include depositing mask material 232 on the first region 200 and the second region 300 (Figures 10A and 10B), forming a patterned photoresist layer 234 on the mask material 232 in the second region (but not the first region) (Figures 11A and 11B), and using the patterned photoresist layer 234 as an etching mask to etch the mask material 232 in the first region (Figures 11A and 11B). Step 114 may be performed as appropriate, and in some embodiments, step 114 may be omitted. In some embodiments, the mask material 232 includes a base antireflective coating material and provides a platform for coating and patterning the photoresist. The base antireflective coating material may include silicon oxynitride, silicon carbide, polymers, or other suitable materials. In one embodiment, the masking material 232 can be formed by any suitable process, such as chemical vapor deposition, or spin-coating an under-antireflective coating material onto the substrate 202 to fill the source / drain trenches 228 and openings 229, and baking the under-antireflective coating material to crosslink it.

[0033] As shown in Figures 11A and 11B, the mask material 232 in the first region 200 is removed. After forming the mask material 232, a patterned photoresist layer 234 can be formed on the mask material 232. In one example of the process, the photoresist layer can be deposited blanket-like on the structure 10, including the mask material 232 in the first region 200 and the second region 300. The photoresist layer is then exposed with rays passing through or reflected from the photomask, followed by a baking process to bake the photoresist, and then developed in a developer solution to form the patterned photoresist layer 234, as shown in Figures 11A and 11B. In the embodiment, the patterned photoresist layer 234 is formed in the second region 300, but not in the first region 200. The patterned photoresist layer 234 is then used as an etching mask, and an etching process 236 is performed to recess the mask material 232. The etching process 236 may include an isotropic etching process or anisotropic etching process. Etching process 236 can be a dry etching process. Dry etching process can use plasma with argon, oxygen, nitrogen, hydrogen, or a combination of the above.

[0034] After removing the masking material 232 from the area not covered by the patterned photoresist layer 234 (such as the first region 200), the masking material 232 remaining in the second region 300 becomes the masking layer 232'. The patterned photoresist layer 234 can be selectively removed. In some examples, the patterned photoresist layer 234 can be removed during or after the etching process 236. Once step 114 is completed, the channel assembly 2080 in the first region 200 can be exposed in the source / drain trench 228 and the opening 229.

[0035] As shown in Figures 1 and 12A to 13B, step 116 of method 100 performs an etching process 238 on the channel assembly 2080 in the first region 200. Figures 13A and 13B show further enlarged views of portion A in Figure 12A. During step 116, a mask layer 232' protects the channel assembly 2080 in the second region 300 from contact with the etchant. The gate spacer layer 226 and the gate top hard mask layer 222 protect the dummy gate stack 220 in the first region 200 from damage during etching process 238. Etching process 238 trims the exposed channel assembly 2080 in the source / drain trench 228 and opening 229 (i.e., removes a portion of the channel assembly 2080), thereby forming an enlarged opening 229'. Etching process 238 may include selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, etching process 238 may be a selective isotropic dry etching process that selectively etches a portion of channel assembly 2080. In some embodiments, step 112 does not completely remove germanium impurities from sacrificial layer 206, while etching process 238 removes the remainder of germanium impurities in channel assembly 2080. The amount of recess in channel assembly 2080 may be controlled by the timing of the etching process. In one embodiment, the selective dry etching process may employ one or more fluorine-based etchants such as fluorinated fluorides or hydrocarbons. In some embodiments, etching process 238 differs from the etching process performed in step 112. For example, the etching process embodied in step 112 includes selective wet etching in a first chamber, and etching process 238 includes selective dry etching in a second chamber, where the first chamber differs from the second chamber.

[0036] Once step 116 is completed, the thickness T2 (or sheet height) of the channel assembly 2080 in the first region 200 along the Z direction can be from about 4 nm to about 5 nm, and the enlarged opening 229' can have a height S2 along the Z direction. The thickness T2 in the second region 300 can be less than the thickness T1 as described above, while the height S2 in the second region 300 can be greater than the height S1 as described above. The ratio of height S1 to height S2 (S1 / S2) can be from about 0.6 to 1. In some embodiments, the ratio of thickness T2 to thickness T1 (T2 / T1) is from about 0.7 to 1. If the ratio T2 / T1 is too small, the thickness T2 will be too small, and the channel resistance of the channel assembly in the first region 200 may be too large. The upper surfaces of the source / drain region 212SD in the first region 200 and the substrate fin structure 212B in the channel region 212C may be lower than the corresponding upper surfaces of the substrate fin structure 212B in the second region 300 by a distance such as distances D1 and D2, as shown in Figures 12A and 12B. Distance D1 (or distance D2) may be approximately half the difference between thicknesses T1 and T2 (or approximately half the difference between heights S1 and S2). The horizontal centerline of the channel assembly 2080 (such as the bottommost channel assembly 2080) in the first region 200 may be aligned with the horizontal centerline of the corresponding channel assembly 2080 (such as the bottommost channel assembly 2080) in the second region 300.

[0037] In some embodiments, the channel assembly 2080 in the first region 200 has a rectangular cross-sectional shape, as shown in FIG12A. In some other embodiments of FIG13A, the etching process 238 may round the corners of the channel assembly 2080 and the substrate fin structure 212B. In some other embodiments of FIG13B, the etching process 238 etches more of the end portions of the channel assembly 2080 and the substrate fin structure 212B than the middle portions, so the upper and lower surfaces of the end portions may be inclined as shown in the figure.

[0038] As described above, step 112 can reduce germanium impurities in the channel components 2080 in the first region 200 and the second region 300. Etching process 238 can further reduce germanium impurities in the channel components 2080 in the first region 200. In embodiments where the first region 200 includes static random access memory (SRAM) cells, implementing the disclosure method 100 (as in steps 112 to 116) can increase the thickness uniformity of the channel components 2080 and reduce threshold voltage variations, minimum operating voltages, and short-channel effects of the SRAM cells. The minimum operating voltage can be the lowest voltage required to read the SRAM cells. A lower minimum operating voltage consumes less power. Furthermore, the channel components 2080 in the second region 300 can have a greater thickness to achieve higher current and improve the performance of the second region 300. Therefore, the overall performance of structure 10 can be improved.

[0039] In embodiments where step 114 is omitted, an etching process 238 is performed on the channel components 2080 in the first region 200 and the second region 300. In these embodiments, the ratio of thickness T2 to thickness T1 (T2 / T1) is equal to 1.

[0040] As shown in Figures 1, 14A, and 14B, step 118 of method 100 selectively removes the mask layer 232' from the second region 300. One or more etching processes can be performed to selectively remove the mask layer 232' without substantially etching other structures such as the channel assembly 2080, the substrate fin structure 212B, and the gate spacer layer 226. The removal method for the mask layer 232' can employ an ashing process or a dry etching process, including the use of plasmas containing argon, oxygen, nitrogen, hydrogen, or combinations thereof. In embodiments where step 114 is omitted, step 118 can be omitted.

[0041] As shown in Figures 1, 15A, and 15B, step 120 of method 100 deposits a dummy layer 240 around the channel assembly 2080 in the first region 200 and the second region 300, and over the source / drain trench 228. The dummy layer 240 may include a dielectric material. The dielectric material may include oxides, nitrides, carbides, or combinations thereof. Examples of dielectric materials may include silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, or aluminum oxide. In some embodiments, the dummy layer 240 includes silicon oxide and / or aluminum oxide. The deposition method of the dummy layer 240 may employ plasma-assisted chemical vapor deposition, flowable chemical vapor deposition, plasma-assisted atomic layer deposition, atomic layer deposition, or a rapid thermal oxidation process. As shown in Figures 15A and 15B, the dummy layer 240 fills the enlarged opening 229' between the channel components 2080 in Figure 14A (or the opening 229 in Figure 14B) and covers the end sidewall of the channel components 2080. Furthermore, the dummy layer 240 directly contacts the sidewall of the gate spacer layer 226 and the upper surface of the substrate 202 or the base fin structure 212B.

[0042] As shown in Figures 1, 16A, and 16B, step 122 of method 100 selectively recesses the dummy layer 240 to form an inner spacer recess 242, without substantially etching the exposed portions of the gate spacer layer 226, the dummy gate stack 220, the substrate 202 or the substrate fin structure 212B, and the channel assembly 2080. In one embodiment, the channel assembly 2080 is substantially composed of silicon, the dummy layer 240 is composed of silicon oxide, and the process of selectively recessing the dummy layer 240 can employ a selective wet etching process or a selective dry etching process. Examples of selective dry etching processes include carbon tetrafluoride, nitrogen trifluoride, hydrogen, or mixtures thereof. Examples of selective wet etching processes include hydrofluoric acid, ammonium fluoride, or mixtures thereof.

[0043] As shown in Figures 1, 17A, and 17B, step 124 of method 100 forms an inner spacer structure 244 in an inner spacer recess 242. Although not shown, step 124 may include depositing inner spacer material on structure 10 and etching back the inner spacer material to form the inner spacer structure 244 in the inner spacer recess 242 (as shown in Figures 16A and 16B). After forming the inner spacer recess 242, inner spacer material is deposited on structure 10, including on the inner spacer recess 242. The inner spacer material may include metal oxides, silicon oxide, silicon carbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low dielectric constant dielectric material. Metal oxides may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not shown, the inner spacer material may be a single layer or multiple layers. In some embodiments, the deposition method for the inner spacer material may employ chemical vapor deposition, plasma-assisted chemical vapor deposition, sub-pressure chemical vapor deposition, atomic layer deposition, or other suitable methods. The inner spacer material is deposited into the inner spacer recess 242 and onto the sidewalls of the channel assembly 2080 exposed in the source / drain trench 228. As shown in Figures 17A and 17B, the deposited inner spacer material is then etched back to remove it from the sidewalls of the channel assembly 2080, forming an inner spacer structure 244 in the inner spacer recess 242. The inner spacer structure 244 in the first region 200 may extend the contours of the upper and lower surfaces of the end portions of the adjacent channel assembly 2080 (or substrate fin structure 212B) (as shown in Figures 12A, 13A, and 13B). In some embodiments, the inner spacer structure 244 in the first region 200 has a thickness T3 along the Z direction, while the inner spacer structure 244 in the second region 300 has a thickness T4 along the Z direction. The ratio of thickness T4 to thickness T3 (T4 / T3) is about 0.6 to 1.

[0044] As shown in Figures 1, 18A, and 18B, step 126 of method 100 forms a source / drain structure 246 on the source / drain region 212SD. Although not illustrated, method 100 prior to the formation of any epitaxial layer may include a cleaning process to clean the surface of structure 10. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may employ a mixture of deionized water and ammonium peroxide and hydrogen peroxide, a mixture of deionized water and hydrogen chloride and hydrogen peroxide, a mixture of sulfuric acid and hydrogen peroxide, and / or hydrofluoric acid for removing oxides. Dry cleaning processes may include helium and hydrogen treatment. Hydrogen treatment can convert silicon on the surface into silane, which can be extracted and removed.

[0045] The source / drain structure can be considered as a source or drain individually or together, depending on the context. The source / drain structure 246 is coupled to the channel region 212C. Each source / drain structure 246 can be selectively formed by epitaxy from an exposed semiconductor surface, and the formation method can employ epitaxial processes such as vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy, and / or other suitable processes. The n-type source / drain structure may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and can be in-situ doped with n-type dopants such as phosphorus, arsenic, or antimony during epitaxial growth, or ex-situ doped using a junction implantation process. The p-type source / drain structure may include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and can be in-situ doped with p-type dopants such as boron or gallium during epitaxial growth, or ex-situ doped using a junction implantation process. In some embodiments, the n-type source / drain structure and the p-type source / drain structure may each comprise multiple semiconductor layers with different doping concentrations. The n-type source / drain structure and the p-type source / drain structure can be formed in any suitable order.

[0046] Step 126 may further include depositing a contact etch stop layer 250 on the source / drain structure 246 and depositing an interlayer dielectric layer 252 on the contact etch stop layer 250. As shown in Figures 18A and 18B, the contact etch stop layer 250 is deposited on structure 10, including on the source / drain structure 246. The contact etch stop layer 250 may include silicon nitride or aluminum nitride. In some embodiments, the deposition method of the contact etch stop layer 250 may be chemical vapor deposition or atomic layer deposition. The interlayer dielectric layer 252 is then deposited on the contact etch stop layer 250. In some embodiments, the interlayer dielectric layer 252 may comprise a tetraethoxysilane oxide, undoped silicate glass, doped silica (such as borosilicate glass, fluorosilicone glass, phosphosilicone glass, or borosilicate glass), and / or other suitable dielectric materials. The deposition method for the interlayer dielectric layer 252 can employ chemical vapor deposition, flowable chemical vapor deposition, spin coating, or a suitable deposition technique. After depositing the interlayer dielectric layer 252, the structure 10 can be planarized by a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical polishing process. Exposing the dummy gate stack 220 can be used to remove the dummy gate stack 220.

[0047] As shown in Figures 1 and 19A to 21B, step 128 of method 100 replaces the dummy gate stack 220 and the dummy layer 240 to form a gate structure 256. Figure 20A is a partial cross-sectional view of the first region 200 along section line B-B' in Figure 19A. Figure 20B is a partial cross-sectional view of the second region 300 along section line B-B' in Figure 19B. Step 128 may include removing the dummy gate stack 220 (as shown in Figures 19A to 20B), removing the dummy layer 240 (as shown in Figures 19A to 20B), and depositing the gate structure 256 to cover each channel assembly 2080 (as shown in Figures 21A and 21B). In the first region 200, the gate structure 256 may form a device (such as transistor 258) having an active region such as a fin structure 212. In the second region 300, the gate structure 256 may form a device (such as transistor 260) having an active region such as a fin structure 212.

[0048] As shown in Figures 19A to 20B, the dummy gate stack 220 is removed. The method for removing the dummy gate stack 220 may include one or more etching processes that are selective for the material of the dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove the dummy gate stack 220.

[0049] After removing the dummy gate stack 220, the channel assembly 2080 and the sidewalls of the dummy layer 240 in the channel region 212C are exposed. As shown in Figures 19A to 20B, separate etching processes can be performed to selectively remove the dummy layer 240 in the channel region 212C. For example, a selective wet etching process or a selective dry etching process can be performed to remove the dummy layer 240. Examples of selective wet etching processes include diluted hydrofluoric acid, or a combination of hydrofluoric acid and ammonium fluoride. Examples of selective dry etching processes include anhydrous hydrofluoric acid vapor, trifluoromethane, nitrogen trifluoride, hydrogen, ammonia, carbon tetrafluoride, sulfur hexafluoride, or a combination thereof. After selectively removing the dummy layer 240, the channel assembly 2080 in the channel region 212C is exposed again, as shown in Figures 19A to 20B. Selective removal of the dummy layer 240 can form a gate trench 254, which includes an opening 229 (or an enlarged opening 229') between adjacent channel assemblies 2080. Due to the removal of germanium impurities in steps 112 and 116, the channel width loss in step 128 is negligible. In the embodiments shown in Figures 20A and 20B, the sidewalls of the channel assembly 2080 are aligned with the topmost sidewalls of the underlying substrate fin structure 212B, as shown by the dashed lines. The channel assembly 2080 and the substrate fin structure 212B in the first region 200 may have the aforementioned contours shown in the embodiments of Figures 12A, 13A, and 13B.

[0050] As shown in Figures 21A and 21B, a gate structure 256 is formed to enclose each released channel assembly 2080. After the channel assembly 2080 is released, the gate structure 256 is formed to enclose each channel assembly 2080. Although not shown in Figures 21A and 21B, the gate structure 256 includes an interface layer at the junction of the channel assembly 2080 in the channel region 212C and the substrate fin structure 212B, with a gate dielectric layer located on the interface layer and the gate layer located on the gate dielectric layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. The gate dielectric layer may include a dielectric material with a high dielectric constant, such as hafnium oxide. The gate dielectric layer can be replaced with other dielectric materials with high dielectric constants, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium dioxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, zirconium oxide, yttrium oxide, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, combinations thereof, or other suitable materials. The gate dielectric layer can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, oxidation, and / or other suitable methods.

[0051] The gate layer of gate structure 256 may include a single-layer or multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to improve device performance, a pad layer, a wetting layer, an adhesive layer, a metal alloy, or a metal silicate. For example, the gate layer may include titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, tantalum silicon nitride, copper, other refractory metals, other suitable metallic materials, or combinations thereof. In various embodiments, the gate layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. In various embodiments, a chemical mechanical polishing process may be performed to remove excess metal, thereby providing a substantially flat upper surface of the gate structure. Gate structure 256 includes a portion 256a sandwiched between channel components 2080 in channel region 212C.

[0052] A portion 256a in the first region 200 may have the aforementioned height S2, while a portion 256a in the second region 300 may have the aforementioned height S1. In some embodiments, the gate structure 256 has widths G2 and G1 along the X direction in the first region 200 and the second region 300, respectively. Width G1 may be the same as or different from width G2. In some embodiments, width G1 is equal to width G2. The ratio of thickness T1 to width G1 (T1 / G1) is about 0.3 to about 0.45, or about 0.35 to about 0.45. The ratio of thickness T2 to width G2 (T2 / G2) is about 0.2 to about 0.4, or about 0.2 to about 0.35. If the ratio T2 / G2 is too small (e.g., less than about 0.2), the thickness T2 may be too small, the surface area of ​​the channel assembly 2080 may be too small, and the short-channel effect and critical voltage variation may be too large, affecting the performance of the first region 200 and the overall performance of the structure 10.

[0053] Subsequent processes can be performed on structure 10 to form various structures and regions known in the art. For example, subsequent processes can form additional interlayer dielectric layers, contacts / vias / circuits, and multilayer interconnect structures (such as metal layers and interlayer dielectric layers) on substrate 202, which are arranged to connect various structures to form functional circuits, and the functional circuits may include one or more devices containing structure 10. In this example, multilayer interconnects may include vertical interconnects such as vias or contacts, and horizontal interconnects such as metal lines. Various interconnect structures may employ various conductive materials such as copper, tungsten, and / or silicates. In one example, damascene and / or dual damascene processes are used to form copper-related multilayer interconnect structures.

[0054] Figure 22 is a circuit diagram of an exemplary static random access memory (SRAM) cell 400, which can be implemented as a memory cell in the first region 200 and further implemented in the semiconductor structure 10 in Figures 2A and 2B. In this embodiment, the SRAM cell 400 is a single-port six-transistor SRAM cell. In various embodiments, the SRAM cell 400 can be other types of memory cells, such as dual-port memory cells or memory cells with more than six transistors. Figure 22 has been simplified for clarity and to facilitate understanding of the inventive concept of the embodiments of the present invention. External structures can be added to the single-port SRAM cell 400, and other embodiments of the single-port SRAM cell 400 can replace, adjust, or omit some of the following structures.

[0055] An exemplary static random access memory (SRAM) unit 400 is a single-port SRAM unit comprising six transistors, such as a through-gate transistor PG-1, a through-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. The through-gate transistors PG-1 and PG-2 provide access to the storage portion of the SRAM unit 400, which includes cross-coupled pairs of inverters 462 and 466. Inverter 462 includes pull-up transistors PU-1 and PD-1, while inverter 466 includes pull-up transistors PU-2 and PD-2. In some embodiments, the pull-up transistors PU-1 and PU-2 are configured as p-type fin field-effect transistors or p-type fully wound gate transistors, while the pull-down transistors PD-1 and PD-2 are configured as n-type fin field-effect transistors or n-type fully wound gate transistors.

[0056] The gate of pull-up transistor PU-1 is sandwiched between its source (electrically coupled to a power supply voltage such as the first voltage VDD) and the first common drain CD1, while the gate of pull-down transistor PD-1 is sandwiched between its source (electrically coupled to a power supply voltage such as the second voltage VSS, which may be electrically grounded) and the first common drain CD1. The gate of pull-up transistor PU-2 is sandwiched between its source (electrically coupled to a power supply voltage such as the first voltage VDD) and the second common drain CD2, while the gate of pull-down transistor PD-2 is sandwiched between its source (electrically coupled to a power supply voltage such as the second voltage VSS) and the second common drain CD2. In some embodiments, the first common drain is a storage node SN that stores data in its true form, and the second common drain is a complementary storage node SNB that stores data in its complementary form. The second common drain CD2 is coupled to the gate of pull-up transistor PU-1 and the gate of pull-down transistor PD-1, and the first common drain CD1 is coupled to the gate of pull-up transistor PU-2 and the gate of pull-down transistor PD-2. The gate of through-gate transistor PG-1 is sandwiched between the source (electrically coupled to bit line BL) and the drain (electrically coupled to the first common drain CD1). The gate of through-gate transistor PG-2 is sandwiched between the source (electrically coupled to complementary bit line BLB) and the drain (electrically coupled to the second common drain CD2). The word line WL is electrically coupled to the gates of through-gate transistors PG-1 and PG-2. In some embodiments, through-gate transistors PG-1 and PG-2 can provide access to storage node SN and complementary storage node SNB during read and / or write steps. For example, the through-gate transistors PG-1 and PG-2 are coupled to the storage node SN and the complementary storage node SNB to the bit line BL and the complementary bit line BLB, respectively, in response to the voltage applied to the gate of the through-gate transistors PG-1 and PG-2 by the word line WL.

[0057] Figure 23 is a partial layout diagram of the Static Random Access Memory (SRAM) cell 400. The dashed boxes represent the boundaries of the SRAM cell 400. In some embodiments, the SRAM cell 400 includes n-type three-dimensional active regions, such as n-type active regions 212n, each located within a p-type doped region, such as a p-type well 468P, and p-type three-dimensional active regions, such as p-type active regions 212p, each located within an n-type doped region, such as an n-type well 468N. Adjacent p-type wells 468P and n-type wells 468N may share a well boundary 470, as shown. In some embodiments, the p-type active regions 212p and n-type active regions 212n may resemble the active regions, such as the fin structure 212, in the first region 200 described above. The p-type active region 212p may have a width W1 along the Y direction, while the n-type active region 212n may have a width W2 along the Y direction. The width W2 may be greater than the width W1. The static random access memory (SRAM) cell 400 includes gate structures 256-1 to 256-4, which are similar to gate structure 256 in the first region 200 described above and are located above the n-type active region 212n and / or the p-type active region 212p, to form various transistors: pull-down transistors PD-1 and PD-2, pull-up transistors PU-1 and PU-2, and through-gate transistors PG-1 and PG-2. The method and structure for forming the various transistors are similar to the method and structure for forming transistor 258 in the first region 200 described above. In these embodiments, step 114 forms a masking layer 232' on the second region 300, but not on the first region 200 containing the SRAM cell 400.

[0058] Figures 24A and 24B are partial top views of other structures 20 completing step 114 of method 100 of Figure 1 in some embodiments. The difference between these embodiments and those forming structure 10 includes that the masking layer 232' is further formed over the n-type well 468N in the first region 200, exposing a sub-region of the p-type well 468P in the first region 200. In other words, the second region in step 114 of method 100 further includes a sub-region of the n-type well 468N in the first region 200, while the first region includes a sub-region of the p-type well 468P in the first region 200. In these embodiments, the masking layer 232' in the top views of Figures 24A and 24B may have a strip pattern in the first region 200 and include strip portions 232a'. In the top views, each strip portion 232a' may extend along the X direction and may be separated from each other along the Y direction. In these embodiments, the masking layer 232' protects the channel assembly 2080 on the n-type well 468N from the etching process 238 of step 116. The differences from structure 10 include the method and structure of forming the p-type transistors (such as pull-up transistors PU-1 and PU-2) on the n-type well 468N, which is similar to the method and structure of forming the transistor 260 in the second region 300 in Figures 3 to 21B.

[0059] Figure 25 is a partial cross-sectional view of the static random access memory (SRAM) cell 400 along section line C-C' in Figure 24A. As shown, the channel assembly 2080 of pull-down transistor PD-1 and through-gate transistor PG-2 has the aforementioned thickness T2, while the channel assembly 2080 on the n-type well 468N has the aforementioned thickness T1, similar to the channel assembly 2080 of pull-up transistor PU-1. The SRAM cell 400 includes a gate isolation structure 480 between gate structures 256-3 and 256-4. The upper surface of the base fin structure 212B on the p-type well 468P is lower than the upper surface of the base fin structure 212B on the n-type well 468N.

[0060] Additional advantages over structure 10 may include improved maximum voltage level of static random access memory cell 400 and further improved overall performance of structure 20 (compared to structure 10).

[0061] Figures 26 and 27 are partial top views of another structure 30 completing step 114 of method 100 of Figure 1 in some embodiments. Figure 26 uses four static random access memory cells 400 as an example. The difference between the embodiments of the embodiments forming structure 20 is that the masking layer 232' is further formed on the sub-region of the first region 200 where the pull-down transistor is formed, and exposes the sub-region of the first region 200 where the through-gate transistor is formed. In other words, in step 114 of method 100, the second region further includes the sub-region of the first region 200 where the pull-down transistor is formed, while the first region includes the sub-region of the first region 200 where the through-gate transistor is formed. In these embodiments, the masking layer 232' has a striped checkerboard pattern in the first region 200 in the top views of Figures 26 and 27. The differences in the embodiments shown in Figures 24A to 25 include, in the top view, that the masking layer 232', in addition to the strip portion 232a', includes rectangular portions 232b' that protrude from and / or connect to adjacent strip portions 232a'. The rectangular portions 232b' form a checkerboard pattern. The sidewalls of adjacent rectangular portions 232b' (sidewalls 232s-1 and 232s-2 in Figure 26) connect to the same strip portion 232a' and are alignable along the Y direction. In these embodiments, the masking layer 232' protects the channel assembly 2080 in the sub-region of the first region 200 where the pull-down transistor is formed from the etching process 238 of step 116. The differences from structure 20 include the formation method and structure of the pull-down transistors PD-1 and PD-2, which are similar to the formation method and structure of the transistor 260 in the second region 300 in Figures 3 to 21B.

[0062] Figures 28 and 29 are partial cross-sectional views of structure 30 along sections C-C' and D-D' in Figure 26, respectively. As shown, the channel assembly 2080 of the through-gate transistors (such as through-gate transistors PG-2 and PG-4) has the aforementioned thickness T2. The channel assemblies 2080 of the pull-down transistors PD-1, PD-2, and PD-4, and the channel assembly 2080 on the n-type well 468N (such as the channel assembly 2080 of the pull-up transistor PU-1) have the aforementioned thickness T1. In the embodiment, the upper surface of the base fin structure 212B of the through-gate transistor is lower than the upper surface of the base fin structure 212B of the pull-up and pull-down transistors. As shown in Figure 29, the static random access memory cell 400 further includes a source / drain contact 482 on the source / drain structure 246. In some embodiments, the static random access memory cell 400 further includes a silicon layer 486 located between the source / drain junction 482 and the underlying source / drain structure 246.

[0063] Additional advantages compared to structure 10 may include an improved beta ratio of the static random access memory (SRAM) cell 400, a ratio of the saturation current of the pull-down transistor to the saturation current of the bypass transistor greater than 1, improved maximum voltage level of the SRAM cell 400, and further improved overall performance of structure 30 (compared to structure 10). The ratio of the drive current of the pull-down transistor to the drive current of the individual bypass transistor in the SRAM cell is the beta ratio. The beta ratio affects the stability of the SRAM cell.

[0064] Figures 30A and 30B are partial top views of another structure 40 completing step 114 of method 100 of Figure 1 in some embodiments. The difference between these embodiments and those forming structure 10 includes that the masking layer 232' is further formed over the p-type well 468P in the first region 200, exposing a sub-region of the n-type well 468N in the first region 200. In other words, in step 114 of method 100, the second region further includes a sub-region of the p-type well 468P in the first region 200, and the first region includes a sub-region of the n-type well 468N in the first region 200. In these embodiments, the masking layer 232' in the top views of Figures 30A and 30B may have a strip pattern in the first region 200 and include strip portions 232c'. In the top views, each strip portion 232c' may extend along the X direction and be separated from each other in the Y direction. In Figure 30A, the rectangular strip portions 232c' may each be approximately half the size of the strip portion 232c' in Figure 30B, and the strip portion 232c' in Figure 30A may be merged with the strip portion 232c' of an adjacent static random access memory cell to form the strip portion 232c' in Figure 30B. In these embodiments, the mask layer 232' protects the channel assembly on the p-type well 468P from the etching process of step 116. The differences from structure 10 include the method and structure of forming the n-type transistors (such as pull-down transistors PD-1 and PD-2 and through-gate transistors PG-1 and PG-2) on the p-type well 468P, which may be similar to the method and structure of forming the transistor 260 in the second region 300 in Figures 3 to 21B.

[0065] Figure 31 is a partial cross-sectional view of the static random access memory (SRAM) cell 400 along section line C-C' in Figure 30A. As shown, the channel assembly 2080 of the pull-down transistor PD-1 and the through-gate transistor PG-2 may have a thickness T5 (or sheet height) along the Z direction, while the channel assembly 2080 on the n-type well 468N, such as the channel assembly 2080 of the pull-up transistor PU-1, may have a thickness T6 (or sheet height) along the Z direction. The ratio of thickness T6 to thickness T5 (T6 / T5) may be approximately 0.5 to 1, or approximately 0.7 to 1. Thickness T6 may be approximately 3 nm to approximately 5 nm, or approximately 4 nm to approximately 5 nm. The SRAM cell 400 includes a gate isolation structure 480 between gate structures 256-3 and 256-4. The upper surface of the basal fin structure 212B on p-type well 468P is higher than the upper surface of the basal fin structure 212B on n-type well 468N.

[0066] Additional advantages compared to configuration 10 may include reducing the minimum operating voltage of the static random access memory cell 400 and maintaining a lower resistance of the channel assembly 2080 of the n-type transistor in the static random access memory cell 400.

[0067] In some embodiments, the static random access memory (SRAM) cell 400 may be other types of memory cells, such as a dual-port SRAM cell containing seven or eight transistors. The above embodiments remain feasible when the SRAM cell 400 is another type of memory cell. For example, method 100 includes forming a mask layer 232' in the second region 300, and, where appropriate, forming a mask layer 232' in specific sub-regions of other types of memory cells in the first region 200 (such as sub-regions forming p-type transistors), similar to the above. Therefore, in these embodiments, the channel assembly 2080 in different regions and / or sub-regions may have different dimensions (such as thickness), similar to the above.

[0068] As shown in some embodiments of FIG32, the dual-port static random access memory (SRAM) unit 400 includes seven transistors. The dual-port SRAM unit 400 may include a write port portion 400W. In these embodiments, the write port portion 400W includes pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and bypass transistors PG-1 and PG-2. In these embodiments, pull-up transistors PU-1 and PU-2 are p-type transistors, while bypass transistors PG-1 and PG-2 and pull-down transistors PD-1 and PD-2 are n-type transistors. The drains of pull-up transistors PU-1 and PD-1 are coupled together, while the drains of pull-up transistors PU-2 and PD-2 are coupled together. Pull-up transistors PU-1 and PD-1 are cross-coupled with pull-up transistors PU-2 and PD-2 to form a data latch. The gates of pull-up transistors PU-1 and PD-1 are coupled together and to the common drain of pull-up transistors PU-2 and PD-2 to form a storage node SN. The gates of pull-up transistors PU-2 and PD-2 are coupled together and to the common drain of pull-up transistors PU-1 and PD-1 to form a complementary storage node SNB. The sources of pull-up transistors PU-1 and PU-2 are coupled to a power line, which is configured to provide a first voltage VDD (this power line can be considered as the first voltage VDD line). The sources of pull-down transistors PD-1 and PD-2 are coupled to a power line, which is configured to provide a second voltage VSS (this power line can be considered as the second voltage VSS line, and in some embodiments may be electrically grounded).

[0069] The data latching storage node SN is coupled to the 400W bit line W_BL of the write port section (which can be considered as a write bit line or a bit line of the write port) via the through-gate transistor PG-2, while the complementary storage node SNB is coupled to the 400W complementary bit line W_BLB of the write port section (which can be considered as a complementary write bit line or a bit line of the complementary write port) via the through-gate transistor PG-1. Storage node SN and complementary storage node SNB are complementary nodes, typically at opposite logic levels (e.g., logic high or logic low). The gates of through-gate transistors PG-1 and PG-2 are coupled to the 400W word line W_WL of the write port section (which can be considered as a write word line or a word line of the write port).

[0070] The dual-port static random access memory (SRAM) cell 400 also includes a read port portion 400R coupled to a write port portion 400W. The read port portion 400R of the SRAM cell 400 includes a through-gate transistor R-PG. One source / drain terminal (e.g., the source terminal) of the through-gate transistor R-PG is electrically coupled to the bit line R_BL of the read port portion 400R. The bit line R_BL of the read port portion 400R can be considered as a read port bit line or a read bit line. The other source / drain terminals (e.g., the drain terminal) of the through-gate transistor R-PG are electrically coupled to the storage node SN (or electrically coupled to the gates of pull-up transistor PU-1 and pull-down transistor PD-1). The gate of the through-gate transistor R-PG is coupled to the word line R_WL of the read port portion 400R. The word line R_WL of the read port portion 400R can be regarded as a read word line or a read port word line. In the embodiment described, the through-gate transistor R-PG is a p-type transistor. That is, in the dual-port static random access memory unit 400, the through-gate transistor in the write port portion 400W is an n-type transistor, while the through-gate transistor in the read port portion 400R is a p-type transistor.

[0071] One or more embodiments of the present invention can provide numerous advantages to semiconductor devices, but are not limited thereto. For example, by performing additional etching processes on channel components in specific regions of a semiconductor structure and replacing the sacrificial layer with a dummy layer, channel components in different regions can have different thicknesses to implement different functions and reduce impurities in the channel components. For example, it can improve the uniformity of channel component thickness, improve the critical voltage variation, short-channel effect, and minimum operating voltage of memory cells in memory regions, and reduce the channel resistance of channel components in logic regions. Therefore, the overall performance of the semiconductor device can be improved.

[0072] An embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes providing a structure. The structure includes a substrate; a first stack of staggered first channel layers and a first sacrificial layer is located on the substrate; a first source / drain trench exposes the sidewalls of the first sacrificial layer; a second stack of staggered second channel layers and a second sacrificial layer is located on the substrate; and a second source / drain trench exposes the sidewalls of the second sacrificial layer. The method further includes performing a first etching process to selectively remove the first and second sacrificial layers; performing a second etching process on the first channel layers but not the second channel layers; forming a first source / drain structure in the first source / drain trench and forming a second source / drain structure in the second source / drain trench; and forming a first gate structure to cover the first channel layer and forming a second gate structure to cover the second channel layer.

[0073] In some embodiments, the step of performing a second etching process on the first channel layer instead of the second channel layer includes: forming a mask material on the first channel layer and the second channel layer; forming a patterned photoresist layer on a first portion of the mask material on the second channel layer; using the patterned photoresist layer as an etching mask, etching a second portion of the mask material on the first channel layer to remove the second portion of the mask material; and etching the first channel layer. In some embodiments, the second etching process reduces a first thickness of the first channel layer to less than a second thickness of the second channel layer. In some embodiments, the method further includes forming a dummy layer around the first channel layer and the second channel layer after performing the second etching process; and removing the dummy layer after forming a first source / drain structure in a first source / drain trench and forming a second source / drain structure in a second source / drain trench. In some embodiments, the method further includes selectively recessing a dummy layer portion to form a plurality of first inner spacers recessed between first channel layers and a plurality of second inner spacers recessed between second channel layers; and forming a plurality of first inner spacer structures in the first inner spacer recesses and forming a plurality of second inner spacer structures in the second inner spacer recesses. A first thickness of at least one of the first inner spacer structures is greater than a second thickness of at least one of the second inner spacer structures. In some embodiments, a second source / drain structure is connected to the first channel layer and the second channel layer. In some embodiments, the first channel layer is a channel layer of a first transistor, and the second channel layer is a channel layer of a second transistor, wherein the first transistor and the second transistor are transistors of the same static random access memory cell. In some embodiments, the step of performing a second etching process removes the top of the substrate beneath the first channel layer.

[0074] Another exemplary embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes forming a first region and a second region on a substrate. The first region includes a first stack of interleaved first channel layers and a first sacrificial layer, and the second region includes a second stack of interleaved second channel layers and a second sacrificial layer. The method further includes forming a first dummy gate structure on the first stack of interleaved first channel layers and first sacrificial layers, and forming a second dummy gate structure on the second stack of interleaved second channel layers and second sacrificial layers; forming a first source / drain recess in the first stack of interleaved first channel layers and first sacrificial layers adjacent to the first dummy gate structure; forming a second source / drain recess in the second stack of interleaved second channel layers and second sacrificial layers adjacent to the second dummy gate structure; selectively removing the first and second sacrificial layers to release the first channel layers and second sacrificial layers. A second channel layer; forming a masking layer on the second region instead of the first region; removing a portion of the first channel layer to reduce the thickness of the first channel layer; removing the masking layer; depositing a first dummy layer around the first channel layer, and depositing a second dummy layer around the second channel layer; forming a first source / drain structure in the first source / drain recess, and forming a second source / drain structure in the second source / drain recess; and replacing the first dummy gate structure and the first dummy layer to form a first metal gate structure, and replacing the second dummy gate structure and the second dummy layer to form a second metal gate structure.

[0075] In some embodiments, the mask layer forms a strip pattern in the top view. In some embodiments, the second region in the top view surrounds the first region. In some embodiments, the first region includes a memory region, and the second region includes a logic region. In some embodiments, the step of forming the mask layer on the second region instead of the first region includes depositing mask material on the first and second regions; forming a patterned photoresist layer on the second region; and using the patterned photoresist layer as an etching mask to remove the mask material from the first region. The portion of the mask material remaining on the second region forms the mask layer. In some embodiments, the first source / drain structure and the second source / drain structure have different conductivity types. In some embodiments, the step of removing a portion of the first channel layer includes performing a wet etching process on the first channel layer.

[0076] Another exemplary embodiment of the present invention relates to a semiconductor structure. The semiconductor structure includes a substrate; a first stack of a plurality of first channel layers located on the substrate; a first source / drain structure connected to the first stack of the first channel layers; a second stack of a plurality of second channel layers located on the substrate; a second source / drain structure connected to the second stack of the second channel layers; and a metal gate structure covering the first channel layers and extending along a direction in its length direction. At least one of the first channel layers has a first thickness and a first width along the direction, and at least one of the second channel layers has a second thickness and a second width along the direction, the second thickness being greater than the first thickness and the second width being less than or equal to the first width.

[0077] In some embodiments, the semiconductor structure further includes a second metal gate structure covering the second channel layer. In some embodiments, a first metal gate structure further covers the second channel layer. In some embodiments, a second source / drain structure is connected to a first stack of the first channel layer. In some embodiments, the ratio of the first thickness to the second thickness is about 0.7 to about 1.

[0078] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

[0079] A,256a: Part A-A',B-B',C-C',D-D': Section lines BL, W_BL, R_BL: Bit lines BLB,W_BLB: Complementary bit lines CD1: First Common Drain CD2: Second Common Drain D1, D2: Distance G1, G2, W1, W2: Width PD-1, PD-2, PD-4, PD-4: Pull-down transistors PU-1, PU-2, PU-3, PU-4: Pull-up transistors R-PG, PG-1, PG-2, PG-3, PG-4: Through-gate transistors SN: Storage Node SNB: Complementary Storage Node S1, S2: Height T1, T2, T3, T4, T5, T6: Thickness VDD: First voltage VSS: Second voltage WL,R_WL,W_WL: Character lines 10, 20, 30, 40: Structure 100: Method 102,104,106,108,110,112,114,116,118,120,122,124, 126,128: Steps 200: Zone 1 202:Substrate 204: Stacking 206: Sacrifice Layer 208: Channel Layer 212: Fin-like structure 212B: Basal fin structure 212C: Passage Area 212n: n-type active region 212p: p-type active region 212SD: Source / Drain Region 214: Isolation Structure 216: Virtual Dielectric Layer 218: Dummy Electrode Layer 220: Virtual Gate Stack 222: Gate top hard shielding layer 223: Silicon oxide layer 224: Silicon nitride layer 226: Gate spacer layer 228: Source / Drain Trench 229,229': Opening 232: Masking Material 232': Mask layer 232a', 232c': Strip-shaped portion 232b': Rectangular portion 232s-1, 232s-2: Sidewall 234: Patterned photoresist layer 236, 238: Etching process 240: Virtual Layer 242: Indentation of the inner spacer 244: Inner spacer structure 246: Source / Drain Structure 250: Contact Etching Stop Layer 252: Interlayer dielectric layer 254: Gate trench 256, 256-1, 256-2, 256-3, 256-4: Gate structure 258, 260: Transistors 300: Second District 400: Static Random Access Memory Unit 400R: Read Port Section 400W: Write port section 462, 466: Inverter 468N: n-type well 468P:p-type well 470: Well boundary 480: Gate isolation structure 482: Source / drain contact 486: Silicon layer 2080: Channel Component

Claims

1. A method for forming a semiconductor structure, comprising: A structure is provided, comprising: a substrate; a first stack of staggered first channel layers and a first sacrificial layer on the substrate; a first source / drain trench exposing the sidewalls of the first sacrificial layers; a second stack of staggered second channel layers and a second sacrificial layer on the substrate; and a second source / drain trench exposing the sidewalls of the second sacrificial layers; performing a first etching process to selectively remove the first and second sacrificial layers; performing a second etching process on the first channel layers but not the second channel layers to reduce a first thickness of the first channel layers to less than a second thickness of the second channel layers; forming a first source / drain structure in the first source / drain trench and forming a second source / drain structure in the second source / drain trench; and forming a first gate structure to cover the first channel layers and forming a second gate structure to cover the second channel layers.

2. The method for forming a semiconductor structure as described in claim 1, wherein the step of performing the second etching process on the first channel layers but not the second channel layers includes: A masking material is formed on the first channel layers and the second channel layers; A patterned photoresist layer is formed on a first portion of the mask material on the second channel layers; the patterned photoresist layer is used as an etching mask to etch a second portion of the mask material on the first channel layers to remove the second portion of the mask material; and the first channel layers are etched.

3. The method for forming a semiconductor structure as described in claim 1 or 2 further includes: After the second etching process is performed, a dummy layer is formed around the first channel layers and the second channel layers; And after forming the first source / drain structure in the first source / drain trench and forming the second source / drain structure in the second source / drain trench, the dummy layer is removed.

4. A method for forming a semiconductor structure, comprising: A first region and a second region are formed on a substrate, wherein the first region includes a first stack of interleaved first channel layers and a first sacrificial layer, and wherein the second region includes a second stack of interleaved second channel layers and a second sacrificial layer; a first dummy gate structure is formed on the first stack of interleaved first channel layers and the first sacrificial layers, and a second dummy gate structure is formed on the second stack of interleaved second channel layers and the second sacrificial layers; a first source / drain is formed in the first stack of interleaved first channel layers and the first sacrificial layers to be adjacent to the first dummy gate structure; a second source / drain is formed in the second stack of interleaved second channel layers and the second sacrificial layers to be adjacent to the second dummy gate structure; the first sacrificial layers and the second sacrificial layers are selectively removed to release the first channel layers and the second channel layers; a masking layer is formed on the second region but not on the first region; A portion of the first channel layers is removed to reduce the thickness of the first channel layers to less than the thickness of the second channel layers; the masking layer is removed; a first dummy layer is deposited around the first channel layers, and a second dummy layer is deposited around the second channel layers; a first source / drain structure is formed in the first source / drain recess, and a second source / drain structure is formed in the second source / drain recess; and the first dummy gate structure and the first dummy layer are replaced to form a first metal gate structure, and the second dummy gate structure and the second dummy layer are replaced to form a second metal gate structure.

5. A method for forming a semiconductor structure as described in claim 4, wherein the masking layer forms a strip pattern in a top view.

6. A method of forming a semiconductor structure as described in claim 4 or 5, wherein the second region in the top view surrounds the first region.

7. A semiconductor structure comprising: One substrate; A first stack of multiple first channel layers is located on the substrate; A first source / drain structure connected to the first stack of the first channel layers; a second stack of a plurality of second channel layers located on the substrate; a second source / drain structure connected to the second stack of the second channel layers; and a first metal gate structure covering the first channel layers and extending along a direction in its length direction; wherein at least one of the first channel layers has a first thickness and a first width along the direction; wherein at least one of the second channel layers has a second thickness and a second width along the direction, and wherein the second thickness is greater than the first thickness, and the second width is less than or equal to the first width.

8. The semiconductor structure as described in claim 7 further includes a second metal gate structure covering the second channel layers.

9. The semiconductor structure as described in claim 7, wherein the first metal gate structure further covers the second channel layers.

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