Input control methods for energy recovery systems

Abstract

This invention discloses an input control method for an energy recovery system, which sets the maximum values ​​of the input voltage and the output voltage. Next, an input voltage equal to the maximum value is input to the energy recovery system, and the input power is controlled to increase gradually from 0 in fixed increments to calculate the first maximum duty cycle of the main control signal corresponding to the input power when the output voltage equals the maximum value. Then, the input power is controlled to increase gradually from 0 in fixed increments, while the input voltage decreases gradually from the maximum value in fixed increments to calculate the second maximum duty cycle of the main control signal corresponding to the input power and input voltage when the output voltage equals the maximum value. Finally, multiple duty cycle and input power curves corresponding to different input voltages are generated based on the calculation results, and the energy recovery system is controlled accordingly.

Description

Technical Field

[0001] This invention relates to a control method, and more particularly to an input control method. Prior Technology

[0002] Traditional boost converters have a simple architecture. In order to recover power from the grid, the DC link voltage output by a single-phase inverter with a 220-volt input AC power is usually above 380 volts. The preceding DC voltage converter must be able to boost the voltage to more than 380 volts in order to perform power recovery.

[0003] Existing energy recovery systems have DC link voltage designs ranging from 400 to 525 volts, adjustable according to the input DC voltage range of 40 to 60 volts. The first-stage full-bridge voltage converter uses open-loop control with a fixed duty cycle. To reduce input current ripple and stabilize the DC link voltage, the second-stage DC-DC buck-boost converter employs outer voltage loop and inner current loop control to achieve fixed current and voltage requirements. However, under these fixed current and voltage requirements, the expected output specifications cannot be achieved due to the upper limit of the input voltage.

[0004] Therefore, the present invention proposes an input control method to address the aforementioned problems and solve the issues arising from conventional methods. Summary of the Invention

[0005] This invention provides an input control method that increases the upper limit of the input voltage to achieve the desired output specifications.

[0006] In one embodiment of the present invention, an input control method is provided, which is applied to an energy recovery system. The input control method includes the following steps: setting a first maximum value of the input voltage and a second maximum value of the output voltage of the energy recovery system, wherein when the input power of the energy recovery system is 0, the output voltage generated by the energy recovery system receiving the first maximum value, a main control signal, and a conversion control signal is less than or equal to the second maximum value; inputting an input voltage equal to the first maximum value, the main control signal, and the conversion control signal to the energy recovery system, and controlling the input power to increase gradually from 0 in a first fixed amount, so as to calculate when the output voltage is equal to the second maximum value. The system calculates the first maximum duty cycle of the main control signal corresponding to the input power; inputs an input voltage equal to the first maximum value, the main control signal, and the conversion control signal to the energy recovery system; controls the input power to increase gradually from 0 with a first fixed amount, and controls the input voltage to decrease gradually from the first maximum value with a second fixed amount; calculates the second maximum duty cycle of the main control signal corresponding to the input power and the input voltage when the output voltage equals the second maximum value; and creates multiple duty cycle and input power curves corresponding to different input voltages based on the input voltage, input power, first maximum duty cycle, and second maximum duty cycle, and controls the energy recovery system accordingly.

[0007] In one embodiment of the present invention, the energy recovery system includes a full-bridge isolated DC-DC converter circuit and a boost converter. The full-bridge isolated DC-DC converter circuit receives input voltage, input power, and a main control signal. The boost converter is coupled to the full-bridge isolated DC-DC converter circuit, receives a conversion control signal, and generates an output voltage.

[0008] In one embodiment of the present invention, the full-bridge isolated DC-DC voltage conversion circuit includes a first field-effect transistor (FET), a second FET, a third FET, a fourth FET, a first transformer, a fifth FET, a sixth FET, a seventh FET, an eighth FET, a second transformer, a ninth FET, a tenth FET, an eleventh FET, and a twelfth FET. The drain of the second FET is coupled to the source of the first FET, the drain of the third FET is coupled to the drain of the first FET, the drain of the fourth FET is coupled to the source of the third FET, and the source of the fourth FET is coupled to the source of the second FET. The drains of the first and third FETs and the sources of the second and fourth FETs receive the input voltage. One end of the primary side of the first transformer is coupled to the node between the first and second field-effect transistors (FETs) through a first inductor, and the other end is coupled to the node between the third and fourth FETs. The drain of the sixth FET is coupled to the source of the fifth FET, the drain of the seventh FET is coupled to the drain of the fifth FET, the drain of the eighth FET is coupled to the source of the seventh FET, and the source of the eighth FET is coupled to the source of the sixth FET. The drains of the fifth and seventh FETs and the sources of the sixth and eighth FETs receive the input voltage. One end of the primary side of the second transformer is coupled to the node between the fifth and sixth FETs through a second inductor, and the other end is coupled to the node between the seventh and eighth FETs. The drain of the tenth field-effect transistor is coupled to the source of the ninth field-effect transistor; the drain of the eleventh field-effect transistor is coupled to the drain of the ninth field-effect transistor; the drain of the twelfth field-effect transistor is coupled to the source of the eleventh field-effect transistor; and the source of the twelfth field-effect transistor is coupled to the source of the tenth field-effect transistor. One end of the secondary side of the first transformer is coupled to one end of the secondary side of the second transformer; the other end of the secondary side of the first transformer is coupled to the node between the ninth and tenth field-effect transistors; and the other end of the secondary side of the second transformer is coupled to the node between the eleventh and twelfth field-effect transistors. The gates of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth field-effect transistors respectively receive the main control signal.

[0009] In one embodiment of the present invention, in the step of controlling the energy recovery system according to multiple duty cycles and input power curves, the first maximum duty cycle, the second maximum duty cycle, or both are adjusted to reduce the source voltage of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth field-effect transistors to below a preset source withstand voltage value, thereby reducing the number of different slopes of the duty cycles and input power curves, and then the energy recovery system is controlled according to multiple duty cycles and input power curves.

[0010] In one embodiment of the present invention, the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the eighth field-effect transistor, the ninth field-effect transistor, the tenth field-effect transistor, the eleventh field-effect transistor, and the twelfth field-effect transistor are N-channel metal-oxide-semiconductor field-effect transistors.

[0011] In one embodiment of the present invention, the boost converter includes a first capacitor, a thirteenth field-effect transistor (FET), a fourteenth field-effect transistor (FET), and a second capacitor. The first capacitor is coupled between the drain of the eleventh FET and the source of the twelfth FET. The source of the thirteenth FET is coupled to the node between the first capacitor and the drain of the eleventh FET through a third inductor. The drain of the fourteenth FET is coupled to the node between the third inductor and the source of the thirteenth FET. One end of the second capacitor is coupled to the source of the fourteenth FET, and the other end is coupled to the drain of the thirteenth FET. The second capacitor outputs the aforementioned output voltage, and the gates of the thirteenth and fourteenth FETs receive the conversion control signal.

[0012] In one embodiment of the present invention, the thirteenth field-effect transistor and the fourteenth field-effect transistor are N-channel insulated-gate bipolar transistors.

[0013] In one embodiment of the present invention, the second maximum value is less than or equal to the withstand voltage of the second capacitor.

[0014] In one embodiment of the present invention, when the thirteenth field-effect transistor is in the on state, the fourteenth field-effect transistor is in the off state. When the fourteenth field-effect transistor is in the on state, the thirteenth field-effect transistor is in the off state.

[0015] In one embodiment of the present invention, the first, fourth, fifth, eighth, ninth, and twelfth field-effect transistors all receive the same master control signal. The second, third, sixth, seventh, tenth, and eleventh field-effect transistors all receive the same master control signal. When the first, fourth, fifth, eighth, ninth, and twelfth field-effect transistors are in a conducting state, the second, third, sixth, seventh, tenth, and eleventh field-effect transistors are in a turning-off state. When the second, third, sixth, seventh, tenth, and eleventh field-effect transistors are in the on state, the first, fourth, fifth, eighth, ninth, and twelfth field-effect transistors are in the off state.

[0016] Based on the above, the input control method establishes a table for the duty cycle of the main control signal according to the input power and input voltage, so as to increase the upper limit of the input voltage and achieve the expected output specifications.

[0017] To enable your review committee to gain a better understanding of the structural features and effects achieved by the present invention, preferred embodiment diagrams and detailed descriptions are provided below: Simple Explanation of the Diagram

[0018] Figure 1 is a schematic diagram of an energy recovery system according to an embodiment of the present invention. Figure 2 is a flowchart of an input control method according to an embodiment of the present invention. Figure 3 is a waveform diagram of the main control signal and the switching control signal according to an embodiment of the present invention. Figure 4 is a schematic diagram of the duty period versus input power curve according to an embodiment of the present invention. Implementation

[0019] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals in the drawings and description represent the same or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0020] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may be unnecessary.

[0021] In the following description of "one embodiment" or "an embodiment," the term refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of "one embodiment" or "an embodiment" appearing in various places below do not refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0022] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". Furthermore, "coupled" here includes any direct and indirect means of connection. Therefore, if the text describes a master element coupled to a slave element, it means that the master element can be directly connected to the slave element via electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signalally connected to the slave element via other elements or connection means.

[0023] The disclosure is specifically described with reference to the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. Throughout the specification and claims, unless explicitly stated otherwise, the words “a” and “the” include “a or at least one” of the element or component. Furthermore, as used in this disclosure, the singular article also includes descriptions of multiple elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and throughout the claims below, unless explicitly stated otherwise, “in which” may include both “in which” and “on which”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the context of this disclosure and in specific contexts. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing this disclosure. Examples throughout this specification, including examples of any terms discussed herein, are merely illustrative and do not limit the scope or meaning of this disclosure or any illustrative terms. Similarly, this disclosure is not limited to the various embodiments set forth in this specification.

[0024] The following presents an input control method of the present invention, which establishes a table of the duty cycle of the main control signal based on the input power and input voltage to increase the upper limit of the input voltage in order to achieve the expected output specifications.

[0025] Figure 1 is a schematic diagram of an energy recovery system according to an embodiment of the present invention, and Figure 2 is a flowchart of an input control method according to an embodiment of the present invention. Referring to Figures 1 and 2, the input control method of the present invention is described below, which is applied to an energy recovery system 1. The energy recovery system 1 includes a full-bridge isolated DC-DC converter circuit 10, a boost converter 11, and a signal controller 12. The signal controller 12 is coupled to the full-bridge isolated DC-DC converter circuit 10 and the boost converter 11. The full-bridge isolated DC-DC converter circuit 10 is coupled to a battery B, and the boost converter 11 is coupled to the full-bridge isolated DC-DC converter circuit 10. The battery B provides the input voltage and input power to the energy recovery system 1. The signal controller 12 generates main control signals S1 and S2 and conversion control signals S3 and S4. The full-bridge isolated DC-DC converter circuit 10 receives the input voltage, input power, and main control signals S1 and S2. The boost converter 11 receives the conversion control signals S3 and S4 and generates an output voltage Vo.

[0026] In some embodiments of the present invention, the full-bridge isolation stage DC voltage conversion circuit 10 may include a first field-effect transistor T1, a second field-effect transistor T2, a third field-effect transistor T3, a fourth field-effect transistor T4, a first transformer F1, a fifth field-effect transistor T5, a sixth field-effect transistor T6, a seventh field-effect transistor T7, an eighth field-effect transistor T8, a second transformer F2, a ninth field-effect transistor T9, a tenth field-effect transistor T10, an eleventh field-effect transistor T11, and a twelfth field-effect transistor T12. The first field-effect transistor T1, the second field-effect transistor T2, the third field-effect transistor T3, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the eighth field-effect transistor T8, the ninth field-effect transistor T9, the tenth field-effect transistor T10, the eleventh field-effect transistor T11, and the twelfth field-effect transistor T12 can be, but are not limited to, N-channel metal-oxide-semiconductor field-effect transistors. The first field-effect transistor T1, the third field-effect transistor T3, the fifth field-effect transistor T5, and the seventh field-effect transistor T7 are coupled to the positive electrode of battery B, and the second field-effect transistor T2, the fourth field-effect transistor T4, the sixth field-effect transistor T6, and the eighth field-effect transistor T8 are coupled to the negative electrode of battery B. The gates of the first field-effect transistor T1, the second field-effect transistor T2, the third field-effect transistor T3, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the eighth field-effect transistor T8, the ninth field-effect transistor T9, the tenth field-effect transistor T10, the eleventh field-effect transistor T11, and the twelfth field-effect transistor T12 are respectively coupled to the signal controller 12. The drain of the second field-effect transistor T2 is coupled to the source of the first field-effect transistor T1, the drain of the third field-effect transistor T3 is coupled to the drain of the first field-effect transistor T1, the drain of the fourth field-effect transistor T4 is coupled to the source of the third field-effect transistor T3, and the source of the fourth field-effect transistor T4 is coupled to the source of the second field-effect transistor T2. The drains of the first and third field-effect transistors T1 and the sources of the second and fourth field-effect transistors T2 receive the input voltage. One end of the primary side of the first transformer F1 is coupled through the first inductor L1 to the node between the first field-effect transistor T1 and the second field-effect transistor T2, and the other end is coupled to the node between the third field-effect transistor T3 and the fourth field-effect transistor T4. The drain of the sixth field-effect transistor T6 is coupled to the source of the fifth field-effect transistor T5, the drain of the seventh field-effect transistor T7 is coupled to the drain of the fifth field-effect transistor T5, the drain of the eighth field-effect transistor T8 is coupled to the source of the seventh field-effect transistor T7, and the source of the eighth field-effect transistor T8 is coupled to the source of the sixth field-effect transistor T6. The drains of the fifth and seventh field-effect transistors T5 and the sources of the sixth and eighth field-effect transistors T6 receive the input voltage.One end of the primary side of the second transformer F2 is coupled through a second inductor L2 to the node between the fifth field-effect transistor T5 and the sixth field-effect transistor T6, and the other end is coupled to the node between the seventh field-effect transistor T7 and the eighth field-effect transistor T8. The drain of the tenth field-effect transistor T10 is coupled to the source of the ninth field-effect transistor T9, the drain of the eleventh field-effect transistor T11 is coupled to the drain of the ninth field-effect transistor T9, the drain of the twelfth field-effect transistor T12 is coupled to the source of the eleventh field-effect transistor T11, and the source of the twelfth field-effect transistor T12 is coupled to the source of the tenth field-effect transistor T10. One end of the secondary side of the first transformer F1 is coupled to one end of the secondary side of the second transformer F2, the other end of the secondary side of the first transformer F1 is coupled to the node between the ninth field-effect transistor T9 and the tenth field-effect transistor T10, and the other end of the secondary side of the second transformer F2 is coupled to the node between the eleventh field-effect transistor T11 and the twelfth field-effect transistor T12. The gates of the first field-effect transistor T1, the second field-effect transistor T2, the third field-effect transistor T3, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the eighth field-effect transistor T8, the ninth field-effect transistor T9, the tenth field-effect transistor T10, the eleventh field-effect transistor T11, and the twelfth field-effect transistor T12 respectively receive the main control signals S1 and S2.

[0027] In some embodiments of the present invention, the boost converter 11 may include a first capacitor C1, a thirteenth field-effect transistor T13, a fourteenth field-effect transistor T14, and a second capacitor C2. The thirteenth and fourteenth field-effect transistors T13 and T14 may be, but are not limited to, N-channel insulated-gate bipolar transistors. The gates of the thirteenth and fourteenth field-effect transistors T13 and T14 are respectively coupled to the signal controller 12. The first capacitor C1 is coupled between the drain of the eleventh field-effect transistor T11 and the source of the twelfth field-effect transistor T12. The source of the thirteenth field-effect transistor T13 is coupled through a third inductor L3 to the node between the first capacitor C1 and the drain of the eleventh field-effect transistor T11. The drain of the fourteenth field-effect transistor T14 is coupled to the node between the third inductor L3 and the source of the thirteenth field-effect transistor T13. One end of the second capacitor C2 is coupled to the source of the fourteenth field-effect transistor T14, and the other end is coupled to the drain of the thirteenth field-effect transistor T13. The second capacitor C2 outputs the output voltage Vo, and the gates of the thirteenth and fourteenth field-effect transistors T13 and T14 receive the switching control signals S3 and S4.

[0028] In the input control method, as shown in step S10, the signal controller 12 sets a first maximum value for the input voltage of the energy recovery system 1 and a second maximum value for the output voltage Vo. When the input power of the energy recovery system 1 is 0, the output voltage Vo generated by the energy recovery system 1 receiving the first maximum value, main control signals S1 and S2, and conversion control signals S3 and S4 is less than or equal to the second maximum value. When the input power of the energy recovery system 1 is 0, the energy recovery system 1 is not connected to any load. In a preferred embodiment, the second maximum value is less than or equal to the withstand voltage of the second capacitor C2. As shown in step S12, the signal controller 12 and battery B input an input voltage equal to the first maximum value, main control signals S1 and S2, and conversion control signals S3 and S4 to the energy recovery system 1, and control the input power to increase gradually from 0 with a first fixed amount to calculate the first maximum duty cycle of the main control signals S1 and S2 corresponding to the input power when the output voltage Vo equals the second maximum value. For example, the first fixed amount can be, but is not limited to, 250 watts. As shown in step S14, the signal controller 12 sends the input voltage equal to the first maximum value to the battery B, along with the main control signals S1 and S2 and the conversion control signals S3 and S4 to the energy recovery system 1. It controls the input power to increase gradually from 0 with a first fixed amount, and the input voltage to decrease gradually from the first maximum value with a second fixed amount. This is to calculate the second maximum duty cycle of the main control signals S1 and S2 corresponding to the input power and input voltage when the output voltage Vo equals the second maximum value. The second fixed amount can be, but is not limited to, 1 volt. Finally, as shown in step S16, the signal controller 12 generates multiple duty cycle and input power curves corresponding to different input voltages based on the input voltage, input power, first maximum duty cycle, and second maximum duty cycle, and controls the energy recovery system 1 accordingly. If substantially the same result can be obtained, these steps do not necessarily need to be performed in the order shown in Figure 2. To reduce the burden of table lookup, in step S16, the signal controller 12 can adjust the first maximum duty cycle, the second maximum duty cycle, or both, to reduce the source voltage of the first field-effect transistor T1, the second field-effect transistor T2, the third field-effect transistor T3, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the eighth field-effect transistor T8, the ninth field-effect transistor T9, the tenth field-effect transistor T10, the eleventh field-effect transistor T11, and the twelfth field-effect transistor T12 to below the preset source voltage withstand value. This reduces the number of different slopes of the duty cycle and input power curves, ensuring that each duty cycle and input power curve maintains a fixed slope as much as possible. Then, the energy recovery system 1 is controlled according to the above multiple duty cycles and input power curves.

[0029] Figure 3 is a waveform diagram of the main control signal and the conversion control signal according to an embodiment of the present invention. Referring to Figures 1 and 3, in order to ensure the smooth operation of the energy recovery system 1, the voltage waveforms of the main control signals S1 and S2 and the conversion control signals S3 and S4 are shown in Figure 3. The main control signal S1 received by the first field-effect transistor T1, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the eighth field-effect transistor T8, the ninth field-effect transistor T9, and the twelfth field-effect transistor T12 are all the same. The main control signal S2 received by the second field-effect transistor T2, the third field-effect transistor T3, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the tenth field-effect transistor T10, and the eleventh field-effect transistor T11 are all the same. When the first field-effect transistor T1, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the eighth field-effect transistor T8, the ninth field-effect transistor T9, and the twelfth field-effect transistor T12 are in the on state, the second field-effect transistor T2, the third field-effect transistor T3, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the tenth field-effect transistor T10, and the eleventh field-effect transistor T11 are in the off state. When the second field-effect transistor T2, the third field-effect transistor T3, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the tenth field-effect transistor T10, and the eleventh field-effect transistor T11 are in the on state, the first field-effect transistor T1, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the eighth field-effect transistor T8, the ninth field-effect transistor T9, and the twelfth field-effect transistor T12 are in the off state. Furthermore, when the thirteenth field-effect transistor T13 is in the on state, the fourteenth field-effect transistor T14 is in the off state. When the fourteenth field-effect transistor T14 is in the on state, the thirteenth field-effect transistor T13 is in the off state.

[0030] The full-bridge isolated DC-DC voltage conversion circuit 10 employs open-loop control. The boost converter 11 controls the input current and output voltage Vo supplied by battery B to the full-bridge isolated DC-DC voltage conversion circuit 10. In practical operation, the input voltage can be 60~66 volts DC, and the output voltage Vo can reach 400~525 volts DC, which can be used by the subsequent inverter for energy recovery from the 220 volt AC mains power system. Based on the circuit diagram in Figure 1 and the flow chart in Figure 2, the data in Table 1 can be obtained. In Table 1, the input voltage is designed to be 60~66 volts, the output voltage Vo is designed to be 525 volts, and the input power is 0~5000 watts. Because all the data is too large, only a portion of the data is extracted and shown in Table 1 to illustrate the trend of data changes. enter Power (watts) Maximum duty cycle, source voltage (volts) 5000 22.7%,87.3 22.7%,89.3 19.7%,95.2 19.7%,95.7 19.8%,95.9 4500 22.7%,86.2 22.7%,87.9 19.7%,94.6 19.7%,94.7 19.8%,94.8 4000 22.7%,84.7 22.7%,86.3 19.7%,93.4 19.7%,93.4 19.8%,93.4 3500 22.7%,82.4 22.7%,84.7 19.7%,87.9 19.7%,91.1 19.8%,91.1 3200 22.7%,81.6 22.7%,83.2 19.7%,87.1 19.7%,90.3 19.7%,90.3 3000 22.7%,82.4 22.7%,82.4 19.7%,86.3 19.6%,90.3 19.5%,90.3 2500 22.7%,80 22.7%,80 19.6%,84 17.5%,90.3 17.4%,90.3 2200 22.7%,72.1 22.7%,72.9 19.7%,80 16%,89.5 16%,89.5 2000 22.7%,72.1 22.7%,66.6 19.7%,76 15%,89.5V 15.1%,89.5 1800 18.2%,83.1 18%,83.1 17.7%,83.1 14.1%,89.5 14.3%,89.5 1500 15.7%,84 15.7%,84 15.5%,84.7 12.7%,88.7 12.8%,89.5 1000 11.7%,83.2 11.6%,83.9 11.7%,83.9 10.4%,86.3 10.5%,85.5 800 10.4%,82.4 10.2%,82.4 10.4%,82.4 8.7%,85.5 8.3%,87.1 500 7.8%,79..2 7.9%,79.2 8%,79.2 5.9%,84.7 6%,83.1 300 6.5%,71.3 6.4%, 72.1 6.4%, 71.3 4.3%, 74.5 4.3%, 72.1 0 4%, 0 4%, 0 4%, 0 4%, 0 4%, 0 enter Voltage (volts) 60 63 64 65 66 Table 1

[0031] Figure 4 is a schematic diagram of the duty cycle and input power curve according to an embodiment of the present invention. Please refer to Figure 4 and Figure 1. Figure 4 is made according to Table 1, where the thick line indicates an input voltage less than or equal to 64 volts, and the thin line indicates an input voltage greater than 64.5 volts. Figure 4 can satisfy the requirement that the output voltage Vo will not exceed the withstand voltage of the second capacitor C2 under the upper limit of the input voltage, and can still achieve the expected output specifications. Moreover, the drain voltages of the first field-effect transistor T1, the second field-effect transistor T2, the third field-effect transistor T3, the fourth field-effect transistor T4, the fifth field-effect transistor T5, the sixth field-effect transistor T6, the seventh field-effect transistor T7, the eighth field-effect transistor T8, the ninth field-effect transistor T9, the tenth field-effect transistor T10, the eleventh field-effect transistor T11, and the twelfth field-effect transistor T12 will also be lower than the preset drain withstand voltage value. The input control method of this invention can enable the input voltage to exceed 60 volts. Therefore, the input voltage can be provided by connecting 15 3.7-volt lithium polymer batteries or 17 or 18 3.2-volt lithium iron batteries in series, which can meet more usage requirements.

[0032] According to the above embodiments, the input control method builds a table of the duty cycle of the main control signal based on the input power and input voltage to increase the upper limit of the input voltage in order to achieve the expected output specifications.

[0033] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent changes and modifications made to the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

[0034] 1: Energy Recovery System 10: Full-bridge isolated DC-DC voltage conversion circuit 11: Boost Converter 12: Signal Controller B: Battery S1, S2: Main control signals S3, S4: Switching control signals Vo: Output voltage T1: First field-effect transistor T2: Second Field-Effect Transistor T3: Third Field Effect Transistor T4: Fourth Field-Effect Transistor T5: Fifth Field Effect Transistor T6: Sixth Field Effect Transistor T7: Seventh Field Effect Transistor T8: Eighth Field-Effect Transistor T9: Ninth Field-Effect Transistor T10: Tenth Field-Effect Transistor T11: Eleventh Field Effect Transistor T12: Twelfth Field-Effect Transistor T13: Thirteenth Field-Effect Transistor T14: Fourteenth Field-Effect Transistor F1: First Transformer F2: Second Transformer L1: First Inductor L2: Second inductor C1: First capacitor C2: Second capacitor S10, S12, S14, S16: Steps

Claims

1. An input control method for an energy recovery system, comprising the following steps: setting a first maximum value for the input voltage and a second maximum value for the output voltage of the energy recovery system, wherein when the input power of the energy recovery system is 0, the output voltage generated by the energy recovery system receiving the first maximum value, a main control signal, and a conversion control signal is less than or equal to the second maximum value; inputting the input voltage equal to the first maximum value, the main control signal, and the conversion control signal to the energy recovery system, and controlling the input power to increase gradually from 0 by a first fixed amount, to calculate the first maximum duty cycle of the main control signal corresponding to the input power when the output voltage is equal to the second maximum value; The system inputs the input voltage equal to the first maximum value, the main control signal, and the conversion control signal to the energy recovery system, and controls the input power to increase gradually from 0 with the first fixed amount, and the input voltage to decrease gradually from the first maximum value with the second fixed amount, to calculate the second maximum duty cycle of the main control signal corresponding to the input power and the input voltage when the output voltage equals the second maximum value; and generates multiple duty cycle and input power curves corresponding to different input voltages based on the input voltage, the input power, the first maximum duty cycle, and the second maximum duty cycle, and controls the energy recovery system accordingly.

2. The input control method for the energy recovery system as described in claim 1, wherein the energy recovery system comprises: a full-bridge isolated DC-DC converter circuit that receives the input voltage, the input power, and the main control signal; and a boost converter coupled to the full-bridge isolated DC-DC converter circuit, receiving the conversion control signal, and generating the output voltage.

3. The input control method for the energy recovery system as described in claim 2, wherein the full-bridge isolation stage DC voltage conversion circuit comprises: a first field-effect transistor; a second field-effect transistor, the drain of which is coupled to the source of the first field-effect transistor; a third field-effect transistor, the drain of which is coupled to the drain of the first field-effect transistor; a fourth field-effect transistor, the drain of which is coupled to the source of the third field-effect transistor, the source of which is coupled to the source of the second field-effect transistor, wherein the drains of the first and third field-effect transistors and the sources of the second and fourth field-effect transistors receive the input voltage; a first transformer, one end of which is coupled to the node between the first and second field-effect transistors through a first inductor, and the other end of which is coupled to the node between the third and fourth field-effect transistors; and a fifth field-effect transistor; A sixth field-effect transistor, the drain of which is coupled to the source of the fifth field-effect transistor; a seventh field-effect transistor, the drain of which is coupled to the drain of the fifth field-effect transistor; an eighth field-effect transistor, the drain of which is coupled to the source of the seventh field-effect transistor, and the source of which is coupled to the source of the sixth field-effect transistor, wherein the drains of the fifth and seventh field-effect transistors and the sources of the sixth and eighth field-effect transistors receive the input voltage; a second transformer, one end of which is coupled to the node between the fifth and sixth field-effect transistors through a second inductor, and the other end of which is coupled to the node between the seventh and eighth field-effect transistors; a ninth field-effect transistor; and a tenth field-effect transistor, the drain of which is coupled to the source of the ninth field-effect transistor. An eleventh field-effect transistor, the drain of which is coupled to the drain of the ninth field-effect transistor; and a twelfth field-effect transistor, the drain of which is coupled to the source of the eleventh field-effect transistor, and the source of the twelfth field-effect transistor being coupled to the source of the tenth field-effect transistor; wherein one end of the secondary side of the first transformer is coupled to one end of the secondary side of the second transformer, the other end of the secondary side of the first transformer is coupled to the node between the ninth and tenth field-effect transistors, the other end of the secondary side of the second transformer is coupled to the node between the eleventh and twelfth field-effect transistors, and the gates of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth field-effect transistors respectively receive the main control signal.

4. The input control method for the energy recovery system as described in claim 3, wherein in the step of controlling the energy recovery system according to the plurality of duty cycles and input power curves, the first maximum duty cycle, the second maximum duty cycle, or both are adjusted to reduce the source voltage of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth field-effect transistors to below a preset source withstand voltage value, thereby reducing the number of different slopes of the duty cycles and input power curves, and then the energy recovery system is controlled according to the plurality of duty cycles and input power curves.

5. The input control method of the energy recovery system as described in claim 3, wherein the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, the sixth field-effect transistor, the seventh field-effect transistor, the eighth field-effect transistor, the ninth field-effect transistor, the tenth field-effect transistor, the eleventh field-effect transistor, and the twelfth field-effect transistor are N-channel metal-oxide-semiconductor field-effect transistors.

6. The input control method for the energy recovery system as described in claim 3, wherein the boost converter comprises: a first capacitor coupled between the drain of the eleventh field-effect transistor and the source of the twelfth field-effect transistor; a thirteenth field-effect transistor, the source of which is coupled through a third inductor to a node between the first capacitor and the drain of the eleventh field-effect transistor; a fourteenth field-effect transistor, the drain of which is coupled to a node between the third inductor and the source of the thirteenth field-effect transistor; and a second capacitor, one end of which is coupled to the source of the fourteenth field-effect transistor and the other end of which is coupled to the drain of the thirteenth field-effect transistor, wherein the second capacitor outputs the output voltage, and the gates of the thirteenth and fourteenth field-effect transistors receive the conversion control signal.

7. The input control method for the energy recovery system as described in claim 6, wherein the thirteenth field-effect transistor and the fourteenth field-effect transistor are N-channel insulated-gate bipolar transistors.

8. An input control method for an energy recovery system as described in claim 6, wherein the second maximum value is less than or equal to the withstand voltage of the second capacitor.

9. The input control method of the energy recovery system as described in claim 6, wherein when the thirteenth field-effect transistor is in the on state, the fourteenth field-effect transistor is in the off state, and when the fourteenth field-effect transistor is in the on state, the thirteenth field-effect transistor is in the off state.

10. The input control method for the energy recovery system as described in claim 3, wherein the main control signal received by the first, fourth, fifth, eighth, ninth, and twelfth field-effect transistors is the same, and the main control signal received by the second, third, sixth, seventh, tenth, and eleventh field-effect transistors is the same, and the input control signal received by the first, fourth, fifth, eighth, and ninth field-effect transistors is the same. When the twelfth field-effect transistor and the first field-effect transistor are in the on state, the second, third, sixth, seventh, tenth, and eleventh field-effect transistors are in the off state. When the second, third, sixth, seventh, tenth, and eleventh field-effect transistors are in the on state, the first, fourth, fifth, eighth, ninth, and twelfth field-effect transistors are in the off state.

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