Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a substrate, a dielectric layer on the substrate, an oxide semiconductor layer disposed on the dielectric layer, a gate insulating layer, a gate electrode, a protective layer, and a plurality of source / drain electrode layers. The gate insulating layer is formed on the surface of the oxide semiconductor layer. The gate electrode is formed on the surface of the gate insulating layer. The protective layer extends from the edge of the gate insulating layer along the surface of the oxide semiconductor layer. The source / drain electrode layers are located on the oxide semiconductor layer and the protective layer on both sides of the gate electrode.

Description

Technical Field

[0001] This invention relates to a semiconductor manufacturing technology, and more particularly to a semiconductor device and a method for manufacturing the same. Prior Technology

[0002] Oxide semiconductor field-effect transistors (OSFETs) are provided in a BEOL (back-end) structure for advanced applications, such as oxide semiconductor (OS) / silicon (Si) drivers for organic light-emitting diode (OLED) displays.

[0003] However, during the etching of the source / drain electrode layers of an OSFET, metal residues can easily remain on the oxide semiconductor layer, potentially affecting the device's electrical characteristics, such as source-drain short circuits. Furthermore, the etching method for the source / drain electrode layers is typically plasma etching, which can damage the surface of the oxide semiconductor layer, leading to degradation of the OSFET's characteristics and reliability. Summary of the Invention

[0004] The present invention provides a semiconductor device and a method for manufacturing the same, which can prevent the surface of the oxide semiconductor layer from being damaged by etching residues and plasma.

[0005] The semiconductor device of the present invention includes a substrate, a dielectric layer, an oxide semiconductor layer, a gate insulating layer, a gate electrode, a protective layer, and a plurality of source / drain electrode layers. The dielectric layer is disposed on the substrate. The oxide semiconductor layer is disposed on the dielectric layer. The gate insulating layer is formed on the surface of the oxide semiconductor layer. The gate electrode is formed on the surface of the gate insulating layer. The protective layer extends from the edge of the gate insulating layer along the surface of the oxide semiconductor layer. The source / drain electrode layers are disposed on the oxide semiconductor layer and the protective layer on both sides of the gate electrode.

[0006] In one embodiment of the present invention, in a top view, the extension direction of the protective layer is the same as the extension direction of the gate electrode.

[0007] In one embodiment of the present invention, in a top view, the extension direction of the protective layer is perpendicular to the extension direction of the oxide semiconductor layer.

[0008] In one embodiment of the present invention, a first portion of the oxide semiconductor layer is covered by a protective layer, and a second portion of the oxide semiconductor layer is covered by a source / drain electrode layer.

[0009] In embodiments of the present invention, the semiconductor device further includes an interlayer dielectric layer formed on the source / drain electrode layer and the substrate.

[0010] In an embodiment of the present invention, the gate insulating layer is further disposed on the sidewall of the gate electrode.

[0011] In an embodiment of the present invention, in a cross-sectional view, the gate electrode protrudes from a plurality of source / drain electrode layers.

[0012] In one embodiment of the present invention, the plurality of source / drain electrode layers are further disposed on the sidewall of the oxide semiconductor layer.

[0013] The method for manufacturing a semiconductor device according to the present invention includes: forming a dielectric layer on a substrate; forming an oxide semiconductor layer on the dielectric layer; forming a protective layer on a portion of the oxide semiconductor layer; forming a metal layer on the oxide semiconductor layer and the protective layer; forming an interlayer dielectric layer on the metal layer; forming a trench on top of the interlayer dielectric layer, the metal layer and the protective layer by plasma etching; removing the residue of the protective layer below the trench by wet etching until the surface of the oxide semiconductor layer is exposed; forming a gate insulating layer on the surface of the oxide semiconductor layer and forming a gate electrode on the gate insulating layer.

[0014] In another embodiment of the invention, the step of forming the gate insulating layer includes conformally depositing an oxide layer on the sidewalls of the trench and on the surface of the oxide semiconductor layer.

[0015] In another embodiment of the invention, after the metal layer is formed, the metal layer is patterned to define the boundaries of the source / drain electrode layers.

[0016] In another embodiment of the invention, the boundary of the above-mentioned source / drain electrode layer is defined outside the oxide semiconductor layer.

[0017] In another embodiment of the invention, the plasma etching is performed in a time-based mode.

[0018] In another embodiment of the invention, the material of the protective layer includes silicon oxide, and the etchant for wet etching includes hydrofluoric acid (HF).

[0019] In another embodiment of the invention, the material of the protective layer includes silicon nitride, and the etchant for wet etching includes phosphoric acid (H3PO4).

[0020] In another embodiment of the present invention, the step of forming the gate electrode includes forming a conductive material on a substrate to fill the trench, and then removing the conductive material outside the trench.

[0021] Based on the above, since a protective layer is formed on the surface of the oxide semiconductor layer before etching the source / drain electrode layer, the surface of the oxide semiconductor layer can be protected from etching residues and plasma damage. Therefore, source / drain short circuits can be avoided, and the degradation of device performance and reliability is also eliminated.

[0022] To make the above content clearer and easier to understand, several embodiments will be described in detail below with reference to the figures. Simple Explanation of the Diagram

[0023] Figure 1 is a top view of a semiconductor device according to a first embodiment of the present invention. Figure 2 is a cross-sectional view along line II-II' in Figure 1. Figure 3 is a cross-sectional view along line III-III' in Figure 1. Figures 4A to 4F are cross-sectional schematic diagrams of the manufacturing process of a semiconductor device according to a second embodiment of the present invention. Implementation

[0024] To fully understand this disclosure, please refer to the following embodiments and figures. These embodiments have been described in sufficient detail to enable those skilled in the art to practice this disclosure. However, this disclosure can be implemented in many other different forms and should not be limited to the embodiments described below. Other embodiments can be utilized and structural, logical, and electrical changes can be made without departing from the scope of this disclosure. In the figures, elements and their relative dimensions may not be drawn to scale for clarity. For ease of understanding, the same elements in the following embodiments will be represented by the same element symbols.

[0025] Figure 1 is a top view of a semiconductor device according to a first embodiment of the present invention. Figure 2 is a cross-sectional view along line II-II' of Figure 1. Figure 3 is a cross-sectional view along line III-III' of Figure 1.

[0026] Referring to Figures 1, 2, and 3, the semiconductor device 100 of the first embodiment includes at least a substrate 102, a dielectric layer 103, an oxide semiconductor layer OS, a gate electrode 104, a gate insulating layer 106, a protective layer 108, and source / drain electrode layers 110a and 110b. The dielectric layer 103 is disposed on the substrate 102. In some embodiments, the dielectric layer 103 may be a layer in a back-end process (BEOL) structure (not shown), but is not limited thereto. The oxide semiconductor layer OS is disposed on the dielectric layer 103, wherein the material of the oxide semiconductor layer OS is, for example, gallium oxide (GaOx), zinc gallium oxide (Ga₂ZnxOy), or indium gallium zinc oxide (IGZO). The gate insulating layer 106 is formed on the surface S1 of the oxide semiconductor layer OS. The gate electrode 104 is formed on the surface 106s of the gate insulating layer 106, wherein the material of the gate electrode 104 may be a metallic material, such as Cu, Al, Mo, Cr, Ti, TiN, W, and / or Ta. In some embodiments, a gate insulating layer 106 is also disposed on the sidewall 104s of the gate electrode 104. In some embodiments, the material of the gate insulating layer 106 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, gallium oxide, or zinc gallium oxide. A protective layer 108 is formed extending from the edge 106a of the gate insulating layer 106 along the surface S1 of the oxide semiconductor layer OS, wherein the material of the protective layer 108 is, for example, silicon oxide, silicon nitride, etc.

[0027] In some embodiments, in the top view, the extension direction of the protective layer 108 is the same as the extension direction of the gate electrode 104. The extension direction of the protective layer 108 is parallel to line III-III' of FIG1. ​​In some embodiments, in the top view, the extension direction of the protective layer 108 is perpendicular to the extension direction of the oxide semiconductor layer OS, wherein the extension direction of the oxide semiconductor layer OS is parallel to line II-II' of FIG1.

[0028] The source / drain electrode layers 110a and 110b are disposed on the oxide semiconductor layer OS and the protective layer 108 on both sides of the gate electrode 104. The materials of the source / drain electrode layers 110a and 110b can be metallic materials such as Cu, Al, Mo, Cr, Ti, TiN and / or Ta. In some embodiments, a first portion P1 of the oxide semiconductor layer OS is covered by the protective layer 108, and a second portion P2 of the oxide semiconductor layer OS is covered by the source / drain electrode layers 110a and 110b. In some embodiments, for good electrical characteristics, the length L1 of the first portion P1 can be in the range of 0.1 μm to 0.2 μm; while the length L2 of the second portion P2 can be greater than 0.2 μm to form a via in the metallic material. In some embodiments, the gate electrode 104 in FIG. 2 protrudes from the source / drain electrode layers 110a and 110b. In some embodiments, the semiconductor device 100 may further include an interlayer dielectric layer 112 formed on the source / drain electrode layers 110a and 110b and the dielectric layer 103, and the top surface of the interlayer dielectric layer 112 may be coplanar with the top surface of the gate electrode 104.

[0029] In some embodiments, the source / drain electrode layers 110a and 110b may also be disposed on the sidewall S2 of the oxide semiconductor layer OS. Therefore, the source / drain electrode layers 110a and 110b are in direct contact with the oxide semiconductor layer OS and the protective layer 108. Furthermore, the source / drain electrode layers 110a and 110b may be symmetrical with respect to the gate electrode 104, but are not limited thereto. The gate electrode 104, the gate insulating layer 106, the source / drain electrode layers 110a and 110b, the protective layer 108, and the oxide semiconductor layer OS may constitute an oxide semiconductor field-effect transistor.

[0030] Figures 4A to 4F are cross-sectional schematic diagrams of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. The same element symbols as those in the first embodiment are used to represent the same or similar parts and components. The relevant content of the same or similar parts and components can also refer to the content of the first embodiment, and will not be repeated here.

[0031] Referring to FIG4A, a dielectric layer 103 is formed on a substrate 102, and an oxide semiconductor layer OS is formed on the dielectric layer 103. In some embodiments, the step of forming the oxide semiconductor layer OS includes depositing an oxide semiconductor material (not shown) on the dielectric layer 103 and then patterning the oxide semiconductor material.

[0032] Next, referring to FIG4B, a protective layer 108 is formed on a portion of the oxide semiconductor layer OS. In some embodiments, the step of forming the protective layer 108 includes depositing a protective material (not shown) on the oxide semiconductor layer OS and the dielectric layer 103, and then patterning the protective material until a portion of the oxide semiconductor layer OS is exposed. Next, a metal layer 400 is formed on the oxide semiconductor layer OS and the protective layer 108.

[0033] Then, referring to FIG4C, the metal layer 400 can be patterned to define the boundary b1 of the subsequently formed source / drain electrode layer. In some embodiments, the boundary b1 is defined outside the oxide semiconductor layer OS. In some embodiments, an interlayer dielectric layer 112 can be formed on the metal layer 400 and the dielectric layer 103, wherein the method for forming the interlayer dielectric layer 112 includes CVD, spin coating, etc.

[0034] Next, referring to FIG4D, trenches 402 are formed in the top 108t of the interlayer dielectric layer 112, the metal layer 400 of FIG4C, and the protective layer 108 by plasma etching 404, thereby forming source / drain electrode layers 110a and 110b. In some embodiments, during plasma etching 404, a patterned mask 406 is formed on the interlayer dielectric layer 112 as an etching mask, wherein the patterned mask 406 may be a patterned photoresist. In some embodiments, plasma etching 404 is performed in time mode.

[0035] Next, referring to FIG4E, wet etching is performed to remove residues of the protective layer 108 below trench 402 until the surface S1 of the oxide semiconductor layer OS is exposed. In some embodiments, the material of the protective layer 108 includes silicon oxide, and the etchant for wet etching may include hydrofluoric acid (HF). In some embodiments, the material of the protective layer 108 includes silicon nitride, and the etchant for wet etching may include phosphoric acid (H3PO4). In some embodiments, the patterned mask 406 described above may serve as an etching mask during wet etching.

[0036] Next, referring to FIG4F, after removing the patterned mask 406 of FIG4E, a gate insulating layer 106 is formed on the surface S1 of the oxide semiconductor layer OS, and then a gate electrode 104 is formed on the gate insulating layer 106. In some embodiments, the step of forming the gate insulating layer 106 includes conformally depositing an oxide layer on the sidewall S3 of the trench 402 and the surface S1 of the oxide semiconductor layer OS. In some embodiments, the step of forming the gate electrode 104 includes forming a conductive material 408 on the substrate 102 to fill the trench 402, and then removing the conductive material 408 outside the trench 402. In some embodiments, the step of removing the conductive material 408 may include performing a planarization process on the conductive material 408, such as a chemical mechanical polishing (CMP) process, until the top 112t of the interlayer dielectric layer 112 is exposed.

[0037] In summary, the semiconductor device of the present invention has a protective layer on the surface of the oxide semiconductor layer, which protects the surface of the oxide semiconductor layer during plasma etching of the source / drain electrodes. Therefore, etching residues on the oxide semiconductor layer can be prevented, and plasma damage to the oxide semiconductor layer can be prevented. Thus, source / drain short circuits can be avoided, and degradation of device performance and reliability is eliminated.

[0038] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0039] 100: Semiconductor devices 102:Substrate 103: Dielectric layer 104: Gate electrode 104s, S2, S3: Sidewall 106: Gate insulation layer 106a: Edge 106s, S1: Surface 108: Protective layer 108t, 112t: Top 110a, 110b: Source / Drain Electrode Layers 112: Interlayer dielectric layer 400: Metal layer 402: Trench 404: Plasma Etching 406: Patterned Spectrum 408: Conductive materials b1: Boundary L1, L2: Length OS: Oxide semiconductor layer P1: Part 1 P2: Part Two

Claims

1. A semiconductor device, comprising: substrate; A dielectric layer is disposed on the substrate; An oxide semiconductor layer is disposed on the dielectric layer; A gate insulating layer is formed on the surface of the oxide semiconductor layer; A gate electrode is formed on the surface of the gate insulating layer; a protective layer is formed extending from the edge of the gate insulating layer along the surface of the oxide semiconductor layer, and the protective layer is separated from the gate electrode by the gate insulating layer; and a plurality of source / drain electrode layers are disposed on the oxide semiconductor layer and the protective layer on both sides of the gate electrode, wherein the gate insulating layer is further disposed on the sidewall of the gate electrode.

2. The semiconductor device of claim 1, wherein, in a top view, the protective layer extends in the same direction as the gate electrode.

3. The semiconductor device of claim 1, wherein, in a top view, the extension direction of the protective layer is perpendicular to the extension direction of the oxide semiconductor layer.

4. The semiconductor device of claim 1, wherein a first portion of the oxide semiconductor layer is covered by the protective layer, and a second portion of the oxide semiconductor layer is covered by the plurality of source / drain electrode layers.

5. The semiconductor device as claimed in claim 1, further comprising an interlayer dielectric layer formed on the plurality of source / drain electrode layers and the substrate.

6. The semiconductor device of claim 1, wherein, in a cross-sectional view, the gate electrode protrudes from the plurality of source / drain electrode layers.

7. The semiconductor device as claimed in claim 1, wherein the plurality of source / drain electrode layers are further disposed on the sidewalls of the oxide semiconductor layer.

8. A method for manufacturing a semiconductor device, comprising: A dielectric layer is formed on the substrate; An oxide semiconductor layer is formed on the dielectric layer; A protective layer is formed on a portion of the oxide semiconductor layer; A metal layer is formed on the oxide semiconductor layer and the protective layer; an interlayer dielectric layer is formed on the metal layer; a trench is formed on top of the interlayer dielectric layer, the metal layer and the protective layer using a plasma etching method; the residue of the protective layer below the trench is removed by wet etching until the surface of the oxide semiconductor layer is exposed; a gate insulating layer is formed on the surface of the oxide semiconductor layer; and a gate electrode is formed on the gate insulating layer.

9. A method of manufacturing a semiconductor device as claimed in claim 8, wherein the step of forming the gate insulating layer comprises: An oxide layer is conformally deposited on the sidewalls of the trench and on the surface of the oxide semiconductor layer.

10. A method of manufacturing a semiconductor device as claimed in claim 8, wherein after forming the metal layer, the method further includes patterning the metal layer to define the boundaries of a plurality of source / drain electrode layers.

11. A method of manufacturing a semiconductor device as claimed in claim 10, wherein the boundaries of the plurality of source / drain electrode layers are defined outside the oxide semiconductor layer.

12. A method of manufacturing a semiconductor device as claimed in claim 8, wherein the plasma etching is performed in a time-mode.

13. A method of manufacturing a semiconductor device as claimed in claim 8, wherein the material of the protective layer comprises silicon oxide, and the etchant of the wet etching comprises hydrofluoric acid.

14. A method of manufacturing a semiconductor device as claimed in claim 8, wherein the material of the protective layer comprises silicon nitride, and the etchant of the wet etching comprises phosphoric acid.

15. A method of manufacturing a semiconductor device as claimed in claim 8, wherein the step of forming the gate electrode comprises: A conductive material is formed on the substrate to fill the trench; And remove the conductive material outside the trench.

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