Decoder, decoding method, memory controller and memory system

Abstract

This invention provides a decoder, including a first memory and a message update circuit. The first memory is configured to store posterior probability messages. The message update circuit is configured to sequentially read the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory according to a first read order, the first read order being determined based on the position of each non-zero submatrix of the current layer; obtain updated posterior probability messages corresponding to each non-zero submatrix of the current layer based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration; and sequentially write the updated posterior probability messages corresponding to each non-zero submatrix of the current layer into the first memory according to a first write order, the first write order being determined based on the first read order.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and to, but is not limited to, a decoder, a decoding method, a memory controller, and a memory system. Prior Technology

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the storage market due to its high storage density, controllable production costs, and suitable write and erase speeds. However, as people's requirements for storage devices continue to increase, memory devices and their systems still have considerable room for improvement. Summary of the Invention

[0003] This invention provides a decoder, a decoding method, a memory controller, and a memory system.

[0004] In a first aspect, embodiments of the present invention provide a decoder configured to perform layered iterative decoding based on a parity check matrix corresponding to a codeword to be decoded. The decoder includes a first memory and a message update circuit. The first memory is configured to store posterior probability messages. The message update circuit is configured to: sequentially read the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory according to a first reading order; the first reading order is determined based on the position of each non-zero submatrix of the current layer; obtain updated posterior probability messages corresponding to each non-zero submatrix of the current layer based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration; and sequentially write the updated posterior probability messages corresponding to each non-zero submatrix of the current layer into the first memory according to a first writing order; the first writing order is determined based on the first reading order.

[0005] In a second aspect, embodiments of the present invention provide a memory controller, comprising: a processor configured to: receive information of a first read order; and a decoder as described in any of the above embodiments, wherein the message update circuit of the decoder is configured to: sequentially read posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory according to the first read order provided in the information of the first read order.

[0006] Thirdly, embodiments of the present invention provide a memory system, including: a memory device configured to output read data; and a decoder as described in any of the above embodiments, configured to decode codewords to be decoded in the read data.

[0007] In some embodiments, the memory system further includes: an encoder configured to: receive write data and encode the write data; the memory device is further configured to: receive the encoded write data.

[0008] Fourthly, embodiments of the present invention provide a decoding method, comprising: sequentially reading posterior probability messages corresponding to each non-zero submatrix of the current layer from a first memory according to a first reading order; the first reading order being determined based on the position of each non-zero submatrix of the current layer; obtaining updated posterior probability messages corresponding to each non-zero submatrix of the current layer based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration; and sequentially writing the updated posterior probability messages corresponding to each non-zero submatrix of the current layer into the first memory according to a first writing order; the first writing order being determined based on the first reading order.

[0009] In this embodiment of the invention, during layered iterative decoding, the posterior probability messages corresponding to each non-zero submatrix of the current layer are sequentially read from the first memory according to a first reading order, and the updated posterior probability messages corresponding to each non-zero submatrix of the current layer are sequentially written into the first memory according to a first writing order, wherein the first writing order is determined based on the first reading order. By optimizing the reading and writing order of posterior probability messages within a layer, this embodiment of the invention can avoid read / write conflicts of posterior probability messages between layers, thereby effectively reducing idle time and improving decoding efficiency. Simple Explanation of the Diagram

[0010] Figure 1 is a schematic diagram of an exemplary system with a memory system according to an embodiment of the present invention. Figure 2 is a schematic diagram of an exemplary memory card with a memory system according to an embodiment of the present invention. Figure 3 is a schematic diagram of an exemplary solid-state driver with a memory system according to an embodiment of the present invention. Figure 4 is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present invention. Figure 5 is a schematic diagram of an exemplary memory including a memory array and peripheral circuitry according to an embodiment of the present invention. Figure 6 is a second schematic diagram of an exemplary system with a memory system according to an embodiment of the present invention. Figure 7 is an LDPC code parity check matrix according to an embodiment of the present invention. Figure 8 is a two-part diagram corresponding to the LDPC code parity check matrix shown in Figure 7. Figure 9 is an operation block diagram of the layered decoding algorithm of LDPC code according to an embodiment of the present invention. Figure 10 is a schematic diagram of reading and writing a posteriori probability message according to an embodiment of the present invention. Figure 11 is a schematic diagram of the reading and writing sequence of a posteriori probability message corresponding to each non-zero submatrix under a parity check matrix according to an embodiment of the present invention. Figure 12 is a schematic diagram of the structure of a decoder according to an embodiment of the present invention. Figure 13 is a schematic diagram (2) illustrating the reading and writing order of posterior probability messages corresponding to each non-zero submatrix under a parity check matrix according to an embodiment of the present invention. Figure 14 is a schematic diagram (3) illustrating the reading and writing order of posterior probability messages corresponding to each non-zero submatrix under a parity check matrix according to an embodiment of the present invention. Figure 15 is a schematic diagram of the message update circuit according to an embodiment of the present invention. Figure 16 is a schematic diagram (2) illustrating the decoder according to an embodiment of the present invention. Figure 17 is a schematic diagram of the variable node message processing circuit according to an embodiment of the present invention. Figure 18 is a schematic diagram of the posterior probability message processing circuit according to an embodiment of the present invention. Figure 19 is a schematic diagram of the hard-determination process according to an embodiment of the present invention. Figure 20 is a flowchart (1) illustrating the decoding process according to an embodiment of the present invention. Figure 21 is a flowchart (2) illustrating the decoding process according to an embodiment of the present invention. Figure 22 is a flowchart (3) illustrating the decoding process according to an embodiment of the present invention. Figure 23 is a flowchart (4) illustrating the decoding process according to an embodiment of the present invention. Figure 24 is a flowchart (5) illustrating the decoding process according to an embodiment of the present invention. Implementation

[0011] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0012] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, to avoid obscuring the invention, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0013] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0014] It should be understood that spatial relation terms such as "below," "under," "below," "below," "above," "over," etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as "below" or "under" or "below" the other element or feature will be oriented "over" the other element or feature. Therefore, the exemplary terms "below" and "under" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0015] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "compose" and / or "comprise," when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0016] To improve the reliability of data transmission and storage, error-correcting code (ECC) technology has been widely applied in the fields of communication, such as wireless and fiber optic communication, and data storage, such as memory systems. Among various error-correcting codes, LDPC (Low Density Parity Check) code is a parallel iterative decoding algorithm based on a sparse array. It has performance approaching the tractor limit, is simple to decode, and can be performed in parallel, making it one of the most widely used error-correcting codes.

[0017] As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the storage market due to its high storage density, controllable production costs, and suitable write and erase speeds. During data transmission and storage in NAND memory, data errors may occur due to hardware failures, software failures, disk errors, etc. To ensure the integrity of user data, LDPC codes have been proposed for error detection and correction of data stored in memory systems including NAND memory. The memory system provided by this invention will be described below using a memory system including three-dimensional NAND memory as an example.

[0018] Figure 1 is a schematic diagram of an exemplary system with a memory system provided in an embodiment of the present invention. In this embodiment, system 100 may be a mobile phone, desktop computer, notebook computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory. As shown in Figure 1, system 100 may include a host 101 and a memory system 102, and memory system 102 may include one or more memory devices 103 and a memory controller 104. Host 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). Host 101 may be configured to send data to memory system 102 or receive data from memory system 102.

[0019] In some embodiments, memory controller 104 is coupled to memory device 103 and host 101 and is configured to control memory device 103. Memory controller 104 can manage data stored in memory device 103 and communicate with host 101. In some embodiments, memory controller 104 is designed to operate in low-duty-cycle environments, such as in secure digital cards, compact flash memory cards (CFC), and universal serial bus (USB) flash memory drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 104 is designed to operate in high-duty-cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0020] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0021] In one example shown in Figure 2, the memory controller 104 and a single memory device 103 can be integrated into a memory card 201. The memory card 201 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 201 may also include a memory card connector 202 that couples the memory card 201 to a host device (e.g., host 101 in Figure 1). In another example shown in Figure 3, the memory controller 104 and multiple memory devices 103 can be integrated into an SSD (Solid State Disk or Solid State Drive) 203. SSD 203 may also include an SSD connector 204 that couples SSD 203 to a host device (e.g., host 101 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of SSD 203 is greater than the storage capacity and / or operating speed of memory card 201.

[0022] Figure 4 is a circuit diagram of an exemplary memory device 300 including peripheral circuitry provided in an embodiment of the present invention. The memory device 300 may be an example of the memory device 103 in Figure 1. The memory device 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. Taking a three-dimensional NAND-type memory array as an example, the memory cells 305 are NAND memory cells, provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may maintain a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0023] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0024] As shown in Figure 4, each memory cell string 304 may include a bottom select transistor (BST) 307 at its source end and a top select transistor (TST) 306 at its drain end. The bottom select transistor 307 and the top select transistor 306 can be configured to activate the selected memory cell string 304 during read and program operations. In some embodiments, the sources of memory cell strings 304 within the same memory block 303 can be coupled via a common source line (CSL) 310. In other words, all memory cell strings 304 within the same memory block 303 share a common source (ACS). According to some embodiments, the top select transistor 306 of each memory cell string 304 is coupled to a corresponding bit line (BL) 311, and data can be read from or written to the bit line 311 via an output bus (not shown). In some implementations, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0025] As shown in Figure 4, the memory cell string 304 can be organized into multiple memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory cell strings 304 can be coupled via word lines (WL) 312, which selects which row of memory cells 305 is affected by a read or program operation.

[0026] In some embodiments, peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit lines 311, word lines 312, common-source lines 310, bottom select lines 309, and top select lines 308, thereby enabling operation of the memory array 301. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0027] Figure 5 illustrates some exemplary memory devices 300. Peripheral circuitry 302 (not shown) includes a page buffer / sensor amplifier 401, a column decoder / bit line (BL) driver 402, a row decoder / word line (WL) driver 403, a voltage generator 404, control logic 405, a register bank 406, a flash memory interface (I / F) 407, and a data bus 408. It should be understood that in some examples, the memory device 300 may also include additional peripheral circuitry not shown in Figure 5.

[0028] Page buffer / sensor amplifier 401 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory cell strings by applying a bit line voltage generated from voltage generator 404.

[0029] The line decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of memory array 301 and select / deselect word lines of memory blocks. The line decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the line decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the line decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines(s). The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0030] Control logic 405 can be coupled to each part of the peripheral circuitry described above and is configured to control the operation of each part of the peripheral circuitry. A register group 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each part of the peripheral circuitry. Flash memory interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from a host device (not shown) and relay such control commands to control logic 405, and to buffer status information received from control logic 405 and relay such status information to the memory controller. Flash memory interface 407 can also be coupled to column decoder / bit line driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay such data to or from memory array 301.

[0031] Figure 6 is a schematic diagram of a system including a host and a memory system provided in an embodiment of the present invention. As shown in Figure 6, the memory system 102 is connected to the host 101. The memory system 102 may include a memory controller 104 and a memory device 103. The memory controller 104 is used to control the memory device 103 to perform read, write, erase, and other operations. The memory controller 104 and the memory device 103 may also be coupled in any suitable manner. The memory controller 104 may include a host interface (I / F) 1041, a memory interface (I / F) 1042, a control unit 1043, a debugging module 1044, a cache memory 1047, and a bus 1040. The host interface 1041 is a connection interface between the host 101 and the memory controller 104. The host interface 1041 allows the host 101 and the memory controller 104 to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1042 is the connection interface between the memory controller 104 and the memory device 103, and is used to realize data transmission between the memory controller 104 and the memory device 103. The control unit 1043 is used to control the memory system 102 as a whole.

[0032] In some specific embodiments, the control unit 1043 may include one or more units with logic operation capabilities, such as a central processing unit (CPU) and / or a microcontroller unit (MCU).

[0033] In some specific embodiments, cache memory 1047 is used to cache data and can be a volatile memory device with relatively fast read and write speeds, such as static random-access memory (SRAM) and / or dynamic random-access memory (DRAM).

[0034] In some specific embodiments, the debugging module 1044 can be configured to encode and decode data in the memory system using debugging code technology. Specifically, the debugging module 1044 may include an encoder 1045 and a decoder 1046, wherein the encoder 1045 can be configured to encode data to be written to the memory device during a write operation; and the decoder 1046 can be configured to decode codewords to be decoded in the read data during a read operation.

[0035] In some embodiments, the decoder can decode the codeword to be decoded using LDPC layered decoding. Figure 7 shows an exemplary LDPC code parity-check matrix, and Figure 8 is the bipartite graph (also known as a bipartite graph) corresponding to the LDPC code parity-check matrix shown in Figure 7. As shown in Figures 7 and 8, one set of vertices represents the symbol variables, called variable nodes (VN), and the other set of vertices represents the local constraints, called constraint nodes or parity-check nodes (CN). The i-th parity-check node (CNi) and the j-th variable node (CNj) are connected by an edge if and only if the element hij in the parity-check matrix is ​​1. There are m parity-check nodes and n variable nodes in the bipartite graph, corresponding to the m rows and n columns of the parity-check matrix, respectively. For a (n, dv, dc) regular LDPC code, its bipartite graph has m*dc = n*dv edges, and each variable node is connected by dv edges, and each parity-check node is connected by dc edges. In the bipartite graph shown in Figure 8, there are 5 check nodes (i.e., C1, C2, C3, C4 and C5) and 10 variable nodes (i.e., V1, V2, V3, V4, V5, V6, V7, V8, V9 and V10), which correspond to the 5 rows and 10 columns of the check matrix shown in Figure 7, respectively. The bipartite graph has 5*6=10*3 edges, and each variable node is connected by 3 edges, and each check node is connected by 6 edges.

[0036] The basic idea of ​​layered decoding is to divide an LDPC code into multiple sub-codes for iterative decoding. Generally, the rows (check nodes) of the parity-check matrix are divided into several groups, each group representing a layer (one sub-code), and each layer includes multiple sub-matrices. A serial iteration strategy is used between groups, while a conventional fully parallel iteration strategy is used within groups. Intra-group iterative decoding can employ the Sum-Product Algorithm (SPA), the Min-Sum Algorithm (MSA), and a modified MSA. For quasi-cyclic low-density parity-check codes (QC-LDPC), Z rows can be used as a layer, where Z is the size of the sub-matrices.

[0037] In layered decoding, variable nodes are updated after all check nodes for a subcode have been updated; that is, variable nodes are updated after each set of check nodes has been updated. Therefore, in one iteration, the updates of check nodes in later layers utilize variable node messages already updated in earlier layers, unlike the original SPA which uses node information from the previous iteration. This speeds up the decoding convergence. One iteration generally refers to completing one pass of updates to all check nodes. The layered decoding algorithm performs message calculation, updates, and message passing according to the check nodes from low to high order. This ensures that updated confidence messages are immediately transmitted, thereby accelerating convergence and reducing the number of iterations.

[0038] The specific process of layered decoding will be further explained below.

[0039] Figure 9 shows the operation flowchart of the layered decoding algorithm for LDPC codes. As shown in Figure 9, the decoding process of the m-th layer subcode includes: in the current iteration, by adding the posterior probability message (L(Qi)) corresponding to each non-zero submatrix of the m-th layer to the check node message (L(δij,m)) corresponding to each non-zero submatrix of the m-th layer in the previous iteration, the variable node message (L(qij,m)) corresponding to each non-zero submatrix of the m-th layer is obtained. Here, the posterior probability message corresponding to each non-zero submatrix of the m-th layer can be understood as the posterior probability updated during the decoding process of the (m-1)-th layer in the current iteration. The probability messages are obtained by combining the variable node messages (L(qij,m)) corresponding to each non-zero submatrix in layer m with algorithms such as the sum-product decoding algorithm and the minimum sum algorithm. Then, the variable node messages corresponding to each non-zero submatrix in layer m are added to the check node messages corresponding to each non-zero submatrix in layer m to obtain the updated posterior probability messages corresponding to each non-zero submatrix in layer m. In the decoding of layer m, only the posterior probability messages corresponding to the non-zero submatrix in layer m are updated. These posterior probability messages are also called the Log-Likelihood Ratio (LLR).

[0040] As can be seen from the above decoding process, the posterior probability messages updated in the layered decoding iterations all use the latest check node messages. This is why the layered decoding algorithm converges faster than the minimum sum decoding algorithm. However, the message updates in the layered algorithm are sequentially updated row by row. Increasing the parallelism of the sequential decoding is a challenge for achieving high throughput. During sequential decoding, the next layer of decoding usually needs the posterior probability information output by the previous layer. Therefore, it is necessary to wait for the previous layer to output the posterior probability information before proceeding to the next layer. This waiting time is called the "idle time". Specifically, as shown in Figure 10, when decoding Layer II, updating the check node message requires reading the posterior probability messages corresponding to all non-zero submatrices in Layer II (the posterior probability messages corresponding to each non-zero submatrix in Layer II are the updated posterior probability messages from Layer I decoding, i.e., the updated posterior probability messages from Layer I written by LLR as shown in Figure 10). Only after the check node message (C2V) is valid can the posterior probability messages be updated, and the updated posterior probability messages for each non-zero submatrix in Layer II be written back. Before the posterior probability message for a certain column in Layer I is written back, the posterior probability message for that column in Layer II cannot be read. The cache in Figure 10 can be understood as the third memory in the following text, which is configured to store variable node messages.

[0041] Figure 11 shows a schematic diagram of the reading and writing order of the posterior probability messages corresponding to each non-zero submatrix under a parity check matrix. As shown in Figure 11, the verification matrix includes 16 columns (1 to 16) and 8 layers (I to VIII). In the LLR readout related to layer I, the posterior probability messages corresponding to each non-zero submatrix of layer I are read, and these posterior probability messages are the updated posterior probability messages of layer VIII in the previous iteration. In the LLR writeout related to layer I, the updated posterior probability messages of each non-zero submatrix of layer I in the current iteration are written. In the LLR readout related to layer II, the posterior probability reading for the non-zero submatrix in the same column as layer I actually reads the updated posterior probability messages of the corresponding non-zero submatrix in layer I. Therefore, the updated posterior probability messages of the corresponding non-zero submatrix in layer I must be written before the posterior probability messages of the corresponding non-zero submatrix in layer II can be read. Referring to Figure 11, the second column of layer I is a zero submatrix. Therefore, during the decoding of layer I, it is not necessary to update the posterior probability message corresponding to the zero submatrix in the second column. After the LLR related to layer I is read out, the posterior probability message of the non-zero submatrix in the second column of layer II can be read out immediately. However, the reading out of the posterior probability message of the non-zero submatrix in the third column of layer II can only be performed after the updated posterior probability message of the non-zero submatrix in the third column of layer I is written out. Therefore, there will be a certain idle time between the reading out of the posterior probability message corresponding to the non-zero submatrix in the second column of layer II and the reading out of the posterior probability message corresponding to the non-zero submatrix in the third column of layer II.

[0042] In the above embodiments, sequential reading and sequential writing of post-proof probability messages can easily cause inter-layer read / write conflicts, requiring waiting for write-back before reading again, resulting in idle time. How to reduce idle time and improve decoding efficiency has become an urgent problem to be solved at this stage.

[0043] The present invention proposes the following embodiments.

[0044] This invention provides a decoder configured to perform hierarchical iterative decoding based on the parity check matrix corresponding to the codeword to be decoded, as shown in Figure 12. The decoder includes a first memory 501 and a message update circuit 502. The first memory 501 is configured to store posterior probability messages. The message update circuit 502 is configured to: sequentially read the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory 501 according to a first reading order; the first reading order is determined based on the position of each non-zero submatrix of the current layer; obtain updated posterior probability messages corresponding to each non-zero submatrix of the current layer based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration; and sequentially write the updated posterior probability messages corresponding to each non-zero submatrix of the current layer into the first memory 501 according to a first writing order; the first writing order is determined based on the first reading order.

[0045] In this embodiment of the invention, during layered iterative decoding, the posterior probability messages corresponding to each non-zero submatrix of the current layer are sequentially read from the first memory 501 according to a first reading order, and the updated posterior probability messages corresponding to each non-zero submatrix of the current layer are sequentially written to the first memory 501 according to a first writing order, wherein the first writing order is determined based on the first reading order. By optimizing the reading and writing order of posterior probability messages within a layer, this embodiment of the invention can avoid conflicts between reading and writing posterior probability messages between layers, thereby effectively reducing idle time and improving decoding efficiency.

[0046] In this embodiment of the invention, the first memory 501 is a volatile memory, including but not limited to Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).

[0047] In some embodiments, the first reading order is determined based on the positional relationship between each non-zero submatrix of the current layer and the non-zero submatrix of the previous layer and the two layers before the current layer.

[0048] Figure 13 illustrates a second schematic diagram of the reading and writing sequence of posterior probability messages corresponding to each non-zero submatrix under a check matrix. Referring to the check matrix shown in Figure 13, this check matrix includes eight layers, from layer I to layer VIII, and consists of 16 columns, from column 1 to column 16. Each layer includes both zero and non-zero submatrixes. The layer preceding layer I is layer VIII, and the two layers preceding layer I are layer VII; the layer preceding layer II is layer I, and the two layers preceding layer II are layer VIII; the layer preceding layer III is layer II, and the two layers preceding layer III are layer I; the situations for the layers preceding and preceding layers of other layers are similar and will not be described further.

[0049] In some embodiments, based on the positional relationship between the non-zero submatrices of each layer and the non-zero submatrices of the previous and two layers prior to each layer, the non-zero submatrices of each layer are divided into a first category, a second category, and a third category; wherein, in the column containing the non-zero submatrices of the first category of the current layer, the previous layer and the two layers prior to the current layer are both zero submatrices; in the column containing the non-zero submatrices of the second category of the current layer, the previous layer of the current layer is a zero submatrice, and the two layers prior to the current layer are non-zero submatrices; in the column containing the non-zero submatrices of the third category of the current layer, the previous layer of the current layer is a non-zero submatrice.

[0050] As shown in step 1 of Figure 13, the non-zero sub-matrices of layer I are divided into three categories. The first category includes the non-zero sub-matrices of layer I in column 16, and layers VII and VIII in column 16 are all zero sub-matrices. The second category includes the non-zero sub-matrices of layer I in columns 1, 4, 9, and 14, and layers VIII in columns 1, 4, 9, and 14 are all zero sub-matrices, and layers VII in columns 1, 4, 9, and 14 are all non-zero sub-matrices. The third category includes the non-zero sub-matrices of layer I in columns 3, 6, 8, 11, and 13, and layers VIII in columns 3, 6, 8, 11, and 13 are all non-zero sub-matrices. The non-zero submatrices of layer II are divided into three categories. The first category includes the non-zero submatrices of layer II in column 5, while layers I and VIII in column 5 are all zero submatrices. The second category includes the non-zero submatrices of layer II in columns 2, 10, and 15, while layers I in columns 2, 10, and 15 are all zero submatrices, and layers VIII in columns 2, 10, and 15 are all non-zero submatrices. The third category includes the non-zero submatrices of layer II in columns 3, 8, 13, and 16, while layers I in columns 3, 8, 13, and 16 are all non-zero submatrices. The division of the non-zero submatrices of other layers into these three categories is similar and will not be elaborated further.

[0051] In some embodiments, the message update circuit 502 is configured to sequentially read from the first memory 501 the posterior probability messages corresponding to non-zero submatrices of the first class in the current layer, the posterior probability messages corresponding to non-zero submatrices of the second class in the current layer, and the posterior probability messages corresponding to non-zero submatrices of the third class in the current layer.

[0052] Following the first reading order, the posterior probability messages corresponding to the first type of non-zero submatrices, the second type of non-zero submatrices, and the third type of non-zero submatrices in the current layer are read sequentially from the first memory 501. This can be understood as follows: in the first reading order, the reading of the posterior probability messages corresponding to the first type of non-zero submatrices is arranged first, the reading of the posterior probability messages corresponding to the second type of non-zero submatrices is arranged in the middle, and the reading of the posterior probability messages corresponding to the third type of non-zero submatrices is arranged last.

[0053] Referring to Figure 13, in the reading of the posterior probability message of the first layer, the posterior probability message corresponding to the non-zero submatrix of the first class in the first layer (the non-zero submatrix of the first layer in column 16) is read first, then the posterior probability message corresponding to the non-zero submatrix of the second class in the first layer (the non-zero submatrix of the first layer in columns 1, 4, 9, and 14) is read, and finally the posterior probability message corresponding to the non-zero submatrix of the third class in the first layer (the non-zero submatrix of the first layer in columns 3, 6, 8, 11, and 13) is read. In reading the posterior probability messages of the second layer, the posterior probability messages corresponding to the non-zero submatrices of the first class in the second layer (the non-zero submatrices of the second layer in column 5) are read first, then the posterior probability messages corresponding to the non-zero submatrices of the second class in the second layer (the non-zero submatrices of the second layer in columns 2, 10, and 15) are read, and finally the posterior probability messages corresponding to the non-zero submatrices of the third class in the second layer (the non-zero submatrices of the second layer in columns 3, 8, 13, and 16) are read.

[0054] In some embodiments, when reading the posterior probability message corresponding to the non-zero submatrix belonging to the second category in the non-zero submatrix of the current layer, the message update circuit 502 is configured to: sequentially read the posterior probability message corresponding to the first part of the non-zero submatrix, the posterior probability message corresponding to the second part of the non-zero submatrix, and the posterior probability message corresponding to the third part of the non-zero submatrix from the first memory 501; wherein, in the column where the first part of the non-zero submatrix is ​​located, the non-zero submatrix of the first two layers of the current layer belongs to the first category; in the column where the second part of the non-zero submatrix is ​​located, the non-zero submatrix of the first two layers of the current layer belongs to the second category; and in the column where the third part of the non-zero submatrix is ​​located, the non-zero submatrix of the first two layers of the current layer belongs to the third category.

[0055] The sequential reading of the posterior probability messages corresponding to the first part of the non-zero submatrix, the second part of the non-zero submatrix, and the third part of the non-zero submatrix from the first memory 501 can be understood as follows: when reading the posterior probability messages corresponding to the non-zero submatrix belonging to the second category in the current layer, the posterior probability messages corresponding to the first part of the non-zero submatrix are read first, then the posterior probability messages corresponding to the second part of the non-zero submatrix are read, and finally the posterior probability messages corresponding to the third part of the non-zero submatrix are read.

[0056] Figure 14 illustrates the reading and writing order of posterior probability messages corresponding to each non-zero submatrix under a parity check matrix. Step 2 in Figure 14 further adjusts the reading order of posterior probability messages corresponding to the second and third types of non-zero submatrixes. Referring to Figure 14, when the current layer is layer I, layer I does not contain the first part of non-zero submatrixes; the second part of non-zero submatrixes in layer I consists of the non-zero submatrixes in columns 1, 4, and 14 of layer I, and the non-zero submatrixes in columns 1, 4, and 14 of layer VII belong to the second type; the third part of non-zero submatrixes in layer I consists of the non-zero submatrixes in column 9 of layer I, and the non-zero submatrixes in column 9 of layer VII belong to the third type. When reading the posterior probability messages corresponding to the non-zero submatrices of the second class in the non-zero submatrices of the first layer, the posterior probability messages corresponding to the non-zero submatrices of the first layer in columns 1, 4, and 14 are read first, and the posterior probability messages corresponding to the non-zero submatrices of the first layer in column 9 are read last.

[0057] Referring back to Figure 14, when the current layer is layer II, layer II does not contain the first part of the non-zero sub-matrix; the second part of the non-zero sub-matrix in layer II consists of the non-zero sub-matrixes in columns 2, 10, and 15 of layer II, and the non-zero sub-matrixes in columns 2, 10, and 15 of layer VIII belong to the second category; layer II does not contain the third part of the non-zero sub-matrix. When reading the posterior probability messages corresponding to the non-zero sub-matrixes belonging to the second category in the non-zero sub-matrix of layer II, the posterior probability messages corresponding to the non-zero sub-matrixes in columns 2, 10, and 15 of layer II are read sequentially.

[0058] In some embodiments, when reading the posterior probability message corresponding to the non-zero submatrix belonging to the third category in the non-zero submatrix of the current layer, the message update circuit 502 is configured to: sequentially read the posterior probability message corresponding to the fourth part of the non-zero submatrix, the posterior probability message corresponding to the fifth part of the non-zero submatrix, and the posterior probability message corresponding to the sixth part of the non-zero submatrix from the first memory 501; wherein, in the column where the fourth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the first category; in the column where the fifth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the second category; and in the column where the sixth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the third category.

[0059] The sequential reading of the posterior probability messages corresponding to the fourth, fifth, and sixth non-zero submatrices from the first memory 501 can be understood as follows: when reading the posterior probability messages corresponding to the third type of non-zero submatrices in the current layer, the posterior probability messages corresponding to the fourth, fifth, and sixth non-zero submatrices are read first.

[0060] Referring to Figure 14, when the current layer is Layer I, the fourth part of the non-zero submatrix in Layer I consists of the non-zero submatrixes in columns 3, 8, and 13 of Layer I, and the non-zero submatrixes in columns 3, 8, and 13 of Layer VIII belong to the first category; Layer I does not contain the fifth part of the non-zero submatrix; the sixth part of the non-zero submatrix in Layer I consists of the non-zero submatrixes in columns 6 and 11 of Layer I, and the non-zero submatrixes in columns 6 and 11 of Layer VIII belong to the third category. When reading the posterior probability messages corresponding to the non-zero submatrixes belonging to the third category in the non-zero submatrixes of Layer I, the posterior probability messages corresponding to the non-zero submatrixes in columns 3, 8, and 13 of Layer I are read first, and the posterior probability messages corresponding to the non-zero submatrixes in columns 6 and 11 of Layer I are read last.

[0061] Referring back to Figure 14, when the current layer is Layer II, the fourth non-zero submatrix in Layer II is the non-zero submatrix of Layer II in column 16, and the non-zero submatrix of Layer I in column 16 belongs to the first category; Layer II does not contain the fifth non-zero submatrix; the sixth non-zero submatrix in Layer II is the non-zero submatrix of Layer II in columns 3, 8, and 13, and the non-zero submatrix of Layer I in columns 3, 8, and 13 belongs to the third category. When reading the posterior probability messages corresponding to the non-zero submatrix of Layer II belonging to the third category, the posterior probability messages corresponding to the non-zero submatrix of Layer II in column 16 are read first, and the posterior probability messages corresponding to the non-zero submatrix of Layer II in columns 3, 8, and 13 are read last.

[0062] In some embodiments, the first write order is determined based on the first read order and the positional relationship between each non-zero submatrix of the current layer and the non-zero submatrix of the next layer.

[0063] Referring to the verification matrix shown in Figure 14, the layer following layer VIII is layer I, the layer following layer I is layer II, and the situation of the layer following each of the other layers is similar, and will not be described again.

[0064] In some embodiments, the message update circuit 502 is configured to sequentially write the posterior probability message corresponding to the non-zero submatrix of the current layer whose column is a non-zero submatrix in the next layer of the current layer, and the posterior probability message corresponding to the non-zero submatrix of the current layer whose column is a zero submatrix in the next layer of the current layer into the first memory 501.

[0065] The phrase "a non-zero submatrix of the current layer whose column is a non-zero submatrix in the next layer" mentioned above and below refers to a non-zero submatrix of the current layer whose column is a non-zero submatrix in the next layer. Similarly, the phrase "a non-zero submatrix of the current layer whose column is a zero submatrix in the next layer" mentioned above and below refers to a non-zero submatrix of the current layer whose column is a zero submatrix in the next layer. Furthermore, the sequential writing of the posterior probability messages corresponding to the non-zero submatrices of the current layer whose columns are non-zero submatrices in the next layer of the current layer, and the posterior probability messages corresponding to the non-zero submatrices of the current layer whose columns are zero submatrices in the next layer of the current layer, into the first memory 501 can be understood as follows: the writing of the posterior probability messages corresponding to the non-zero submatrices of the current layer whose columns are non-zero submatrices in the next layer of the current layer is first, and the writing of the posterior probability messages corresponding to the non-zero submatrices of the current layer whose columns are zero submatrices in the next layer of the current layer is second.

[0066] Referring to Figure 14, when the current layer is layer I, columns 16, 3, 8, and 13 of layer II are all non-zero submatrices, and columns 1, 4, 14, 9, 6, and 11 of layer II are all zero submatrices. Based on the first reading order, further adjustments are made: the posterior probability messages corresponding to the non-zero submatrices of layer I in columns 16, 3, 8, and 13 are written first, and the posterior probability messages corresponding to the non-zero submatrices of layer I in columns 1, 4, 14, 9, 6, and 11 are written later. The writing order of the posterior probability messages corresponding to each non-zero submatric of layer I in columns 16, 3, 8, and 13 is consistent with the reading order, and the writing order of the posterior probability messages corresponding to each non-zero submatric of layer I in columns 1, 4, 14, 9, 6, and 11 is consistent with the reading order.

[0067] As shown in Figure 14, by optimizing the reading and writing order of the posterior probability messages within the layer, the posterior probability messages corresponding to each non-zero submatrix of the second layer have no idle time when being read out, thereby greatly improving the decoding efficiency.

[0068] In some embodiments, the message update circuit 502 is configured to: obtain updated posterior probability messages corresponding to each non-zero submatrix of the current layer based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the check node messages corresponding to each non-zero submatrix of the current layer in the previous iteration.

[0069] In some embodiments, as shown in Figures 15 and 16, the message update circuit 502 includes: a variable node message processing circuit 503, a check node message processing circuit 504, and a posterior probability message processing circuit 505; wherein, the variable node message processing circuit 503 is configured to: sequentially read the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory 501 according to a first reading order; and, based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the check node messages corresponding to each non-zero submatrix of the current layer in the previous iteration, obtain the corresponding posterior probability messages of each non-zero submatrix of the current layer. The variable node message processing circuit 504 is configured to: obtain the check node message corresponding to each non-zero submatrix of the current layer based on the variable node message corresponding to each non-zero submatrix of the current layer and the first algorithm; the posterior probability message processing circuit 505 is configured to: obtain the updated posterior probability message corresponding to each non-zero submatrix of the current layer based on the variable node message corresponding to each non-zero submatrix of the current layer and the check node message corresponding to each non-zero submatrix of the current layer; and, sequentially write the updated posterior probability message corresponding to each non-zero submatrix of the current layer into the first memory 501 according to the first writing order.

[0070] In this embodiment of the invention, during the decoding of the current layer, after reading the posterior probability messages corresponding to each non-zero submatrix of the current layer sequentially from the first memory 501 according to the first reading order, the variable node message processing circuit 503 is configured to: add the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration to the check node messages corresponding to each non-zero submatrix of the current layer in the negative previous iteration, thereby obtaining the variable node messages corresponding to each non-zero submatrix of the current layer. The posterior probability message processing circuit 505 is configured to: add the variable node messages corresponding to each non-zero submatrix of the current layer to the check node messages corresponding to each non-zero submatrix of the current layer, thereby obtaining the updated posterior probability messages corresponding to each non-zero submatrix of the current layer. After obtaining the updated posterior probability messages corresponding to each non-zero submatrix of the current layer, the posterior probability message processing circuit 505 is configured to: write the updated posterior probability messages corresponding to each non-zero submatrix of the current layer sequentially into the first memory 501 according to the first writing order.

[0071] In some embodiments, the first algorithm includes a sum-product decoding algorithm and a minimum sum algorithm.

[0072] In some embodiments, as shown in Figures 12 and 16, the decoder further includes a second memory 509; as shown in Figures 16 and 17, the variable node message processing circuit 503 includes a first control circuit 506, a third memory 507, and a variable node message update circuit 508; wherein, the first control circuit 506 is configured to: obtain a read order table from the second memory 509; and, read the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory 501 in the first read order according to the first read order table; the variable node message update circuit 508 is configured to: perform a first operation on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the check node messages corresponding to each non-zero submatrix of the current layer in the previous iteration to obtain the variable node messages corresponding to each non-zero submatrix of the current layer; the third memory 507 is configured to: store the variable node messages corresponding to each non-zero submatrix of the current layer.

[0073] In some specific examples, the variable node message update circuit 508 includes, but is not limited to, multipliers and adders.

[0074] In some specific examples, the second memory 509 and the third memory 507 are both volatile memories, including but not limited to random access memory, dynamic random access memory, static random access memory, synchronous dynamic random access memory, and double data rate synchronous dynamic random access memory.

[0075] The first operation here includes, but is not limited to, addition. By adding the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the check node messages corresponding to each non-zero submatrix of the current layer in the negative previous iteration, the variable node messages corresponding to each non-zero submatrix of the current layer are obtained.

[0076] In some embodiments, the first reading order can be determined by script software through analysis of the parity check matrix. In some specific examples, the information of the first reading order can be embedded together with the information of the parity check matrix in the firmware of the memory controller, and written into the second memory 509 in the decoder by the control unit of the memory controller.

[0077] In some embodiments, the second memory 509 further stores flag information; the flag information is used to indicate whether the column containing each non-zero submatrix of the current layer is a non-zero submatrix in the next layer of the current layer; as shown in Figures 16 and 18, the posterior probability message processing circuit 505 includes: an address update circuit 510, a second control circuit 511, a posterior probability update circuit 512, and a third control circuit 513; wherein, the address update circuit 510 is configured to: generate a second reading order based on the first reading order and the flag information; in the second reading order, the variable node messages corresponding to the non-zero submatrix of the current layer whose column is a non-zero submatrix in the next layer of the current layer are read first, and the messages corresponding to the non-zero submatrix of the current layer whose column is a non-zero submatrix in the next layer of the current layer are read first. The variable node messages corresponding to the non-zero submatrices of the current layer that are zero submatrices in the next layer of the current layer are read in the order of the second control circuit 511, which is configured to read the variable node messages corresponding to each non-zero submatrice of the current layer stored in the third memory 507 according to the second read order; the posterior probability update circuit 512 is configured to obtain the updated posterior probability messages corresponding to each non-zero submatrice of the current layer based on the check node messages and variable node messages corresponding to each non-zero submatrices of the current layer; the third control circuit 513 is configured to write the updated posterior probability messages corresponding to each non-zero submatrices of the current layer into the first memory 501 according to the first write order; the first write order is the same as the second read order.

[0078] In some specific examples, the posterior probability update circuit 512 includes, but is not limited to, an adder.

[0079] In some specific examples, the flag information corresponding to each non-zero submatrix in the current layer can be represented by 1 bit. For example: when a column containing a non-zero submatrix in the current layer is also a non-zero submatrix in the layer below, the flag information corresponding to that non-zero submatrix is ​​1; when a column containing a non-zero submatrix in the current layer is also a zero submatrix in the layer below, the flag information corresponding to that non-zero submatrix is ​​0. Alternatively, when a column containing a non-zero submatrix in the current layer is also a non-zero submatrix in the layer below, the flag information corresponding to that non-zero submatrix is ​​0; when a column containing a non-zero submatrix in the current layer is also a zero submatrix in the layer below, the flag information corresponding to that non-zero submatrix is ​​1.

[0080] In some specific examples, the third memory 507 not only stores variable node messages but also the addresses of the posterior probability messages corresponding to the variable node messages. The address update circuit 510 divides the variable node messages written to the third memory 507 into two columns based on flag information. The first column contains variable node messages corresponding to non-zero submatrices in the current layer whose column contains a non-zero submatrix in the next layer. The second column contains variable node messages corresponding to non-zero submatrices in the current layer whose column contains a zero submatrix in the next layer. The address update circuit 510 can identify the corresponding flag information and reads the variable node messages from the third memory 507 first, followed by the variable node messages from the second column, thus generating a second reading order. The second control circuit 511 reads the variable node messages corresponding to each non-zero submatrix in the current layer stored in the third memory 507 according to the second reading order. When reading the variable node messages corresponding to each non-zero submatrix of the current layer stored in the third memory 507, the second control circuit 511 also reads out the address of the posterior probability message corresponding to the variable node message, generates a first writing order and propagates it along with the posterior probability message, and the third control circuit 513 executes the writing of the posterior probability message according to the first writing order.

[0081] In this embodiment of the invention, the first control circuit 506, the second control circuit 511, and the third control circuit 513 may each include one or more units with logical operation capabilities, such as a central processing unit (CPU) and / or a microcontroller unit (MCU).

[0082] The second reading order is the order in which the variable nodes corresponding to each non-zero submatrix of the current layer are read. This second reading order can be arranged according to the column number of each non-zero submatrix in the current layer. For example, if the current layer is layer I, the second reading order is 16, 3, 8, 13, 1, 4, 14, 9, 11, 6, that is, arranged from front to back. The first writing order is the order in which the updated posterior probability messages corresponding to each non-zero submatrix of the current layer are written. This first writing order can be arranged according to the column number of each non-zero submatrix in the current layer. For example, if the current layer is layer I, the first writing order is 16, 3, 8, 13, 1, 4, 14, 9, 11, 6, that is, arranged from front to back. The fact that the first writing order and the second reading order are the same in the above embodiment can be understood as the column number of each non-zero submatrix in the current layer being in the same order.

[0083] In some embodiments, as shown in FIG12, the decoder further includes a hard decision circuit 514; the hard decision circuit 514 is configured to: generate a decoding output vector based on the posterior probability messages corresponding to each non-zero submatrix of the current layer; obtain the decoding result of the current layer in the current iteration based on the decoding output vector and the parity check matrix; and determine whether to stop decoding based on the decoding result, whether the current layer is the last layer of the parity check matrix, and whether the number of iterations exceeds the number of iterations threshold.

[0084] In some embodiments, the hard decision circuit 514 is configured to: determine that the element in the decoded output vector corresponding to the first posterior probability message is 0 based on the first posterior probability message in the posterior probability messages corresponding to each non-zero submatrix of the current layer being greater than or equal to 0; determine that the element in the decoded output vector corresponding to the first posterior probability message is 1 based on the first posterior probability message in the posterior probability messages corresponding to each non-zero submatrix of the current layer being less than 0; perform a second operation on the decoded output vector and the transpose of the parity check matrix to obtain the decoding result of the current layer after decoding in the current iteration; and stop decoding based on the decoding result being 0, or based on the current iteration number being equal to the iteration number threshold and the current layer being the last layer of the parity check matrix.

[0085] The decoded output vector includes multiple elements, each determined by a corresponding posterior probability message. The first posterior probability message is any posterior probability message among the posterior probability messages corresponding to each non-zero submatrix of the current layer. When the first posterior probability message is greater than or equal to 0, the element in the decoded output vector corresponding to the first posterior probability message is 0; when the first posterior probability message is less than 0, the element in the decoded output vector corresponding to the first posterior probability message is 1.

[0086] In some embodiments, if a submatrix in the current layer is a zero submatrix, the posterior probability message corresponding to that zero submatrix will not be updated in the decoding of the current layer. Instead, the posterior probability message corresponding to that zero submatrix will use the latest posterior probability message from the column where the zero submatrix was located. Each submatrix in the current layer corresponds to an element in the decoded output vector.

[0087] In some specific examples, the hard-decision circuit 514 is further configured to: determine that the element in the decoded output vector corresponding to the second a posteriori probability message is 0 based on the second a posteriori probability message in the a posteriori probability messages corresponding to each zero submatrix of the current layer being greater than or equal to 0; and determine that the element in the decoded output vector corresponding to the second a posteriori probability message is 1 based on the second a posteriori probability message in the a posteriori probability messages corresponding to each non-zero submatrix of the current layer being less than 0. The second a posteriori probability message is any a posteriori probability message among the a posteriori probability messages corresponding to each zero submatrix of the current layer. When the second a posteriori probability message is greater than or equal to 0, the element in the decoded output vector corresponding to the second a posteriori probability message is 0; when the second a posteriori probability message is less than 0, the element in the decoded output vector corresponding to the second a posteriori probability message is 1.

[0088] After obtaining the decoding result of the current layer in the current iteration, decoding can be stopped if the decoding result is 0, or if the current iteration number is equal to the iteration number threshold and the current layer is the last layer of the check matrix.

[0089] Referring to Figure 19, the following section further describes the hard-decision decoding process, taking the posterior probability messages corresponding to the updated non-zero submatrices of the m-th layer as an example. Specifically: when the posterior probability message corresponding to the updated non-zero submatrices of the m-th layer is greater than or equal to 0, the elements in the decoding output vector corresponding to that posterior probability message are 0; when the posterior probability message corresponding to the updated non-zero submatrices of the m-th layer is less than 0, the elements in the decoding output vector corresponding to that posterior probability message are 1. The decoding output vector is then multiplied by the transpose of the parity check matrix to obtain the decoding result for the m-th layer in the current iteration. If the decoding result is 0, then decoding stops and the decoded output vector is used as the decoded output. If the decoding result is not 0 and the m-th layer is not the last layer of the parity check matrix, then the next layer (m+1) is decoded. If the decoding result is not 0, the m-th layer is the last layer of the parity check matrix, and the current iteration count has not yet reached the set iteration count threshold, then the next iteration is performed. If the decoding result is not 0, the m-th layer is the last layer of the parity check matrix, and the current iteration count has reached the set iteration count threshold, then decoding stops.

[0090] Based on the above decoder, this embodiment of the invention also provides a memory controller, including: a processor configured to: receive information of a first reading order; and a decoder as described in any of the above embodiments, wherein the message update circuit 502 of the decoder is configured to: sequentially read the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory of the decoder according to the first reading order provided in the information of the first reading order.

[0091] The memory controller here can be the memory controller 104 shown in Figures 1, 2, 3, and 6. The processor here can be understood as the control unit 1043 shown in Figure 6. Other details about the memory controller have been described in detail above, and will not be repeated here for the sake of brevity.

[0092] Based on the above decoder, embodiments of the present invention also provide a memory system, including: a memory device configured to: output read data; and a decoder as described in any of the above embodiments, configured to: decode codewords to be decoded in the read data.

[0093] In some embodiments, the memory system further includes: an encoder configured to: receive write data and encode the write data; the memory device is further configured to: receive the encoded write data.

[0094] The structure and composition of the memory system described here can be found in the detailed description of Figures 1 to 6, and will not be repeated here for the sake of brevity. The memory device here can be the memory device 103 shown in Figures 1 to 6.

[0095] Based on the above decoder, this embodiment of the invention also provides a decoding method, as shown in FIG20. The decoding method includes: step S1001: sequentially reading the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory according to a first reading order; the first reading order is determined according to the position of each non-zero submatrix of the current layer; step S1002: obtaining updated posterior probability messages corresponding to each non-zero submatrix of the current layer based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration; and step S1003: sequentially writing the updated posterior probability messages corresponding to each non-zero submatrix of the current layer into the first memory according to a first writing order; the first writing order is determined according to the first reading order.

[0096] In this embodiment of the invention, during layered iterative decoding, the posterior probability messages corresponding to each non-zero submatrix of the current layer are sequentially read from the first memory according to a first reading order, and the updated posterior probability messages corresponding to each non-zero submatrix of the current layer are sequentially written to the first memory according to a first writing order, wherein the first writing order is determined based on the first reading order. By optimizing the reading and writing order of posterior probability messages within a layer, this embodiment of the invention can avoid conflicts between reading and writing posterior probability messages between layers, thereby effectively reducing idle time and improving decoding efficiency.

[0097] In some embodiments, the first reading order is determined based on the positional relationship between each non-zero submatrix of the current layer and the non-zero submatrix of the previous layer and the two layers before the current layer.

[0098] In some embodiments, the first write order is determined based on the first read order and the positional relationship between each non-zero submatrix of the current layer and the non-zero submatrix of the next layer.

[0099] In some embodiments, based on the positional relationship between the non-zero submatrices of each layer and the non-zero submatrices of the previous and second-to-last layers, the non-zero submatrices of each layer are divided into a first category, a second category, and a third category; wherein, in the column containing the non-zero submatrices of the first category of the current layer, the previous layer and the second-to-last layer of the current layer are both zero submatrices; in the column containing the non-zero submatrices of the second category of the current layer, the previous layer of the current layer is a zero submatrice, and the second-to-last layer of the current layer is a non-zero submatrice; in the column containing the non-zero submatrices of the third category of the current layer, the previous layer of the current layer is a non-zero submatrice; the posterior probability messages corresponding to each non-zero submatrice of the current layer are sequentially read from the first memory according to a first reading order, including: sequentially reading the posterior probability messages corresponding to the non-zero submatrices of the first category, the non-zero submatrices of the second category, and the non-zero submatrices of the third category of the current layer from the first memory according to the first reading order.

[0100] In some embodiments, reading the posterior probability message corresponding to the non-zero submatrix belonging to the second category in the non-zero submatrix of the current layer from the first memory includes: sequentially reading the posterior probability message corresponding to the first part of the non-zero submatrix, the posterior probability message corresponding to the second part of the non-zero submatrix, and the posterior probability message corresponding to the third part of the non-zero submatrix from the first memory; wherein, in the column where the first part of the non-zero submatrix is ​​located, the non-zero submatrix of the first two layers of the current layer belongs to the first category; in the column where the second part of the non-zero submatrix is ​​located, the non-zero submatrix of the first two layers of the current layer belongs to the second category; and in the column where the third part of the non-zero submatrix is ​​located, the non-zero submatrix of the first two layers of the current layer belongs to the third category. In some embodiments, reading the posterior probability message corresponding to the non-zero submatrix belonging to the third category in the non-zero submatrix of the current layer from the first memory includes: sequentially reading the posterior probability message corresponding to the fourth part of the non-zero submatrix, the posterior probability message corresponding to the fifth part of the non-zero submatrix, and the posterior probability message corresponding to the sixth part of the non-zero submatrix from the first memory; wherein, in the column where the fourth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the first category; in the column where the fifth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the second category; and in the column where the sixth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the third category.

[0101] In some embodiments, the posterior probability messages corresponding to each non-zero submatrix of the current layer are sequentially written to the first memory in a first writing order, including: sequentially writing the posterior probability messages corresponding to the non-zero submatrix of the current layer whose column is a non-zero submatrix in the next layer of the current layer, and the posterior probability messages corresponding to the non-zero submatrix of the current layer whose column is a zero submatrix in the next layer of the current layer, to the first memory.

[0102] In some embodiments, based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration, the updated posterior probability messages corresponding to each non-zero submatrix of the current layer are obtained, including: based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the verification node messages corresponding to each non-zero submatrix of the current layer in the previous iteration, the updated posterior probability messages corresponding to each non-zero submatrix of the current layer are obtained.

[0103] In some embodiments, as shown in FIG21, based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the verification node messages corresponding to each non-zero submatrix of the current layer in the previous iteration, the updated posterior probability messages corresponding to each non-zero submatrix of the current layer are obtained, including: step S2001: based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the verification node messages corresponding to each non-zero submatrix of the current layer in the previous iteration, the variable node messages corresponding to each non-zero submatrix of the current layer are obtained; step S2002: based on the variable node messages corresponding to each non-zero submatrix of the current layer and the first algorithm, the verification node messages corresponding to each non-zero submatrix of the current layer are obtained; and step S2003: based on the variable node messages corresponding to each non-zero submatrix of the current layer and the verification node messages corresponding to each non-zero submatrix of the current layer, the updated posterior probability messages corresponding to each non-zero submatrix of the current layer are obtained.

[0104] In some embodiments, as shown in FIG22, the variable node messages corresponding to each non-zero submatrix of the current layer are obtained based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the verification node messages corresponding to each non-zero submatrix of the current layer in the previous iteration, including: step S3001: obtaining a read order table from the second memory; and reading the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory in the first read order according to the first read order in the read order table; step S3002: performing a first operation on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the verification node messages corresponding to each non-zero submatrix of the current layer in the previous iteration to obtain the variable node messages corresponding to each non-zero submatrix of the current layer.

[0105] In some embodiments, as shown in FIG23, based on the variable node messages corresponding to each non-zero submatrix of the current layer and the check node messages corresponding to each non-zero submatrix of the current layer, an updated posterior probability message corresponding to each non-zero submatrix of the current layer is obtained, including: Step S4001: Based on the first reading order and flag information, a second reading order is generated; in the second reading order, the variable node messages corresponding to the non-zero submatrix of the current layer whose column is a non-zero submatrix in the next layer of the current layer are read first, and the variable node messages corresponding to the non-zero submatrix of the current layer whose column is a zero submatrix in the next layer of the current layer are read first. The variable node messages corresponding to the non-zero submatrices of the previous layer are read in order of priority; Step S4002: Read the variable node messages corresponding to each non-zero submatric of the current layer stored in the third memory according to the second reading order; Step S4003: Obtain the updated posterior probability messages corresponding to each non-zero submatric of the current layer based on the check node messages and variable node messages corresponding to each non-zero submatric of the current layer; and Step S4004: Write the updated posterior probability messages corresponding to each non-zero submatric of the current layer into the first memory according to the first writing order; The first writing order is the same as the second reading order.

[0106] In some embodiments, as shown in FIG24, the method further includes: step S5001: generating a decoding output vector based on the posterior probability messages corresponding to each non-zero submatrix of the updated current layer; step S5002: obtaining the decoding result of the current layer after decoding in the current iteration based on the decoding output vector and the parity check matrix; and step S5003: determining whether to stop decoding based on the decoding result, whether the current layer is the last layer of the parity check matrix, and whether the number of iterations exceeds the iteration number threshold.

[0107] The decoding methods mentioned in the above embodiments have been described in detail in the foregoing embodiments concerning decoders, and will not be repeated here for the sake of brevity.

[0108] Based on the above decoding method, this embodiment of the invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the decoding method of any of the above embodiments.

[0109] Here, implementing all or part of the decoding methods in the above embodiments can be accomplished by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium. When executed, the program can include the processes of the embodiments of the above methods. The storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; the storage medium can also include combinations of the above types of memory.

[0110] The features disclosed in the several device embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new device embodiments.

[0111] The methods disclosed in the several method embodiments provided by this invention can be arbitrarily combined without conflict to obtain new method embodiments.

[0112] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

[0113] 100: System 101: Host 102: Memory System 103: Memory Device 104: Memory controller 1040: Busbar 1041: Host Interface 1042: Memory Interface 1043: Control Department 1044: Debugging Module 1045: Encoder 1046: Decoder 1047: Cache memory 201: Memory Card 202: Memory Card Connector 203: SSD 204: SSD connector 300: Memory device 301: Storage Array 302: Peripheral Circuits 303: Storage Block 304: String of memory cells 305: Storage Unit 306: Top Select Transistor 307: Bottom selection transistor 308: Top Selection Line 309: Bottom Selection Line 310: Common source pole line 311: Bitline 312: Character Line 401: Page Buffer / Sensor Amplifier 402: Column decoder / bitline driver 403: Line decoder / character line driver 404: Voltage Generator 405: Control Logic 406: Temporary Register Set 407: Flash Memory Interface 408: Data Bus 501: First Memory 502: Message Update Circuit 503: Variable Node Message Processing Circuit 504: Verification Node Message Processing Circuit 505: Posterior probability message processing circuit 506: First control circuit 507: Third Memory 508: Variable Node Message Update Circuit 509: Second Memory 510: Address Update Circuit 511: Second control circuit 512: Posterior probability update circuit 513: Third control circuit 514: Hard-determined circuit S1001, S1002, S1003, S2001, S2002, S2003, S3001, S3002, S4001, S4002, S4003, S4004, S5001, S5002, S5003: Steps

Claims

1. A decoder configured to perform hierarchical iterative decoding based on a parity-check matrix corresponding to a codeword to be decoded, the decoder comprising: A first memory and a message update circuit; wherein, the first memory is configured to store posterior probability messages; the message update circuit is configured to: sequentially read the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory according to a first reading order; the first reading order is determined based on the position of each non-zero submatrix of the current layer; obtain updated posterior probability messages corresponding to each non-zero submatrix of the current layer based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration; and sequentially write the updated posterior probability messages corresponding to each non-zero submatrix of the current layer into the first memory according to a first writing order; the first writing order is determined based on the first reading order; the first reading order is determined based on the positional relationship between each non-zero submatrix of the current layer and the non-zero submatrix of the previous layer and the two layers before the current layer.

2. The decoder according to claim 1, wherein, The first write order is determined based on the first read order and the positional relationship between each non-zero submatrix of the current layer and the non-zero submatrix of the next layer.

3. The decoder according to claim 2, wherein, Based on the positional relationship between the non-zero submatrices of each layer and the non-zero submatrices of the previous and second-to-last layers, the non-zero submatrices of each layer are divided into three categories: a first category, a second category, and a third category. In the column containing the non-zero submatrices of the first category in the current layer, the previous and second-to-last layers are all zero submatrices. In the column containing the non-zero submatrices of the second category in the current layer, the previous layer is a zero submatrice, and the second-to-last layer is a non-zero submatrice. In the column containing the non-zero submatrices of the third category in the current layer, the previous layer is a non-zero submatrice. The message update circuit is configured to sequentially read from the first memory the posterior probability messages corresponding to the non-zero submatrices of the first category, the non-zero submatrices of the second category, and the non-zero submatrices of the third category in the current layer.

4. The decoder according to claim 3, wherein, When reading the posterior probability message corresponding to the non-zero submatrix belonging to the second category in the current layer's non-zero submatrix, the message update circuit is configured to: sequentially read the posterior probability message corresponding to the first part of the non-zero submatrix, the posterior probability message corresponding to the second part of the non-zero submatrix, and the posterior probability message corresponding to the third part of the non-zero submatrix from the first memory; wherein, in the column containing the first part of the non-zero submatrix, the non-zero submatrix of the first two layers of the current layer belongs to the first category; in the column containing the second part of the non-zero submatrix, the non-zero submatrix of the first two layers of the current layer belongs to the second category; and in the column containing the third part of the non-zero submatrix, the non-zero submatrix of the first two layers of the current layer belongs to the third category. When reading the posterior probability message corresponding to the non-zero submatrix belonging to the third category in the current layer's non-zero submatrix, the message update circuit is configured to: sequentially read the posterior probability messages corresponding to the fourth part of the non-zero submatrix, the fifth part of the non-zero submatrix, and the sixth part of the non-zero submatrix from the first memory; wherein, in the column where the fourth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the first category; in the column where the fifth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the second category; and in the column where the sixth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the third category.

5. The decoder according to claim 1, wherein, The message update circuit is configured to sequentially write the posterior probability message corresponding to the non-zero submatrix of the current layer whose column is a non-zero submatrix in the next layer of the current layer, and the posterior probability message corresponding to the non-zero submatrix of the current layer whose column is a zero submatrix in the next layer of the current layer into the first memory.

6. The decoder according to claim 1, wherein, The message update circuit is configured to: obtain updated posterior probability messages for each non-zero submatrix of the current layer based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the verification node messages corresponding to each non-zero submatrix of the current layer in the previous iteration.

7. The decoder according to claim 6, wherein, The message update circuit includes: a variable node message processing circuit, a check node message processing circuit, and a posterior probability message processing circuit; wherein, the variable node message processing circuit is configured to: sequentially read the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory according to a first reading order; and obtain the variable node messages corresponding to each non-zero submatrix of the current layer based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the check node messages corresponding to each non-zero submatrix of the current layer in the previous iteration; the check node message processing circuit is configured to: obtain the check node messages corresponding to each non-zero submatrix of the current layer based on the variable node messages corresponding to each non-zero submatrix of the current layer and a first algorithm; the posterior probability message processing circuit is configured to: obtain the updated posterior probability messages corresponding to each non-zero submatrix of the current layer based on the variable node messages corresponding to each non-zero submatrix of the current layer and the check node messages corresponding to each non-zero submatrix of the current layer; and sequentially write the updated posterior probability messages corresponding to each non-zero submatrix of the current layer into the first memory according to the first writing order.

8. The decoder according to claim 7, wherein, The first algorithm includes a sum-product decoding algorithm and a minimum sum algorithm.

9. The decoder according to claim 7, wherein, It also includes a second memory; the variable node message processing circuit includes: a first control circuit, a third memory, and a variable node message update circuit; wherein, the first control circuit is configured to: obtain a read order table from the second memory; and, according to a first read order in the read order table, sequentially read the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory; the variable node message update circuit is configured to: perform a first operation on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the check node messages corresponding to each non-zero submatrix of the current layer in the previous iteration to obtain the variable node messages corresponding to each non-zero submatrix of the current layer; the third memory is configured to: store the variable node messages corresponding to each non-zero submatrix of the current layer.

10. The decoder according to claim 9, wherein, The second memory also stores flag information; the flag information is used to indicate whether the column containing each non-zero submatrix in the current layer is a non-zero submatrix in the next layer of the current layer; The posterior probability message processing circuit includes: an address update circuit, a second control circuit, a posterior probability update circuit, and a third control circuit; wherein, the address update circuit is configured to: generate a second reading order based on the first reading order and the flag bit information; in the second reading order, the variable node messages corresponding to the non-zero submatrices of the current layer whose columns are non-zero submatrices in the next layer are read first, and the variable node messages corresponding to the non-zero submatrices of the current layer whose columns are zero submatrices in the next layer are read last; the second control circuit is configured to: read the variable node messages corresponding to each non-zero submatric of the current layer stored in the third memory based on the second reading order; the posterior probability update circuit is configured to: obtain updated posterior probability messages corresponding to each non-zero submatric of the current layer based on the check node messages corresponding to each non-zero submatric of the current layer and the variable node messages corresponding to each non-zero submatric of the current layer; The third control circuit is configured to write the posterior probability messages corresponding to each non-zero submatrix of the updated current layer into the first memory based on the first write order; the first write order is the same as the second read order.

11. The decoder according to claim 1, wherein, It also includes a hard decision circuit; the hard decision circuit is configured to: generate a decoded output vector based on the posterior probability messages corresponding to each non-zero submatrix of the current layer; obtain the decoding result of the current layer in the current iteration based on the decoded output vector and the parity check matrix; and determine whether to stop decoding based on the decoding result, whether the current layer is the last layer of the parity check matrix, and whether the number of iterations exceeds the number of iterations threshold.

12. The decoder according to claim 11, wherein, The hard decision circuit is configured to: determine that the element in the decoded output vector corresponding to the first posterior probability message is 0 based on the first posterior probability message in the posterior probability messages corresponding to each non-zero submatrix of the current layer being greater than or equal to 0; determine that the element in the decoded output vector corresponding to the first posterior probability message is 1 based on the first posterior probability message in the posterior probability messages corresponding to each non-zero submatrix of the current layer being less than 0; perform a second operation on the decoded output vector and the transpose of the parity check matrix to obtain the decoding result of the current layer in the current iteration; and stop decoding based on the decoding result being 0, or based on the current iteration number being equal to the iteration number threshold and the current layer being the last layer of the parity check matrix.

13. A memory controller, comprising: The processor is configured to receive information in the first read order; And a decoder as described in any one of claims 1 to 12, wherein the message update circuit of the decoder is configured to: sequentially read the posterior probability messages corresponding to each non-zero submatrix of the current layer from the first memory of the decoder according to the first read order provided in the information of the first read order.

14. A memory system, comprising: The memory device is configured to output read data; And a decoder as described in any one of claims 1 to 12, configured to decode the codewords to be decoded in the read data.

15. The memory system according to claim 14, further comprising: The encoder is configured to receive written data and encode the written data; The memory device is also configured to receive encoded write data.

16. A decoding method, comprising: The posterior probability messages corresponding to each non-zero submatrix of the current layer are read sequentially from the first memory according to the first reading order. The first reading order is determined based on the position of each non-zero submatrix in the current layer; based on the posterior probability messages corresponding to each non-zero submatrix in the current layer in the current iteration, the updated posterior probability messages corresponding to each non-zero submatrix in the current layer are obtained; and the updated posterior probability messages corresponding to each non-zero submatrix in the current layer are sequentially written to the first memory according to the first writing order; the first writing order is determined based on the first reading order; the first reading order is determined based on the positional relationship between each non-zero submatrix in the current layer and the non-zero submatrix in the previous layer and the two layers before the current layer.

17. The decoding method according to claim 16, wherein, The first write order is determined based on the first read order and the positional relationship between each non-zero submatrix of the current layer and the non-zero submatrix of the next layer.

18. The decoding method according to claim 17, wherein, Based on the positional relationship between the non-zero submatrices of each layer and the non-zero submatrices of the previous and second layers, the non-zero submatrices of each layer are divided into three categories: a first category, a second category, and a third category. In the column containing the non-zero submatrices of the first category in the current layer, the previous and second layers are all zero submatrices. In the column containing the non-zero submatrices of the second category in the current layer, the previous layer is a zero submatrice, and the second layer is a non-zero submatrice. In the column containing the non-zero submatrices of the third category in the current layer, the previous layer is a non-zero submatrice. The step of sequentially reading the posterior probability messages corresponding to each non-zero submatric of the current layer from the first memory according to the first reading order includes: sequentially reading the posterior probability messages corresponding to the non-zero submatrices of the first category, the non-zero submatrices of the second category, and the non-zero submatrices of the third category in the current layer from the first memory according to the first reading order.

19. The decoding method according to claim 18, wherein, Reading the posterior probability messages corresponding to the non-zero sub-matrices belonging to the second category in the current layer from the first memory includes: sequentially reading the posterior probability messages corresponding to the first part of the non-zero sub-matrices, the second part of the non-zero sub-matrices, and the third part of the non-zero sub-matrices from the first memory; wherein, in the column containing the first part of the non-zero sub-matrices, the non-zero sub-matrices of the two layers preceding the current layer belong to the first category; in the column containing the second part of the non-zero sub-matrices, the non-zero sub-matrices of the two layers preceding the current layer belong to the second category; and in the column containing the third part of the non-zero sub-matrices, the non-zero sub-matrices of the two layers preceding the current layer belong to the third category. Reading the posterior probability message corresponding to the non-zero submatrix belonging to the third category in the current layer from the first memory includes: sequentially reading the posterior probability message corresponding to the fourth part of the non-zero submatrix, the posterior probability message corresponding to the fifth part of the non-zero submatrix, and the posterior probability message corresponding to the sixth part of the non-zero submatrix from the first memory; wherein, in the column where the fourth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the first category; in the column where the fifth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the second category; and in the column where the sixth part of the non-zero submatrix is ​​located, the non-zero submatrix of the previous layer of the current layer belongs to the third category.

20. The decoding method according to claim 16, wherein, The step of sequentially writing the posterior probability messages corresponding to each non-zero submatrix of the current layer according to the first writing order includes: sequentially writing the posterior probability messages corresponding to the non-zero submatrix of the current layer whose column is a non-zero submatrix in the next layer of the current layer, and the posterior probability messages corresponding to the non-zero submatrix of the current layer whose column is a zero submatrix in the next layer of the current layer, into the first memory.

21. The decoding method according to claim 16, wherein, The step of obtaining updated posterior probability messages for each non-zero submatrix of the current layer based on the posterior probability messages for each non-zero submatrix of the current layer in the current iteration includes: obtaining updated posterior probability messages for each non-zero submatrix of the current layer based on the posterior probability messages for each non-zero submatrix of the current layer in the current iteration and the verification node messages for each non-zero submatrix of the current layer in the previous iteration.

22. The decoding method according to claim 21, wherein, The process of obtaining updated posterior probability messages for each non-zero submatrix of the current layer based on the posterior probability messages for each non-zero submatrix of the current layer in the current iteration and the verification node messages for each non-zero submatrix of the current layer in the previous iteration includes: obtaining variable node messages for each non-zero submatrix of the current layer based on the posterior probability messages for each non-zero submatrix of the current layer in the current iteration and the verification node messages for each non-zero submatrix of the current layer in the previous iteration; obtaining verification node messages for each non-zero submatrix of the current layer based on the variable node messages for each non-zero submatrix of the current layer and the first algorithm; and obtaining updated posterior probability messages for each non-zero submatrix of the current layer based on the variable node messages for each non-zero submatrix of the current layer and the verification node messages for each non-zero submatrix of the current layer.

23. The decoding method according to claim 22, wherein, The step of obtaining variable node messages corresponding to each non-zero submatrix of the current layer based on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the check node messages corresponding to each non-zero submatrix of the current layer in the previous iteration includes: obtaining a read order list from a second memory; and reading the posterior probability messages corresponding to each non-zero submatrix of the current layer sequentially from the first memory according to the first read order in the read order list; performing a first operation on the posterior probability messages corresponding to each non-zero submatrix of the current layer in the current iteration and the check node messages corresponding to each non-zero submatrix of the current layer in the previous iteration to obtain variable node messages corresponding to each non-zero submatrix of the current layer; and storing the variable node messages corresponding to each non-zero submatrix of the current layer.

24. The decoding method according to claim 23, wherein, The step of obtaining updated posterior probability messages for each non-zero submatrix of the current layer based on the variable node messages and check node messages corresponding to each non-zero submatrix of the current layer includes: generating a second reading order based on the first reading order and flag information; in the second reading order, the variable node messages corresponding to the non-zero submatrix of the current layer whose column is a non-zero submatrix in the next layer are read first, and the variable node messages corresponding to the non-zero submatrix of the current layer whose column is a zero submatrix in the next layer are read last; reading the stored variable node messages corresponding to each non-zero submatrix of the current layer based on the second reading order; obtaining updated posterior probability messages corresponding to each non-zero submatrix of the current layer based on the check node messages and variable node messages corresponding to each non-zero submatrix of the current layer; and writing the updated posterior probability messages corresponding to each non-zero submatrix of the current layer into the first memory based on the first writing order; the first writing order is the same as the second reading order.

25. The decoding method according to claim 16 further includes: Based on the updated posterior probability messages corresponding to each non-zero submatrix of the current layer, a decoding output vector is generated; Based on the decoded output vector and the parity check matrix, the decoding result of the current layer in the current iteration is obtained; and based on the decoding result, whether the current layer is the last layer of the parity check matrix, and whether the number of iterations exceeds the iteration number threshold, it is determined whether to stop decoding.

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