Method of forming semiconductor device

Abstract

An exemplary flowable chemical vapor deposition method includes depositing a flowable dielectric material on a substrate, UV curing the flowable dielectric material, and annealing the UV-cured flowable dielectric material. The flowable dielectric material fills the space between a first gate structure and a second gate structure. The annealing temperature is less than about 500°C. The thickness of the flowable dielectric material deposited on top of the first and second gate structures is less than about 200 nm. The UV power, temperature, and deposition thickness can be selected based on the expected germanium stacking characteristics at the interface between the inner spacer and the source / drain.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to the flowable chemical vapor deposition technology used in high aspect ratio gap-filling applications. [Previous Technology]

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per unit wafer area) typically increases as the geometry (i.e., the smallest component that the manufacturing process can produce) shrinks. Shrinking processes generally facilitate increased production capacity and reduced associated costs. Shrinking also increases the complexity of handling and manufacturing integrated circuits. To achieve these advancements, similar developments in integrated circuit materials and manufacturing are required. [Summary of the Invention]

[0003] An exemplary method for forming a semiconductor device includes depositing a flowable dielectric material on a substrate. The flowable dielectric material fills the space between a first gate structure and a second gate structure. The method further includes ultraviolet curing of the flowable dielectric material and annealing of the ultraviolet-cured flowable dielectric material. The ultraviolet power of the ultraviolet curing is greater than about 80%, and the annealing temperature is less than about 500°C.

[0004] An exemplary method for forming a semiconductor device includes: performing a flowable chemical vapor deposition process to form a first interlayer dielectric layer on a substrate; and performing a chemical vapor deposition process to form a second interlayer dielectric layer on the first interlayer dielectric layer. In some embodiments, the first interlayer dielectric layer fills a plurality of gaps between a plurality of gate structures, the ultraviolet power of the flowable chemical vapor deposition is about 80% to about 100%, and the temperature of the flowable chemical vapor deposition process is about 300°C to about 500°C.

[0005] Another exemplary method for forming a semiconductor device includes: analyzing germanium stacking profile characteristics corresponding to multiple inner spacers of a group of multiple devices and multiple interface regions of multiple source / drain structures in an interlayer dielectric layer having multiple device layers. Each interlayer dielectric layer of the device layers has a corresponding set of flowable chemical vapor deposition process parameters. The method further includes selecting multiple flowable chemical vapor deposition process parameters based on the analyzed germanium stacking profile characteristics for use in the interlayer dielectric layers of individual device layers formed by the flowable chemical vapor deposition process.

Implementation Method

[0007] Embodiments of the present invention provide a flowable chemical vapor deposition technique for high aspect ratio gap-filling applications, such as a flowable chemical vapor deposition technique for forming a high-quality interlayer dielectric layer in the high aspect ratio gap between the gates of a multi-gate transistor (e.g., a fin field-effect transistor, a fully wound gate transistor, such as a nanowire transistor or a nanosheet transistor, a forked transistor, or the like).

[0008] The following detailed description is illustrated in conjunction with the accompanying drawings to facilitate understanding of various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0009] The following detailed description is illustrated in conjunction with the accompanying drawings to facilitate understanding of various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity. Different embodiments or examples provided below may implement different structures of embodiments of the invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the invention. For example, a description of a first component forming on a second component includes direct contact between the two, or that the two are separated by other additional components rather than in direct contact. Furthermore, spatial relative terms such as "below," "under," "lower side," "above," "upper side," or similar terms may be used to simplify the description of the relative relationship between one element and another element in the illustrations. Spatial relative terms may extend to elements used in other directions, rather than being limited to the illustrated direction. Various embodiments of the invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] Furthermore, when a numerical value or range is described using terms such as "about," "approximately," or similar expressions, those skilled in the art should understand that it includes a reasonable range that takes into account inherent variations in manufacturing. For example, based on known manufacturing tolerances for structures related to that value, the value or range covers a reasonable range of the value, such as within + / -10% of the value. For instance, a material layer with a thickness of "about 5 nm" can cover a size range of 4.5 nm to 5.5 nm, while those skilled in the art know that the manufacturing tolerances associated with deposited material layers are + / -10%. Furthermore, taking into account inherent variations in any manufacturing process, when a device structure is described as having "substantially" characteristics and / or properties, this term refers to characteristics within the tolerances of the manufacturing process. For example, "substantially vertical" or "substantially horizontal" refers to a structure that is approximately vertical and horizontal within a given tolerance of the manufacturing process for manufacturing such a structure, but not a mathematically or completely vertical or horizontal structure.

[0011] Figure 1 is a flowchart of part or all of a method 10 for forming a dielectric structure on a device according to various embodiments of the present invention. The dielectric structure may include more than one interlayer dielectric layer. Step 20 of method 10 forms a first interlayer dielectric layer by flowable chemical vapor deposition. The flowable chemical vapor deposition in step 22 includes depositing a flowable dielectric material on a substrate, step 24 curing the flowable dielectric material with ultraviolet light, and step 26 annealing the ultraviolet-cured flowable dielectric material. The flowable dielectric material may fill gaps with high aspect ratios, such as the gap between a first gate structure and a second gate structure. Parameters of the flowable chemical vapor deposition are set to optimize the quality of the first interlayer dielectric layer and simultaneously optimize wafer acceptance testing performance, as described herein. For example, step 22 may adjust the deposition of the flowable dielectric material to provide a thin layer of flowable dielectric material on top of the first gate structure and the second gate structure (e.g., the height of the flowable dielectric material on top of the first gate structure and the second gate structure is less than about 200 nm), the UV power / energy of the UV curing step exposing the flowable dielectric material to UV light is greater than 80%, and the annealing process is a low-temperature annealing process (e.g., an annealing process below about 500°C). Step 30 may perform a planarization process on the first interlayer dielectric layer. The planarization process may be a chemical mechanical polishing process. The planarization process may remove a portion of the first interlayer dielectric layer on top of the first gate structure and the second gate structure. In some embodiments, a first contact etch stop layer may be formed before forming the first interlayer dielectric layer. In these embodiments, the first contact etch stop layer partially fills the gaps, the first interlayer dielectric layer fills the remaining gaps, and the composition of the first contact etch stop layer and the first interlayer dielectric layer are different to achieve etch selectivity between the two.

[0012] Step 40 of method 10 forms a second interlayer dielectric layer, which may be formed by chemical vapor deposition. Since the second interlayer dielectric layer may not be formed in the gaps between device structures and / or in gaps with small aspect ratios, the second interlayer dielectric layer may be formed by a deposition process different from that of the first interlayer dielectric layer, such as a different type of chemical vapor deposition. For example, the second interlayer dielectric layer may be formed by plasma-assisted chemical vapor deposition instead of flowable chemical vapor deposition. In this example, the second interlayer dielectric layer may be a plasma-assisted oxide layer. In some embodiments, the dummy gates of the first gate structure and the second gate structure may be replaced to form a gate stack before forming the second interlayer dielectric layer. In some embodiments, a second contact etch stop layer may be formed before forming the second interlayer dielectric layer. In these embodiments, the composition of the second contact etch stop layer is different from that of the second interlayer dielectric layer to achieve etch selectivity between them. Step 50 may perform a planarization process on the second interlayer dielectric layer. The planarization process can be a chemical mechanical polishing process. In some embodiments, the dielectric structure can be formed on the source / drain, and the source / drain contact structure can be formed in the second interlayer dielectric layer, in the first interlayer dielectric layer, and on the source / drain. Additional steps can be provided before, during, and after method 10, and some of the steps can be substituted, replaced, or eliminated by additional implementation forces of method 10. An apparatus can be fabricated according to the description of method 10 to include a dielectric structure (such as an interlayer dielectric layer). As can be understood from the description herein, dielectric structures such as interlayer dielectric layers fabricated according to the methods described in the embodiments of the present invention are superior to dielectric structures fabricated by other methods. However, it should be understood that different implementation forces can have different advantages, and no embodiment need to have a particular advantage.

[0013] FIG2 is a partial or complete top view of the device 100 in various embodiments of the present invention, and the device 100 may be processed to form a dielectric structure thereon (e.g., formed by method 10 of FIG1). FIG3A to 10A are partial or complete cross-sectional views of the device 100 along section line AA of FIG2 in various fabrication sections (as shown in the fabrication sections related to method 10 of FIG1) in various embodiments of the present invention. FIG3B to 10B are partial or complete cross-sectional views of the device 100 along section line BB of FIG2 in various fabrication sections (as shown in the fabrication sections related to method 10 of FIG1) in various embodiments of the present invention. FIG8C is a partial or complete cross-sectional view of the device 100 along section line CC of FIG2 in the fabrication sections of FIG8A and 8B in various embodiments of the present invention. FIG11 and FIG12 are data and / or results related to dielectric structures fabricated by a flowable chemical vapor deposition process in various embodiments of the present invention, and the dielectric structure may be a dielectric structure fabricated on the device 100 and / or a dielectric structure fabricated by method 10 of FIG1. Figures 2, 3A to 10A, 3B to 10B, 8C, 11, and 12 are described herein for ease of explanation and understanding. Figures 2, 3A to 10A, 3B to 10B, 8C, 11, and 12 have been simplified for clarity and to facilitate understanding of the inventive concept of the embodiments of the present invention. Additional structures may be added to device 100, and other embodiments of device 100 may replace, adjust, or eliminate some of the following structures.

[0014] Device 100 may include at least one transistor, such as a fully wound gate transistor (i.e., the gate of a transistor at least partially surrounds a suspended channel, which is a nanowire, nanosheet, nanorod, or the like extending between the source and drain). Device 100 may be included in a microprocessor, memory, other integrated circuit devices, or combinations thereof. In some embodiments, device 100 is part of an integrated circuit chip, or a system-on-a-chip, or a portion thereof. Device 100 may include a variety of passive and / or active electronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors, n-type field-effect transistors, metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor transistors, bipolar junction transistors, laterally diffused metal-oxide-semiconductor transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0015] As shown in Figures 2, 3A, and 3B, a precursor for forming and / or receiving device 100 can be formed, and then processed as described herein. Device 100 may include a substrate 105, a mesa 105', a multilayer stack 110 (e.g., containing mesa 105P', a sacrificial layer 115, and a semiconductor layer 120), a substrate isolation structure 125, and a gate structure 128. Gate structures 128 may each include individual dummy gate stacks 130 and individual gate spacers 132. Device 100 may further include inner spacers 145 and source / drain structures 150. Source / drain structures 150 may each be multilayer structures, which may include a semiconductor layer 152, an insulating layer 154, a semiconductor layer 156, and a semiconductor layer 158. The active region 160 of device 100 extends along the x-direction (i.e., length along the x-direction, width along the y-direction, and height along the z-direction), and the orientation of the active region 160 may be substantially parallel to the orientation of another active region. The active region 160 may include a channel region C, a source region, and a drain region, and the source region and drain region may be considered together as a source / drain region S / D. In the described embodiment, the processing device 100 includes a fully wound gate transistor, and the active region 160 is an active region dominated by the fully wound gate. In these embodiments, the active region 160 may have a source / drain region formed by the source / drain structure 150 and a channel region formed by the semiconductor layer 120.

[0016] The substrate 105, mesa 105', and mesa 105P' include semiconductor elements (such as silicon and / or germanium), semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium arsenide phosphide, or combinations thereof), or combinations thereof. In some embodiments, the substrate 105 is a silicon substrate. In some embodiments, the substrate 105 is a semiconductor-on-insulator substrate such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. The substrate 105 (and mesa 105') may include various doped regions such as p-type doped regions (e.g., p-type wells), n-type doped regions (e.g., n-type wells), or combinations thereof. The n-type doped region includes n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof. p-type doped regions include p-type dopants such as boron, indium, gallium, other p-type dopants, or combinations thereof. In some embodiments, the doped region includes both p-type and n-type dopants. The doped region may provide p-type well structures, n-type well structures, dual-well structures, bump structures, other suitable structures, or combinations thereof. In some embodiments, substrate 105 and / or mesa 105' and the semiconductor layer thereon may include n-type wells and / or p-type wells. For example, substrate 105 and / or mesa 105' may include p-type wells in n-type transistor regions and n-type wells in p-type transistor regions.

[0017] The sacrificial layer 115 and the semiconductor layer 120 are vertically stacked (e.g., along the z-direction) from the top of the substrate 105 in an alternating and / or staggered manner. The composition of the sacrificial layer 115 differs from that of the semiconductor layer 120 to achieve etch selectivity. For example, the sacrificial layer 115 and the semiconductor layer 120 comprise different materials, atomic percentages, weight percentages, other properties, or combinations thereof to achieve etch selectivity. In some embodiments, the sacrificial layer 115 comprises silicon germanium, the semiconductor layer 120 comprises silicon, and the etch rate of the semiconductor layer 120 with a given etchant differs from the etch rate of the sacrificial layer 115 with a given etchant. In some embodiments, the sacrificial layer 115 and the semiconductor layer 120 comprise the same material with different atomic percentages. For example, the sacrificial layer 115 and the semiconductor layer 120 may comprise silicon germanium with different germanium atomic percentages. In some embodiments, the sacrificial layer 115 is a dielectric layer (e.g., an oxide layer) and the semiconductor layer 120 is a silicon layer to provide etch selectivity. The sacrificial layer 115 and the semiconductor layer 120 may comprise any combination of materials that provides the desired etch selectivity, the desired oxidation rate difference, the desired performance characteristics, or a combination thereof (such as materials that maximize current), and the combination of materials includes any of the materials described herein.

[0018] Semiconductor layer 120 or a portion thereof may form transistor channels of device 100. In FIG. 3A, multilayer stack 110 includes three sacrificial layers 115 and three semiconductor layers 120. Thus, multilayer stack 110 includes three pairs of semiconductor layers on substrate 105, and each pair of semiconductor layers has an individual sacrificial layer 115 and an individual semiconductor layer 120. After the fabrication process of multilayer stack 110, this arrangement results in the transistor having three channels. However, in some embodiments, multilayer stack 110 includes a different number of semiconductor layers 120, depending on the design requirements of device 100 and / or the number of channels required by the transistor. For example, multilayer stack 110 may include two to six pairs of semiconductor layers, and each pair of semiconductor layers may have an individual sacrificial layer 115 and an individual semiconductor layer 120.

[0019] The substrate isolation structure 125 may surround and be adjacent to the lower portion of the multilayer stack 110 (such as its mesa 105P'), and the active region 160 may be separated from other active regions and / or device regions by the substrate isolation structure 125. The substrate isolation structure 125 may electrically isolate the active region 160 (such as its mesa 105P' and / or source / drain structure 150) from other active regions and / or device regions. The substrate isolation structure 125 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including silicon, oxygen, nitrogen, carbon, other suitable isolation components, or combinations thereof), or combinations thereof. The substrate isolation structure 125 may have a multilayer structure. For example, the substrate isolation structure 125 may include a substrate dielectric layer (such as an oxide layer) on top of a dielectric pad (such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or combinations thereof). In another example, the substrate isolation structure 125 may include a substrate dielectric layer on a doped pad such as a borosilicate glass pad and / or a phospholipid glass pad. The dimensions and / or characteristics of the substrate isolation structure 125 may be configured to provide a shallow trench isolation structure, a deep trench isolation structure, a localized silicon oxide structure, other suitable isolation structures, or a combination thereof.

[0020] A gate structure 128 is formed on the channel region C (e.g., multilayer stack 110) of the active region 160 and between the source / drain regions S / D (e.g., source / drain structure 150) of the active region 160. As described above, the gate structure 128 may include individual dummy gate stacks 130 and individual gate spacers 132. The extension direction of the gate structure 128 (which may also be considered as a gate line) is different from (e.g., perpendicular to) the length direction of the active region 160, such that the gate structure 128 is located on the channel region of the active region 160 and the substrate isolation structure 125. For example, the gate structure 128 extends along the y-direction and has a length along the y-direction, a width along the x-direction, and a height along the z-direction. As shown, the extension directions of the gate structures 128 may be substantially parallel to each other, and there is a space S between the gate structures 128. In Figure 3A (e.g., XZ plane), gate structure 128 is located on top of individual channel regions of active region 160 (e.g., multilayer stack 110), between individual source / drain structures (e.g., source / drain structure 150) of active region 160, and gate structure 128 has a height H1. In Figure 3B (e.g., XZ plane), gate structure 128 is located on top of substrate isolation structure 125, and gate structure 128 has a height H2. Height H2 is greater than height H1. In another cross-sectional view (e.g., YZ plane), gate structure 128 may cover individual channel regions of active region 160.

[0021] In Figures 3A and 3B, gate structures 128 are spaced by a space S. Gate structures 128 have a height H1 on the active region (e.g., on the channel region of active region 160) and a height H2 on the isolation region (e.g., on the substrate isolation structure 125). The aspect ratio of the gaps between gate patterns (e.g., gate structures 128) in the active region 160 is the ratio of height H1 to space S, and the aspect ratio of the gaps between gate patterns in the isolation region is the ratio of height H2 to space S. Height H2 is greater than height H1, such that the aspect ratio of the gaps between gate structures 128 in the isolation region is greater than the aspect ratio of the gaps between gate structures 128 in the active region 160. In some embodiments, the aspect ratio of the gaps between gate structures 128 in the isolation region is greater than about 10 (e.g., the ratio of height H2 to space S is at least 10:1). In some embodiments, the aspect ratio of the gaps between gate structures 128 in the active region is greater than about 2.

[0022] The dummy gate stack 130 may include a dummy gate dielectric layer and a dummy gate. The dummy gate dielectric layer includes a dielectric material such as silicon oxide and / or other suitable dielectric materials. The dummy gate may include a suitable dummy gate material such as polysilicon. The dummy gate stack 130 may further include a hard mask configured to protect the dummy gate dielectric layer and / or the dummy gate during fabrication. For example, the hard mask may include materials resistant to etching processes (such as etching processes associated with forming source / drain recesses and / or etching processes associated with forming source / drain junction openings) to protect the dummy gate dielectric layer and / or the dummy gate layer from etching processes. In some embodiments, the hard mask has a multilayer structure. The hard mask includes any suitable hard mask material.

[0023] Gate spacer 132 is adjacent to and along the sidewall of dummy gate stack 130. Gate spacer 132 comprises a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable dielectric compositions, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, silicon carbonitride, silicon carbon oxynitride, or combinations thereof). In some embodiments, gate spacer 132 has a multilayer structure, such as two or more dielectric layers with different compositions. In some embodiments, gate spacer 132 comprises more than one set of spacers, such as sealing spacers, compensating spacers, sacrificial spacers, dummy spacers, primary spacers, or combinations thereof. In these embodiments, the multiple sets of spacers may have different compositions.

[0024] The inner spacer 145 is located below the gate structure 128 (such as below the gate spacer 132 of the gate structure 128) and along the sidewall of the sacrificial layer 115. The inner spacer 145 is located between the sacrificial layer 115 and the source / drain structure 150, between adjacent semiconductor layers 120, and between the bottommost semiconductor layer 120 and the mesa 105P'. The dielectric material included in the inner spacer 145 contains silicon, oxygen, carbon, nitrogen, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or the like. In some embodiments, the inner spacer 145 includes a dielectric material with a low dielectric constant. In some embodiments, a dopant (such as a p-type and / or n-type dopant) is introduced into the dielectric material, and the inner spacer 145 includes the doped dielectric material.

[0025] The source / drain structure 150 includes a semiconductor material, which may be doped with n-type dopants and / or p-type dopants, and may have the same or different compositions and / or materials. In some embodiments, the semiconductor material of the source / drain structure 150 is formed by an epitaxial process, and the composition of the source / drain structure 150 is an epitaxially grown / deposited semiconductor material. In these embodiments, the source / drain structure 150 may be considered as an epitaxial source / drain. In some embodiments where an n-type transistor is formed, the source / drain structure 150 may include silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof. In some embodiments where a p-type transistor is formed, the source / drain structure 150 may include silicon-germanium or germanium doped with boron, other p-type dopants, or combinations thereof. In some embodiments, doped regions such as heavily doped source / drain regions, lightly doped source / drain regions, other doped regions, or combinations thereof are located in the source / drain structure 150. In some embodiments, the doped region, such as a lightly doped source / drain region, may extend into the channel region. The source / drain region, source / drain, source / drain structure, epitaxial source / drain, epitaxial source / drain structure, or the like described herein may be regarded as the source of device 100, the drain of device 100, or the source and / or drain of multiple devices (including device 100).

[0026] The source / drain structure 150 may each include an individual semiconductor layer 152, an individual insulating layer 154, an individual semiconductor layer 156, and an individual semiconductor layer 158. The semiconductor layer 152 may be located on the mesa 105P' and / or the substrate 105. In the embodiment described, the semiconductor layer 152 comprises an undoped semiconductor material (i.e., substantially free of n-type and p-type dopants). For example, no doping is intentionally performed when forming the semiconductor layer 152 (e.g., during an epitaxial growth process). Therefore, the semiconductor layer 152 provides a high-resistivity path at the bottom of the source / drain structure 150, thereby hindering leakage current from flowing between the source / drain structures 150 via the mesa 105P' and / or the substrate 105. In some embodiments, the composition of the undoped semiconductor layer includes silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. For example, the semiconductor layer 152 may be an undoped silicon layer or an undoped silicon-germanium layer.

[0027] An insulating layer 154 is located on the semiconductor layer 152, and the insulating layer 154 may be located between the semiconductor layer 158 and the semiconductor layer 152. The insulating layer 154 includes an electrically insulating material such as a dielectric material, which may also prevent unwanted leakage current from flowing through the mesa 105P' and / or the substrate 105 between the source / drain structures 150 (such as its semiconductor layer 158). In some embodiments, the insulating layer 154 includes a silicon-containing dielectric material such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, silicon carbonitride, other silicon-containing dielectric materials (which may include silicon with nitrogen, carbon, oxygen, other suitable dielectric compositions, or combinations thereof), or combinations thereof. In some embodiments, the insulating layer 154 includes a metal-containing dielectric material such as a metal oxide material (such as aluminum oxide and / or hafnium oxide) and / or a metal nitride material. In some embodiments, the insulating layer 154 comprises a doped semiconductor material having a dopant of the opposite type to that of the semiconductor layer 158. For example, when the source / drain structure 150 is a portion of a p-type transistor having a p-type doped semiconductor layer, the insulating layer 154 may comprise an n-type doped semiconductor material such as phosphorus-doped silicon. In another example, when the source / drain structure 150 is a portion of an n-type transistor having an n-type doped semiconductor layer, the insulating layer 154 may comprise a p-type doped semiconductor material such as boron-doped silicon.

[0028] Semiconductor layers 156 and 158 are located on insulating layer 154 and coupled to semiconductor layer 120. Semiconductor layer 156 may be located between semiconductor layer 158 and semiconductor layer 120. In the embodiment described, semiconductor layer 156 and semiconductor layer 158 comprise semiconductor materials doped with n-type and / or p-type dopant (such as silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof). Semiconductor layer 156 and semiconductor layer 158 may have different compositions and / or different sizes / positions, and different compositions may be different semiconductor materials, different dopants, different atomic percentages of compositions, different dopant concentrations, or combinations thereof. For example, semiconductor layer 158 may be a heavily doped semiconductor layer, while semiconductor layer 156 may be a lightly doped semiconductor layer, wherein the dopant concentration of the heavily doped semiconductor layer is greater than the dopant concentration of the lightly doped semiconductor layer. In some embodiments, semiconductor layers 156 and 158 may comprise silicon doped with different concentrations of carbon, phosphorus, arsenic, antimony, other n-type dopants, or combinations thereof. In another embodiment, semiconductor layers 156 and 158 may comprise silicon-germanium doped with different concentrations of boron, gallium, other p-type dopants, or combinations thereof. In some embodiments, the materials and / or dopants comprised in semiconductor layers 156 and 158 may provide the required tensile and / or compressive stresses in the channel region.

[0029] Prior to forming the source / drain structure 150, the multilayer stack 110 (such as its mesa 105', sacrificial layer 115, and semiconductor layer 120) may extend substantially continuously along the x-direction, having a length along the x-direction, a width along the y-direction, and a height along the z-direction. The multilayer stack 110 may be regarded as a fin, fin structure, fin unit, active fin region, active region, or the like. In some embodiments, the mesa 105' is a patterned protrusion and / or extension of the substrate 105, and the mesa 105' may be regarded as a substrate extension, substrate fin portion, fin portion, etched substrate portion, or the like. When forming the source / drain structure 150, the sacrificial layer 115, semiconductor layer 120, and mesa 105' may be removed to form a source / drain recess in the source / drain region of the active region 160, and the source / drain structure 150 will be formed in the source / drain recess. After the source / drain recesses are formed (which may extend into the mesa 105'), portions of the multilayer stack 110 may remain in the channel region of the active region 160, and these portions may include the mesa 105P', the sacrificial layer 115, and the semiconductor layer 120, as shown.

[0030] As shown in Figures 4A and 4B, a contact etch stop layer 162 may be formed on the device 100, such as on the gate structure 128, the source / drain structure 150, the substrate isolation structure 125, and the substrate 105 (such as its mesa 105'). The contact etch stop layer 162 partially fills the gaps / spaces S between the gate structures 128. The composition of the contact etch stop layer 162 differs from the composition of the subsequently formed interlayer dielectric layer to achieve etch selectivity between the two. In some embodiments, the contact etch stop layer 162 comprises a silicon-containing dielectric material. For example, the contact etch stop layer 162 comprises silicon and nitrogen and / or carbon, such as silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbonoxide, other silicon-containing dielectric materials (which may include silicon and nitrogen, carbon, oxygen, other suitable dielectric compositions, or combinations thereof), or combinations thereof. In some embodiments, the contact etch stop layer 162 comprises a metal-containing dielectric material. For example, the contact etch stop layer 162 comprises a metal and oxygen, nitrogen, carbon, or any combination thereof, such as metal oxides (e.g., aluminum oxide) and / or metal nitrides (e.g., aluminum nitride). The metal may be aluminum, hafnium, titanium, copper, manganese, vanadium, other suitable metals, or combinations thereof. In some embodiments, the contact etch stop layer 162 has a multilayer structure. The contact etch stop layer 162 may be formed by chemical vapor deposition, atomic layer deposition, other suitable deposition processes, or combinations thereof.

[0031] As shown in Figures 4A to 6A and Figures 4B to 6B, an interlayer dielectric layer 164 is formed on the device 100, for example, on the contact etch stop layer 162. The interlayer dielectric layer 164 fills the remaining gaps / spaces S between the gate structures 128. The interlayer dielectric layer 164 comprises a silicon- and oxygen-containing dielectric material. For example, the interlayer dielectric layer 164 is a silicon oxide layer. In some embodiments, the silicon- and oxygen-containing dielectric material is a low dielectric constant dielectric material, which is generally considered to be a dielectric material with a dielectric constant lower than that of silicon oxide (about 3.9). For example, the interlayer dielectric layer 164 may be a porous silicon oxide layer with a dielectric constant less than about 2.5. In another example, the interlayer dielectric layer 164 may be a carbon-doped silicon oxide layer with a dielectric constant less than about 2.5. In some embodiments, the interlayer dielectric layer 164 is a doped silicon oxide layer such as a carbon-doped silicon oxide layer, a phosphorus-doped silicon oxide layer such as phosphosilicate glass, a boron-doped silicon oxide layer such as borosilicate glass, a boron and phosphorus-doped silicon oxide layer such as borophosphosilicate glass, a fluorine-doped silicon oxide layer such as fluorosilicate glass, other suitable doped silicon oxide layers, or combinations thereof. In some embodiments, the interlayer dielectric layer 164 is an oxide layer formed of tetraethoxysilane. In some embodiments, the interlayer dielectric layer 164 is a dielectric layer based on benzocyclobutene.

[0032] Stacked channels can increase device density and improve device performance. For example, providing transistors with stacked semiconductor layers 120 can reduce the area consumed by the transistors, allowing more transistors to be placed in a given area, and can also promote the drive current of the transistors. However, as the height of device structures (such as gates) increases to accommodate the stacked channel arrangement, and the space between device structures remains small or reduced to accommodate the higher device density of scaled-down integrated circuit technology nodes, the aspect ratio of the gaps between device structures faces gap-filling challenges. For example, voids / gaps are more likely to form in insulating materials such as interlayer dielectric layers 164 that fill high aspect ratio gaps (such as the high aspect ratio gaps between the gate structures 128 of device 100). In summary, as shown in Figures 4A to 6A and Figures 4B to 6B, to optimize the filling effect of the high aspect ratio gaps between the gate structures 128 (e.g., reducing and / or eliminating voids / gaps in the interlayer dielectric layer 164), the interlayer dielectric layer 164 can be formed by a flowable chemical vapor deposition process. In the embodiment described, the flowable chemical vapor deposition process includes depositing a flowable dielectric material 164' onto the device 100 (Figures 4A and 4B), which fills the high aspect ratio gaps / spaces S between the gate structures 128; performing ultraviolet curing 170 on the deposited flowable dielectric material 164' (Figures 5A and 5B); and performing an annealing process 175 on the ultraviolet-cured flowable dielectric material 164' (Figures 6A and 6B), thereby providing the interlayer dielectric layer 164.

[0033] In the described embodiment, the flowable dielectric material 164' is a flowable silicon-oxygen-containing dielectric material. As its name suggests, the flowable dielectric material can flow during deposition to fill gaps or spaces with high aspect ratios (e.g., gaps between gate structures 128), and has negligible voids / gaps or no voids / gaps. In some embodiments, various chemical agents such as nitrogen-hydrides are added to the silicon-containing deposition precursor to make the deposited silicon-oxygen-containing dielectric material flowable. For example, the flowable dielectric material 164' can be a flowable silicon, oxygen, and nitrogen dielectric material. Exemplary flowable dielectric precursors (specifically flowable silica precursors) include silicates, siloxanes, methyl silsesquioxanes, hydrosilsesquioxanes, perhydrosilazanes, perhydropolysilazanes, tetraethoxysilanes, silylamines such as trimethylsilylamine, other suitable precursors, or combinations thereof.

[0034] Next, UV curing 170 and annealing processes 175 are performed to physically densify and / or chemically transform the flowable dielectric material 164' into an interlayer dielectric layer 164 (such as a solid dielectric material). In the embodiments described, UV curing 170 and / or annealing processes 175 transform the flowable dielectric material 164' (e.g., a silicon, oxygen, and nitrogen-containing dielectric material) into an interlayer dielectric layer 164 (e.g., a silicon and oxygen-containing dielectric material such as a silicon oxide layer). In these embodiments, UV curing 170 and / or annealing processes 175 may promote the formation of silicon-silicon bonds and / or silicon-oxygen bonds, and reduce silicon-nitrogen bonds and / or silicon-hydrogen bonds. In some embodiments, UV curing 170 and / or annealing processes 175 may convert silicon-hydroxy bonds, silicon-hydrogen bonds, silicon-nitrogen bonds, or combinations thereof into silicon-oxygen bonds. In some embodiments, UV curing 170 and / or annealing processes 175 harden the flowable dielectric material 164', thereby providing an interlayer dielectric layer 164. In some embodiments, UV curing 170 and / or annealing processes 175 may remove unwanted elements (such as nitrogen) and / or bonds to densify the deposited flowable dielectric material 164'. In some embodiments, UV curing 170 and / or annealing processes 175 remove moisture and / or residues from the flowable dielectric material 164'.

[0035] The parameters of the flowable chemical vapor deposition process are set to optimize the quality of the interlayer dielectric layer 164 and the wafer acceptance test performance. For example, during the fabrication of device 100, native oxide may be formed between the inner spacer 145 and the sacrificial layer 115 and / or between the inner spacer 145 and the source / drain structure 150, and the sacrificial layer 115 may be a sacrificial semiconductor layer such as a sacrificial silicon-germanium layer (which will later be replaced by a gate stack). Embodiments of the present invention recognize that high annealing temperatures, such as annealing temperatures greater than 500°C, may unnecessarily push oxygen from the native oxide into the semiconductor layer 120 (such as a silicon layer, which will form the transistor channel layer of device 100) during the flowable chemical vapor deposition process. This oxygen diffusion unnecessarily increases the channel resistance and / or degrades the electrical performance (such as its DC performance) of the transistor of device 100. In some cases, transistors fail wafer acceptance testing due to channel resistance and / or electrical performance degradation, necessitating the discarding of wafers / wafers containing these transistors. Therefore, the annealing process 175 is performed at an annealing temperature lower than about 500°C (e.g., about 300°C to about 500°C) to eliminate and / or reduce oxygen diffusion, thereby minimizing the increase in channel resistance and / or electrical performance degradation caused by oxygen diffusion, and thus improving wafer acceptance testing performance. For example, the low annealing temperature performed in the annealing process 175 may reduce the oxygen diffusion length, thus reducing oxygen diffusion to the ends of semiconductor layer 120 (which can be considered as sheet-like end oxide propagation). In some embodiments, the annealing process 175 heats the wafer site and fixes the device 100 thereon to the annealing temperature. In some embodiments, the annealing process 175 heats the environment (such as the ambient environment) of the process chamber where the device 100 is located to the annealing temperature. In some embodiments, the annealing process 175 heats the flowable dielectric material 164' to an annealing temperature to facilitate hardening / densification of the flowable dielectric material 164'. The annealing process 175 may be performed via a wafer / substrate site (on which a substrate 105 may be fixed), an lamp source, a laser source, other heat sources, or a combination of the above heating devices 100.

[0036] When the source / drain structure 150 includes germanium, embodiments of the present invention further recognize that the amount of oxidation of the source / drain will further affect the advance of the sheet-like end oxide and the amount of germanium deposit at the interface between the source / drain structure 150 and the inner spacer 145. For example, oxygen in the inner spacer 145 can react with germanium in the source / drain structure 150 (such as a p-type doped silicon-germanium source / drain of a p-type transistor) to form germanium oxide, which may undesirably diffuse into the semiconductor layer 120 during subsequent thermal processes. The low annealing temperature implemented in the annealing process 175 can also reduce germanium deposits (i.e., the amount of germanium at the interface between the inner spacer and the source / drain), thereby reducing source / drain oxidation and thus reducing the advance of the sheet-like end oxide. For example, Figure 11 is an illustrative graph 200 showing the germanium depth profile obtained by experimental / simulated secondary ion mass spectrometry analysis at the interface region between the inner spacers and the source / drain after forming the interlayer dielectric layer using flowable chemical vapor deposition processes with different annealing temperatures in various embodiments of the present invention. The germanium depth profile shows the percentage of germanium atoms at the depth along the interface region between the inner spacers and the source / drain (e.g., from the depth / distance in the individual inner spacer INSP near the interface IF of the inner spacers and the source / drain to the depth in the individual source / drain S / D). In some embodiments, the depth represents the distance along the channel length direction from the interface between the individual inner spacers and the sacrificial layer, through the inner spacer to the interface between the individual inner spacers and the source / drain, and the distance along the channel length direction from the interface between the individual inner spacers and the source / drain to the source / drain. In Figure 200, germanium depth profile 202 corresponds to the interface region between the inner spacer and the source / drain after the interlayer dielectric layer is formed by a flowable chemical vapor deposition process without annealing. germanium depth profile 204 corresponds to the interface region between the inner spacer and the source / drain after the interlayer dielectric layer is formed by a flowable chemical vapor deposition process with high-temperature annealing (e.g., annealing temperature of about 500°C to about 700°C). germanium depth profile 206 corresponds to the interface region between the inner spacer and the source / drain after the interlayer dielectric layer is formed by a flowable chemical vapor deposition process with low-temperature annealing (e.g., annealing temperature of about 300°C to about 500°C). As clearly shown in Figure 200, the percentage of germanium atoms is highest at the interface between the inner spacer and the source / drain after the high-temperature annealed interlayer dielectric layer, while it is lowest at the interface after the low-temperature annealed interlayer dielectric layer (such as the annealing process implemented in the disclosed flowable chemical vapor deposition process). The disclosed flowable chemical vapor deposition process can therefore reduce germanium buildup, thereby reducing source / drain oxidation (such as the amount of germanium oxide at the interface between the inner spacer and the source / drain). Reducing source / drain oxidation can further reduce unintended lamellar end oxide propagation, which can degrade transistor performance. Different embodiments may have different advantages, and no single embodiment needs to have a specific advantage.

[0037] Embodiments of the present invention further recognize that annealing processes with predetermined lower thermal budgets may undesirably degrade the quality of the interlayer dielectric layer film, since the quality of the interlayer dielectric layer film is positively correlated with the annealing temperature (e.g., lowering the annealing temperature may reduce the quality of the interlayer dielectric layer film). To compensate for the reduced interlayer dielectric layer quality caused by lower-temperature annealing processes, a disclosed flowable chemical vapor deposition process deposits a thinner layer of flowable dielectric material 164', and exposes the flowable dielectric material 164' to higher UV power (e.g., UV power / density of about 80% to about 100%) during UV curing 170. For example, the flowable dielectric material 164' has a thickness T1 on the source / drain structure 150 (FIG. 4A), a thickness T2 on the substrate isolation structure 125 (FIG. 4B), and a thickness T3 on the top of the gate structure 128 (FIG. 4A). Thickness T3 is approximately equal to the height H3 of the flowable dielectric material 164' on top of the gate structure 128, i.e., thickness T3 = height H3 - thickness of the contact etch stop layer 162, or thickness T3 ≈ height H3. In this embodiment, thickness T3 is less than about 200 nm (e.g., about 100 nm to about 200 nm) to improve the efficiency of UV curing 170. For example, reducing thickness T3 can reduce thickness T1 (e.g., the thickness of a portion of the flowable dielectric material 164' filling the gap between the gate structures 128 in the active region) and thickness T2 (e.g., the thickness of a portion of the flowable dielectric material 164' filling the gap between the gate structures 128 in the isolation region). Reducing thickness T1 and thickness T2 reduces the distance that UV light must travel during UV curing 170, allowing the flowable dielectric material 164' to be exposed to UV light from top to bottom. In this embodiment, thickness T2 is less than about 350 nm, e.g., about 250 nm to about 350 nm. Even if the ultraviolet light has a high power / density, it still cannot completely penetrate a thicker flowable dielectric material (such as a thickness T3 greater than 200 nm and / or a thickness T2 greater than 350 nm), preventing the bottom of the thicker flowable dielectric material from being exposed to ultraviolet light and thus preventing ultraviolet curing.

[0038] By increasing the amount of flowable dielectric material 164' exposed to ultraviolet light, the flowable dielectric material 164' can be exposed to higher ultraviolet power, such as about 80% to about 100% of the ultraviolet power / intensity, to improve the efficiency of ultraviolet curing 170. If the ultraviolet power / density is less than 80%, it cannot completely penetrate the flowable dielectric material, so that the bottom of the flowable dielectric material cannot be sufficiently exposed to ultraviolet light and cannot be ultraviolet cured. Increasing the ultraviolet power / intensity can achieve a shorter ultraviolet curing time, such as a curing time of about 60 seconds to about 100 seconds. In some embodiments, in order to improve the densification and / or hardening (and ultraviolet curing effect) of the flowable dielectric material 164', ultraviolet curing 170 can expose the flowable dielectric material 164' to ozone. Exposing the flowable dielectric material 164' to ozone may include additional oxygen. In some embodiments, ultraviolet curing 170 exposes the flowable dielectric material 164' to ozone for about 20 seconds to about 40 seconds. In some embodiments, UV curing 170 includes a UV pulse (which exposes the flowable dielectric material 164' to UV light) and an ozone pulse (which exposes the flowable dielectric material 164' to ozone). In some embodiments, the UV pulse and the ozone pulse may be performed separately or at least partially simultaneously. In some embodiments, the pressure in the process chamber during UV curing 170 (such as during UV curing and / or exposure to ozone) is maintained at about 100 Torr to about 130 Torr.

[0039] Compared to the wet etch rate of the interlayer dielectric layer formed by exposing the flowable dielectric material to low UV power (e.g., UV power / intensity of about 40% to about 60%) and increasing the thickness of the deposited flowable dielectric material (e.g., increasing the thickness on the top of the gate structure 128 to about 200 nm to about 350 nm) using a flowable chemical vapor deposition process, the wet etch rate of the interlayer dielectric layer formed by exposing the flowable dielectric material to high UV power (e.g., UV power / intensity of about 80% to about 100%) and decreasing the thickness of the deposited flowable dielectric material (e.g., reducing the thickness on the top of the gate structure 128 to about 100 nm to about 200 nm) can be improved. For example, Figure 12 is an illustrative graph 210 of wet etch rate (e.g., nanometers per minute) in various embodiments of the present invention, where the wet etch rate is a function of the annealing temperature (°C) of the interlayer dielectric layer, and the interlayer dielectric layer is fabricated using different UV powers and different deposition thicknesses. In Figure 210, one set of experimental / simulated data points corresponds to line segment 212, while another set corresponds to line segment 214. Line segment 212 (and its associated experimental / simulated data) corresponds to the wet etch rate of an interlayer dielectric layer fabricated using UV power / intensity of approximately 40% to approximately 60%, with a deposition thickness on the gate structure greater than 200 nm (e.g., approximately 200 nm to approximately 350 nm). Line segment 214 (and its associated experimental / simulated data) corresponds to the wet etch rate of an interlayer dielectric layer fabricated using UV power / intensity of approximately 80% to approximately 100%, with a deposition thickness on the gate structure less than approximately 200 nm (e.g., approximately 100 nm to approximately 200 nm), such as the wet etch rate of the interlayer dielectric layer 164 fabricated using the disclosed flowable chemical vapor deposition process. As clearly shown in Figure 210, increasing the annealing temperature reduces the wet etch rate, and increasing the UV power and decreasing the deposition thickness significantly reduce the wet etch rate of the interlayer dielectric layer (e.g., from the wet etch rate of corresponding segment 212 to the wet etch rate of corresponding segment 214). The interlayer dielectric layer fabricated here exhibits a lower wet etch rate and improved quality. In some examples, the wet etch rate of interlayer dielectric layer 164 can be reduced by 20% compared to the wet etch rate of interlayer dielectric layers fabricated by flowable chemical vapor deposition processes with low UV power / density (e.g., from about 40% to about 60%) and deposition thickness (e.g., thickness T3 / height H3) of about 200 nm to about 350 nm.

[0040] In some embodiments, a flowable chemical vapor deposition process is performed with one or more of the following process parameters to optimize high aspect ratio interstitial filling capability (e.g., minimizing void / gap formation), optimize interlayer dielectric film quality (e.g., reducing wet etch rate of interlayer dielectric), minimize lamellar end oxide propagation, minimize germanium deposition at the interface between the inner spacer and the source / drain, optimize wafer acceptance testing performance, or a combination thereof. Process parameters may include a total deposition thickness of less than about 350 nm, a thickness of less than about 200 nm on the device structure (e.g., gate structure 128), UV power / intensity of about 80% to about 100%, UV exposure time of about 60 seconds to 100 seconds, exposure time to ozone during UV curing of about 20 seconds to 40 seconds, annealing temperature of about 400°C to about 500°C, annealing time of about 1 hour to about 12 hours, or a combination thereof. In some embodiments, the deposited flowable dielectric material 164' has a thickness of about 200 nm. UV curing 170 exposes the flowable dielectric material 164' to UV light at a power / intensity of about 90% for about 80 seconds. UV curing 170 exposes the flowable dielectric material 164' to ozone for about 20 seconds at a pressure of about 100 Torr. The annealing process 175 has an annealing temperature of about 400°C to about 500°C and an annealing time of about 1 hour to about 5 hours. In some embodiments, the annealing temperature is about 400°C. In some embodiments, the annealing temperature is about 450°C. In some embodiments, the annealing temperature is about 500°C. The process parameters are not randomly selected but specifically set to achieve a high-quality interlayer dielectric layer (with a reduced wet etch rate), optimizing electrical performance and thus improving wafer acceptance test metrics. For example, if the deposition thickness is too thick (e.g., greater than 200 nm on the top of the gate structure 128), the UV power is too low (e.g., less than 80%), and the annealing temperature is too low (e.g., less than 300°C), the flowable dielectric material 164' cannot be sufficiently cured / annealed, resulting in poor quality of the interlayer dielectric layer 164. For example, when forming the source / drain contacts, the etching rate of the interlayer dielectric layer 164 may be higher than the required etching rate, thus the interlayer dielectric layer 164 may have undercut and / or other adverse effects. On the other hand, if the annealing temperature is too high (e.g., above approximately 500°C), the advance of the wafer-end oxide and / or germanium accumulation may alter the performance of the device 100, sometimes even causing device failure / discard. Therefore, a specific range of process parameters can be provided to optimize the quality of the interlayer dielectric layer and the wafer acceptance test results, which can improve the overall performance of the device 100 without negatively impacting manufacturing throughput and / or manufacturing complexity.

[0041] Since embodiments of the present invention recognize that the amount of oxidation at the source / drain corresponds to the amount of germanium deposited, embodiments of the present invention further monitor and / or predict the oxidation of the source / drain by evaluating / monitoring the germanium deposit profile. For example, FIG13 is a partial or complete flowchart of method 300 of various embodiments of the present invention, and the method improves the quality of the flowable chemical vapor deposition layer and / or the electrical performance of the device containing these layers based on the germanium deposit profile. Method 300 can be implemented by method 10. Step 310 of method 300 detects the germanium deposit profile, and step 320 selects flowable chemical vapor deposition process parameters based on the detected germanium deposit profile. For example, if the detected germanium stack profile is above the stacking threshold (which corresponds to a harmful amount of source / drain oxidation, potentially increasing the oxide advance level at the edge of the wafer and degrading device performance, causing corresponding devices such as transistors to fail during wafer acceptance testing), a high-power, low-temperature flowable chemical vapor deposition process (UV power of approximately 80% to approximately 100% and annealing temperature of approximately 400°C to approximately 500°C) can be performed to form an interlayer dielectric layer on the source / drain, as described herein and above. If the detected germanium stack profile is below the stacking threshold (which corresponds to negligible or acceptable amounts of source / drain oxidation, allowing the semiconductor device to pass wafer acceptance testing), a low-power, high-temperature flowable chemical vapor deposition process (UV power of approximately 40% to approximately 60% and annealing temperature of approximately 500°C to approximately 700°C) can be performed to form an interlayer dielectric layer. Low-power, high-temperature flowable chemical vapor deposition (CVD) processes can be configured to deposit thicker interlayer dielectric layers, such as an interlayer dielectric layer with a total thickness greater than about 300 nm and a top layer thickness greater than about 200 nm. High-power, low-temperature flowable CVD processes can be configured to deposit thinner interlayer dielectric layers, such as an interlayer dielectric layer with a total thickness less than about 300 nm and a top layer thickness less than about 200 nm. In some embodiments, the germanium stack profile detected is based on measurement and / or simulation characteristics of an apparatus for fabricating the interlayer dielectric layer thereon and / or multiple apparatuses for fabricating the interlayer dielectric layer thereon. The germanium stack profile may be a secondary ion mass spectrometry profile, which may be a simulated secondary proton mass spectrometry profile or an actual secondary ion mass spectrometry profile. In some embodiments, the flowable CVD process parameters may be selected based on the germanium stack profile of the entire wafer or a portion thereof at the source / drain, and the flowable CVD process forms the interlayer dielectric layer on the source / drain of the wafer. Some embodiments implement method 300, where step 20 of method 10 adjusts the flowable chemical vapor deposition process parameters to achieve the desired interlayer dielectric layer quality. Additional steps may be provided before, during, and after method 300, and additional embodiments of method 300 may replace, substitute, or eliminate some of the steps.

[0042] As shown in Figures 7A and 7B, a planarization process (such as chemical mechanical polishing) is performed on the interlayer dielectric layer 164 and the contact etch stop layer 162. The planarization process is performed until the gate structure 128 is exposed as its dummy gate stack 130. The planarization process may remove portions of the interlayer dielectric layer 164 extending above and / or located on top of the gate structure 128 and portions of the contact etch stop layer 162. The remaining interlayer dielectric layer 164 and contact etch stop layer 162 may form a device layer dielectric layer 178 on the source / drain structure 150 and the substrate isolation structure 125. The device layer dielectric layer 178 may fill the gaps / spaces between adjacent gate structures 128 (such as between gate spacers 132 of gate structures 128) and / or between adjacent source / drain structures 150 along the y-direction and / or in the YZ plane. In some embodiments, the dummy gate stack 130 (such as its hard mask) and / or gate spacer 132 may serve as a planarization stop layer (such as a chemical mechanical polishing stop layer). In some embodiments, the planarization process is performed for a period sufficient to expose the dummy gate stack 130. The planarization process may planarize the upper surface of the dielectric layer 178 of the device layer (which may be formed by the interlayer dielectric layer 164 and the contact etch stop layer 162), the upper surface of the dummy gate stack 130, and the upper surface of the gate spacer 132. The planarized upper surface after the planarization process may form a substantially flat surface of the device 100.

[0043] The planarization process can reduce the thickness of the interlayer dielectric layer 164. For example, the planarization process reduces the thickness of the interlayer dielectric layer 164 on the source / drain structure 150 from thickness T1 to thickness T4, reduces the thickness of the interlayer dielectric layer 164 on the substrate isolation structure 125 from thickness T2 to thickness T5, and reduces the thickness of the interlayer dielectric layer 164 on the gate structure 128 from thickness T3 to 0. In some embodiments, the planarization process removes about 100 nm to about 200 nm of the interlayer dielectric layer 164.

[0044] As shown in some embodiments of FIG8A to 8C, a gate replacement process can be performed to replace the dummy gate stack 130 with a gate stack 180. In some embodiments, the dummy gate stack 130 is removed to form a gate opening (e.g., formed between gate spacers 132) to expose a multilayer stack 110 (e.g., its semiconductor layer 120 and sacrificial layer 115) in the channel region of the active region 160. For example, an etching process selectively removes the dummy gate stack 130 while negligibly removing (or not removing) the dielectric layer 178 of the device layer, the gate spacers 132, the inner spacers 145, the sacrificial layer 115, the semiconductor layer 120, or a combination thereof. The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the etching process may employ a patterned mask layer as an etching mask. The patterned masking layer may cover the dielectric layer 178 of the device layer and / or the gate spacer 132, and has an opening therein to expose the dummy gate stack 130.

[0045] During the gate replacement process, a channel release process can be performed before forming the gate stack 180 to form a suspended channel layer. For example, the sacrificial layer 115 exposed by the gate opening can be selectively removed to form gaps between the semiconductor layers 120 and between the semiconductor layers 120 and the mesa 105P', thereby suspending the semiconductor layers 120 in the channel region. In the embodiment, each channel region has three suspended semiconductor layers 120 (hereinafter referred to as channel layers 120') stacked vertically along the z-direction, providing three channels for current to pass through the individual source / drain structures 150 when the transistor of the device 100 is operated. In some embodiments, the etching process selectively etches the sacrificial layer 115 while minimizing (or not etching) the semiconductor layers 120, the mesa 105P', the gate spacer 132, the inner spacer 145, the dielectric layer 178 of the device layer, or a combination thereof. In some embodiments, the etchant used in the etching process is selected such that it etches germanium silicon (e.g., sacrificial layer 115) at a rate higher than it etches silicon (e.g., semiconductor layer 120, mesa 105P', and the like) and dielectric materials (e.g., gate spacer 132, inner spacer 145, dielectric layer 178 of the device layer, and the like). In some embodiments, the etchant used in the etching process is selected such that it etches dielectric materials having a first composition (e.g., sacrificial layer 115) at a rate higher than it etches silicon (e.g., semiconductor layer 120, mesa 105P', and the like) and dielectric materials with compositions different from the first composition (e.g., gate spacer 132, inner spacer 145, dielectric layer 178 of the device layer, and the like). The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, an oxidation process may convert sacrificial layer 115 into a germanium silicon oxide layer prior to the etching process, and the etching process may then remove the germanium silicon oxide layer. In some embodiments, an etching process is performed to adjust the contour of the semiconductor layer 120 / channel layer 120' to achieve the target channel size and / or target channel shape.

[0046] A gate stack 180 (which can also be considered as a high-dielectric-constant gate dielectric layer and a metal gate) may then be formed in the gate openings and / or gaps. A portion of the gate stack 180 is located between individual gate spacers 132, while other portions of the gate stack 180 are located between individual inner spacers 145. The gate stack 180 is further located between channel layers 120' and between channel layers 120' and mesa 105P'. In the described embodiment, the device 100 includes a fully wound gate transistor, and the gate stack 180 may surround and connect individual channel layers 120' in the YZ plane (see FIG. 8C). In some embodiments, the gate stack 180 may cover and / or partially surround individual channel layers 120' (i.e., located on at least both sides of individual channel layers 120').

[0047] The gate stack 180 may each include a gate dielectric layer 182. The gate dielectric layer 182 is located on the channel layer 120', the mesa 105P', the inner spacer 145, the gate spacer 132, or a combination thereof. The gate dielectric layers 182 may have the same or different compositions and / or arrangements. The gate dielectric layer 182 includes at least one dielectric layer, such as an interface layer and / or a high dielectric constant dielectric layer. The interface layer includes dielectric materials such as silicon oxide, germanium silicon oxide, hafnium silicon oxide, silicon oxynitride, other dielectric materials, or a combination thereof. High dielectric constant dielectric layers include dielectric materials with high dielectric constants, which are generally considered to be dielectric materials with a dielectric constant greater than that of silicon oxide, such as hafnium oxide, hafnium silicon oxide, hafnium silicate, hafnium silicon oxynitride, hafnium lanthanum oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium aluminum oxide, zirconium oxide, zirconium dioxide, zirconium silicon oxide, aluminum oxide, aluminum silicon oxide, aluminum oxide, titanium oxide, titanium dioxide, lanthanum oxide, lanthanum silicon oxide, lanthanum trioxide, lanthanum trioxide, tantalum trioxide, tantalum pentoxide, yttrium oxide, strontium titanate, barium zirconium oxide, barium titanate, barium strontium titanate, hafnium-aluminum oxide, other high dielectric constant dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layers 182 may each comprise a hafnium-based oxide such as a hafnium oxide layer and / or a zirconium-based oxide such as a zirconium oxide layer. The gate stacks 180 may each comprise a gate 184. Gates 184 are located on the gate dielectric layers 182. Gates 184 may have the same or different compositions and / or arrangements, and each gate 184 comprises at least one conductive layer composed of a conductive material, which may include aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, tantalum nitride, nickel silicate, cobalt silicate, titanium nitride, tungsten nitride, titanium aluminum, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, tantalum silicon nitride, other conductive compositions, or combinations thereof. In some embodiments, the gate 184 comprises a work function layer. The work function layer is a conductive layer that can be adjusted to have a desired work function (e.g., an n-type work function or a p-type work function). The work function layer includes a work function metal and / or its alloys, such as titanium, tantalum, aluminum, silver, manganese, zirconium, tungsten, ruthenium, molybdenum, titanium carbide, titanium aluminum, titanium aluminum carbide, titanium aluminum silicon carbide, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, titanium silicon nitride, titanium nitride, tantalum nitride, tantalum sulfide, tungsten nitride, tungsten carbonitride, zirconium silicate, molybdenum silicate, tantalum silicate, nickel silicate, tantalum aluminum, tantalum aluminum carbide, tantalum aluminum carbide, titanium aluminum carbide, or combinations thereof. In some embodiments, the gate 184 includes a substrate layer located on the gate dielectric layer 182 and / or the work function layer. The substrate layer may include aluminum, tungsten, copper, titanium, tantalum, titanium nitride, tantalum nitride, polycrystalline silicon, other suitable metals and / or alloys thereof, or combinations thereof. In some embodiments, the gate 184 includes a barrier layer located on the work function layer and / or the gate dielectric layer 182. The barrier layer includes a material that can prevent compositional diffusion and / or reaction between adjacent layers, and / or promote adhesion between adjacent layers such as the work function layer and the substrate layer.In some embodiments, the barrier layer comprises a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides, or combinations thereof.

[0048] A method of forming the gate stack 180 may include depositing a gate dielectric material (such as an interface layer, a high dielectric constant dielectric layer, and the like) to partially fill the gate opening, depositing a gate material (such as a work function layer, a barrier layer, a substrate layer, and the like) to fill the remaining portion of the gate opening, and performing a planarization process to remove portions of the gate dielectric material and / or the gate material on the dielectric layer 178 of the device layer. In some embodiments, a method of fabricating the device 100 may further include etching back the gate stack 180 and forming a hard mask (such as a self-aligned cap structure) on the etched-back gate stack 180. The self-aligned cap structure comprises a material different from the interlayer dielectric layer 164 and / or the subsequently formed dielectric layer to achieve etch selectivity. In some embodiments, the self-aligned cap structure includes silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, other silicon nitrides, other silicon carbides, or combinations thereof. In some embodiments, the self-aligned cap structure includes metal and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, hafnium oxide, aluminum zirconium oxide, other metal oxides, other metal nitrides, or combinations thereof. Although the embodiments described herein fabricate the gate stack 180 according to a post-gate fabrication process, embodiments of the present invention may fabricate the metal gate stack of the apparatus 100 according to a gate-first process or a hybrid gate-first / gate-second process.

[0049] As shown in Figures 9A and 9B, dielectric layer 186 may be formed on dielectric layer 178 of device layer. In some embodiments, dielectric layer 186 includes a contact etch stop layer 187 and an interlayer dielectric layer 188. The contact etch stop layer 187 is formed on interlayer dielectric layer 164 and gate structure 128, while the interlayer dielectric layer 188 is formed on contact etch stop layer 187. In some embodiments, the method of forming dielectric layer 186 includes depositing contact etch stop layer 187 on dielectric layer 178 of device layer, depositing interlayer dielectric layer 188 on contact etch stop layer 187, and performing chemical mechanical polishing and / or other planarization processes on interlayer dielectric layer 188. Since the device 100 following the dielectric layer 178 of the device layer does not have gaps between device structures and / or includes gaps with an aspect ratio smaller than the gaps between gate structures 128, different types of chemical vapor deposition processes can be implemented to form the interlayer dielectric layer 188. For example, the aspect ratio can be 0, and the interlayer dielectric layer 188 can be formed by plasma-assisted chemical vapor deposition rather than flowable chemical vapor deposition.

[0050] The interlayer dielectric layer 188 may be configured similarly to the interlayer dielectric layer 164. For example, the interlayer dielectric layer 188 may include a dielectric material such as silicon oxide, carbon-doped silicon oxide, an oxide formed from tetraethoxysilane, phospholipid glass, borosilicate glass, borosilicate glass, fluorosilicone glass, desiccant, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene-based dielectric material, polyimide, other suitable dielectric materials, or combinations thereof. The dielectric material may be the same as or different from the dielectric material of the interlayer dielectric layer 164. In some embodiments, the interlayer dielectric layer 188 is a low dielectric constant dielectric layer, such as a silicon and oxygen-containing dielectric layer with a dielectric constant less than about 3.9 (less than about 2.5 in some embodiments).

[0051] The method of setting and / or forming the contact etch stop layer 187 may be similar to that of the contact etch stop layer 162. The contact etch stop layer 187 comprises a material different from that of the interlayer dielectric layer 188 to achieve etch selectivity between the two. For example, the dielectric material of the contact etch stop layer 187 is different from that of the interlayer dielectric layer 188. In some embodiments, the contact etch stop layer 187 comprises silicon and nitrogen. For example, the contact etch stop layer 187 is a silicon nitride layer and / or a silicon oxynitride layer. In some embodiments, the interlayer dielectric layer 188 and / or the contact etch stop layer 187 may have a multilayer structure and / or comprise multiple dielectric materials.

[0052] As shown in some embodiments of FIG10A and 10B, at least one source / drain contact 190 to an individual source / drain structure 150 is formed. In the embodiments, the source / drain contact 190 is formed in a dielectric layer 178 of the device layer (such as an interlayer dielectric layer 164 and a contact etch stop layer 162) and a dielectric layer 186 (such as an interlayer dielectric layer 188 and a contact etch stop layer 187). In some embodiments, the method of forming the source / drain contact 190 includes forming a source / drain contact opening extending through the dielectric layer 186 and the dielectric layer 178 of the device layer to expose the individual source / drain structure 150 by an etching process, depositing at least one conductive material (such as a metal substrate material) on the dielectric layer 186 and filling the source / drain contact opening, and performing a planarization process to remove any conductive material located on top of the dielectric layer 186. A planarization process can be performed until the interlayer dielectric layer 188 is exposed. In some embodiments, the retained conductive material forms metal plugs and one or more pads for the source / drain contacts. Conductive materials include tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. Because the interlayer dielectric layer 164 is fabricated using the method described herein, the profile of the source / drain contact openings is improved, increasing the likelihood that the device 100 will pass wafer acceptance testing. For example, when the interlayer dielectric layer 164 is formed using other flowable chemical vapor deposition processes, it may have significant undercut, resulting in voids in the interlayer dielectric layer 164. Voids may be filled with undesirable conductive material, undesirably reducing the distance between the source / drain contact 190 and the conductive device structure (such as gate structure 128 and its gate stack 180), causing an electrical short circuit between the source / drain contact 190 and the conductive device structure, making device 100 a defective device. In contrast, because the interlayer dielectric layer is fabricated using the method described herein (with a lower etch rate), the interlayer dielectric layer 164 after forming the source / drain contact opening may not have an undercut and / or has a negligible undercut, so that the interlayer dielectric layer 164 does not have voids therein (voids could cause the source / drain contacts to extend too far laterally). Some embodiments form a silicon layer on the exposed doped semiconductor layer before depositing the conductive material.

[0053] This invention provides many different embodiments. An exemplary method of forming a semiconductor device includes depositing a flowable dielectric material on a substrate. The flowable dielectric material fills the space between a first gate structure and a second gate structure. The method further includes ultraviolet curing of the flowable dielectric material and annealing of the ultraviolet-cured flowable dielectric material. The ultraviolet curing ultraviolet power is greater than about 80%, and the annealing temperature is less than about 500°C.

[0054] In some embodiments, the thickness of the flowable dielectric material deposited on top of the first gate structure and the second gate structure is less than about 200 nm. In some embodiments, the method further includes selecting the thickness of the flowable dielectric material deposited on top of the first gate structure and the second gate structure based on the expected germanium stacking characteristics at the interface between the inner spacer and the source / drain. In some embodiments, the method further includes selecting the ultraviolet power and annealing temperature based on the expected germanium stacking characteristics at the interface between the inner spacer and the source / drain.

[0055] In some embodiments, the annealing temperature is from about 400°C to about 500°C; and the annealing time is from about 1 hour to about 5 hours. In some embodiments, UV curing includes exposing the flowable dielectric material to ozone. In some embodiments, the UV curing power is from about 80% to about 100%, and the UV curing time is from about 60 seconds to 100 seconds. In some embodiments, the UV power is 90% and the annealing temperature is 400°C. In some embodiments, the UV power is 90% and the annealing temperature is 450°C. In some embodiments, the UV power is 90% and the annealing temperature is 500°C.

[0056] An exemplary method of forming a semiconductor device includes: performing a flowable chemical vapor deposition process to form a first interlayer dielectric layer on a substrate; and performing a chemical vapor deposition process to form a second interlayer dielectric layer on the first interlayer dielectric layer. In some embodiments, the first interlayer dielectric layer fills a plurality of gaps between a plurality of gate structures, the ultraviolet power of the flowable chemical vapor deposition is about 80% to about 100%, and the temperature of the flowable chemical vapor deposition process is about 300°C to about 500°C. In some embodiments, performing the chemical vapor deposition process includes performing a plasma-assisted chemical vapor deposition process. In some embodiments, the flowable chemical vapor deposition process includes a deposition process, a curing process for applying ultraviolet power, and a thermal process for applying the temperature; and the time of the curing process is less than the time of the thermal process. In some embodiments, the gaps between the gate structures have a first aspect ratio in the isolation region and a second aspect ratio in the active region, and the first aspect ratio is greater than the second aspect ratio. In some embodiments, the first aspect ratio is greater than 10. In some embodiments, the method further includes selecting ultraviolet power, temperature, and deposition thickness of the first interlayer dielectric layer based on a sheet-end oxide propulsion model, and generating a sheet-end oxide propulsion model based on the expected germanium stacking characteristics at the interface between the inner spacer and the source / drain.

[0057] In some embodiments, the deposition thickness of the first interlayer dielectric layer on top of the gate structure is less than about 200 nm, and the method further includes performing a planarization process on the first interlayer dielectric layer. In some embodiments, the method further includes forming a source / drain contact in the second interlayer dielectric layer and the first interlayer dielectric layer. The source / drain contact is located between the first and second gate structures.

[0058] Another exemplary method for forming a semiconductor device includes: analyzing germanium stacking profile characteristics corresponding to multiple inner spacers of a plurality of devices and multiple interface regions of a plurality of source / drain structures in an interlayer dielectric layer having multiple device layers. Each interlayer dielectric layer of the device layers has a corresponding set of flowable chemical vapor deposition process parameters. The method further includes selecting multiple flowable chemical vapor deposition process parameters based on the analyzed germanium stacking profile characteristics for use in the interlayer dielectric layer of an individual device layer formed by the flowable chemical vapor deposition process. In some embodiments, the method further includes forming the interlayer dielectric layer of the individual device layer using the selected flowable chemical vapor deposition process parameters. The interlayer dielectric layer of the individual device layer is formed on a plurality of source / drain structures and fills multiple gaps between a plurality of gate structures. In some embodiments, the flowable chemical vapor deposition process parameters include ultraviolet power of an ultraviolet curing process, annealing temperature of an annealing process, and deposition thickness.

[0059] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention. [Simplified Explanation of the Diagram]

[0006] Figure 1 is a flowchart of part or all of the method for forming a dielectric structure on a device according to various embodiments of the present invention. Figure 2 is a top view of part or all of the device according to various embodiments of the present invention, on which the device will be processed to form a dielectric structure. Figures 3A to 10A are partial or all of the cross-sectional views of the device of Figure 2 along section line AA at various fabrication stages (e.g., related to the method of Figure 1) according to various embodiments of the present invention. Figures 3B to 10B are partial or all of the cross-sectional views of the device of Figure 2 along section line BB at various fabrication stages (e.g., related to the method of Figure 1) according to various embodiments of the present invention. Figure 8C is a cross-sectional view of the device of Figure 2 along section line CC at the fabrication stages related to Figures 8A and 8B according to various embodiments of the present invention. Figure 11 is a germanium depth profile of the interface region between the inner spacer and the source / drain after forming an interlayer dielectric layer using a flowable chemical vapor deposition process with different annealing temperatures (related to the method of Figure 1) according to various embodiments of the present invention. Figure 12 is a comparative diagram of interlayer dielectric layers formed by dielectric structures such as different flowable chemical vapor deposition processes (related to the method of Figure 1) in various embodiments of the present invention. Figure 13 is a flowchart of part or all of the method implemented in Figure 1 in various embodiments of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: A flowable dielectric material is deposited on a substrate, wherein the flowable dielectric material fills a space between a first gate structure and a second gate structure. The flowable dielectric material is cured by ultraviolet light; The flowable dielectric material is annealed and cured with ultraviolet light, wherein the annealing temperature is less than about 500°C, wherein the thickness of the flowable dielectric material deposited on the top of the first gate structure and the second gate structure, the ultraviolet power of the ultraviolet curing of the flowable dielectric material, and the selection of the annealing temperature are based on the germanium stacking characteristics analyzed at the interface between an inner spacer and the source / drain.

2. The method of forming a semiconductor device as claimed in claim 1, wherein the thickness of the flowable dielectric material deposited on top of the first gate structure and the second gate structure is less than about 200 nm.

3. A method for forming a semiconductor device, comprising: A flowable chemical vapor deposition process is performed to form a first interlayer dielectric layer on a substrate, wherein the first interlayer dielectric layer fills multiple gaps between multiple gate structures, and the flowable chemical vapor deposition process is performed at a temperature of approximately 300°C to approximately 500°C, wherein the deposition thickness of the first interlayer dielectric layer and the selection of the ultraviolet power and temperature of the flowable chemical vapor deposition process are based on germanium stacking characteristics analyzed at the interface between an inner spacer and the source / drain; and a chemical vapor deposition process is performed to form a second interlayer dielectric layer on the first interlayer dielectric layer.

4. The method for forming a semiconductor device as claimed in claim 3, wherein performing the chemical vapor deposition process includes performing a plasma-assisted chemical vapor deposition process.

5. A method for forming a semiconductor device as claimed in claim 3 or 4, wherein: The flowable chemical vapor deposition process includes a deposition process, a curing process applying the ultraviolet power, and a thermal process applying the temperature; and the time of the curing process is less than the time of the thermal process.

6. A method for forming a semiconductor device, comprising: The germanium stacking profile characteristics corresponding to multiple inner spacers of multiple devices and multiple interface regions of multiple source / drain structures in an interlayer dielectric layer with multiple device layers are analyzed, wherein each of the interlayer dielectric layers of these device layers has a corresponding set of flowable chemical vapor deposition process parameters; and multiple flowable chemical vapor deposition process parameters are selected based on the analyzed germanium stacking profile characteristics for use in an interlayer dielectric layer of a separate device layer formed by a flowable chemical vapor deposition process.

7. The method of forming a semiconductor device as claimed in claim 6 further includes forming an interlayer dielectric layer of the individual device layer using selected flowable chemical vapor deposition process parameters, wherein the interlayer dielectric layer of the individual device layer is formed on a plurality of source / drain structures and fills a plurality of gaps between a plurality of gate structures.

8. A method for forming a semiconductor device as claimed in claim 6 or 7, wherein the flowable chemical vapor deposition process parameters include ultraviolet power of an ultraviolet curing process, annealing temperature of an annealing process, and a deposition thickness.

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