Semiconductor device structure and method of forming the same

Abstract

This document discloses a method for fabricating a multi-gate transistor using a dummy oxide interposer. An exemplary method includes forming a multilayer stack comprising a plurality of first semiconductor layers, a plurality of sacrificial semiconductor layers, and a substrate extension. Removal portions of the semiconductor layers, sacrificial semiconductor layers, and substrate extension in the source / drain regions is performed to form source / drain recesses, and a source / drain structure is formed within the source / drain recesses. The source / drain structure includes a second semiconductor layer and an insulating layer, with the insulating layer located between the second semiconductor layer and the substrate extension. Before forming the source / drain structure, the sacrificial semiconductor layer is replaced with a sacrificial dielectric layer. After forming the source / drain structure, the sacrificial dielectric layer is removed from the channel region to form a portion of the gate opening. A gate stack is formed in the portion of the gate opening.

Description

[Technical Field]

[0001] This invention relates to a multi-gate device, such as a fully wound gate transistor, used to improve overall performance, and its manufacturing method. [Previous Technology]

[0002] Multi-gate devices have recently been introduced to improve gate control, and the gates of multi-gate devices can extend partially or completely around the channel to contact at least both sides of the channel. Exemplary multi-gate devices include finned field-effect transistors and fully wound gate transistors such as nanowire transistors. Multi-gate devices can significantly reduce the size of integrated circuit technology, maintain gate control, mitigate short-channel effects, and seamlessly integrate into existing integrated circuit manufacturing processes and / or technologies. As the size of multi-gate devices continues to shrink, advanced technologies are needed to optimize their reliability and / or performance. [Summary of the Invention]

[0003] An exemplary method of forming a semiconductor device structure includes forming a multilayer stack on a protrusion, the multilayer stack including a plurality of first semiconductor layers and a plurality of first sacrificial layers, the first sacrificial layers having a first composition. A portion of the first semiconductor layers, the first sacrificial layers, and the protrusion is removed from a source / drain region to form a source / drain recess, and a source / drain structure is formed in the source / drain recess. The source / drain structure includes a second semiconductor layer and an insulating layer, wherein the insulating layer is located between the second semiconductor layer and the protrusion. Before forming the source / drain structure, the first sacrificial layers are replaced with a plurality of second sacrificial layers, the second composition of which differs from the first composition. After forming the source / drain structure, the second sacrificial layers are removed from a channel region to form a portion of a gate opening; and a gate stack is formed in the portion of the gate opening.

[0004] Another exemplary method of forming a semiconductor device structure includes forming a multilayer stack comprising a plurality of semiconductor layers, a plurality of sacrificial semiconductor layers, and a substrate extension. The method further includes removing a portion of the semiconductor layers, sacrificial semiconductor layers, and substrate extension in a source / drain region to form a source / drain recess; and forming a source / drain structure in the source / drain recess. The method of forming the source / drain structure may include forming an undoped semiconductor layer on the substrate extension to partially fill the source / drain recess; forming an insulating layer on the undoped semiconductor layer to partially fill the source / drain recess; and forming a doped semiconductor layer on the insulating layer to fill the remaining source / drain recess. The method further includes replacing the sacrificial semiconductor layer in the channel region with a plurality of sacrificial oxide layers before forming the source / drain structure in the source / drain recess. The method further includes replacing the sacrificial oxide layer in the channel region with a gate stack after forming the source / drain structure in the source / drain recess.

[0005] An exemplary semiconductor device structure includes a first p-type transistor, comprising a first semiconductor layer of a first length extending from a first p-type doped source / drain to a second p-type source / drain, a first gate stack on the first semiconductor layer, and a plurality of first inner spacers. The device structure further includes a second p-type transistor, comprising a second semiconductor layer of a second length extending from a third p-type doped source / drain to a fourth p-type source / drain, a second gate stack on the second semiconductor layer, and a plurality of second inner spacers. A portion of the first gate stack is located between the first inner spacers, the first inner spacers extending beyond the ends of the first semiconductor layer, and the first p-type source / drain is located on a first source / drain insulating layer. A portion of the second gate stack is located between the second inner spacers, the second length being greater than the first length, and the third p-type doped source / drain is located on the second source / drain insulating layer.

Implementation Method

[0007] The following detailed description is illustrated in conjunction with the accompanying drawings to facilitate understanding of various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in this field. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0008] The different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or the two being spaced apart by other additional components rather than in direct contact. Furthermore, spatial relative terms such as "lower," "upper," "horizontal," "vertical," "above," "below," "under," "top," "bottom," or similar terms, and their derivatives such as "horizontally," "downward," "upward," or similar terms, are used to describe the relationship between some structures and another structure in the drawings. These spatial relative terms include different orientations of the apparatus containing the structures. Additionally, when descriptions of numerical values ​​or ranges are accompanied by terms such as "about," "approximately," or similar terms, it is intended to cover numerical values ​​within a reasonable range, such as those of ordinary skill in the art considering inherent variations arising during the manufacturing process. For example, based on known manufacturing tolerances related to numerical values, the numerical value or range covers a reasonable range including the number, such as within + / - 20% of the number. For example, when the thickness of the material layer is about 5 nm and those skilled in the art know that the manufacturing tolerance for deposited material layers is 15%, the included size range is 4.25 nm to 5.75 nm. Furthermore, various embodiments of the invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or settings do not necessarily have the same correspondence.

[0009] The gate structure of a multi-gate device extends partially or completely around the channel region to contact at least both sides of the channel region. One type of multi-gate device is a fully wound gate device, in which the channel regions are stacked vertically or horizontally and suspended on a substrate, such that the gate stack covers (or surrounds) and connects to the channel regions. The channel layer extends between the source region and the drain region (e.g., epitaxial source / drain), and a voltage can be applied to the gate stack, the source region, and / or the drain region to control the current flowing between the source and drain regions. Fully wound gate devices can significantly improve the contact area between the gate stack and the channel region, and compared with other multi-gate devices such as fin field-effect transistors, can reduce subcritical oscillation, reduce short-channel effects, increase device current, and / or improve channel control.

[0010] However, as integrated circuit technology nodes shrink (e.g., increasing device density by increasing the number of interconnect devices in a given wafer area, and / or reducing geometry such as device structure and / or space between device structures), leakage current in fully wound gate devices becomes a significant challenge. For example, parasitic transistors may form between the gate stack, the substrate protrusion (the portion of the channel layer and gate stack located thereon), and the epitaxial source / drain, and undesirable current may flow / leak through the substrate protrusion between the epitaxial source / drain. Since the gate stack may cover the substrate protrusion (rather than surround the channel layer), the gate stack's control over the leakage current in the off state in the substrate protrusion is limited to three sides (e.g., three-gate control), which has proven insufficient as integrated circuit technology nodes shrink, and can induce and / or exacerbate drain-induced barrier degradation and performance degradation.

[0011] In embodiments of the present invention, an insulating material (such as a dielectric layer) and / or a material with lower conductivity (such as an undoped epitaxial layer at the bottom) is inserted between the epitaxial source / drain and the substrate to reduce leakage current through the underlying substrate and / or the raised portion of the substrate (hereinafter referred to as a mesa). However, embodiments of the present invention further recognize that epitaxial sources / drains formed on an insulating material (such as an amorphous surface) rather than on a semiconductor material may have lower stress / strain than epitaxial sources / drains formed on a semiconductor material. Therefore, incorporating an insulating material into the source / drain structure can reduce parasitic capacitance and / or leakage current, but it also reduces the required source / drain stress / strain undesirably. Specifically, p-type epitaxial sources / drains formed on an insulating layer (such as p-type doped silicon-germanium sources / drains) may experience significant stress loss, which degrades the performance of the p-type transistor.

[0012] Therefore, embodiments of the present invention propose reducing, during fabrication, other undesirable stresses that may be introduced into the epitaxial source / drain and / or channels of the transistor to compensate for source / drain stress losses caused by the inclusion of a bottom source / drain isolation layer therein. For example, embodiments of the present invention recognize that a sacrificial dummy semiconductor layer (such as a sacrificial silicon-germanium layer, which can be considered as a sacrificial silicon-germanium interposer) is interspersed with a semiconductor layer (which is later transformed into a channel layer of the transistor) in the channel region, and the sacrificial semiconductor layer may induce undesirable stresses in the channel layer, such as inducing undesirable tensile stresses in the channel layer of a p-type transistor. Therefore, embodiments of the present invention propose replacing the sacrificial dummy semiconductor layer with a sacrificial dummy dielectric layer such as a dummy oxide layer (which can be considered as a dummy oxide interposer) to eliminate stresses induced in the channel layer during fabrication. Thus, the dummy dielectric interposer can compensate for any source / drain stress / strain losses caused by integrating the bottom source / drain isolation layer into the source / drain structure. Transistors made with a dummy dielectric interlayer and a source / drain bottom insulating layer have less performance loss compared to transistors made with a dummy semiconductor interlayer and a source / drain bottom insulating layer.

[0013] Details of the method for fabricating a multi-gate device (such as a p-type fully wound gate transistor) with a bottom source / drain isolation layer using a dummy dielectric interposer will be described below. From the description herein, it will be understood that the multi-gate device fabricated using the method of the embodiments of the present invention can provide more advantages than other methods, such as multi-gate devices fabricated using a dummy semiconductor interposer. However, it should be understood that different methods may have different advantages, and no particular embodiment requires a specific advantage.

[0014] Figure 1 is a partial or complete flowchart of a method 10 for fabricating a multi-gate device using a sacrificial dielectric layer (which can also be considered as a dummy oxide interposer) in various embodiments of the present invention. Step 15 of method 10 forms a multilayer stack including a sacrificial semiconductor layer (such as a silicon-germanium layer), a semiconductor layer (such as a silicon layer), and a substrate extension. Step 20 may form a gate structure on the multilayer stack in the channel region. The gate structure may include a dummy gate stack and a gate spacer. Step 25 removes a portion of the multilayer stacked semiconductor layer, the sacrificial semiconductor layer, and the substrate extension in the source / drain region to form a source / drain recess. Step 30 of method 10 further includes removing the multilayer stacked sacrificial semiconductor layer from the channel region to form a first gap between the multilayer stacked semiconductor layers in the channel region. Step 35 forms a sacrificial dielectric layer (such as an oxide layer) in the first gap. Step 40 of method 10 may recess the sacrificial dielectric layer to form an inner spacer recess between the ends of the multilayer stacked semiconductor layers in the channel region, and step 45 may form an inner spacer in the inner spacer recess. Step 50 of method 10 may form a source / drain structure in the source / drain recess, which may include step 52 of forming an undoped semiconductor layer, step 54 of forming an insulating layer, and step 56 of forming a doped semiconductor layer. Step 60 of method 10 may remove a dummy gate stack to form a gate opening, step 65 may remove the sacrificial dielectric layer to form a second gap between the multilayer stacked semiconductor layers in the channel region, and step 70 may form a gate stack in the gate opening and the second gap. Embodiments of the present invention may implement additional processes. Additional steps may be provided before, during, and after method 10, and additional embodiments of method 10 may substitute, replace, or eliminate some of the steps. The following apparatus may be fabricated according to method 10.

[0015] FIG2 is a partial or complete top view of device 100 in various embodiments of the present invention, which may be processed by method 10 of FIG1 to include a bottom source / drain insulating layer. FIG3A to 19A are cross-sectional views along section line AA of part or all of device 100 of FIG2 in various manufacturing stages (as shown in the manufacturing stages related to method 10 of FIG1) in various embodiments of the present invention. FIG3B to 19B are cross-sectional views along section line BB of part or all of device 100 of FIG2 in various manufacturing stages (as shown in the manufacturing stages related to method 10 of FIG1) in various embodiments of the present invention. FIG17C is a cross-sectional view along section line CC of part or all of device 100 of FIG2 in various embodiments of the present invention during the manufacturing stages of FIG17A and 17B. FIG2, FIG3A to 19A, FIG3B to 19B, and FIG17C will be described here simultaneously for ease of understanding. FIG2, FIG3A to 19A, FIG3B to 19B, and FIG17C have been simplified for clarity to facilitate understanding of the inventive concept of the embodiments of the present invention. Additional structures may be added to device 100, and other embodiments of device 100 may replace, adjust, or eliminate some of the following structures.

[0016] After the processes described in Figures 2, 3A to 19A, 3B to 19B, and related to Figure 17C, device 100 may include at least one fully wound gate transistor (i.e., a transistor whose gate at least partially surrounds a floating channel, which may be a nanowire, nanosheet, nanorod, or the like extending between the source and drain). In the embodiments described, device 100 is processed using a dummy dielectric interlayer (such as an oxide) to fabricate a p-type transistor with a bottom source / drain insulating layer to improve its performance. For example, a p-type transistor fabricated using the methods described herein may have lower leakage current, lower parasitic capacitance, lower channel resistance, lower bottom source / drain insulation R0 penalty, or a combination thereof, compared to a p-type transistor fabricated using a dummy semiconductor interlayer such as silicon germanium with a bottom source / drain insulating layer. In some embodiments, device 100 is processed to form an n-type transistor. In some embodiments, device 100 is processed to form n-type transistors and p-type transistors. In these embodiments, device 100 may include a complementary metal-oxide-semiconductor (CMOS). Device 100 may be included in a microprocessor, memory, other integrated circuit devices, or combinations thereof. In some embodiments, device 100 is part of an integrated circuit chip or a system-on-a-chip or a portion thereof, and device 100 may include a variety of passive electronic devices and / or active electronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors, n-type field-effect transistors, CMOS field-effect transistors, complementary CMOS, bipolar junction transistors, laterally diffused CMOS, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0017] As shown in Figures 2, 3A, and 3A, a method of fabricating device 100 may include forming and / or receiving device precursors, which may include a substrate 105 and a multilayer stack 110. The multilayer stack 110 may include a sacrificial semiconductor layer 115 and a semiconductor layer 120, and the multilayer stack 110 may be located on a mesa 105' (protrusion) of the substrate 105. The multilayer stack 110 may correspond to and / or define an active region 122 of device 100. The active region 122 extends along the x-direction (i.e., has a length along the x-direction, a width along the y-direction, and a height along the z-direction), and the orientation of the active region 122 is substantially parallel to the orientation of other active regions. The active region 122 may include a channel region C, a source region, and a drain region. The source region and the drain region may be considered together as a source / drain region S / D.

[0018] The substrate 105 includes semiconductor elements (such as silicon and / or germanium), semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium arsenide phosphide, or combinations thereof), or combinations thereof. In some embodiments, the substrate 105 is a silicon substrate. In some embodiments, the substrate 105 is a semiconductor-on-insulator substrate such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. The substrate 105 (and mesa 105') may include various doped regions, such as p-type doped regions (such as p-type wells), n-type doped regions (such as n-type wells), or combinations thereof. The n-type doped region includes n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The p-type doped region includes p-type dopants such as boron, indium, gallium, other p-type dopants, or combinations thereof. In some embodiments, the doped region includes both p-type and n-type dopants. The doped region may be formed in a substrate 105, a mesa 105', a multilayer stack 110, or a combination thereof.

[0019] In some embodiments, the multilayer stack 110 is formed by depositing a sacrificial semiconductor layer 115 and a semiconductor layer 120 on a substrate 105 and patterning the sacrificial semiconductor layer 115 and the semiconductor layer 120. In some embodiments, the patterning process extends to the substrate 105 to form its mesa 105'. The sacrificial semiconductor layer 115 and the semiconductor layer 120 are stacked vertically (e.g., along the z-direction) from the top of the substrate 105 in an alternating arrangement. In some embodiments, the deposition method includes epitaxially growing the sacrificial semiconductor layer 115 and the semiconductor layer 120 in the said alternating arrangement. For example, a first sacrificial semiconductor layer 115 is epitaxially grown on the substrate 105, a first semiconductor layer 120 is epitaxially grown on a first sacrificial semiconductor layer 115, a second sacrificial semiconductor layer 115 is epitaxially grown on a first semiconductor layer 120, and so on until the multilayer stack 110 has the desired number of sacrificial semiconductor layers 115 and semiconductor layers 120. In these embodiments, the sacrificial semiconductor layer 115 and the semiconductor layer 120 can be considered as epitaxial layers. In some embodiments, the method for epitaxially growing the sacrificial semiconductor layer 115 and the semiconductor layer 120 is a molecular beam epitaxy process, a chemical vapor deposition process, a metal-organic chemical vapor deposition process, other suitable epitaxial growth processes, or a combination thereof.

[0020] The composition of the sacrificial semiconductor layer 115 differs from that of the semiconductor layer 120 to achieve etch selectivity. For example, the sacrificial semiconductor layer 115 and the semiconductor layer 120 comprise different materials, atomic percentages, weight percentages, other properties, or combinations thereof to achieve etch selectivity. In some embodiments, the sacrificial semiconductor layer 115 comprises silicon germanium, the semiconductor layer 120 comprises silicon, and the semiconductor layer 120 and the sacrificial semiconductor layer 115 have different etch rates for a given etchant. In some embodiments, the sacrificial semiconductor layer 115 and the semiconductor layer 120 comprise the same material with different atomic percentages. For example, the sacrificial semiconductor layer 115 and the semiconductor layer 120 may comprise silicon germanium, and the germanium atomic percentages of the sacrificial semiconductor layer 115 and the semiconductor layer 120 differ to provide etch selectivity. The sacrificial semiconductor layer 115 and the semiconductor layer 120 may comprise any combination of materials to provide the desired etch selectivity, the desired difference in oxidation rate, the desired performance characteristics (such as materials that maximize current), or combinations thereof.

[0021] Semiconductor layer 120 or a portion thereof may form channels for the transistor. In the described embodiment, the multilayer stack 110 includes three sacrificial semiconductor layers 115 and three semiconductor layers 120. The multilayer stack 110 thus includes three pairs of semiconductor layers on the substrate 105, and each pair of semiconductor layers has an individual sacrificial semiconductor layer 115 and an individual semiconductor layer 120. This arrangement allows the transistor to have three channels after the fabrication process of the multilayer stack 110. However, in some embodiments, the multilayer stack 110 includes a different number of semiconductor layers 120, depending on the number of channels required by the transistor. For example, the multilayer stack 110 may include two to six pairs of semiconductor layers, and each pair of semiconductor layers has an individual sacrificial semiconductor layer 115 and an individual semiconductor layer 120.

[0022] The patterned multilayer stack 110 includes a semiconductor layer stack (i.e., sacrificial semiconductor layer 115 and semiconductor layer 120) located on a mesa 105', and the mesa 105' can be considered as a substrate extension, substrate fin portion, fin-like portion, protrusion, etched substrate portion, or the like. The multilayer stack 110 can be considered as a fin, fin structure, fin unit, active fin region, active region, or the like. In some of the illustrated embodiments, the mesa 105' can be considered as part of the multilayer stack 110. The multilayer stack 110 extends substantially along the x-direction and has a length along the x-direction, a width along the y-direction, and a height along the z-direction. In some embodiments, lithography and / or etching processes are performed to pattern the sacrificial semiconductor layer 115, semiconductor layer 120, and substrate 105 to form the multilayer stack 110. In some embodiments, the method for forming the multilayer stack 110 may be a plurality of patterning processes, such as a dual-patterned lithography process (e.g., lithography-etching-lithography-etching process, self-aligned dual-patterned process, process where the spacer is a dielectric layer, other dual-patterned processes, or combinations thereof), a triple-patterned process (e.g., lithography-etching-lithography-etching-lithography-etching process, self-aligned triple-patterned process, other triple-patterned processes, or combinations thereof), other multiple-patterned processes (e.g., self-aligned quadruple-patterned process), or combinations thereof. In some embodiments, directional self-assembly technology may be implemented. In some embodiments, the multilayer stack 110 may be formed by a fin fabrication process.

[0023] The substrate isolation structure 125 may surround and be adjacent to the lower portion of the multilayer stack 110 (such as its mesa 105'), and the multilayer stack 110 may be separated from other multilayer stacks and / or other devices by the substrate isolation structure 125. The substrate isolation structure 125 may electrically isolate active device regions (such as multilayer stack 110) from other device regions such as other multilayer stacks. The substrate isolation structure 125 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including silicon, oxygen, nitrogen, carbon, other suitable isolation components, or combinations thereof), or combinations thereof. The substrate isolation structure 125 may have a multilayer structure. For example, the substrate isolation structure 125 may include a substrate dielectric layer (such as an oxide layer) on top of a dielectric pad (such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or combinations thereof). In another example, the substrate isolation structure 125 may include a substrate dielectric layer on a doped pad (such as a borosilicate glass pad and / or a phosphosilicate glass pad). The dimensions and / or characteristics of the substrate isolation structure 125 may be configured to provide a shallow trench isolation structure, a deep trench isolation structure, a localized silicon oxide structure, other suitable isolation structures, or a combination thereof.

[0024] As shown in Figures 4A and 4B, a gate structure 130 may be formed above the channel region C of the active region 122 and between the individual source / drain regions S / D of the active region 122. Each gate structure 130 may include an individual dummy gate stack 132 and an individual gate spacer 134. The dummy gate stack 132 extends in a direction different from (e.g., perpendicular to) the length direction of the multilayer stack 110. For example, the dummy gate stack 132 extends along the y-direction and has a length along the y-direction, a width along the x-direction, and a height along the z-direction. The extension directions of the dummy gate stack 132 may be substantially parallel to each other. In Figure 4A (a cross-sectional view along the gate width direction), the dummy gate stack 132 is located on top of the individual channel regions and between the individual source / drain regions. In a cross-sectional view along the length of the gate, the dummy gate stack 132 may cover individual channel regions (such as those located on the top and sidewalls of the channel regions), and the dummy gate stack 132 may be located on top of the substrate isolation structure 125.

[0025] The dummy gate stack 132 may each include a dummy gate 136 and a hard mask 138. In some embodiments, the dummy gate 136 includes a dummy gate dielectric layer and a dummy gate. The dummy gate dielectric layer includes a dielectric material, such as silicon oxide and / or other suitable dielectric materials. The dummy gate includes a suitable dummy gate material such as polysilicon. In some embodiments, the method of forming the dummy gate stack 132 includes depositing a dummy gate dielectric layer on the multilayer stack 110, depositing a dummy gate layer on the dummy gate dielectric layer, and depositing a hard mask layer on the dummy gate layer. Next, one or more photolithography and etching processes are performed to pattern the hard mask layer, the dummy gate layer, and the dummy gate dielectric layer. The remaining hard mask layer, dummy gate layer, and dummy gate dielectric layer can respectively form the dummy gate dielectric layer, dummy gate, and hard mask of the dummy gate stack 132, as shown in the figure.

[0026] Next, a gate spacer 134 is formed adjacent to the sidewall of the dummy gate stack 132. In some embodiments shown in FIG4B, a fin spacer 135 is formed adjacent to the sidewall of the multilayer stack 110. The gate spacer 134 and the fin spacer 135 can be formed by any suitable process. In some embodiments, the gate spacer 134 and the fin spacer 135 can be formed simultaneously. The gate spacer 134 and the fin spacer 135 comprise a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable dielectric compositions, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, silicon carbon oxynitride, silicon carbon oxynitride, or combinations thereof). In some embodiments, the gate spacer 134 and / or the fin spacer 135 have a multilayer structure, such as two or more dielectric layers with different compositions. In some embodiments, the gate spacer 134 includes more than one set of spacers such as sealing spacers, compensating spacers, sacrificial spacers, dummy spacers, primary spacers, or combinations thereof. In these embodiments, the multiple sets of spacers may have different compositions.

[0027] As shown in Figures 5A and 5B, the source / drain etching method removes portions of the uncovered multilayer stack 110 of the gate structure 130 to form a source / drain recess (trench) 140. For example, the source / drain etching method removes the semiconductor layer 120 and the sacrificial semiconductor layer 115 in the source / drain region to expose the mesa 105' in the source / drain region. The source / drain etching method may further remove some, but not all, of the mesa 105' in the source / drain region, so that the source / drain recess 140 extends into (but not through) the mesa 105'. After etching the source / drain, the sacrificial semiconductor layer 115, the semiconductor layer 120, and the protrusion formed from the mesa 105' (hereinafter referred to as mesa 105P') remain in the channel region, while the source / drain recess 140 exposes the sidewalls of the sacrificial semiconductor layer 115, the semiconductor layer 120, and the mesa 105P' retained in the channel region. The source / drain etching method is dry etching, wet etching, or a combination thereof. In some embodiments, the source / drain etching method is a multi-step etching process that may switch etchants to separately and interleave the etching of the sacrificial semiconductor layer 115 and the semiconductor layer 120. In some embodiments, the parameters of the etched source / drain (such as their etchant) are adjusted to selectively remove semiconductor materials (such as semiconductor layer 120, sacrificial semiconductor layer 115, and mesa 105') while negligibly or not etching dielectric materials (such as dummy gate stack 132, gate spacer 134, fin spacer 135, substrate isolation structure 125, and the like).

[0028] As shown in Figures 6A to 8A and Figures 6B to 8B, the sacrificial semiconductor layer 115 is replaced with a sacrificial oxide layer 146. As shown in Figures 6A and 6B, the etching process selectively removes the sacrificial semiconductor layer 115 exposed in the source / drain recess 140 to form gaps 144 in the channel region. The etching process can selectively remove the sacrificial semiconductor layer 115 relative to the substrate 105, semiconductor layer 120, dummy gate stack 132 (such as its hard mask 138), gate spacer 134, fin spacer 135, or a combination thereof. In other words, the etching process removes the sacrificial semiconductor layer 115 while negligibly or not removing the substrate 105, semiconductor layer 120, dummy gate stack 132 (such as its hard mask 138), gate spacer 134, fin spacer 135, or a combination thereof. In some embodiments, the etchant used in the etching process is selected to etch silicon-germanium (e.g., sacrificial semiconductor layer 115) at a higher rate and to etch or not etch silicon (e.g., semiconductor layer 120 and mesa 105') and dielectric materials (e.g., gate spacers 134, fin spacers 135, and hard mask 138 of dummy gate stack 132) at a lower rate. The etching process may be dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, an oxidation process may be performed during the etching process to convert the sacrificial semiconductor layer 115 into a semiconductor oxide layer (e.g., silicon-germanium oxide layer). In these embodiments, the etching process removes the semiconductor oxide layer to form gaps 144.

[0029] After the sacrificial semiconductor layer 115 is removed, the semiconductor layer 120 remains in the channel region and is suspended above the mesa 105P'. In the embodiment, each channel region has three suspended semiconductor layers 120, which can then be considered as channel layers 120'. The channel layers 120' are stacked vertically along the z-direction and provide three channels for current to pass through between the subsequently formed source / drain. In some embodiments, after the sacrificial semiconductor layer 115 is removed, an etching process can be performed to adjust the profile of the channel layers 120' to provide a target size and / or target shape for the channel layers 120'. For example, the etching process can provide a cylindrical profile (such as a nanowire), a rectangular cross-section (such as a nanorod), a sheet profile (such as a nanosheet), or any other suitable shape profile for the channel layers 120'. In some embodiments, the channel layers 120' have a nanometer-sized shape and can be considered as a nanostructure. In some embodiments, the channel layers 120' have sub-nanometer dimensions and / or other suitable dimensions.

[0030] As shown in Figures 7A, 7B, 8A, and 8B, a sacrificial oxide layer 146 is formed in the gap 144. The sacrificial oxide layer 146 includes oxygen and silicon, carbon, nitrogen, other suitable compositions, or combinations thereof. For example, the sacrificial oxide layer 146 includes oxygen and silicon, and the sacrificial oxide layer 146 is a silicon oxide layer. In some embodiments, the sacrificial oxide layer 146 is formed by depositing an oxide layer 146' on the device 100 (as shown in Figures 7A and 7B) and etching the oxide layer 146' to remove the oxide layer 146' from the source / drain region (rather than the channel region) of the device 100 (as shown in Figures 8A and 8B). As shown in Figures 7A and 7B, the deposited oxide layer 146' fills the gap 144, partially fills the source / drain recess 140, and pads the source / drain recess 140. The deposited oxide layer 146' may further be located on the gate structure 130, the substrate isolation structure 125, the fin spacer 135, other structures of the device 100, or combinations thereof. The oxide layer 146' is formed by flowable chemical vapor deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, other deposition processes, or combinations thereof. In some embodiments, the sacrificial oxide layer 146 has a multilayer structure, such as a first oxide layer and a second oxide layer. The first oxide layer and the second oxide layer may be composed of the same material (e.g., silicon oxide) formed by different deposition processes. For example, the first oxide layer is formed by atomic layer deposition, and the second oxide layer formed on the first oxide layer is formed by flowable chemical vapor deposition. In some embodiments, the first oxide layer and the second oxide layer are composed of the same type of deposition process or different oxide materials formed by different types of deposition processes.

[0031] As shown in Figures 8A and 8B, the etching process removes exposed portions of the oxide layer 146' (such as portions where gaps 144 are not filled). For example, the etching process may remove portions of the oxide layer 146' located on the sidewalls of the channel layer 120', the sidewalls of the mesa 105P', the surface of the mesa 105' (forming the bottom of the source / drain recess 140), the top and sidewalls of the fin spacers 135, the top and sidewalls of the gate spacers 134, the top of the dummy gate stack 132, and the top of the substrate isolation structure 125. The remaining oxide layer 146' may serve as a sacrificial oxide layer 146 in the channel region. The etching process may selectively remove the oxide layer 146' relative to the substrate 105, the channel layer 120', the dummy gate stack 132 (such as its hard mask 138), the gate spacers 134, the fin spacers 135, the substrate isolation structure 125, or a combination thereof. In other words, the etching process removes the oxide layer 146' while negligibly or not removing the substrate 105, channel layer 120', dummy gate stack 132, gate spacer 134, fin spacer 135, substrate isolation structure 125, or a combination thereof. In some embodiments, an etchant is selected to etch the oxide material (such as the oxide layer 146') at a higher rate and to etch or not etch silicon (such as the channel layer 120' and mesa 105') and dielectric materials different from the oxide material (such as the gate spacer 134, fin spacer 135, hard mask 138, or the like) at a lower rate. The etching process is dry etching, wet etching, other suitable etching, or a combination thereof.

[0032] As shown in Figures 9A and 9B, an etching process (such as an isotropic etching process) causes the sacrificial oxide layer 146 to be laterally recessed to form a recess 148 under the gate structure 130 (such as under its gate spacer 134). For example, the etching process may etch the sacrificial oxide layer 146 laterally (such as along the x-direction and / or y-direction) to reduce its length along the x-direction, such that the length of the sacrificial oxide layer 146 is less than the length of the channel layer 120'. The sacrificial oxide layer 146 may be removed from the end of the channel layer 120', thereby exposing the top and bottom of the end of the channel layer 120'. In some embodiments, the recess 148 extends laterally (such as along the x-direction) under the dummy gate stack 132. In some embodiments, the etching process may cause the substrate isolation structure 125 to be recessed. In these embodiments, the substrate isolation structure 125 may have an arcuate (such as recessed) upper surface. As shown in Figures 10A and 10B, inner spacers 149 are formed in recesses 148, and the remaining sacrificial oxide layers 146 are located between the individual inner spacers 149. The inner spacers 149 may replace the ends of the sacrificial oxide layers 146. The inner spacers 149 along the sidewalls of the sacrificial oxide layers 146 are located below the gate spacers 134. Furthermore, the inner spacers 149 are located between the ends of individual semiconductor layers 120, and the bottom inner spacers 149 are located between the ends of individual bottom semiconductor layers 120 and individual mesa 105P'. The inner spacers 149 can be formed by depositing inner spacers and etching inner spacers. The method of depositing inner spacers forms an inner spacer layer on the device 100 and at least partially fills the recesses 148. In some embodiments, a single deposition process is performed to form the inner spacer layer and fill the recesses 148. In some embodiments, the inner spacer 149 has a multilayer structure, and the method of depositing the inner spacer includes more than one deposition process to form multiple layers of inner spacer, such as a first deposition process to form a first inner spacer sublayer and a second deposition process to form a second inner spacer sublayer. The first inner spacer sublayer partially fills the recess 148, while the second inner spacer sublayer may partially or completely fill the recess 148. The composition of the first inner spacer sublayer may be the same as or different from the composition of the second inner spacer sublayer.

[0033] The method of etching the inner spacers may selectively etch the inner spacer layer while ignoring or not etching the channel layer 120', mesa 105P', dummy gate stack 132 (such as its hard mask 138), gate spacer 134, fin spacer 135, substrate isolation structure 125, or combinations thereof. The remaining inner spacer layer may provide inner spacers 149, as shown. To achieve the desired etching selectivity, the composition of the inner spacer layer (and inner spacers 149) may differ from the composition of the channel layer 120', mesa 105P', dummy gate stack 132, gate spacer 134, fin spacer 135, substrate isolation structure 125, or combinations thereof. In some embodiments, the dielectric material included in the inner spacer layer contains silicon, oxygen, carbon, nitrogen, other suitable dielectric compositions, or combinations thereof. For example, the inner spacer layer may be a silicon carbide layer, a silicon carbonitride layer, a silicon carbonitride layer, a silicon carbonitride layer, or a combination thereof. The method for etching the inner spacer may be dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, parameters for depositing and / or etching the inner spacer are set and / or adjusted to provide an inner spacer 149 with an air gap. In some embodiments, the device 100 does not include the inner spacer 149. In these embodiments, the processes associated with the device 100 of Figures 9A, 9B, 10A, and 10B may be omitted.

[0034] As shown in Figures 11A to 13A and Figures 11B to 13B, a source / drain structure 150 is formed in a source / drain recess 140. The source / drain structure 150 may each include an undoped semiconductor layer 152, an insulating layer 154, and a doped semiconductor layer 156. In some embodiments, the doped semiconductor layer 156 has a multilayer structure. For example, the doped semiconductor layer 156 may each include a doped semiconductor layer 158 and a doped semiconductor layer 160. In some embodiments, the source / drain structure 150 forms the source / drain of a p-type transistor, and the source / drain structure 150 may include semiconductor materials doped with p-type dopants such as boron, gallium, other p-type dopants, or combinations thereof. In some embodiments, the source / drain structure 150 forms the source / drain of an n-type transistor, and the source / drain structure 150 may include a semiconductor material doped with an n-type dopant such as carbon, phosphorus, arsenic, antimony, other n-type dopant, or a combination thereof. The terms source / drain, source / drain region, source / drain structure, epitaxial source / drain, epitaxial source / drain structure, or similar terms used herein can be considered as the source of device 100, the drain of device 100, or the source and / or drain of multiple devices (including device 100).

[0035] As shown in Figures 11A and 11B, a semiconductor layer, such as an undoped semiconductor layer 152, can be formed in the source / drain recess 140. The undoped semiconductor layer 152 can be formed in the bottom of the source / drain recess 140. The undoped semiconductor layer 152 is below the bottommost channel layer 120' (e.g., below the bottom of the bottommost channel layer 120'). In the embodiment, the undoped semiconductor layer 152 extends slightly above the upper surface of the mesa 105P'. In some embodiments, the upper surface of the undoped semiconductor layer 152 is substantially flush with or below the upper surface of the mesa 105P', i.e., the undoped semiconductor layer 152 does not extend beyond the upper surface of the mesa 105P'. The undoped semiconductor layer 152 is undoped and substantially free of n-type and p-type dopants. For example, doping is not intentionally performed when forming the undoped semiconductor layer 152. The undoped semiconductor layer 152 provides a high-resistance path at the bottom of the source / drain, thereby suppressing leakage current into the substrate 105 / mesa 105P'. The undoped semiconductor layer 152 includes silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In the described embodiment, the undoped semiconductor layer 152 is an undoped silicon-germanium layer. In some embodiments, the undoped semiconductor layer 152 is an undoped silicon layer. In some embodiments, the doping concentration of the semiconductor material, such as silicon-germanium, is less than about 5 x 10¹⁸ cm⁻³ (e.g., from about 1 x 10¹⁸ cm⁻³ to about 5 x 10¹⁸ cm⁻³), which can be considered undoped and / or unintentionally doped.

[0036] The undoped semiconductor layer 152 may be deposited on the substrate 105, mesas 105', mesas 105P', or a combination thereof, and / or grown from the substrate 105, mesas 105', mesas 105P', or a combination thereof. In some embodiments, the undoped semiconductor layer 152 is formed by a selective epitaxial growth process, which selectively deposits a semiconductor material (such as silicon-germanium) on an exposed semiconductor surface, or grows a semiconductor material from an exposed semiconductor surface. The undoped semiconductor layer 152 can therefore be considered as an undoped epitaxial layer. The selective epitaxial growth process may employ chemical vapor deposition techniques (such as vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar techniques), molecular beam epitaxy, other suitable epitaxial growth processes, or a combination thereof. In some embodiments, the undoped semiconductor layer 152 is formed by a bottom-up deposition process to deposit semiconductor material on the mesa 105P', mesa 105', and / or substrate 105 (i.e., in the bottom of the source / drain recess 140), while minimizing or eliminating the deposition of semiconductor material on the channel layer 120'. In some embodiments, an etching process may be performed after the bottom-up deposition process to remove any semiconductor material on the channel layer 120'. Post-deposition etching may be dry etching, wet etching, other suitable etching, or a combination thereof.

[0037] As shown in Figures 12A and 12B, an insulating layer 154 may be formed in the source / drain recess 140 on the undoped semiconductor layer 152. The insulating layer 154 partially fills the source / drain recess 140 and is lower than the bottommost channel layer 120' (e.g., lower than the bottom of the bottommost channel layer 120'). The insulating layer 154 may be located on the bottommost inner spacer 149 and / or mesa 105P', as shown. The insulating layer 154 includes an electrically insulating material such as a dielectric material, which can reduce undesirable leakage current, such as undesirable current flowing between the doped semiconductor layers 156 via the mesa 105P'. Taking Figure 26A as an example, the substrate leakage current of a device with a source / drain structure having a bottom source / drain insulating layer (such as insulating layer 154) (corresponding to line segments K1 and K2) is less than the substrate leakage current of a device without a bottom source / drain insulating layer (corresponding to line segments L1 and L2). Furthermore, as shown in Figure 26B, the capacitance of a device with a bottom source / drain insulating layer having a source / drain structure (corresponding to line segments O1 and O2) is less than the capacitance of a device without a bottom source / drain insulating layer (corresponding to line segments N1 and N2). In some embodiments, insulating layer 154 includes a silicon-containing dielectric material such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, other silicon-containing dielectric materials (which may include silicon and nitrogen, carbon, oxygen, other suitable dielectric compositions, or combinations thereof), or combinations thereof. For example, the insulating layer 154 in the embodiment is a silicon nitride layer. In some embodiments, the insulating layer 154 includes a metal-containing dielectric material, such as a metal oxide material and / or a metal nitride material.

[0038] The insulating layer 154 can be formed by depositing insulating material on the device 100 and etching the insulating material so that the remaining insulating material is located on the undoped semiconductor layer 152. The deposition method can be chemical vapor deposition, physical vapor deposition, other suitable processes, or a combination thereof. The deposited insulating material can be located on the top of the gate structure 130 (such as the top of the gate spacer 134 and the dummy gate stack 132), the sidewalls of the gate structure 130 (such as the sidewalls of the gate spacer 134), the sidewalls of the channel layer 120', the sidewalls of the inner spacer 149, and the sidewalls of the mesa 105P'. In some embodiments, the characteristics of the deposition process cause the thickness of the insulating material on horizontal surfaces (such as the top of the undoped semiconductor layer 152 and the top of the gate structure 130) to be greater than the thickness of the insulating material on vertical surfaces (such as the sidewalls of the gate structure 130, the sidewalls of the channel layer 120', and the sidewalls of the inner spacer 149). Therefore, etching parameters can be adjusted to remove vertical portions of the insulating material, such as the insulating material on the sidewalls of the gate structure 130, the channel layer 120', and the inner spacer 149. In these embodiments, the etching load effect causes the etching to also remove horizontal portions of the insulating material on the top of the gate structure 130 (i.e., the etching process can thin these portions), but without removing or with minimal removal of the horizontal and / or vertical portions of the insulating material in the bottom of the source / drain recess 140 (such as located on the undoped semiconductor layer 152). In some embodiments, the deposited insulating material fills the source / drain recess 140, and etching causes the insulating material to be recessed at least to the bottom sacrificial oxide layer 146. The etching may be dry etching, wet etching, other suitable etching, or a combination thereof.

[0039] As shown in Figures 13A and 13B, a doped semiconductor layer 156 may be formed in the source / drain recesses 140 on the insulating layer 154 and / or the undoped semiconductor layer 152. The doped semiconductor layer 156 may fill the remaining source / drain recesses 140, and the doped semiconductor layer 156 is coupled to the edge / end of the channel layer 120'. In the embodiment, the doped semiconductor layer 156 includes a doped semiconductor layer 158 and a doped semiconductor layer 160. The doped semiconductor layer 158 may be formed on the channel layer 120' and partially fill the source / drain recesses 140, while the doped semiconductor layer 160 may be formed on the doped semiconductor layer 158 and / or the insulating layer 154 and fill the remaining source / drain recesses 140. A doped semiconductor layer 158 is located between channel layer 120' and doped semiconductor layer 160, while an insulating layer 154 is located between doped semiconductor layer 160 and an undoped epitaxial layer, such as undoped semiconductor layer 152. In the embodiments described, the doped semiconductor layer 158 is discontinuous and consists of separate spacers, each of which is located at the end of an individual channel layer 120' (i.e., portions of the doped semiconductor layer 158 are located on adjacent channel layers 120' and are not connected to each other). In these embodiments, the doped semiconductor layer 160 may cover the doped semiconductor layer 158, and / or the doped semiconductor layer 160 may extend to and be located on the inner spacer 149. In some embodiments, the spacers of one or more separate doped semiconductor layers 158 may cover individual channel layers 120', such that the separate spacers are formed on the top and / or bottom of individual channel layers 120'. In some embodiments, the separate separating portions extend on and / or to the inner spacer 149. In some embodiments, the separating portions of the separate doped semiconductor layers 158 are connected. In these embodiments, a portion of the doped semiconductor layer 160 may be separated from the inner spacer 149 by the doped semiconductor layer 158. In some embodiments, the doped semiconductor layer 158 covers the doped semiconductor layer 160, and the doped semiconductor layer 158 is further located between the inner spacer 149 and the doped semiconductor layer 160.

[0040] The doped semiconductor layer 158 and the doped semiconductor layer 160 include silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, the doped semiconductor layer 158 and the doped semiconductor layer 160 include the same semiconductor material but with different concentrations. For example, the doped semiconductor layer 158 and the doped semiconductor layer 160 may include silicon-germanium and p-type dopants such as boron and / or gallium, but with different germanium concentrations and / or p-type dopant concentrations, as in the source / drain structure 150 belonging to a p-type transistor. In this example, the germanium concentration (e.g., germanium%) and / or p-type dopant concentration (e.g., boron%) of the doped semiconductor layer 158 may be less than the germanium concentration and / or p-type dopant concentration of the doped semiconductor layer 160. In other words, the doped semiconductor layer 160 may be a heavily doped semiconductor layer, while the doped semiconductor layer 158 may be a lightly doped semiconductor layer. In another example, the doped semiconductor layer 158 and the doped semiconductor layer 160 may include silicon and n-type dopants (such as phosphorus and / or arsenic), but the concentrations of the n-type dopants are different, as in the source / drain structure 150 belonging to an n-type transistor. In this example, the concentration of the n-type dopant (such as phosphorus%) in the doped semiconductor layer 158 is less than the concentration of the n-type dopant in the doped semiconductor layer 160. In some embodiments, the doped semiconductor layer 158 and the doped semiconductor layer 160 have different semiconductor materials having the same or different compositional concentrations. In some embodiments, the material and / or dopants included in the doped semiconductor layer 156 provide compressive stress in the channel layer 120', as in the source / drain structure 150 belonging to a p-type transistor. In some embodiments, the material and / or dopants included in the doped semiconductor layer 156 provide tensile stress in the channel layer 120', as in the source / drain structure 150 belonging to an n-type transistor.

[0041] The doped semiconductor layer 158 may be deposited on and / or grown from the channel layer 120', and the doped semiconductor layer 160 may be deposited on and / or grown from the doped semiconductor layer 158. In some embodiments, the doped semiconductor layer 158 and the doped semiconductor layer 160 are formed by individual selective epitaxial growth processes, which may implement chemical vapor deposition techniques (such as vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar techniques), molecular beam epitaxy, other suitable selective epitaxial growth processes, or combinations thereof. The selective epitaxial growth process may employ gaseous and / or liquid precursors, which interact with the channel layer 120', the doped semiconductor layer 158, or combinations thereof. Epitaxial growth / deposition conditions can be adjusted as described herein to selectively deposit (grow) semiconductor materials such as silicon and germanium on semiconductor surfaces (such as channel layer 120' and / or doped semiconductor layer 158), and to limit (or avoid) the growth of semiconductor materials on self-dielectric surfaces and / or non-semiconductor surfaces (such as inner spacers 149, dummy gate stacks 132, gate spacers 134, fin spacers 135, substrate isolation structures 125, or combinations thereof). In some embodiments, the doped semiconductor layer 158 and / or the doped semiconductor layer 160 are doped during deposition (i.e., in-situ doping), for example, by adding dopants to the material source of the selective epitaxial growth process. In some embodiments, the doped semiconductor layer 158 and / or the doped semiconductor layer 160 are doped after deposition using an ion implantation process. In some embodiments, annealing is performed to activate the doped semiconductor layer 158, the doped semiconductor layer 160, other source / drain structures such as source / drain junction implantation, or the dopants in combinations thereof. The method of fabricating the source / drain structure 150 can be configured to provide source / drain structures 150 of various sizes. For example, in some embodiments, the width (e.g., along the y-direction) of the source / drain structure 150 may differ from the thickness (e.g., along the z-direction) of the source / drain structure 150. In some embodiments, the doped semiconductor layer 160 may have this dimensional difference (e.g., its width may be greater than its thickness).

[0042] As shown in Figures 14A and 14B, a method of fabricating apparatus 100 may include forming a dielectric layer 170 over source / drain structures 150. The dielectric layer 170 may fill the space between adjacent gate structures 130, such as the space between their gate spacers and the space between adjacent source / drain structures 150. The method of forming dielectric layer 170 may include depositing a contact etch stop layer 172, depositing an interlayer dielectric layer 174 on the contact etch stop layer 172, and performing chemical mechanical polishing and / or other planarization processes until the dummy gate stack 132 (or its hard mask 138) is exposed. In some embodiments, the planarization process may partially remove the dummy gate stack 132, such as its hard mask 138, to expose the underlying dummy gate 136 (such as polysilicon). In some embodiments, the planarization process may reduce the height of the dummy gate stack 132 and / or the gate spacers 134.

[0043] The dielectric material included in the interlayer dielectric layer 174 may be silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane oxide, borosilicate glass, phosphosilicone glass, borosilicate phosphosilicone glass, fluorosilicone glass, degel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene-based dielectric material, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the interlayer dielectric layer 174 includes a dielectric material with a low dielectric constant, whose dielectric constant is less than that of silicon dioxide (e.g., dielectric constant less than 3.9). In some embodiments, the interlayer dielectric layer 174 comprises a dielectric material having a dielectric constant of less than about 2.5 (i.e., an extremely low dielectric constant), such as porous silicon oxide, silicon carbide, carbon-doped oxides (e.g., silicon hydroxide-based materials, such as those with silicon-methyl bonds), or combinations thereof, each adjusted / set to have a dielectric constant of less than about 2.5. The contact etch stop layer 172 comprises a material different from the material of the interlayer dielectric layer 174, such as a dielectric material different from the dielectric material of the interlayer dielectric layer 174. For example, when the interlayer dielectric layer 174 comprises a low dielectric constant dielectric material containing silicon and oxygen, the contact etch stop layer 172 may comprise silicon and nitrogen, such as silicon nitride or silicon oxynitride. The interlayer dielectric layer 174 and / or the contact etch stop layer 172 may have a multilayer structure and / or comprise a variety of dielectric materials.

[0044] As shown in Figures 15A to 17A and Figures 15B to 17B, the fabrication method of device 100 may include a gate replacement process that replaces the dummy gate stack 132 and the sacrificial oxide layer 146 to form a gate stack 180. The gate stack 180 (which can also be considered as a high-dielectric-constant dielectric layer and a metal gate) is located between individual gate spacers 134, between individual inner spacers 149, between individual channel layers 120', and between individual channel layers 120' and individual mesa 105P'. Each gate stack 180 may include an individual gate dielectric layer 182 and an individual gate 184. In the embodiment described, device 100 includes a fully wound gate transistor, and the gate stack 180 may surround and connect individual channel layers 120' (e.g., in the YZ plane, see Figure 17C). In some embodiments, the gate stack 180 may cover and / or partially surround the individual channel layer 120' (i.e., located on at least both sides of the channel layer 120').

[0045] As shown in Figures 15A and 15B, a dummy gate stack 132 is removed from the gate structure 130 to form a gate opening 175. The gate opening 175 exposes a channel region, which includes a channel layer 120' and a sacrificial oxide layer 146. In some embodiments, the etching process selectively removes the dummy gate stack 132 (e.g., a polysilicon gate) while negligibly removing or not removing the dielectric layer 170, gate spacer 134, inner spacer 149, sacrificial oxide layer 146, semiconductor layer 120, channel layer 120', or a combination thereof. The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, the etching process uses a patterned mask layer as an etching mask, and the patterned mask layer covers the dielectric layer 170 and / or the gate spacer 134. In some embodiments, the dummy gate dielectric layer (e.g., the dummy oxide layer) of the dummy gate stack 132 is retained.

[0046] As shown in Figures 16A and 16B, the sacrificial oxide layer 146 is removed from the channel region, thereby forming a gap 178 (opening) to expose the channel layer 120'. The gate opening 175 thus extends between the channel layers 120' and between the channel layers 120' and the mesa 105P'. In some embodiments, the etching process may selectively remove the sacrificial oxide layer 146 with respect to the mesa 105P', the channel layer 120', the gate spacer 134, the inner spacer 149, the dielectric layer 170, or a combination thereof. In other words, the etching process removes the sacrificial oxide layer 146 while negligibly or not removing the mesa 105P', the channel layer 120', the gate spacer 134, the inner spacer 149, the dielectric layer 170, or a combination thereof. For example, the etchant used in the etching process is selected to etch oxide materials (such as sacrificial oxide layer 146) at a higher rate and to etch or not etch silicon (such as channel layer 120' and mesa 105P') and dielectric materials with compositions different from oxide materials (such as gate spacer 134, inner spacer 149, contact etch stop layer 172, interlayer dielectric layer 174, and the like) at a lower rate, i.e., the etchant has high selectivity for etching oxide materials. The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the etching process removes any residual dummy gate stack 132, such as its dummy oxide layer.

[0047] As shown in Figures 17A to 17C, a gate stack 180 is formed in the gate opening 175 and / or gap 178. For example, a gate dielectric layer 182 is formed in and partially fills the gate opening 175 and gap 178. The gate dielectric layer 182 is located on individual channel layers 120', individual inner spacers 149, individual gate spacers 134, substrate isolation structure 125, or combinations thereof. The gate dielectric layer 182 includes at least one dielectric layer, such as an interface layer and / or a high dielectric constant dielectric layer. The interface layer includes dielectric materials such as silicon oxide, germanium silicon oxide, hafnium silicon oxide, silicon oxynitride, other dielectric materials, or combinations thereof. The interface layer can be formed by thermal oxidation, chemical oxidation, atomic layer deposition, chemical vapor deposition, other processes, or combinations thereof. High dielectric constant dielectric layers include dielectric materials with high dielectric constants, which can generally be considered as dielectric materials with a dielectric constant greater than that of silicon oxide, such as hafnium oxide, hafnium silicon oxide, hafnium silicate, hafnium silicon oxynitride, hafnium lanthanum oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium aluminum oxide, zirconium oxide, zirconium dioxide, zirconium silicate, aluminum oxide, aluminum silicate, aluminum oxide, titanium oxide, titanium dioxide, lanthanum oxide, lanthanum silicon oxide, lanthanum trioxide, lanthanum trioxide, tantalum trioxide, tantalum pentoxide, yttrium oxide, strontium titanate, barium zirconium oxide, barium titanate, barium strontium titanate, hafnium oxide-aluminum oxide, other high dielectric constant dielectric materials, or combinations thereof. Methods for forming a high-dielectric-constant dielectric layer may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, oxide-based deposition processes, other processes, or combinations thereof. In some embodiments, the high-dielectric-constant dielectric layer comprises a hafnium-based oxide such as a hafnium oxide layer. In some embodiments, the high-dielectric-constant dielectric layer comprises a zirconium-based oxide such as a zirconium oxide layer.

[0048] A gate 184 is formed in and fills the gate opening 175 and the gap 178. The gate 184 is located on the gate dielectric layer 182. The gate 184 includes a conductive layer composed of a conductive material such as aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, tantalum nitride, nickel silicate, cobalt silicate, titanium nitride, tungsten nitride, titanium aluminum, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, tantalum silicon nitride, other conductive materials, or combinations thereof. In some embodiments, the conductive layer includes a work function layer that can be adjusted to have a desired work function (such as an n-type work function or a p-type work function). The work function layer includes a work function metal and / or its alloy, such as titanium, tantalum, aluminum, silver, manganese, zirconium, tungsten, ruthenium, molybdenum, titanium carbide, titanium aluminum, titanium aluminum carbide, titanium aluminum carbide silicon, tantalum carbide, tantalum carbonitride, tantalum nitride silicon, titanium silicon nitride, titanium nitride, tantalum nitride, tantalum nitride silicon, tungsten nitride, tungsten carbonitride, zirconium silicate, molybdenum silicate, tantalum silicate, nickel silicate, tantalum aluminum, tantalum aluminum carbide, tantalum aluminum carbide silicon, titanium aluminum nitride, or combinations thereof. In some embodiments, the conductive layer includes a substrate layer located on the gate dielectric layer and / or the work function layer. The substrate layer may include aluminum, tungsten, copper, titanium, tantalum, titanium nitride, tantalum nitride, polycrystalline silicon, other suitable metals and / or their alloys, or combinations thereof. In some embodiments, the conductive layer includes a barrier layer located on the work function layer and / or the gate dielectric layer. The barrier layer comprises materials that prevent compositional diffusion and / or reaction between adjacent layers, such as the work function layer and the substrate layer, and / or promote adhesion between adjacent layers, such as the work function layer and the substrate layer. In some embodiments, the barrier layer comprises a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides, or combinations thereof.

[0049] The method of forming the gate stack 180 may include depositing a gate dielectric material (such as an interface layer, a high dielectric constant dielectric layer, and the like) to partially fill the gate openings 175 and / or gaps 178, depositing a gate material (such as a work function layer, a barrier layer, a substrate layer, and the like) on the gate dielectric material to fill the remaining gate openings 175 and / or gaps 178, and performing a planarization process to remove portions of the gate dielectric material and / or the gate material on the dielectric layer 170. In some embodiments, the method of fabricating the apparatus 100 may further include etching back the gate stack 180 and forming a hard mask (such as a self-aligned cap structure) on the etched-back gate stack 180. The self-aligned cap structure comprises a material different from the material of the dielectric layer 170 and / or the subsequently formed dielectric layer to achieve etch selectivity. In some embodiments, the self-aligning cap structure comprises silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, other silicon nitrides, other silicon carbides, or combinations thereof. In some embodiments, the self-aligning cap structure comprises metal and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, hafnium oxide, aluminum zirconium oxide, other metal oxides, other metal nitrides, or combinations thereof.

[0050] The device 100 may therefore include at least one transistor T. The transistor T may include individual channels (such as channel layer 120'), source / drain electrodes (such as source / drain structure 150), and individual gates (such as gate stack 180). The gate stack 180 is located along the x-direction between the individual source / drain electrodes (such as source / drain structure 150), and an inner spacer 149 is located between the gate stack 180 and the individual source / drain electrodes. Furthermore, the gate stack 180 connects to the individual channels (such as channel layer 120'), and the individual channels extend along the x-direction between the individual source / drain electrodes (such as source / drain structure 150). In the embodiment described, the transistor T is a fully wound gate transistor. The gate stack 180 may therefore surround individual channel layers, and the gate stack 180 may include a gate dielectric layer (such as gate dielectric layer 182) and a gate (such as gate 184) along the gate length direction to surround individual channels. In some embodiments, the gate stack 180 may cover and / or partially surround its individual channel layer (i.e., located on at least both sides of the channel layer), such as when the transistor T is a forked transistor or other type of multi-gate transistor.

[0051] In the embodiment described, the transistor T is a p-type transistor. For example, the transistor T may include a silicon channel (e.g., channel layer 120' may be a silicon layer) and epitaxial source / drain of silicon and germanium (e.g., doped semiconductor layer 156 may be a silicon-germanium structure). Because the transistor T is fabricated using a one-time / dummy oxide interposer (e.g., sacrificial oxide layer 146), the stress characteristics of the source / drain structure 150 are improved and / or the performance of the transistor T is improved. For example, because the sacrificial semiconductor layer 115 is replaced with the sacrificial oxide layer 146 before fabricating the source / drain, the composition of the dummy interposer (e.g., sacrificial semiconductor layer 115) will not migrate to the channel layer 120' during the fabrication of the source / drain structure 150, such as germanium migration that occurs during the thermal processes associated with this fabrication. Reducing and / or preventing the migration of components such as germanium from the dummy interposer can prevent undesirable changes in the stress characteristics of the channel layer 120' (e.g., undesirably introducing tensile stress into the channel layer 120' under compressive stress, negatively impacting the performance of the p-type transistor). The performance of p-type transistors such as transistor T fabricated according to the disclosed methods (e.g., implementing the sacrificial oxide layer 146) is improved, for example, by lower channel resistance and / or improved stress characteristics (e.g., minimized or no tensile stress). In some examples, p-type transistors fabricated here (i.e., using a dummy oxide interposer) may have lower leakage current, lower parasitic capacitance, lower bottom source / drain insulation R0 penalty, or a combination thereof, compared to p-type transistors fabricated using a dummy semiconductor (e.g., silicon-germanium) interposer and having a bottom source / drain insulation layer.

[0052] As shown in Figures 18A and 18B, a method of fabricating the apparatus 100 may include forming one or more front-side upper source / drain contacts, such as source / drain contacts 190. In some embodiments, forming the source / drain contacts 190 includes forming source / drain contact openings in the dielectric layer 170 to expose individual source / drain structures 150, depositing at least one conductive material (such as a metal substrate material) on the dielectric layer 170 and filling the source / drain contact openings, and performing a planarization process to remove any conductive material located on top of the dielectric layer 170 and / or on top of the gate structure 130. The planarization process may be performed until the gate stack 180, or a self-aligned cap structure on the etch-back gate stack 180 in some embodiments, is exposed. The remaining conductive material forms a metal plug and, in some embodiments, may form one or more lines of the source / drain contacts 190. Conductive materials include tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, a silicide layer is formed on the doped semiconductor layer 160 prior to the deposition of the conductive material. In some embodiments, the conductivity of the silicide layer (which may be considered as a front or top silicide layer) is greater than the conductivity of the doped semiconductor layer 160 and less than the conductivity of the source / drain contact 200.

[0053] The method of manufacturing device 100 may further include a front-side back-end process to form a metallization layer for a front-side multilayer interconnect structure. The front-side multilayer interconnect structure can electrically connect devices (such as transistors T, resistors, capacitors, inductors, or the like), device components (such as gates and / or source / drains), devices in the front-side multilayer interconnect structure, components of the front-side multilayer interconnect structure, or combinations thereof, so that the device and / or its components can operate according to the specifications required by the design. The metallization layer can route signals between the device and / or its components, and / or transmit signals (such as clock signals, voltage signals, ground signals, other signals, or combinations thereof) to the device and / or its components. In some embodiments, the metallization layer includes at least one interconnect structure located in the insulating layer, such as a via (e.g., source / drain via 192) and a conductive line (e.g., metal line 194) located in the dielectric layer (e.g., contact etch stop layer 195, interlayer dielectric layer 196, contact etch stop layer 197, and interlayer dielectric layer 198), wherein the via (e.g., source / drain via 192) connects the conductive line (e.g., metal line 194) to the interconnect of the underlying device layer (e.g., source / drain contact 190) or the metal line of the interconnect in different metallization layers.

[0054] In some embodiments, the method of forming the source / drain via 192 includes forming a dielectric layer (such as a contact etch stop layer 195 and an interlayer dielectric layer 196, whose arrangement and formation methods are similar to those of the contact etch stop layer 172 and the interlayer dielectric layer 174) on a dielectric layer 170, forming a source / drain via opening in the dielectric layer to expose the source / drain contact 190, depositing at least one conductive material (such as a metal substrate material) on the dielectric layer and filling the source / drain via opening, and performing a planarization process to remove any conductive material located on top of the dielectric layer. The planarization process may be performed until the interlayer dielectric layer 196 is exposed. The remaining conductive material may form a metal plug, and in some embodiments may form one or more lines of the source / drain via 192. In some embodiments, the method of forming the metal line 194 includes forming a dielectric layer (such as a contact etch stop layer 197 and an interlayer dielectric layer 198, whose arrangement and formation methods are similar to those of the contact etch stop layer 195 and the interlayer dielectric layer 196, respectively) on the interlayer dielectric layer 196, patterning the dielectric layer to form openings therein (such as exposing the openings of the source / drain via 192), depositing at least one conductive material (such as a metal substrate material) on the dielectric layer and filling the openings, and performing a planarization process to remove any conductive material located on top of the dielectric layer. The planarization process may be performed until the interlayer dielectric layer 198 is exposed. The remaining conductive material forms a metal plug and, in some embodiments, forms one or more lines of the metal line 194. The conductive materials for the source / drain via 192 and / or metal line 194 include tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, the source / drain via 192 and metal line 194 are formed using a dual damascene process. In these embodiments, before forming the source / drain via openings, a contact etch stop layer 197 and an interlayer dielectric layer 198 may be formed on the interlayer dielectric layer 196, exposing the source / drain via openings, and the conductive materials used for the source / drain via 192 and metal line 194 may be deposited simultaneously.

[0055] The metal lines of the first metallization layer (e.g., metal line 194) can be collectively considered as the first metal layer M1, and can also be individually considered as metal lines of the first metal layer M1. The vias of the first metallization layer (e.g., source / drain via 192) can physically and / or electrically connect the contacts of the local device layer (e.g., source / drain contact 190) to the metal lines (e.g., metal line 194). In these embodiments, the vias of the first metallization layer can be collectively considered as the zeroth via layer V0 (and can be independently considered as vias of the zeroth via layer V0). In these embodiments, the zeroth via layer V0 can be the bottommost via layer of the front multilayer interconnect structure. An additional metal layer of the front multilayer interconnect structure can be formed on the first metallization layer. For example, the back-end process may include forming a second metallization layer (i.e., the second metal layer M2 and the first via layer V1), a third metallization layer (i.e., the third metal layer M3 and the second via layer V2), a fourth metallization layer (i.e., the fourth metal layer M4 and the third via layer V3), a fifth metallization layer (i.e., the fifth metal layer M5 and the fourth via layer V4), a sixth metallization layer (i.e., the sixth metal layer M6 and the fifth via layer V5), a seventh metallization layer (i.e., the seventh metal layer M7 and the sixth via layer V6), up to the Xth metallization layer (i.e., the Xth metal layer MX and the Yth via layer VY, where X is the total number of patterned metal lines in the multilayer interconnect structure, and Y is the total number of patterned via layers in the multilayer interconnect structure) on the first metallization layer. Each metallization layer may each include a patterned metal line layer and a patterned via layer, configured to provide at least one back-end interconnect structure in the insulating layer. The front interconnect structure may have any number of metal layers, via layers, dielectric layers, or combinations thereof, depending on design requirements. In some embodiments, the metal layers, via layers, dielectric layers, or combinations thereof may be configured in various sizes, depending on design requirements. For example, in some embodiments, the thickness of the interlayer dielectric layer 196 (which may be the bottom interlayer dielectric layer of the front multilayer interconnect structure and / or its first metallization layer) is greater than the thickness of the interlayer dielectric layer 198 (and / or other interlayer dielectric layers in the metallization layers on the interlayer dielectric layer 196).

[0056] As shown in Figures 19A and 19B, a method of fabricating device 100 may include forming one or more back-side lower-side source / drain contacts, such as source / drain contacts 200. In some embodiments, the method of forming source / drain contacts 200 includes forming source / drain contact openings to expose individual doped semiconductor layers 156 of individual source / drain structures 150 (i.e., removing undoped semiconductor layers 152 and insulating layers 154 when forming source / drain contact openings), depositing at least one conductive material (such as a metal substrate material) on the back side of device 100 to fill the source / drain contact openings, and performing a planarization process to remove any conductive material on the back side of device 100 (which may be formed by substrate 105, or by a dielectric structure that replaces a portion of substrate 105 before forming source / drain contact openings). The remaining portion of the conductive material forms a metal plug, along with one or more lines of the source / drain contacts 200 in some embodiments. Conductive materials include tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, a silicide layer is formed on the doped semiconductor layer 160 prior to the deposition of the conductive material. In some embodiments, the conductivity of the silicide layer (which may be considered as a backside or bottom silicide layer) is greater than the conductivity of the doped semiconductor layer 160 and less than the conductivity of the source / drain contact 200. In some embodiments, the insulating layer 154 of the individual source / drain structure 150 serves as an etch stop layer when forming the source / drain contact opening. In some embodiments, the source / drain contact 200 extends through the undoped semiconductor layer 152 and the insulating layer 154 of the individual source / drain structure. In some embodiments, since the source / drain contact openings can be formed by removing the undoped semiconductor layer 152 and / or insulating layer 154, the source / drain contact 200 is self-aligned with the source / drain structure 150 (such as its doped semiconductor layer 160). In other words, no separate patterning process is required to define the source / drain contact openings. In some embodiments, the method of forming the source / drain contact 200 includes a flipping device 100 for back-side processing. In some embodiments, at least a portion of the substrate 105 is replaced with a dielectric structure such that the source / drain contact 200 is located in and / or extends through the dielectric structure. In some embodiments, the method of forming the source / drain contact 200 includes thinning the substrate 105, such as reducing the thickness of the substrate 105 and exposing the back side of the source / drain structure 150.

[0057] The apparatus 100 made according to the methods described herein can be implemented in various variations. In some embodiments shown in Figures 20 to 22, the source / drain recess 140 may have sloping sidewalls, which can vary the dimensions of the channel layer 120', the inner spacer 149, the gate stack 180, or combinations thereof. In Figure 20, the source / drain recess 140 is formed in conjunction with the description above in conjunction with Figures 5A and 5B, having sloping sidewalls as shown in Figure 20 rather than substantially straight sidewalls. In this way, the source / drain recess 140 has a tapered width (reduced from top to bottom), while the length (along the x-direction) of the semiconductor layer 120 and the sacrificial semiconductor layer 115 retained in the channel region increases from the gate structure 130 to the mesa 105P'. For example, the length of the topmost semiconductor layer 120 is less than the length of the middle semiconductor layer 120, and the length of the middle semiconductor layer 120 is less than the length of the bottommost semiconductor layer 120 (i.e., the length of the semiconductor layer 120 increases from the top to the bottom of the multilayer stack). Furthermore, the length of the topmost sacrificial semiconductor layer 115 is less than the length of the middle sacrificial semiconductor layer 115, and the length of the middle sacrificial semiconductor layer 115 is less than the length of the bottom sacrificial semiconductor layer 115. This difference in the length of the sacrificial semiconductor layers 115 may result in different widths of the inner spacers 149 (e.g., along the x-direction) and / or different lengths of the sacrificial oxide layers 146 (as shown in Figure 21), corresponding to the fabrication stages illustrated in Figures 10A and 10B. In Figure 21, the width of the topmost inner spacer 149 is less than the width of the middle inner spacer 149, and the width of the middle inner spacer 149 is less than the width of the bottom inner spacer 149 (i.e., the width of the inner spacers 149 increases from top to bottom). In some embodiments, the width of the topmost inner spacer 149 is about 3.5 nm to about 4 nm, while the width of the bottommost inner spacer 149 is about 4 nm to about 4.5 nm. Furthermore, the length of the topmost sacrificial oxide layer 146 is less than the length of the middle sacrificial oxide layer 146, and the length of the middle sacrificial oxide layer 146 is less than the length of the bottommost sacrificial oxide layer 146 (i.e., the length of the sacrificial oxide layer 146 increases from top to bottom). This difference in the length of the sacrificial oxide layers 146 may cause portions of the gate stack 180 between the inner spacers 149 to have different widths (along the x-direction) as shown in FIG22, corresponding to the fabrication stages illustrated in conjunction with FIGS. 17A to 17C. For example, the width of the gate stack portion between the topmost inner spacers 149 is less than the width of the gate stack portion between the middle inner spacers 149, and the width of the gate stack portion between the middle inner spacers 149 is less than the width of the gate stack portion between the bottommost inner spacers 149. Figures 20 to 22 are illustrated herein for ease of understanding. Figures 20 to 22 have been simplified for clarity, to facilitate understanding of the inventive concept of the embodiments of the present invention.Additional structures may be added to device 100, and other embodiments of device 100 may replace, adjust, or omit some of the following structures.

[0058] As shown in some embodiments of FIG. 23, FIG. 24, FIG. 25A, and FIG. 25B, after the formation of the undoped semiconductor layer 152 and before the formation of the doped semiconductor layer 156 (and the insulating layer 154 in some embodiments), the method of fabricating the apparatus 100 may include performing an etching process (such as anisotropic etching) to laterally recess the channel layer 120'. For example, the etching process may laterally (e.g., along the x-direction) etch the channel layer 120' to reduce its length along the x-direction (FIG. 23), thereby reducing the distance between the subsequently formed gate stack 180 and the doped semiconductor layer 156 (FIG. 24) to improve the performance of the transistor T. In this example, the length of the channel layer 120' is greater than the length of the sacrificial oxide layer 146 and / or greater than the width of the dummy gate stack 132, but less than the sum of the given length of the sacrificial oxide layer 146 and the total width of the inner spacer 149 (in which the sacrificial oxide layer 146 is located), such that the inner spacer 149 extends beyond the channel layer 120', as shown in FIG23. In some embodiments, the etching process may recess and / or thin the undoped semiconductor layer 152. In these embodiments, the top of the undoped semiconductor layer 152 may be lower than the mesa 105P' in the other device / circuit region, and / or the thickness of the undoped semiconductor layer 152 may be less than the thickness of the undoped semiconductor layer 152 in the other device / circuit region. In these embodiments, the bottom of the insulating layer 154 may be lower than the bottom of the insulating layer 154 in the other device / circuit region. In some embodiments, device 100 may include transistors of a laterally recessed channel layer 120' (such as p-type transistors forming part of a logic region / circuit), as shown in FIG24, FIG25A (top device), FIG25B (top device), or combinations thereof; and transistors of a non-laterally recessed channel layer 120' (such as p-type transistors forming part of a memory region / circuit, or n-type transistors forming part of a logic region or memory region), as shown in FIG17A, FIG25A (bottom device), FIG25B (bottom device), or combinations thereof. In some embodiments, the length l1 of the laterally recessed channel layer 120' (as shown in FIG24 and / or FIG25A, the top device) may be about 20 nm to about 22 nm, while the length l2 of the non-laterally recessed channel layer 120' (as shown in FIG17A and / or FIG25A, the bottom device) may be about 25 nm to about 27 nm. In some embodiments, in a transistor having a laterally recessed channel layer 120' (as shown in the top device of FIG. 24 and / or FIG. 25B), the top of the undoped semiconductor layer 152 is about 4 nm to about 5 nm lower than the top of the mesa 105P' (e.g., distance d1), while in a transistor having a non-recessed channel layer 120' (as shown in FIG. 17A and / or FIG. 25B), the top of the undoped semiconductor layer 152 is about 0 nm to about 2 nm higher than the top of the mesa 105P' (e.g., distance d2).In some embodiments, the thickness of the undoped semiconductor layer 152 of the transistor having a laterally recessed channel layer 120' (as shown in the top device of FIG. 24 and / or FIG. 25) may be less than the thickness of the undoped semiconductor layer 152 of the transistor having a non-recessed channel layer 120' (as shown in the bottom device of FIG. 17A and / or FIG. 25B). In some embodiments, the transistor T is a p-type transistor, and the device 100 further includes an n-type transistor (which may form part of a logic region / circuit or a memory region / circuit), the channel layer length of the n-type transistor may be about 25 nm to about 27 nm (as shown in the bottom device of FIG. 25A and / or FIG. 25B), and the top of the undoped semiconductor layer of the source / drain structure of the n-type transistor may be about 0 nm to about 2 nm higher than the top of its mesa (as shown in the bottom device of FIG. 25A and / or FIG. 25B). FIG. 23, FIG. 24, FIG. 25A, and FIG. 25B are described herein for ease of understanding. Figures 23, 24, 25A, and 25B can be simplified to make the diagrams clearer and facilitate understanding of the concepts of the embodiments of the present invention. Additional structures can be added, and some of the following structures can be replaced, adjusted, or omitted.

[0059] Variables during the manufacturing process cause the bottom source / drain insulating layer (such as insulating layer 154) to have various profiles and / or dimensions. In some embodiments, exemplified by Figures 12A and 12B, insulating layer 154 has a protruding upper surface. In some embodiments, exemplified by Figure 27, insulating layer 154 has a recessed upper surface. In some embodiments, insulating layer 154 has a substantially uniform thickness along the z-direction. For example, the thickness of the central portion of insulating layer 154 may be substantially equal to the thickness of the edge portion (also considered as the corner portion) of insulating layer 154. In some embodiments, the thickness is about 3 nm to about 5 nm. In some embodiments, insulating layer 154 has a thickness variation. As exemplified by Figure 27, the left edge / corner of insulating layer 154 has a thickness E1, the right edge / corner has a thickness E2, and the middle has a thickness C1, and the thicknesses E1, E2, and C1 may be different. In some embodiments, thickness E1 is about 3 nm to about 5 nm, thickness E2 is about 3 nm to about 5 nm, and thickness C1 is about 3 nm to about 5 nm. In some embodiments, thickness C1 is greater than thickness E1 and thickness E2. In some embodiments, thickness C1 is less than thickness E1 and thickness E2. In some embodiments, thickness C1 is greater than thickness E2 and less than thickness E1. In some embodiments, thickness C1 is less than thickness E2 and greater than thickness E1. In some embodiments, thickness E1 is greater than thickness E2. In some embodiments, thickness E2 is greater than thickness E1. In some embodiments, the thickness of insulating layer 154 decreases from left to right, i.e., thickness E1 is greater than thickness C1, and thickness is greater than E2. In some embodiments, the thickness variation of insulating layer 154 depends on the dimensions (e.g., width and / or length) of channel layer 120'. For example, the thickness of insulating layer 154 decreases as channel width increases. In some embodiments, the thickness of insulating layer 154 of a first device having a first channel width (e.g., center thickness of about 4 nm to about 5 nm, and corner thickness of about 3 nm to about 6 nm) may be greater than the thickness of insulating layer 154 of a second device having a second channel width (e.g., center thickness of about 4 nm to about 4.5 nm, and corner thickness of about 2.5 nm to about 4.5 nm), and the second channel width is greater than the first width. The thickness of the insulating layer 154 of the second device having a second channel width may be greater than the thickness of the insulating layer 154 of the third device having a third channel width (e.g., a center thickness of approximately 3 nm to approximately 4 nm and a corner thickness of approximately 2 nm to approximately 3.5 nm), and the third channel width is greater than the second channel width. In another example, the thickness variation of the insulating layer 154 (e.g., the difference between the center thickness and the edge / corner thickness of the insulating layer) may decrease as the channel width increases. In some embodiments, the thickness variation of the insulating layer 154 depends on the contact polysilicon gate spacing (i.e., the distance between adjacent gates such as gate structure 130).For example, the thickness variation of the insulating layer 154 (such as the difference between the thickness at the center and the corners of the insulating layer) may increase with the increase of the contact polysilicon gate spacing. In some embodiments, the thickness of the channel layer 120' along the z-direction is about 5 nm to about 6 nm. In some embodiments, the thickness of the sacrificial oxide layer 146 along the z-direction is greater than the thickness of the channel layer 120'. For example, the thickness of the sacrificial oxide layer 146 in the embodiment is greater than the thickness of the channel layer 120'. In some embodiments, the thickness of the sacrificial oxide layer 146 is about 6 nm to about 7 nm.

[0060] This invention provides many different embodiments. A method for fabricating a multi-gate transistor employing a dummy oxide interposer is disclosed herein. An exemplary method for forming a semiconductor device structure includes forming a multilayer stack on a protrusion, the multilayer stack including a plurality of first semiconductor layers and a plurality of first sacrificial layers, the first sacrificial layers having a first composition. A portion of the first semiconductor layer, the first sacrificial layer, and the protrusion is removed from a source / drain region to form a source / drain recess, and a source / drain structure is formed in the source / drain recess. The source / drain structure includes a second semiconductor layer and an insulating layer, wherein the insulating layer is located between the second semiconductor layer and the protrusion. Before forming the source / drain structure, the first sacrificial layer is replaced with a plurality of second sacrificial layers, the second composition of which differs from the first composition. After forming the source / drain structure, the second sacrificial layer is removed from a channel region to form a portion of a gate opening; and a gate stack is formed in the portion of the gate opening.

[0061] In some embodiments, the method further includes replacing the ends of the second sacrificial layer into a plurality of inner spacers before forming the source / drain structure. In some embodiments, the method further includes forming a front source / drain contact to the source / drain structure. In some embodiments, the method further includes forming a back source / drain contact to the source / drain structure.

[0062] In some embodiments, the first semiconductor layer is composed of a first semiconductor material, the first sacrificial layer is composed of a second semiconductor material, and the second sacrificial layer is composed of a dielectric material. In some embodiments, the first semiconductor material is silicon, the second semiconductor material is silicon germanium, and the dielectric material is silicon oxide. In some embodiments, the insulating layer is a silicon nitride layer.

[0063] In some embodiments, the source / drain structure further includes a third semiconductor layer located between the insulating layer and the protrusion. The second semiconductor layer is a doped semiconductor layer, while the third semiconductor layer is an undoped semiconductor layer. In some embodiments, the method further includes laterally recessing the first semiconductor layer after forming the third semiconductor layer and before forming the insulating layer and the second semiconductor layer. In some embodiments, the step of laterally recessing the first semiconductor layer reduces the thickness of the third semiconductor layer.

[0064] Another exemplary method for forming a semiconductor device structure includes forming a multilayer stack comprising a plurality of semiconductor layers, a plurality of sacrificial semiconductor layers, and a substrate extension. The method further includes removing a portion of the semiconductor layers, sacrificial semiconductor layers, and substrate extension in a source / drain region to form a source / drain recess; and forming a source / drain structure in the source / drain recess. The method for forming the source / drain structure may include forming an undoped semiconductor layer on the substrate extension to partially fill the source / drain recess; forming an insulating layer on the undoped semiconductor layer to partially fill the source / drain recess; and forming a doped semiconductor layer on the insulating layer to fill the remaining source / drain recess. The method further includes replacing the sacrificial semiconductor layer in the channel region with a plurality of sacrificial oxide layers before forming the source / drain structure in the source / drain recess. The method further includes replacing the sacrificial oxide layer in the channel region with a gate stack after forming the source / drain structure in the source / drain recess.

[0065] In some embodiments, the method further includes, before forming the source / drain structure in the source / drain recess, laterally recessing the sacrificial oxide layer to form a plurality of inner spacer recesses; and forming a plurality of inner spacers in the inner spacer recesses. In some embodiments, the method further includes, before forming the source / drain recess, forming a gate structure on a multilayer stack in the channel region. The gate structure may include a dummy gate and a plurality of gate spacers. In these embodiments, the method further includes, after forming the source / drain structure and before replacing the sacrificial oxide layer to form a gate stack, removing the dummy gate to form a gate opening. The gate stack fills the gate opening.

[0066] In some embodiments, the step of forming the insulating layer includes forming a nitrogen-containing dielectric layer on the undoped semiconductor layer. In some embodiments, the method further includes laterally recessing the semiconductor layer in the channel region after forming the undoped semiconductor layer and before forming the insulating layer. In some embodiments, the method further includes forming a front-side source / drain contact to a source / drain structure. In some embodiments, the method further includes forming a back-side source / drain contact to a source / drain structure. In some embodiments, the step of forming the back-side source / drain contact includes removing the undoped semiconductor layer and the insulating layer. In some embodiments, the source / drain recess has beveled sidewalls.

[0067] Another exemplary method of forming a semiconductor device structure includes forming a multilayer stack including a plurality of semiconductor layers, a plurality of sacrificial semiconductor layers, and a substrate extension. The method further includes removing a portion of the semiconductor layers, sacrificial semiconductor layers, and substrate extension in a source / drain region to form a source / drain recess; and forming a source / drain structure in the source / drain recess. The source / drain structure includes a second semiconductor layer and an insulating layer, with the insulating layer located between the second semiconductor layer and the substrate extension. Before forming the source / drain structure, the sacrificial semiconductor layer in the channel region is replaced with a plurality of sacrificial dielectric layers. After forming the source / drain structure, the sacrificial dielectric layer is removed from the word channel region to form a portion of a gate opening. A gate stack is formed in the portion of the gate opening.

[0068] An exemplary semiconductor device structure includes a first p-type transistor, comprising a first semiconductor layer of a first length extending from a first p-type doped source / drain to a second p-type source / drain, a first gate stack disposed on the first semiconductor layer, and a plurality of first inner spacers. The device structure further includes a second p-type transistor, comprising a second semiconductor layer of a second length extending from a third p-type doped source / drain to a fourth p-type source / drain, a second gate stack disposed on the second semiconductor layer, and a plurality of second inner spacers. A portion of the first gate stack is located between the first inner spacers, the first inner spacers extending beyond the ends of the first semiconductor layer, and the first p-type source / drain is located on a first source / drain insulating layer. A portion of the second gate stack is located between the second inner spacers, the second length being greater than the first length, and the third p-type doped source / drain is located on the second source / drain insulating layer.

[0069] In some embodiments, a first p-type transistor forms a portion of a logic circuit, while a second p-type transistor forms a portion of a memory circuit. In some embodiments, a first gate stack is located on a first semiconductor substrate portion; a second gate stack is located on a second semiconductor substrate portion; and the top of a first source / drain insulating layer is lower than the top of the first semiconductor substrate portion, and the top of a second source / drain insulating layer is higher than the top of the second semiconductor substrate portion.

[0070] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention. [Simplified Explanation of the Diagram]

[0006] Figure 1 is a flowchart of part or all of the method for fabricating a multi-gate device (such as a p-type transistor) according to various embodiments of the present invention. Figure 2 is a top view of part or all of the device having a bottom source / drain insulating layer fabricated by a method of implementing a sacrificial dielectric interlayer (as shown in Figure 1) according to various embodiments of the present invention. Figures 3A to 19A are cross-sectional views of part or all of the device of Figure 2 at various fabrication stages (as shown in the method of Figure 1) along section line AA according to various embodiments of the present invention. Figures 3B to 19B are cross-sectional views of part or all of the device of Figure 2 at various fabrication stages (as shown in the method of Figure 1) along section line BB according to various embodiments of the present invention. Figure 17C is a cross-sectional view of part or all of the device of Figure 2 at the fabrication stages of Figures 17A and 17B along section line CC according to various embodiments of the present invention. Figures 20 to 22 are cross-sectional views of part or all of the device of Figure 2 at various fabrication stages (as shown in the method of Figure 1) along section line AA according to various embodiments of the present invention. Figures 23 and 24 are cross-sectional views along section line AA of part or all of the device of Figure 2 at various manufacturing stages (as shown in the method-related stages of Figure 1) in various embodiments of the present invention. Figures 25A and 25B are cross-sectional views of part or all of the device manufactured by implementing a sacrificial dielectric interlayer (as shown in the method of Figure 1) in various embodiments of the present invention. Figures 26A and 26B are graphs showing the performance differences between devices configured with or without a bottom source / drain insulating layer in various embodiments of the present invention. Figure 27 is a cross-sectional view of part or all of the device implementing a bottom source / drain insulating layer in various embodiments of the present invention.

Claims

1. A method for forming a semiconductor device structure, comprising: A multilayer stack is formed on a protrusion, the multilayer stack including a plurality of first semiconductor layers and a plurality of first sacrificial layers, and the first sacrificial layers having a first composition; The process involves: removing the first semiconductor layers, the first sacrificial layers, and a portion of the protrusion from a source / drain region to form a source / drain recess; forming a source / drain structure in the source / drain recess, wherein the source / drain structure includes a second semiconductor layer and an insulating layer, wherein the insulating layer is located between the second semiconductor layer and the protrusion; prior to forming the source / drain structure, replacing the first sacrificial layers with a plurality of second sacrificial layers, wherein a second composition of the second sacrificial layers differs from the first composition; after forming the source / drain structure, removing the second sacrificial layers from a channel region to form a portion of a gate opening; and forming a gate stack in the portion of the gate opening, wherein the source / drain structure further includes a third semiconductor layer located between the insulating layer and the protrusion, wherein the second semiconductor layer is a doped semiconductor layer, and the third semiconductor layer is an undoped semiconductor layer.

2. The method for forming a semiconductor device structure as described in claim 1, wherein the first semiconductor layers are composed of a first semiconductor material, the first sacrificial layers are composed of a second semiconductor material, and the second sacrificial layers are composed of a dielectric material.

3. The method for forming a semiconductor device structure as described in claim 2, wherein the first semiconductor material is silicon, the second semiconductor material is silicon-germanium, and the dielectric material is silicon oxide.

4. A method for forming a semiconductor device structure as described in claim 3, wherein the insulating layer is a silicon nitride layer.

5. A method for forming a semiconductor device structure, comprising: A multilayer stack is formed, comprising multiple semiconductor layers, multiple sacrificial semiconductor layers, and a substrate extension; Remove the semiconductor layers, the sacrificial semiconductor layers, and a portion of the substrate extension in a source / drain region to form a source / drain recess; Forming a source / drain structure in the source / drain recess includes: forming an undoped semiconductor layer on the substrate extension to partially fill the source / drain recess; forming an insulating layer on the undoped semiconductor layer to partially fill the source / drain recess; and forming a doped semiconductor layer on the insulating layer to fill the remaining source / drain recess; replacing the sacrificial semiconductor layers in a channel region with a plurality of sacrificial oxide layers before forming the source / drain structure in the source / drain recess; and replacing the sacrificial oxide layers in the channel region with a gate stack after forming the source / drain structure in the source / drain recess.

6. The method for forming the semiconductor device structure as described in claim 5 further includes: Before forming the source / drain structure in the source / drain recess, the sacrificial oxide layers are laterally recessed to form multiple inner spacer indentations. And to form multiple inner spacers in the recesses of these inner spacers.

7. The method of forming the semiconductor device structure as described in claim 5 or 6 further includes: Before forming the source / drain recess, a gate structure is formed on the multilayer stack in the channel region, wherein the gate structure includes a dummy gate and a plurality of gate spacers; after forming the source / drain structure and before replacing the sacrificial oxide layers to form the gate stack, the dummy gate is removed to form a gate opening; and wherein the gate stack fills the gate opening.

8. A semiconductor device structure, comprising: A first p-type transistor includes a first semiconductor layer of a first length extending from a first p-type doped source / drain to a second p-type source / drain, a first gate stack on the first semiconductor layer, and a plurality of first inner spacers, wherein a portion of the first gate stack is located between the first inner spacers, the first inner spacers extend beyond the ends of the first semiconductor layer, and the first p-type source / drain is located on a first source / drain insulating layer; and a second p-type transistor includes a second semiconductor layer of a second length extending from a third p-type doped source / drain to a fourth p-type source / drain, a second gate stack on the second semiconductor layer, and a plurality of second inner spacers, wherein a portion of the second gate stack is located between the second inner spacers, the second length is greater than the first length, and the third p-type doped source / drain is located on a second source / drain insulating layer.

9. The semiconductor device structure as described in claim 8, wherein the first p-type transistor forms a portion of a logic circuit and the second p-type transistor forms a portion of a memory circuit.

10. The semiconductor device structure as described in claim 8 or 9, wherein: The first gate stack is located on a first semiconductor substrate portion; The second gate stack is located on a second semiconductor substrate portion; and the top of the first source / drain insulating layer is lower than the top of the first semiconductor substrate portion, and the top of the second source / drain insulating layer is higher than the top of the second semiconductor substrate portion.

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