Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for manufacturing resistive random access memory (RAM). The method primarily involves first providing a substrate including an alignment mark region and a resistive RAM region; then forming an interlayer dielectric layer on the substrate; forming a contact plug within the interlayer dielectric layer of the resistive RAM region; forming a first lower electrode layer on the resistive RAM region and the alignment mark region; and finally removing the first lower electrode layer and the interlayer dielectric layer of the alignment mark region to form a groove.

Claims

1. A resistive random access memory (RAM), characterized in that it comprises: an interlayer dielectric layer disposed on a substrate, wherein the substrate includes an alignment mark region and a resistive RAM region; a contact plug disposed within the interlayer dielectric layer; a groove disposed within the alignment mark region; a cover layer disposed within the groove and extending to the interlayer dielectric layer of the resistive RAM; and a lower electrode disposed on the contact plug, wherein the lower electrode comprises: a first lower electrode layer, wherein the first lower electrode layer comprises tantalum metal; and a second lower electrode layer located on the first lower electrode layer.

2. The resistive random access memory as described in claim 1, further comprising: a resistive switching layer disposed on the lower electrode; an upper electrode disposed on the resistive switching layer; a cover layer disposed beside the upper electrode; a first intermetallic dielectric layer surrounding the cover layer; a second intermetallic dielectric layer disposed on the first intermetallic dielectric layer; and a metal interconnect disposed within the second intermetallic dielectric layer and connected to the upper electrode.

3. The resistive random access memory as described in claim 1, wherein the second lower electrode layer comprises a metal nitride.

4. The resistive random access memory as described in claim 1, wherein the top surface of the first lower electrode layer comprises a U-shape.

5. The resistive random access memory as described in claim 1, wherein the bottom surface of the second lower electrode layer comprises a U-shape.

6. The resistive random access memory as described in claim 1, wherein the sidewall of the first lower electrode layer is flush with the sidewall of the second lower electrode layer.

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