Semiconductor device and method for forming the same

Abstract

This application provides a semiconductor device and a method for forming the semiconductor device. The method includes: providing a semiconductor package including a plurality of contact pads formed on a surface of the semiconductor package; providing a template having a plurality of openings; disposing the template on the surface of the semiconductor package, wherein the plurality of openings are respectively aligned with the plurality of contact pads; forming a plurality of solder bumps on the plurality of contact pads and in the plurality of openings; and irradiating the plurality of solder bumps with a homogenizing laser beam to form a solder interconnect between each of the plurality of solder bumps and a corresponding one of the plurality of contact pads.

Description

[Technical Field]

[0001] This application generally relates to semiconductor technology, and more specifically, to a semiconductor device and a method for forming a semiconductor device. [Previous Technology]

[0002] As consumers demand smaller, faster, and higher-performing electronic devices and increasingly package more functions into a single device, the semiconductor industry has faced complex integration challenges. Laser-assisted bonding (LAB) is a technique that can be used to bond semiconductor devices to a substrate. However, LAB can cause stress and damage in semiconductor devices, leading to low reliability.

[0003] Therefore, there is a need for a semiconductor device with improved reliability. [Summary of the Invention]

[0004] The purpose of this application is to provide a method for forming a semiconductor device with improved reliability.

[0005] According to one aspect of this application, a method for forming a semiconductor device is provided. The method may include: providing a semiconductor package including a plurality of contact pads formed on a surface of the semiconductor package; providing a template having a plurality of openings; disposing the template on the surface of the semiconductor package, wherein the plurality of openings are respectively aligned with the plurality of contact pads; forming a plurality of solder bumps on the plurality of contact pads and in the plurality of openings; and irradiating the plurality of solder bumps with a homogenizing laser beam to form a solder interconnect between each of the plurality of solder bumps and a corresponding contact pad of the plurality of contact pads.

[0006] According to another aspect of this application, a method for forming a semiconductor device is provided. The method may include: providing a substrate having a substrate surface, wherein the substrate surface includes at least one bonding region; providing a template having at least one opening; disposing the template on the substrate surface, wherein the bonding region is exposed from the opening of the template; disposing at least one solder bump in the bonding region; and irradiating the bonding region with a homogenizing laser beam to melt the solder bump.

[0007] According to another aspect of this application, a semiconductor device is provided. The semiconductor device can be formed according to the aforementioned method.

[0008] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the invention. Furthermore, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

Implementation Method

[0014] The following detailed description of exemplary embodiments of this application refers to the accompanying drawings, which form a part of this specification. The drawings illustrate specific exemplary embodiments that may be practiced with respect to this application. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice this application. Those skilled in the art may further utilize other embodiments of this application and make logical, mechanical, and other changes without departing from the spirit or scope of this application. Therefore, the reader of the following detailed description should not interpret the description in a limiting sense, and only the appended claims define the scope of the embodiments of this application.

[0015] In this application, unless otherwise specified, the use of the singular includes the plural. In this application, unless otherwise specified, the use of "or" means "and / or". Furthermore, the use of the term "comprising" and other forms such as "including" and "containing" is not restrictive. Additionally, unless otherwise specified, terms such as "element" or "component" cover both elements and components comprising one unit and elements and components comprising more than one sub-unit. Furthermore, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0016] For ease of description, spatial relative terms such as "below," "below," "above," "above," "upper," "lower," "left," "right," "vertical," "horizontal," and "side" may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and one or more other elements or features. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0017] Figure 1 is a schematic diagram of bonding solder bumps 130 to contact pads 124 of substrate 110 using laser-assisted bonding (LAB) technology.

[0018] LAB is an advanced surface mount bonding technology in which a homogenized laser beam (i.e., a two-dimensional beam instead of a one-dimensional beam) is applied to a wafer or device to establish a metallurgical interconnect with the substrate.

[0019] For example, as shown by the dashed arrow in FIG1, the irradiation area of ​​the homogenizing laser beam can be the same size as the substrate 110. That is, both the solder bump 130 and the top surface of the substrate 110 are irradiated by the laser beam. The laser beam can apply energy to the solder bump 130 and heat the solder bump 130 above its melting point. Then, a solder interconnect can be formed between the solder bump 130 and the contact pad 124 of the substrate 110. However, since the top surface of the substrate 110 is also exposed to the laser beam, heat may be generated inside the substrate 110, resulting in stress and / or warping in the substrate 110 and potential damage to other electronic components.

[0020] To address at least one of the above problems, one aspect of this application provides a method for forming a semiconductor device. In this method, a stencil having a plurality of openings is provided. The stencil is disposed on the surface of a semiconductor package, and the plurality of openings in the stencil are aligned with a plurality of contact pads formed on the surface of the semiconductor package. A plurality of solder bumps are simultaneously placed in the plurality of openings on the plurality of contact pads. Then, the plurality of solder bumps are irradiated with a homogenized laser beam to form a solder interconnect between each of the plurality of solder bumps and a corresponding contact pad among the plurality of contact pads. Since the stencil can reflect some of the laser beam irradiating the surface of the semiconductor package, heat generated inside the semiconductor package can be reduced, thereby reducing stress and / or warping in the semiconductor package and potential damage to other electronic components in the semiconductor package.

[0021] Referring to Figures 2A to 2G, various steps of a method for forming a semiconductor device are illustrated according to embodiments of this application. The method will be described in more detail below with reference to Figures 2A to 2G.

[0022] Referring to FIG. 2A, a semiconductor package 201 is provided. Specifically, the semiconductor package 201 may include a substrate 210 providing support and connectivity for electronic components and devices. For example, the substrate 210 may include a printed circuit board (PCB), a carrier substrate, a semiconductor substrate with electrical interconnects, a ceramic substrate, a laminated interposer, a strip interposer, a lead frame, or other suitable substrate. The substrate 210 may include any structure on which or in which an integrated circuit system can be fabricated.

[0023] In the example shown in FIG. 2A, the substrate 210 includes a redistribution structure 220 having one or more dielectric layers and one or more conductive layers between and through the dielectric layers. The conductive layers may define pads, traces, and plugs, and electrical signals or voltages may be distributed horizontally and vertically across the redistribution structure 220 via the pads, traces, and plugs. In the example shown in FIG. 2A, the substrate 210 includes a first surface 210a and a second surface 210b opposite to the first surface 210a, and the conductive layers of the redistribution structure 220 include a plurality of first contact pads 223 formed on the first surface 210a of the substrate 210 and a plurality of second contact pads 224 formed on the second surface 210b of the substrate 210. It is understood that the redistribution structure 220, the first contact pads 223, and the second contact pads 224 may be implemented in various structures and types, but aspects of this application are not limited to the above examples.

[0024] Multiple electronic components may be mounted on the first surface 210a of the substrate 210 and electrically connected to the first contact pads 223. The electronic components may include any of a variety of semiconductor dies, semiconductor packages, or discrete devices. For example, electronic components may include digital signal processors (DSPs), microcontrollers, microprocessors, network processors, power management processors, audio processors, video processors, RF circuits, wireless baseband system-on-chip (SoC) processors, sensors, memory controllers, memory devices, application-specific integrated circuits, discrete devices, etc. In the example of FIG2A, the electronic components may include a semiconductor die 241 and multiple discrete devices 242, such as resistors, capacitors, inductors, etc. The semiconductor die 241 is mounted on the first surface 210a of the substrate 210 using flip-chip bonding technology, such that conductive bumps of the semiconductor die 241 are soldered to some of the first contact pads 223. In other examples, the semiconductor die 241 may include bonding pads and may be connected to the first contact pads 223 using wire bonding technology. It is understood that the semiconductor bare wafer 241 and discrete device 242 shown in FIG2A are merely examples, and this application is not limited thereto.

[0025] A sealant 250 is formed on a first surface 210a of the substrate 210 and seals electronic components 241 and 242. The sealant 250 may be made of a polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with suitable filler, but the scope of this application is not limited thereto. The sealant 250 can protect electronic components 241 and 242 from the influence of the external environment.

[0026] In the example of Figure 2A, only a single unit of the semiconductor package is shown, but this application is not limited thereto. In some other examples, strip-type semiconductor packages can be provided, that is, multiple semiconductor packages arranged in a strip manner. Multiple semiconductor packages can be isolated from each other by a single-unit dicing channel. The single-unit dicing channel can provide a dicing area to cut the package strip single unit into individual semiconductor devices.

[0027] Referring to Figure 2B, a template 300 with multiple openings 310 is provided.

[0028] In some embodiments, the layout of the plurality of openings 310 in the template 300 can be designed according to the position or shape of the corresponding contact pads 224 on the second surface 210b of the substrate 210. For example, each of the plurality of openings 310 may have a cross-sectional shape at its bottom that is substantially the same as or larger than the shape of the corresponding contact pad 224, thereby allowing conductive material (e.g., solder bumps) to completely cover the contact pad 224. In some other examples, the cross-sectional shape at the bottom of each of the plurality of openings 310 may be slightly smaller than the shape of its corresponding contact pad 224, thereby forming a leak-proof seal between the contact pad 224 and the template 300.

[0029] Since the plurality of openings 310 in the stencil 300 may be filled with solder material, and the stencil 300 will be set on and removed from the second surface 210b of the substrate 210 in subsequent processes, the sidewalls of the plurality of openings 310 should be as smooth as possible. In some embodiments, each of the plurality of openings 310 may have a vertical straight sidewall or an inclined wall. For example, each of the plurality of openings 310 may have a truncated shape with a trapezoidal cross-section. In some embodiments, a coating with anti-stick properties, such as a solder paste resist coating, may be formed on the sidewalls of the plurality of openings 310 to prevent solder material from adhering to the stencil 300. It is understood that the shape of the plurality of openings 310 and the thickness of the stencil 300 may vary depending on the configuration of the solder bumps to be formed, and are not limited herein.

[0030] In this application, since the template 300 can be used as a protective layer to reflect the irradiation energy from the homogenized laser beam, the template 300 can have high reflectivity in the laser beam spectrum. For example, the template 300 may include a metallic material with a high damping constant, causing light to travel only a short distance. In some embodiments, the reflectivity of the template 300 to the laser beam spectrum is at least greater than the reflectivity of the substrate 210, preferably greater than 70%, 80%, 90%, or 95%. For example, the template 300 may include Al, Cu, Ag, Au, etc., which have high reflectivity over a wide wavelength range, particularly in the infrared (IR) region of the spectrum.

[0031] In some embodiments, the template 300 may be a single-layer plate made of a metallic material such as Al, Cu, Ag, Au, or any combination thereof. It is understood that this application is not limited to the aforementioned metallic materials, and the template 300 may include other materials with high reflectivity. In some embodiments, the template 300 may be a multilayer laminated structure having a high-reflectivity layer on its upper side. For example, the multilayer laminated structure may include a top layer with high reflectivity (e.g., greater than 70%, 80%, 90%, or 95%) and a bottom layer with low thermal conductivity, such that the top layer can reflect irradiation energy from the laser beam, and the bottom layer can prevent or reduce heat transfer to the substrate 210, thereby minimizing the thermal impact on the entire semiconductor package. In some embodiments, the thermal conductivity of the bottom layer is at least lower than that of the top layer, for example, lower than the thermal conductivity of Al, Cu, Ag, or Au. For example, the top layer may include a metallic material such as Al, Cu, Ag, Au, or any combination thereof, and the bottom layer may include a polymer or ceramic material.

[0032] Referring to Figures 2C and 2D, a template 300 is disposed on the second surface 210b of the substrate 210, wherein a plurality of openings 310 are respectively aligned with a plurality of contact pads 224, and a plurality of solder bumps 230 can be formed on the plurality of contact pads 224 and in the plurality of openings 310.

[0033] Since the multiple openings 310 are designed according to the position or shape of the multiple contact pads 224, the multiple openings 310 can be precisely aligned with the multiple contact pads 224. Multiple solder bumps 230 can be formed in the multiple openings 310 using a stencil printing process, a falling ball process, or an evaporation process. The solder bumps 230 may include eutectic Sn / Pb, high-lead solder, lead-free solder, etc.

[0034] In some embodiments, a plurality of solder bumps 230 (e.g., solder balls) may be placed on a plurality of contact pads 224 manually or using automated equipment known in the art. By positioning the solder bumps 230 within the opening 310 of the stencil 300, the solder bumps 230 can be accurately positioned at the contact pads 224. The opening 310 of the stencil 300 prevents the solder bumps 230 from deviating from the position of the contact pads 224.

[0035] In some embodiments, a stencil printing process can be used to form a plurality of solder bumps 230. Specifically, fluid solder material can be deposited on a stencil 300, and the fluid solder material can flow through openings 310 onto contact pads 224. A squeegee can then be used to planarize the fluid solder material. If the openings 310 are not completely filled with fluid solder material, a squeegee can be pressed against the stencil 300 to drive fluid solder material into the openings 310. The flow of the fluid solder material can depend on the pressure applied by the squeegee, the viscosity of the fluid solder material, and the shape and size of the openings 310. The squeegee can also clean the top surface of the stencil 300 and define the thickness of the fluid solder material filling the openings 310.

[0036] Referring to Figures 2E and 2F, as shown by the dashed arrow in Figure 2E, a plurality of solder bumps 230 are irradiated with a homogenized laser beam to form a solder interconnect between each of the plurality of solder bumps 230 and a corresponding contact pad among the plurality of contact pads 224.

[0037] In some embodiments, laser assisted bonding (LAB) technology can be used to achieve laser irradiation. LAB is an advanced flip-chip and surface mount bonding technology in which a homogenized laser beam (i.e., a two-dimensional beam instead of a one-dimensional beam) is selectively applied to a wafer or component to establish a metallurgical interconnect with the substrate. For example, in LAB, a laser homogenizer can be used to receive a laser beam input via fiber optic cable, waveguide, or other suitable mechanism and output a homogenized laser beam on template 300. The homogenizer can smooth irregularities in the laser beam profile and produce a beam with substantially uniform power across the entire beam profile. For example, the irradiation area of ​​the homogenized laser beam produced by the homogenizer can be the same size as template 300. That is, template 300 and the plurality of solder bumps 230 are both irradiated by the homogenized laser beam.

[0038] Specifically, as shown in FIG2E, the homogenizing laser beam can apply light energy to the stencil 300 and the plurality of solder bumps 230. The light energy of the homogenizing laser beam can be converted into heat energy to heat the plurality of solder bumps 230. The solder bumps 230 can be heated above their melting point and reflowed to form a reliable solder interconnect between each of the plurality of solder bumps 230 and a corresponding contact pad of the plurality of contact pads 224, as shown in FIG2F. The heating temperature can be controlled by the irradiation power and time. Since the laser beam can provide more localized heat than a reflow oven and can reflow solder with a shorter cycle time, the possibility of damage to electronic components mounted on the substrate 210 during the reflow process is reduced. In a specific example, an infrared laser source (e.g., having a wavelength between 900 nm and 1100 nm) is used, and the laser beam is modulated to form a homogeneous spatial power distribution to irradiate multiple solder bumps 230 and stencil 300 for a duration between 1 second and 5 seconds (e.g., 2 seconds, 3 seconds, 4 seconds, etc.). However, this application is not limited to the above example, and the wavelength of the laser beam and the duration of irradiation can vary depending on the intensity of the laser beam, the material and volume of the solder bumps 230, etc.

[0039] On the other hand, the template 300 (e.g., including Al, Cu, Ag, Au, etc.) can have high reflectivity in the spectrum of the homogenized laser beam and can reflect most of the laser beam irradiating it. Therefore, less heat can be generated and transferred inside the substrate 210, thereby reducing stress and / or warping in the substrate 210 and potential damage to electronic components mounted on the substrate 210. Furthermore, since the template 300 can be made of a metallic material and attached to the substrate 210, the template 300 can also provide structural support for the substrate 210 and significantly reduce warping during irradiation.

[0040] Subsequently, referring to Figures 2F and 2G, the template 300 is removed from the second surface 210b of the substrate 210, thereby leaving a plurality of solder bumps 230 on the substrate 210.

[0041] The solder bump 230 can be electrically connected to any electronic component mounted on the first surface 210a of the substrate 210 via a redistribution structure formed in the substrate 210. In the case where the semiconductor device shown in FIG2G is mounted on an external device or, for example, a printed circuit board (PCB) substrate, the solder bump 230 can be used to electrically connect the semiconductor device to the external device or the substrate.

[0042] In some embodiments, as described above, the semiconductor package may include a plurality of semiconductor devices arranged in a strip manner, and the package strip may be individually diced into individual semiconductor devices. For example, laser dicing, sawing, etching, or any other suitable process known in the art may be used to individually diced the package strip into individual semiconductor devices by cutting channels.

[0043] In the embodiments described with reference to Figures 2A to 2G, the method of this application can be used to form solder bumps on contact pads. However, this application is not limited thereto. In some other embodiments, the method of this application can be used to form any solder interconnect in a semiconductor device.

[0044] Referring to FIG3, a method for forming a semiconductor device according to another embodiment of the present application is illustrated. The method can be used to bond a semiconductor bare wafer 450 onto a substrate 410.

[0045] Specifically, a substrate 410 is first provided. The substrate 410 may include a redistribution structure similar to the redistribution structure of the substrate 210 shown in FIG. 2A. The substrate 410 may include a bonding region 410c, i.e., the middle portion of its upper surface as shown in FIG. 3. Then, a template 500 with an opening is provided and disposed on the upper surface of the substrate 410, wherein the bonding region 410c is exposed from the opening of the template 500. Subsequently, a semiconductor bare wafer 450 having a plurality of solder bumps 424 is provided. The semiconductor bare wafer 450 is placed on the substrate 410, wherein the solder bumps 424 contact contact pads formed in the bonding region 410c. Subsequently, as shown by the dashed arrow in FIG. 3, the bonding region 410c may be irradiated with a homogenized laser beam to form a solder interconnect between each of the plurality of solder bumps and a corresponding contact pad of the plurality of contact pads. As shown in Figure 3, a homogenizing laser beam can pass through the semiconductor bare wafer 450 and apply energy to the solder bumps to form solder interconnects. Simultaneously, the template 500 (e.g., comprising Al, Cu, Ag, Au, etc.) can have high reflectivity in the spectrum of the homogenizing laser beam and reflect most of the laser beam irradiating it. The method described with reference to Figure 3 can share characteristics with the methods described with reference to Figures 2A to 2G, and will not be described in detail herein.

[0046] According to another aspect of this application, a semiconductor device is provided. This semiconductor device can be formed by any of the aforementioned methods. For example, the semiconductor device can be the same as the semiconductor device shown in FIG. 2G or the semiconductor device shown in FIG. 3, and will not be repeated here.

[0047] The discussion herein includes numerous illustrative figures illustrating various parts of a semiconductor device and methods for manufacturing the semiconductor device. For clarity, such figures do not show all aspects of each example device. Any example device and / or method provided herein may share any or all characteristics with any or all other devices and / or methods provided herein.

[0048] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes can be made thereto, and other embodiments can be practiced, without departing from the broad scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art from the description and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that this application and the examples herein be considered exemplary only, and the true scope and spirit of the invention are indicated by the list of exemplary claims appended. [Simplified Explanation of the Diagram]

[0009] The accompanying drawings referenced herein form a part of this specification. The features shown in the drawings are only illustrative of some embodiments of this application, and not all embodiments of this application, unless the detailed description clearly indicates otherwise, and the reader of this specification should not infer the contrary.

[0010] Figure 1 is a schematic diagram showing the bonding of solder bumps to contact pads on a substrate using laser-assisted bonding (LAB) technology.

[0011] Figures 2A to 2G are cross-sectional views illustrating various steps of a method for forming a semiconductor device according to an embodiment of the present application.

[0012] FIG3 is a cross-sectional view illustrating a method for forming a semiconductor device according to another embodiment of the present application.

[0013] The same element symbols will be used throughout the drawings to refer to the same or similar parts.

Claims

1. A method for forming a semiconductor device, wherein, The method includes: providing a semiconductor package including a plurality of contact pads formed on a surface of the semiconductor package; providing a template having a plurality of openings; disposing the template on the surface of the semiconductor package, wherein the plurality of openings are respectively aligned with the plurality of contact pads; forming a plurality of solder bumps on the plurality of contact pads and in the plurality of openings; and irradiating the semiconductor package, the surface of which is covered by the template, with a homogenizing laser beam, wherein the template reflects most of the laser beam irradiating thereon, and the laser beam irradiates the plurality of solder bumps to form a solder interconnect between each of the plurality of solder bumps and a corresponding contact pad among the plurality of contact pads.

2. The method according to request item 1, wherein, The semiconductor package includes: a substrate having a first surface and a second surface opposite to the first surface; at least one electronic component mounted on the first surface of the substrate; and a sealant formed on the first surface of the substrate and sealing the electronic component, wherein a plurality of contact pads are formed on the second surface of the substrate.

3. The method according to request item 1, wherein, The template comprises a material with high reflectivity.

4. The method according to request item 3, wherein, The template includes Al, Cu, Ag or Au.

5. The method according to request item 1, wherein, The template is a multilayer laminated structure, which includes a top layer with high reflectivity and a bottom layer with low thermal conductivity.

6. The method according to request item 1, wherein, Irradiating the plurality of solder bumps with the homogenized laser beam includes irradiating the plurality of solder bumps with an infrared laser beam.

7. The method according to request item 1, wherein, Irradiating the plurality of solder bumps with the homogenized laser beam includes irradiating the plurality of solder bumps with the homogenized laser beam for a duration between 1 second and 5 seconds.

8. The method according to request item 1, wherein, The method further includes: removing the template from the surface of the semiconductor package.

9. The method according to claim 1, wherein, The semiconductor package includes a plurality of semiconductor devices arranged in a strip manner, and the method further includes: dicing the semiconductor package into individual semiconductor devices.

10. A method for forming a semiconductor device, wherein, The method includes: providing a substrate having a base surface, wherein the base surface includes at least one bonding region; providing a template having at least one opening; disposing the template on the base surface, wherein the bonding region is exposed from the opening of the template; disposing at least one solder bump in the bonding region; and irradiating the substrate, the surface of which the template is covered, with a homogenizing laser beam, wherein the template reflects most of the laser beam irradiating thereon, and the laser beam irradiates the bonding region to melt the solder bump.

11. The method according to request item 10, wherein, The template comprises a material with high reflectivity.

12. The method according to request item 11, wherein, The template includes Al, Cu, Ag or Au.

13. The method according to claim 10, wherein, The template is a multilayer laminated structure, which includes a top layer with high reflectivity and a bottom layer with low thermal conductivity.

14. The method according to claim 10, wherein, Irradiating the bonding region with the homogenized laser beam includes irradiating the bonding region with an infrared laser beam.

15. The method according to request item 10, wherein, Irradiating the bonding region with the homogenized laser beam includes irradiating the bonding region with the homogenized laser beam for a duration between 1 second and 5 seconds.

16. The method according to claim 10, wherein, The method further includes: removing the template from the substrate surface.

17. A semiconductor device, wherein, The semiconductor device is formed using the method according to any one of claims 1 to 9 or the method according to any one of claims 10 to 16.

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