Electronic devices and methods of manufacturing electronic devices

Abstract

In one example, an electronic device includes a lower substrate, an upper substrate, internal interconnects, a bridging assembly, a lower enclosure, and electronic components. The internal interconnects couple an upper side of one of the lower substrates to a lower side of one of the upper substrates. The bridging assembly includes: a first interconnect coupled to the upper substrate; a second interconnect coupled to the lower substrate; and a bridging signal redistribution structure coupled to the first and second interconnects. The lower enclosure encapsulates the internal components and the bridging assembly. The electronic components are coupled to the internal interconnects and the bridging signal redistribution structure via an upper side of the upper substrate. The bridging signal redistribution structure provides one or more signal paths between the first and second electronic components. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to electronic devices and methods for manufacturing electronic devices. Prior Technology

[0002] Previous electronic packaging and the methods used to form electronic packages were inappropriate, resulting in, for example, excessive costs, reduced reliability, relatively low performance, or excessively large package sizes. Other limitations and disadvantages of such methods will become apparent to those skilled in the art by comparing known and conventional methods with the present disclosure and referring to the figures. [ ] Summary of the Invention

[0003] One aspect of the present invention is a method for manufacturing an electronic device, the method comprising: providing an internal interconnect and a bridging assembly, wherein the bridging assembly includes a bridging substrate and a bridging signal redistribution structure; encapsulating the internal interconnect and the bridging assembly in a lower encapsulation; removing the bridging substrate from the bridging assembly; covering the upper side of the lower encapsulation with an upper substrate such that a conductive structure of the upper substrate is coupled to the internal interconnect and the bridging signal redistribution structure; coupling a first interconnect of a first electronic component to the bridging signal redistribution structure and a second interconnect of the first electronic component to the internal interconnect via the upper substrate; and coupling a first interconnect of a second electronic component to the bridging signal redistribution structure and a second interconnect of the second electronic component to the internal interconnect via the upper substrate.

[0004] Another embodiment of the present invention is an electronic device comprising: a lower substrate including an upper side and a lower side; an upper substrate including an upper side and a lower side; an internal interconnect coupling the upper side of the lower substrate to the lower side of the upper substrate; a bridging assembly comprising: a first bridging interconnect coupled to the lower side of the upper substrate; a second bridging interconnect coupled to the upper side of the lower substrate; a bridging signal redistribution structure coupled to the first bridging interconnect and the second bridging interconnect; and a lower encapsulation encapsulating the internal interconnect and the bridging assembly; a first electronic component coupled to the internal interconnect and the bridging signal redistribution structure via the upper side of the upper substrate; and a second electronic component coupled to the internal interconnect and the bridging signal redistribution structure via the upper side of the upper substrate; wherein the bridging signal redistribution structure provides one or more signal paths between the first electronic component and the second electronic component. Simple Explanation of the Diagram

[0005] [Figure 1] shows a cross-sectional view of an exemplary electronic device. Figures 2A through 2J show cross-sectional views of exemplary methods for manufacturing the exemplary electronic device of Figure 1. [Figure 3] shows a cross-sectional view of another exemplary electronic device. Figures 4A to 4H show cross-sectional views of an exemplary method for manufacturing the electronic device of Figure 3. Implementation

[0006] The following discussion presents various examples of providing electronic devices and methods of manufacturing electronic devices. Such examples are non-limiting, and the scope of the accompanying patent claims should not be limited to the specific examples disclosed. In the following discussion, the terms "examples" and "for example" are non-limiting.

[0007] The figures illustrate the general construction method, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the contents of this disclosure. Furthermore, the elements in the figures are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to aid in understanding the examples discussed in this disclosure. Identical elements in different figures are denoted by the same symbols.

[0008] The term "and / or" means any one or more of the items in a list joined by "and / or". As an example, "x and / or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y and / or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0009] The terms “comprises”, “comprising”, “includes” and “including” are “open” terms that specify the presence of the stated feature, but do not exclude the presence or addition of one or more other features.

[0010] The terms "first," "second," etc., may be used herein to describe various elements, and such elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element discussed herein may be referred to as the second element.

[0011] Unless otherwise specified, the term "coupled" can be used to describe two elements that are in direct contact with each other or two elements that are indirectly coupled through one or more other elements. For example, if element A is coupled to element B, then element A may be in direct contact with element B or indirectly coupled to element B through element C. Similarly, the terms "above" or "on" can be used to describe two elements that are in direct contact with each other or two elements that are indirectly coupled through one or more other elements. As used herein, the term "coupled" can refer to electrical coupling or mechanical coupling.

[0012] In one example, a method of manufacturing an electronic device may include providing internal interconnects and a bridging assembly. The bridging assembly may include a bridging component coupled to a bridging die. The bridging component may include a bridging signal redistribution structure. The method may further include encapsulating the internal interconnects and the bridging assembly in a lower encapsulation, and removing the bridging die from the bridging assembly. Additionally, the method may include covering an upper side of the lower encapsulation with an upper substrate such that a conductive structure of the upper substrate is coupled to the internal interconnects and the bridging signal redistribution structure. The method may also include: coupling a first interconnect of a first electronic component to the signal redistribution conductive structure and coupling a second interconnect of the first electronic component to the internal interconnects via the upper substrate; and coupling a first interconnect of a second electronic component to the signal redistribution conductive structure and coupling a second interconnect of the second electronic component to the internal interconnects via the upper substrate.

[0013] In another example, an electronic device includes a lower substrate, an upper substrate, internal interconnects, a bridging assembly, a lower enclosure, and electronic components. The internal interconnects couple an upper side of one of the lower substrates to a lower side of one of the upper substrates. The bridging assembly includes: a first bridging interconnect coupled to the upper substrate; a second interconnect coupled to the lower substrate; and a bridging signal redistribution structure coupled to the first and second bridging interconnects. The lower enclosure encapsulates the internal components and the bridging assembly. The electronic components are coupled to the internal interconnects and the bridging redistribution structure via an upper side of the upper substrate. The bridging signal redistribution structure provides one or more signal paths between the first and second electronic components.

[0014] Other examples are included in this disclosure. Such examples can be seen in the figures, the claims, or the embodiments of this disclosure.

[0015] Figure 1 shows a cross-sectional view of an exemplary electronic device 100. In the example shown in Figure 1, the electronic device 100 may include a bridging assembly 110, a lower substrate 120, an upper substrate 130, internal interconnects 140, a lower encapsulation 151, an upper encapsulation 152, a first electronic component 171, a second electronic component 172, and external interconnects 180. In some embodiments, the electronic device 100 may include a bottom filler 160.

[0016] The bridging component 110 may include a bridging first interconnect 113a, a bridging second interconnect 113b, and a bridging signal redistribution structure 114. The bridging signal redistribution structure 114 may include a signal redistribution conductive structure 111 and a signal redistribution dielectric structure 112. The signal redistribution conductive structure 111 may provide one or more signal paths through the signal redistribution dielectric structure 112, which may (i) couple one or more of the bridging first interconnects 113a to one or more of the bridging second interconnects 113b, and / or (ii) couple one or more of the bridging first interconnects 113a to other bridging first interconnects 113a. In this manner, the bridging signal redistribution structure 114, via its signal redistribution conductive structure 111, can provide signal, ground, power, and / or other electrical paths between: (i) the first electronic component 171 and the second electronic component 172; (ii) the first electronic component 171 and the lower substrate 120; and / or (iii) the second electronic component 172 and the lower substrate 120. In some embodiments, the internal interconnect 140 can be used to provide ground and / or power to the first electronic component 171 and the second electronic component 172, and the signal redistribution conductive structure 111 can be used for signal paths to and from the first electronic component 171 and the second electronic component 172, and between the first electronic component 171 and the second electronic component 172.

[0017] The lower substrate 120 may include a lower substrate dielectric structure 121 and a lower substrate conductive structure 122. The lower substrate conductive structure 122 may include an upper terminal 122a and a lower substrate lower terminal 122b. The upper substrate 130 may include an upper substrate dielectric structure 131 and an upper substrate conductive structure 132. The upper substrate 130 may include a lower terminal 132a and an upper terminal 132b.

[0018] The first electronic component 171 may include a first interconnect 171a and a second interconnect 171b. The second electronic component 172 may include a first interconnect 172a and a second interconnect 172b.

[0019] The bridging component 110, lower substrate 120, upper substrate 130, internal interconnect 140, lower encapsulation 151, upper encapsulation 152, bottom filler 160, and external interconnect 180 may be referred to as an electronic package, such as a semiconductor package. The electronic package can protect the first electronic component 171 and the second electronic component 172 from exposure to external components or the environment, and / or provide electrical connections between the first electronic component 171 and the second electronic component 172 and / or between external devices / packages and electronic components 171, 172.

[0020] Figures 2A to 2J show cross-sectional views of an exemplary method for manufacturing the exemplary electronic device 100 of Figure 1.

[0021] Figure 2A shows a cross-sectional view of the electronic device 100 in an early manufacturing stage. In the example shown in Figure 2A, a bridging assembly 110a and an internal interconnect 140 may be disposed on the upper side of the first carrier 10. The bridging assembly 110a may include a bridging substrate 115 and a bridging component 110 above the upper side of the bridging substrate 115. Specifically, the internal interconnect 140 may be spaced apart from the sidewalls of the bridging component 110. Furthermore, the internal interconnect 140 may be provided by electrolytic plating, electrodeless plating, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0022] For example, metal layer 10a may cover the upper side of the first carrier 10. Internal interconnects 140 may be disposed on the upper side of metal layer 10a. Here, metal layer 10a may include or be referred to as a seed layer. In some instances, internal interconnects 140 may be made of copper, gold, silver, palladium, or nickel. Internal interconnects 140 may include pillars, guide pillars, vertical lines, bumps, or solder-coated metal core balls. As mentioned above, internal interconnects 140 may be spaced apart from the sidewalls of bridging assembly 110. Internal interconnects 40 may be further spaced apart from each other in a column or row direction.

[0023] The bridging assembly 110 and the bridging substrate 115 may be disposed on the upper side of the first carrier 10. In some embodiments, the pick-and-place device can pick up the bridging assembly 110a, which includes the bridging assembly 110 and the bridging substrate 115, and place the bridging assembly 110a on the upper side of the metal layer 10a covering the first carrier 10. In addition, the bridging assembly 110a may be adhered to the upper side of the metal layer 10a along the bottom surface of the bridging substrate 115 using an adhesive.

[0024] As shown, bridging component 110 can be coupled to the top side of bridging substrate 115. Specifically, bridging signal redistribution structure 114 can be disposed on the upper side of bridging substrate 115. In some embodiments, bridging substrate 15 can contain a semiconductor material, such as silicon. In some embodiments, bridging substrate 115 can contain a mold material, ceramic, or glass. Bridging first interconnect 113a can be coupled to the signal redistribution conductive structure 111 of bridging signal redistribution structure 114 from the lower side of bridging signal redistribution structure 114. Similarly, bridging second interconnect 113b can be coupled to the signal redistribution conductive structure 111 of bridging signal redistribution structure 114 from the upper side of bridging signal redistribution structure 114. Bridging first interconnect 113a can reach the upper side of bridging substrate 115 through bridging insulating body 116. Therefore, the sidewall of bridging first interconnect 113a can contact bridging insulating body 116. The bridging insulating body 116 may be part of the signal redistribution dielectric structure 112. The bridging second interconnect 113b may protrude above the bridging signal redistribution structure 114.

[0025] The bridging substrate 115 may include an upper metal 115a covering the upper side of the bridging substrate 115. The bridging first interconnect 113a can be coupled to the upper side of the bridging substrate 115 via the upper metal 115a. Therefore, the upper metal 115a prevents the metal of the bridging first interconnect 113a from diffusing toward the bridging substrate 115. In some embodiments, the upper metal 115a may comprise a multilayer thin film made of titanium and copper.

[0026] The bridging first interconnect 113a can be provided by electroplating the bridging first interconnect 113a using a mask pattern on the upper side of the upper metal 115a and by using the upper metal 115a as a seed layer. For example, the mask pattern can be provided by photoresist. The mask pattern can then be removed after the bridging first interconnect 113a is provided. The bridging first interconnect 113a can be disposed on the upper side of the bridging substrate 115 such that the bridging first interconnects 113a are spaced apart from each other in a column or row direction. The bridging first interconnect 113a can include or be referred to as pads, bumps, pillars, struts, or vias. In some instances, the bridging first interconnect 113a can include copper, gold, silver, or nickel. In some instances, the bridging first interconnect 113a can be provided by electrodeless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD.

[0027] The bridging insulating body 116 may cover the upper side of the bridging substrate 115. The bridging first interconnect 113a may pass between the upper and lower sides of the bridging insulating body 116. The bridging insulating body 116 may be configured to cover the upper side of the bridging substrate 115 and the upper side of the bridging first interconnect 113a. The upper side of the bridging first interconnect 113a may then be exposed through a planarization process. In some instances, the bridging insulating body 116 may include, or be referred to as, a dielectric layer, a coreless layer, or a fillerless layer of the bridging signal redistribution structure 114. For example, the bridging insulating body 116 may include an electrically insulating material such as polyimide (PI), benzocyclobutene (BCB), polybenzo[a]azole (PBO), resin, molding material, epoxy resin, acrylate polymer, or ANZOC-based additive film (ABF). In some instances, the bridging insulating body 116 may be provided by spin coating, spray coating, dip coating, bar coating, or any other suitable deposition method. In some instances, the thickness of the bridging insulating body 116 may be similar to the thickness of the bridging first interconnect 113a. In some instances, the bridging insulating body 116 may be provided prior to the bridging first interconnect 113a, and the bridging first interconnect 113a may then be provided through the bridging insulating body 116.

[0028] One or more dielectric layers of the signal redistribution dielectric structure 112 may be provided to cover the upper side of the bridging insulating body 116 and the upper side of the bridging first interconnect 113a. An opening may then be provided to expose the upper side of the bridging first interconnect 113a. For example, the opening may be provided by forming a mask pattern on the upper side of the signal redistribution dielectric structure 112 and then removing the exposed portion of the signal redistribution dielectric structure 112 by etching. In some instances, the opening may be referred to as or include a aperture or hole. In some instances, one or more dielectric layers of the signal redistribution dielectric structure 112 may be provided by similar materials and methods used to provide the bridging insulating body 116.

[0029] One or more conductive layers of the signal redistribution conductive structure 111 may be located above one or more dielectric layers of the signal redistribution dielectric structure 112 and above the bridging first interconnect 113a. The one or more conductive layers of the signal redistribution conductive structure 111 may have multiple patterns and be electrically coupled to the bridging first interconnect 113a. In some embodiments, the one or more conductive layers of the signal redistribution conductive structure 111 may include or be referred to as traces, pads, vias, redistribution layers (RDLs), wiring patterns, or circuit patterns. In some embodiments, the one or more conductive layers of the signal redistribution conductive structure 111 may include copper, gold, silver, or nickel.

[0030] One or more dielectric layers of the signal redistribution dielectric structure 112 may be provided to cover one or more conductive layers of the signal redistribution conductive structure 111 and one or more dielectric layers of the signal redistribution dielectric structure 112. One or more conductive layers of the signal redistribution conductive structure 111 may be disposed on the upper side of one or more conductive layers of the signal redistribution conductive structure 111 and on the upper side of one or more dielectric layers of the signal redistribution dielectric structure 112. One or more dielectric layers of the signal redistribution dielectric structure 112 and one or more conductive layers of the signal redistribution conductive structure 111 may be alternately and sequentially disposed. A bridging insulating body 116 may be located between one of the dielectric layers of the signal redistribution dielectric structure 112 and the bridging substrate 115.

[0031] The bridging second interconnect 113b may be disposed on the upper side of the bridging signal redistribution structure 114. Specifically, the bridging second interconnect 113b may protrude above the uppermost conductive layer of the signal redistribution conductive structure 111 and above the uppermost dielectric layer of the signal redistribution dielectric structure 112. The bridging second interconnect 113b may be provided by materials and methods similar to those used to provide bridging the first interconnect 113a.

[0032] In some instances, the signal redistribution dielectric structure 112 may include multiple (e.g., 2, 3, 4, etc.) dielectric layers, and the signal redistribution conductive structure 111 may include multiple (e.g., 2, 3, 4, etc.) conductive layers. One or more layers or elements of the signal redistribution conductive structure 111 may be interleaved with one or more layers or elements of the signal redistribution dielectric structure 112. In some instances, the bridging first interconnect 113a and the bridging second interconnect 113b may be part of or integrated with the signal redistribution conductive structure 111. One or more layers or elements of the signal redistribution conductive structure 111 located on the lowermost side of the signal redistribution conductive structure 111 may include or be referred to as the bridging first interconnect 113a. Similarly, one or more layers or elements of the signal redistribution conductive structure 111 located on the uppermost side of the signal redistribution conductive structure 111 may include or be referred to as the bridging second interconnect 113b. In some instances, the thickness of the bridging second interconnect 113b and / or the bridging first interconnect 113a may be greater than the thickness of the conductive layer of the signal redistribution conductive structure 111.

[0033] After the signal redistribution dielectric structure 112 and signal redistribution conductive structure 111 of the bridging signal redistribution structure 114 are disposed on the upper side of the bridging substrate 115, a unitization process can be performed, wherein the bridging assembly 110 and the bridging substrate 115 are separated into individual bridging assemblies 110a by sawing the bridging substrate 115 and the bridging signal redistribution structure 114. In some instances, a diamond blade or a laser beam can be used during the unitization process.

[0034] The first carrier 10 may comprise a substantially planar plate. In some instances, the first carrier 10 may comprise or be referred to as a plate, board, wafer, panel, or strip. For example, the first carrier 10 may be made of steel, stainless steel, aluminum, copper, ceramic, glass, or a wafer. In some instances, the thickness of the first carrier 10 may be in the range of approximately 300 μm to approximately 2000 μm, and the width or diameter of the first carrier 10 may be in the range of approximately 100 mm to approximately 300 mm. In some instances, the width or diameter of the first carrier 10 may be greater than 300 mm (e.g., 600 mm). The first carrier 10 can be used to enable the processing of multiple components into a single component in the manufacturing process of providing bridging assembly 110, upper substrate 130, internal interconnect 140, lower encapsulation 151, upper encapsulation 152, bottom filler 160, first electronic component 171, and second electronic component 172.

[0035] The first carrier 10 may include a temporary bonding layer 10b disposed on the surface of the first carrier 10. A metal layer 10a may be disposed on the surface of the temporary bonding layer 10b of the first carrier 10. The temporary bonding layer 10b may be disposed on the surface of the first carrier 10 by a coating method (such as spin coating, blade coating, casting, brushing, spraying, slot coating, curtain coating, sliding coating, or blade-over-edge coating); a printing method (such as screen printing, pad printing, gravure printing, flexographic printing, offset printing, or inkjet printing); an intermediate technique between coating and printing; or may be provided by directly attaching a bonding film or bonding tape. In some instances, the temporary bonding layer 10b may include or be referred to as a temporary bonding film, temporary bonding tape, or temporary adhesive coating. For example, the temporary bonding layer may be a heat-release tape (film) or an optically release tape (film), the adhesive strength of which is weakened or removed by heat or light. The temporary bonding layer 10b allows the first carrier 10 to be separated from the lower encapsulation 151 (FIG. 2B) before the lower substrate 120 (FIG. 2I) is provided, and will be described later.

[0036] Figure 2B shows a cross-sectional view of the electronic device 100 in the later manufacturing stage. In the example shown in Figure 2B, a lower encapsulation 151 may be provided to cover the bridging assembly 110a and the internal interconnect 140. In some examples, the lower encapsulation 151 may comprise or be referred to as a body or molding component. For example, the lower encapsulation 151 may comprise an epoxy molding compound, resin, filler-reinforced polymer, B-stage pressed film, or gel. For example, the lower encapsulation 151 may be provided by compression molding, transfer molding, liquid molding, vacuum lamination, paste printing, or film-assisted molding.

[0037] The upper portion of the lower encapsulation 151 can be removed to expose the upper side of the bridging assembly 110a and the upper side of the internal interconnect 140. The lower encapsulation 151 can contact the sidewalls of the bridging assembly 110, the sidewalls of the bridging base 115, and the respective sidewalls of the internal interconnect 140. The lower encapsulation 151 can also contact the respective sidewalls of the bridging second interconnect 113b. In some embodiments, the upper portion of the lower encapsulation 151 can be removed by grinding. In some embodiments, when the upper portion of the lower encapsulation 151 is removed, the upper portions of the internal interconnect 140 and the upper portions of the bridging second interconnect 113b can also be removed. In some embodiments, the upper sides of the bridging second interconnect 113b, the upper sides of the internal interconnect 140, and the upper sides of the lower encapsulation 151 can be coplanar. The thickness (i.e., height) of the lower capsule 151, the height of the internal interconnect 140, and the height of the bridging assembly 110a may be equal or approximately equal.

[0038] Figure 2C shows a cross-sectional view of the electronic device 100 in the later manufacturing stage. In the example shown in Figure 2C, the upper substrate 130 may be disposed above the lower envelope 151, above the bridging second interconnect 113b, and above the internal interconnect 140. The upper substrate 130 may include an upper substrate dielectric structure 131 and an upper substrate conductive structure 132.

[0039] After one or more dielectric layers of the upper substrate dielectric structure 131 cover the upper side of the lower encapsulation 151, the upper side of the bridging second interconnect 113b, and the upper side of the internal interconnect 140, apertures exposing the upper side of the bridging second interconnect 113b and the upper side of the internal interconnect 140 can be provided. One or more dielectric layers of the upper substrate dielectric structure 131 may comprise or be referred to as dielectric layers, coreless layers, or filler-free layers. In some examples, one or more dielectric layers of the upper substrate dielectric structure 131 may comprise electrically insulating materials such as polymers, polyimide (PI), benzocyclobutene (BCB), polybenzo[a]azole (PBO), bismaleimide triterpenoid (BT), molding materials, phenolic resins, epoxy resins, polysiloxane, or acrylate polymers. In some examples, one or more dielectric layers of the upper substrate dielectric structure 131 may be provided by spin coating, spray coating, dip coating, or rod coating. After the mask pattern is set on the upper side of the upper substrate dielectric structure 131, the exposed portion of the upper substrate dielectric structure 131 can be removed by etching to expose the upper side of the bridged second interconnect 113b and the upper side of the internal interconnect 140.

[0040] One or more conductive layers of the upper substrate conductive structure 132 can be patterned. One or more patterned conductive layers of the upper substrate conductive structure 132 can contact and / or couple to the upper side of the bridging second interconnect 113b and / or the upper side of the internal interconnect 140. One or more conductive layers of the upper substrate conductive structure 132 can define signal distribution elements of the upper substrate 130. One or more conductive layers of the upper substrate conductive structure 132 can include or be referred to as traces, pads, vias, RDLs, wiring patterns, or circuit patterns. In some instances, one or more conductive layers of the upper substrate conductive structure 132 can include silver, copper, gold, silver, or nickel. For example, one or more conductive layers of the upper substrate conductive structure 132 can be provided by electrodeless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD.

[0041] According to various examples, the upper substrate dielectric structure 131 and / or the upper substrate conductive structure 132 may comprise any number of layers. Therefore, the upper substrate 130 may comprise, or be referred to as, a redistribution layer ("RDL") substrate or an interposer. When the upper substrate dielectric structure 131 and / or the upper substrate conductive structure 132 comprises multiple layers, such layers of the upper substrate 130 may be alternately and sequentially disposed. Specifically, one or more conductive layers or elements of the upper substrate conductive structure 132 may be interleaved with one or more dielectric layers or elements of the upper substrate dielectric structure 131.

[0042] The upper terminal 132b of the upper substrate 130 may be provided by one or more upper conductive layers or elements of the upper substrate conductive structure 132. The lower terminal 132a of the upper substrate 130 may be provided by one or more lower conductive layers or elements of the upper substrate conductive structure 132. Each of the lower terminals 132a may contact the upper side of the second interconnect 113b and / or the upper side of the internal interconnect 140. The upper terminals 132b may be provided along the upper side of the upper substrate 130 and may be spaced apart from each other in the column direction and / or row direction. The lower terminals 132a may be provided along the lower side of the upper substrate 130 and may be spaced apart from each other in the column direction and / or row direction. The lower terminals 132a and the upper terminals 132b may include or be referred to as pads, solder pads, UBMs, or studs.

[0043] In some instances, the upper substrate 130 may include an RDL substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, and (a) may be formed layer by layer over the electronic component to which the RDL substrate is to be coupled, or (b) may be formed layer by layer over a carrier that may be completely or at least partially removed after the electronic component is coupled to the RDL substrate. The RDL substrate may be fabricated layer by layer on a circular wafer as a wafer-level substrate in a wafer-level process, and / or layer by layer on a rectangular or square panel carrier as a panel-level substrate in a panel-level process. The RDL substrate may be formed in an additive buildup process and may include one or more dielectric layers stacked alternately with one or more conductive layers, defining individual conductive redistribution patterns or traces configured to collectively (a) fan out of the occupied area of ​​the electronic device and / or (b) fan in into the occupied area of ​​the electronic device. Conductive patterns can be formed using electroplating processes such as, for example, electroplating or electrodeless electroplating. Conductive patterns may contain conductive materials, such as, for example, copper or other plated metals. Photolithography processes, such as, for example, photolithography and photoresist materials, can be used to form photolithography masks to determine the location of the conductive patterns. The dielectric layer of the RDL substrate can be patterned using photolithography processes and may include a photolithography mask through which light is exposed to photolithographically pattern desired features (such as vias) in the dielectric layer. The dielectric layer may be made of photodefinable organic dielectric materials such as, for example, PI, BCB, or PBO. Such dielectric materials can be spin-coated or otherwise applied in liquid form rather than attached as a preform. To allow proper formation of the desired photodefinable features, such photodefinable dielectric materials may omit structural reinforcing agents or may be filler-free, without strands, braids, or other particles that could interfere with light from the photolithography process. In some instances, the filler-free nature of filler-free dielectric materials allows for a reduction in the thickness of the resulting dielectric layer. Although the photodefinable dielectric materials described above can be organic, in some instances, the dielectric material of the RDL substrate can comprise one or more inorganic dielectric layers. Some examples of one or more inorganic dielectric layers may comprise silicon nitride (Si3N4), silicon oxide (SiO2), and / or silicon oxynitride (SiON). These one or more inorganic dielectric layers can be formed by growing the inorganic dielectric layers using oxidation or nitriding processes instead of using photodefinable organic dielectric materials. Such inorganic dielectric layers can be filler-free, without strands, braids, or other different inorganic particles. In some instances, the RDL substrate may omit a permanent core structure or carrier, such as (e.g.) dielectric materials comprising bismaleimide trisulfide (BT) or FR4, and such types of RDL substrates may comprise or be referred to as coreless substrates. Other substrates mentioned in this disclosure may also include RDL substrates.

[0044] In some instances, the upper substrate 130 may be a preformed substrate. The preformed substrate may be manufactured prior to attachment to electronic components and may include a dielectric layer between individual conductive layers. The conductive layer may contain copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick, non-optically definable layer and may serve as a preformed film rather than a liquid attachment, and may include a resin with fillers such as strands, braids, and / or other inorganic particles for rigid and / or structural support. Because the dielectric layer may be non-optically definable, features such as vias or openings may be formed using a drill or laser. In some instances, the dielectric layer may contain a prepreg material or an ANSI alpha layer (ABF). The preformed substrate may include a permanent core structure or carrier, such as a dielectric material containing, for example, bismaleimide trisulfite (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In other instances, the preformed substrate may be a coreless substrate with a permanent core structure omitted, and the dielectric and conductive layers may be formed on a sacrificial carrier and removed after the dielectric and conductive layers are formed and before attachment to an electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminated substrate. Such preformed substrates may be formed via a semi-additive or modified semi-additive process. Other substrates described in this disclosure may also include preformed substrates.

[0045] Figure 2D shows a cross-sectional view of the electronic device 100 in the later manufacturing stage. In the example shown in Figure 2D, a first electronic component 171 and a second electronic component 172 may be disposed above an upper substrate 130. The first electronic component 171 and the second electronic component 172 may be contacted and / or electrically coupled to an upper terminal 132b of the upper substrate 130. In some embodiments, the lower side of the first electronic component 171 and the lower side of the second electronic component 172 may include, or be referred to as, the active side of each component. The upper side of the first electronic component 171 and the upper side of the second electronic component 172 may include, or be referred to as, the non-active side of each component. The first electronic component 171 may include a first interconnect 171a and a second interconnect 171b on the lower side of the first electronic component 171. The first interconnect 171a and the second interconnect 171b of the first electronic component 171 may be spaced apart from each other in the column direction and / or the row direction. Similarly, the second electronic component 172 may include a first interconnect 172a and a second interconnect 172b on its underside. The first interconnect 172a and the second interconnect 172b of the second electronic component 172 may be spaced apart from each other in the column direction and / or row direction. Each interconnect 171a, 171b, 172a, and 172b may include or be referred to as a bump, pad, or post. Each interconnect 171a, 171b, 172a, and 172b may be an input / output terminal of a respective electronic component 171, 172. In some instances, each interconnect 171a, 171b, 172a, and 172b may be provided by electrolytic plating, electrodeless plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. For example, after providing photoresist patterns for the bonding pads of exposed electronic components 171, 172, interconnects 171a, 171b, 172a, 172b can be provided to contact the exposed bonding pads. In some instances, the thickness (i.e., height) of interconnects 171a, 171b, 172a, and 172b can range from approximately 1 μm to approximately 100 μm, and the width and / or pitch of interconnects 171a, 171b, 172a, and 172b can range from approximately 5 μm to approximately 200 μm. In some instances, interconnects 171a, 172a that couple individual electronic components 171, 172 to bridging assembly 110 are spaced closer together with a finer pitch or a higher density than interconnects 171b, 172b. Therefore, interconnects 171a and 172a can be called high-density interconnects, and interconnects 171b and 172b can be called low-density interconnects.

[0046] In some instances, the pick-and-place device can pick up electronic components 171 and 172 and place them on the upper side of the upper substrate 130. This placement allows the interconnects 171a, 171b, 172a, and 172b of the electronic components 171 and 172 to be positioned in contact with the upper side of the upper terminal 132b. Subsequently, the interconnects 171a, 171b, 172a, and 172b of the electronic components 171 and 172 can be bonded to the upper terminal 132b through a reflow soldering or thermoforming process. In some instances, hybrid bonding can be used to couple the electronic components 171 and 172 to the upper terminal 132b. In some instances, the electronic components 171 and 172 may comprise or be referred to as a die, chip, or package. In some instances, one of electronic components 171 or 172 may include a logic die or logic device, and the other electronic component 171 and electronic component 172 may include a memory package (e.g., one or more stacked memory dies or memory devices). Electronic components 171 and 172 may be electrically coupled to bridging component 110 and internal interconnect 140 via upper substrate conductive structure 132 on upper substrate 130. Electronic components 171 and 172 may be electrically coupled to each other via upper substrate 130 and bridging component 110. Although two electronic components 171 and 172 are shown, in some instances, electronic device 100 may include a larger number of electronic components.

[0047] Electronic components 171 and 172 are shown in a face-down or flip-chip configuration, wherein component terminals located on the lower side are coupled to the upper substrate 130 via interconnects 171a, 171b, 172a, 172b between the lower side of electronic components 171 and 172 and the upper side of the upper substrate 130. However, in some embodiments, electronic components 171 and 172 may be in a face-up or wire-bonded configuration, wherein component terminals are located on the upper side. In such embodiments, the upper side of electronic components 171 and 172 may include or be referred to as the active side, and the lower side of electronic components 171 and 172 may include or be referred to as the non-active side. The non-active sides of electronic components 171 and 172 may be attached to the upper substrate 130. Electronic components 171 and 172 may have component terminals located on the surface above the active side. Electronic components 171 and 172 may include or be referred to as face-up or wire-bonded components. The terminals of the upward-facing electronic components 171 and 172 can be electrically coupled to the upper terminal 132b of the upper substrate 130 via wire bonding or conductive wires. The conductive wires may include gold, copper, or aluminum wires. In such examples, the terminals of the upward-facing electronic components 171 and 172 can be coupled to the upper terminal 132b of the upper substrate 130 via wire bonding equipment. In some examples, the total thickness of each electronic component 171 and 172 can range from approximately 50 μm to approximately 1000 μm, and the area of ​​each electronic component 171 and 172 can range from approximately 0.5 mm × 0.5 mm to approximately 70 mm × 70 mm.

[0048] Figure 2E shows a cross-sectional view of the electronic device 100 in the later manufacturing stage. In the example shown in Figure 2E, the underfill 160 may be positioned between each electronic component 171, 172 and the upper side of the upper substrate 130. The underfill 160 may contact the lower side of each electronic component 171, 172 and the upper side of the upper substrate 130. The underfill 160 may contact the interconnects 171a, 171b, 172a, 172b of the electronic components 171, 172. The underfill 160 may contain or be referred to as a dielectric layer or non-conductive paste, and may not contain inorganic fillers. In some examples, the underfill 160 may contain or be referred to as capillary underfill (CUF), non-conductive paste (NCP), non-conductive film (NCF), anisotropic conductive film (ACF), or anisotropic conductive paste (ACP). In some instances, when the underfill 160 includes molded underfill (MUF), the underfill 160 may be considered part of or provided by the upper envelope 152. In some instances, the underfill 160 may be inserted between the electronic components 171, 172 and the upper substrate 130. In some instances, after the underfill 160 is provided above the upper side of the upper substrate 130, the interconnects 171a, 171b, 172a, 172b of the electronic components 171, 172 may penetrate the underfill 160 and couple to the upper terminal 132b of the upper substrate 130. The underfill 160 may prevent physical and thermal shocks and / or prevent or reduce the occurrence of separation of the electronic components 171, 172 from the upper substrate 130.

[0049] Figure 2F shows a cross-sectional view of the electronic device 100 in the later manufacturing stage. In the example shown in Figure 2F, an upper encapsulation 152 may be provided to cover the upper side of the upper substrate 130, the bottom filler 160, and the electronic components 171, 172. The upper encapsulation 152 may contact the upper side of the upper substrate 130, the sidewalls of the electronic components 171, 172, and the sidewalls of the bottom filler 160.

[0050] The upper encapsulation 152 may have corresponding elements, features, materials, or manufacturing methods similar to those of the lower encapsulation 151. In some examples, the upper encapsulation 152 may expose the upper side of the electronic components 171, 172. The thickness of the upper encapsulation 152 and the height of each electronic component 171, 172 may be similar. In some examples, the thickness of the upper encapsulation 152 may range from approximately 50 μm to approximately 1800 μm. In some examples, a cover may be provided on the upper side of the electronic components 171, 172 exposed above the upper side of the upper encapsulation 152 and coupled thereto. A thermal interface material (TIM) and a back metal (BSM) may be inserted between the cover and the electronic components 171, 172 to facilitate heat transfer and coupling.

[0051] Figure 2G shows a cross-sectional view of the electronic device 100 in the later manufacturing stage. In the example shown in Figure 2G, a second carrier 20 is provided and coupled to the upper side of the electronic components 171, 172 and the upper side of the upper envelope 152. After this coupling, the first carrier 10 can be removed from the lower envelope 151, the lower side of the bridging assembly 110a, and the lower side of the internal interconnect 140.

[0052] The second carrier 20 may cover the upper sides of each electronic component 171, 172 and the upper side of the upper enclosure 152. The lower side of the second carrier 20 may include a temporary bonding layer 20a. The temporary bonding layer 20a may contact the second carrier 20 and attach the second carrier 20 to the upper sides of each electronic component 171, 172 and the upper enclosure 152. The temporary bonding layer 20a may have corresponding elements, features, materials, or manufacturing methods similar to those of the temporary bonding layer 10b of the first carrier 10. When the electronic device 100 is manufactured, the temporary bonding layer 20a may allow the second carrier 20 to be separated from the electronic components 171, 172 and the upper enclosure 152.

[0053] Figure 2H shows a cross-sectional view of the electronic device 100 in the later manufacturing stage. In the example shown in Figure 2H, the lower portion of the bridging assembly 110a, the lower portion of the internal interconnect 140, and the lower portion of the lower envelope 151 can be removed. For example, after removing the first carrier 10, the lower side of the lower envelope 151, the lower side of the internal interconnect 140, and the lower side of the bridging assembly 110a can be partially removed by grinding and / or etching. The lower side of the internal interconnect 140 and the lower side of the bridging first interconnect 113a of the bridging assembly 110 can be exposed at the lower side of the lower envelope 151. The lower side of the bridging signal redistribution structure 114 can be exposed at the lower side of the lower envelope 151. As shown, grinding and / or etching can remove the bridging substrate 115, thus leaving the bridging assembly 110. The bridging signal redistribution structure 114 provides signal transmission between the first interconnect 113a and the second interconnect 113b via its signal redistribution conductive structure 111. The heights of the bridging assembly 110, the lower encapsulation 151, and the internal interconnect 140 may be equal or substantially equal after this grinding and / or etching.

[0054] Figure 2I shows a cross-sectional view of the electronic device 100 in the later manufacturing stage. In the example shown in Figure 2I, the lower substrate 120 may cover the lower side of the lower envelope 151, the lower side of the internal interconnect 140, and the lower side of the bridging assembly 110.

[0055] The lower substrate 120 may include a lower substrate dielectric structure 121 and a lower substrate conductive structure 122. After one or more dielectric layers of the lower substrate dielectric structure 121 cover the underside of the lower encapsulation 151, the underside of the internal interconnect 140, and the underside of the bridging assembly 110, apertures may be provided to expose the underside of the internal interconnect 140 and the underside of the bridging first interconnect 113a. One or more conductive layers of the lower substrate conductive structure 122 may be provided to contact the underside of the bridging first interconnect 113a and the underside of the internal interconnect 140.

[0056] The lower substrate 120 may have corresponding elements, features, materials, or manufacturing methods similar to those of the upper substrate 130. For example, when the lower substrate conductive structure 122 is multilayered, the lower terminals 122b of the lower substrate 120 may be provided by one or more lower conductive layers of the lower substrate conductive structure 122. Similarly, the upper terminals 122a of the lower substrate 120 may be provided by one or more upper conductive layers of the lower substrate conductive structure 122. Each of the upper terminals 122a may contact the underside of the first interconnect 113a and / or the underside of the internal interconnect 140. The upper terminals 122a may be provided along the upper side of the lower substrate 120 and may be spaced apart from each other in the column direction and / or row direction. The lower terminals 122b may be provided along the lower side of the lower substrate 120 and may be spaced apart from each other in the column direction and / or row direction.

[0057] Figure 2J shows a cross-sectional view of the electronic device 100 in the later manufacturing stage. In the example shown in Figure 2J, external interconnects 180 may be provided along the underside of the lower substrate 120, and the electronic device 100 may undergo a unitization process.

[0058] External interconnect 180 may contact and / or couple to a lower terminal 122b of the lower substrate 120. In some embodiments, external interconnect 180 may comprise tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. For example, external interconnect 180 may be provided by forming a conductive material including solder on the lower terminal 122b using a drop ball method and then performing a reflow process. External interconnect 180 may comprise or be referred to as a conductive ball such as a solder ball, a conductive pillar such as a copper pillar, or a conductive pillar each having a solder cap disposed on the copper pillar. In some embodiments, external interconnect 180 may be a ball grid array or ground grid array along the lower side of the lower substrate 120. In some instances, the size of the external interconnect 180 can range from approximately 0.5 μm to approximately 1000 μm.

[0059] External interconnect 180 can be electrically coupled to electronic components 171 and 172 via lower substrate 120, internal interconnect 140, and upper substrate 130, and / or can be electrically coupled to electronic components 171 and 172 via lower substrate 120, bridging component 110, and upper substrate 130. After providing external interconnect 180, electronic device 100 can undergo a demolding process to separate into individual electronic devices 100 by sawing lower encapsulation 151, upper encapsulation 152, upper substrate 130, and lower substrate 120. In some instances, diamond blades or laser beams can be used during demolding. The second carrier 20 attached to the upper side of discrete electronic device 100 can also be removed. In some instances, external interconnect 180 may include or be referred to as external input / output terminals of discrete electronic device 100.

[0060] The complete electronic device 100 may include a bridging assembly 110, a lower substrate 120, an upper substrate 130, internal interconnects 140, a lower encapsulation 151, an upper encapsulation 152, electronic components 171 and 172, and external interconnects 180. In some embodiments, the electronic device 100 may also include a bottom filler 160.

[0061] Figure 3 shows a cross-sectional view of an exemplary electronic device 200. In the example shown in Figure 3, the electronic device 200 may include a bridging assembly 210, a lower substrate 120, an upper substrate 130, internal interconnects 140, a lower encapsulation 151, an upper encapsulation 152, electronic components 171 and 172, and external interconnects 180. In some examples, the electronic device 200 may also include a bottom filler 160.

[0062] The electronic device 200 of Figure 3 can be implemented in a similar manner to the electronic device 100 of Figure 1. For example, the electronic device 200 may be similar to the electronic device 100 in terms of the lower substrate 120, upper substrate 130, internal interconnect 140, lower encapsulation 151, upper encapsulation 152, electronic components 171, 172, external interconnect 180, and bottom filler 160. However, the electronic device 200 may include a bridging component 210 instead of the bridging component 110 of the electronic device 100. Similar to the bridging component 110 of the electronic device 100, the bridging component 210 of the electronic device 200 may include a bridging signal redistribution structure 114, a bridging first interconnect 113a, a bridging second interconnect 113b, and a bridging insulating body 116. However, the bridging component 210 of the electronic device 200 includes a lower (or second) bridging insulating body 212. In the electronic device 200, the bridging insulating body 116 may be oriented away from the lower substrate 120 and / or at the distal end of the lower substrate 120, and the lower bridging insulating body 212 may be oriented toward and / or approach the lower substrate 120.

[0063] Figures 4A to 4H show cross-sectional views of example methods for manufacturing exemplary electronic devices.

[0064] Figure 4A shows a cross-sectional view of the electronic device 200 in an early manufacturing stage. In the example shown in Figure 4A, the bridging assembly 210a and the internal interconnect 140 may be disposed on the upper side of the first carrier 10.

[0065] The first carrier 10 and the internal interconnect 140 may have corresponding elements, features, materials, or manufacturing methods similar to those of the first carrier 10 and the internal interconnect 140 of the electronic device 100. The bridging assembly 210a may also be similar to the bridging assembly 110a of FIG. 2A. However, the bridging assembly 210a may include a bridging component 210 and may be flipped relative to the bridging assembly 110a of FIG. 2A such that the bridging substrate 115 faces upward, wherein the bridging signal redistribution structure 114 is located between the bridging substrate 115 and the first carrier 10.

[0066] In bridging assembly 210a, bridging substrate 115 may be located on the upper side of bridging assembly 210a, and bridging assembly 210 may be close to the first carrier 10. In bridging assembly 210, the signal redistribution dielectric structure 112 and signal redistribution conductive structure 111 of bridging signal redistribution structure 114 may be located on the lower side of bridging substrate 115. Bridging assembly 210a may be joined and secured to the upper side of the first carrier 10 through lower bridging insulating body 212. Lower bridging insulating body 212 may be inserted between signal redistribution dielectric structure 112 and first carrier 10. Lower bridging insulating body 212 may surround bridging second interconnect 113b. Lower bridging insulating body 212 may contact each sidewall of bridging second interconnect 113b. In some instances, the lower bridging insulation body 212 may include or be referred to as non-conductive paste (NCP), non-conductive film (NCF), anisotropic conductive film (ACF), or anisotropic conductive paste (ACP).

[0067] Figure 4B shows a cross-sectional view of the electronic device 200 in the later manufacturing stage. In the example shown in Figure 4B, the lower envelope 151 is disposed above the bridging assembly 210a (Figure 4A) and the internal interconnect 140, and the bridging substrate 115 is removed from the bridging assembly 210a.

[0068] According to various examples, the upper portion of the lower envelope 151 can be removed to expose the upper side of the bridging first interconnect 113a and the upper side of the internal interconnect 140 of the bridging assembly 210. When the bridging substrate 115 is removed, the bridging assembly 210 may include a bridging signal redistribution structure 114 and a lower bridging insulating body 212. The lower envelope 151 may contact the sidewalls of the bridging assembly 210 and the sidewalls of the internal interconnect 140. In some examples, the upper side of the bridging first interconnect 113a, the upper side of the internal interconnect 140, and the upper side of the lower envelope 151 may be coplanar. In some examples, the lower envelope 151 may have corresponding elements, features, materials, or manufacturing methods similar to those of the lower envelope 151 of the electronic device 100.

[0069] Figure 4C shows a cross-sectional view of the electronic device 200 in the later manufacturing stage. In the example shown in Figure 4C, the upper substrate 130 may be disposed above the lower envelope 151, above the bridging first interconnect 113a, and above the internal interconnect 140. The upper substrate conductive structure 132 of the upper substrate 130 may contact and / or couple to the upper side of the bridging first interconnect 113a and / or the upper side of the internal interconnect 140. The upper substrate 130 may have corresponding elements, features, materials, or manufacturing methods similar to those of the upper substrate 130 of the electronic device 100.

[0070] Figure 4D shows a cross-sectional view of the electronic device 200 in the later manufacturing stage. In the example shown in Figure 4D, electronic components 171, 172 and bottom filler 160 may be disposed on the upper side of the upper substrate 130. Electronic components 171, 172 and bottom filler 160 may have corresponding components, features, materials or manufacturing methods similar to those of electronic components 171, 172 and bottom filler 160 of electronic device 100.

[0071] Figure 4E shows a cross-sectional view of the electronic device 200 in the later manufacturing stage. In the example shown in Figure 4E, the upper encapsulation 152 may cover the upper side of the upper substrate 130, the bottom filler 160, and the electronic components 171, 172. The upper encapsulation 152 may have corresponding elements, features, materials, or manufacturing methods similar to those of the upper encapsulation 152 of the electronic device 100.

[0072] Figure 4F shows a cross-sectional view of the electronic device 200 in the later manufacturing stage. In the example shown in Figure 4F, the second carrier 20 is located above the electronic components 171, 172 and above the upper envelope 152, and the internal interconnect 140 and the bridging second interconnect 113b are exposed.

[0073] According to various examples, after the second carrier 20 is located above the electronic components 171, 172 and above the upper envelope 152, the lower portion of the bridging assembly 210, the lower portion of the internal interconnect 140, and the lower portion of the lower envelope 151 can be removed. Before removing the lower portion of the bridging assembly 210, the lower portion of the internal interconnect 140, and the lower portion of the lower envelope 151, the first carrier 10 can be removed from the lower envelope 151, the lower side of the bridging assembly 210, and the lower side of the internal interconnect 140. The second carrier 20 may have corresponding elements, features, materials, or manufacturing methods similar to those used in manufacturing the electronic device 100. The method for removing the first carrier 10 may be similar to the method for removing the first carrier 10 used in manufacturing the electronic device 100.

[0074] The lower portion of the lower enclosure 151, the lower portion of the internal interconnect 140, and the lower portion of the bridging assembly 210 can be partially removed by grinding and / or etching. The lower side of the internal interconnect 140, the lower side of the bridging second interconnect 113b, and the lower side of the lower bridging insulating body 212 can be exposed from the lower enclosure 151. The bridging signal redistribution structure 114 provides signal transmission between the bridging first interconnect 113a along the upper side of the bridging assembly 210 and the bridging second interconnect 113b along the lower side of the bridging assembly 210 via its signal redistribution conductive structure 111. The heights of the bridging assembly 210, the lower enclosure 151, and the internal interconnect 140 can be equal or substantially equal.

[0075] Figure 4G shows a cross-sectional view of the electronic device 200 in the later manufacturing stage. In the example shown in Figure 4G, the lower substrate 120 is disposed above the lower envelope 151, the internal interconnect 140, and the bridging assembly 210. According to various embodiments, the lower substrate 120 may cover the lower envelope 151, the internal interconnect 140, and the bridging assembly 210. The lower substrate 120 may have corresponding elements, features, materials, or manufacturing methods similar to those of the lower substrate 120 of the electronic device 100.

[0076] Figure 4H shows a cross-sectional view of the electronic device 200 in the later manufacturing stage. In the example shown in Figure 4H, external interconnects 180 can be provided along the lower side of the lower substrate 120, and individualization can be performed to provide individual discrete electronic devices 200. The external interconnects 180 may have corresponding elements, features, materials, or manufacturing methods similar to those of the external interconnects 180 of the electronic device 100.

[0077] In summary, various examples of electronic devices with bridging components are disclosed. These bridging components may include signal redistribution structures that provide electrical paths for supplying signals, power, and / or ground to electronic components and between electronic components of the electronic device. In some specific examples, the bridging component includes a bridging die removed during manufacturing.

[0078] This disclosure includes references to certain examples; however, it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Furthermore, modifications can be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that this disclosure be limited to the disclosed examples, but rather to include all examples falling within the scope of the appended claims.

[0079] 10: The First Carrier 10a: Metal layer 10b: Temporary bonding layer 20: Second Carrier 20a: Temporary bonding layer 100: Electronic devices 110: Bridging component 110a: Bridging assembly 111: Signal redistribution conductive structure 112: Signal redistribution dielectric structure 113a: Bridge the first interconnect 113b: Bridged second interconnect 114: Bridged Signal Redistribution Structure 115: Bridging substrate 115a: Upper metal 116: Bridging Insulation Body 120:Lower base plate 121: Dielectric structure of the lower substrate 122: Conductive structure of the lower substrate 122a: Upper terminal 122b: Lower substrate lower terminal 130:Upper base plate 131: Dielectric structure of the upper substrate 132: Conductive structure of the upper substrate 132a:Lower terminal 132b: Upper terminal 140: Internal interconnect components 151:Lower capsule 152:Upper capsule 160: Bottom filling 171: First Electronic Component 171a: First interconnect 171b: Second interconnect 172: Second Electronic Component 172a: First interconnect 172b: Second interconnect 180: External interconnects 200: Electronic devices 210: Bridging component 210a: Bridging assembly 212: Lower bridging insulation body

Claims

1. A method of manufacturing an electronic device, the method comprising: providing an internal interconnect and a bridging assembly, wherein the bridging assembly includes a bridging substrate, a bridging insulating body, bridging interconnects, and a bridging signal redistribution structure, wherein the bridging substrate covers the bridging insulating body and the bridging interconnects; encapsulating the internal interconnect and the bridging assembly in a lower encapsulation; exposing the bridging insulating body and the bridging interconnects by removing the bridging substrate from the bridging assembly; covering the upper side of the lower encapsulation with an upper substrate such that a conductive structure of the upper substrate is coupled to the internal interconnect and the bridging signal redistribution structure; coupling a first interconnect of a first electronic component to the bridging signal redistribution structure and a second interconnect of the first electronic component to the internal interconnect via the upper substrate; and coupling a first interconnect of a second electronic component to the bridging signal redistribution structure and a second interconnect of the second electronic component to the internal interconnect via the upper substrate.

2. The method of claim 1, wherein removing the bridging substrate comprises grinding the underside of the internal interconnect, the underside of the lower capsule, and the underside of the bridging assembly to remove the lower portion of the internal interconnect, the lower portion of the lower capsule, and the lower portion of the bridging assembly.

3. The method of claim 2, wherein the lower portion of the bridging assembly includes the bridging substrate.

4. The method of claim 1, wherein removing the bridging substrate comprises grinding the upper side of the internal interconnect, the upper side of one of the lower capsules, and the upper side of the bridging assembly to remove the upper portion of the internal interconnect, the upper portion of the lower capsule, and the upper portion of the bridging assembly.

5. The method of claim 4, wherein the upper portion of the bridging assembly includes the bridging base.

6. The method of claim 1, wherein removing the bridging substrate comprises etching the underside of the internal interconnect, the underside of the lower capsule, and the underside of the bridging assembly to remove the lower portion of the internal interconnect, the lower portion of the lower capsule, and the lower portion of the bridging assembly.

7. The method of claim 6, wherein the lower portion of the bridging assembly includes the bridging substrate.

8. The method of claim 1, wherein removing the bridging substrate comprises etching the upper side of the internal interconnect, the upper side of the lower capsule, and the upper side of the bridging assembly to remove the upper portion of the internal interconnect, the upper portion of the lower capsule, and the upper portion of the bridging assembly.

9. The method of claim 8, wherein the upper portion of the bridging assembly includes the bridging base.

10. The method of claim 1, wherein coupling the first interconnect of the first electronic component to the bridging signal redistribution structure and coupling the first interconnect of the second electronic component to the bridging signal redistribution structure would couple one or more of the first interconnects of the first electronic component to one or more of the first interconnects of the second electronic component.

11. The method of claim 1, which includes providing an external interconnect coupled to the underside of the internal interconnect.

12. The method of claim 1, comprising covering the lower side of the lower capsule with a lower substrate such that a conductive structure of the lower substrate is coupled to the internal interconnect and the bridging signal redistribution structure.

13. The method of claim 12, comprising providing an external interconnect coupled to the underside of the internal interconnect via the lower substrate.

14. The method of claim 1, comprising encapsulating the first electronic component and the second electronic component in an upper encapsulation body.

15. The method of claim 1, wherein a bottom filler is disposed between the lower side of the first electronic component and the upper side of the upper substrate.

16. As in request item 1, where: The bridging substrate includes a first material; and the bridging insulation body includes a second material, which is different from the first material.

17. As in request item 1, wherein: The bridging insulating body and the bridging interconnect are coupled to a metal layer that covers the bridging substrate; and the aforementioned removal of the bridging substrate includes the removal of the metal layer.

18. An electronic device comprising: a lower substrate including a upper side and a lower side; an upper substrate including a upper side and a lower side; an internal interconnect coupling the upper side of the lower substrate to the lower side of the upper substrate; a bridging assembly comprising: a first bridging interconnect coupled to the lower side of the upper substrate; a second bridging interconnect coupled to the upper side of the lower substrate; a bridging signal redistribution structure coupled to the first bridging interconnect and the second bridging interconnect; and a lower encapsulation encapsulating the internal interconnect and the bridging assembly; a first electronic component coupled to the internal interconnect and the bridging signal redistribution structure via the upper side of the upper substrate; and a second electronic component coupled to the internal interconnect and the bridging signal redistribution structure via the upper side of the upper substrate; wherein the bridging signal redistribution structure includes a signal redistribution dielectric structure and a signal redistribution conductive structure; The signal redistribution conductive structure provides one or more signal paths between the first electronic component and the second electronic component; and the lower side of the signal redistribution dielectric structure is exposed at the lower side of the lower encapsulation.

19. The electronic device of claim 18, comprising a first external interconnect coupled to the lower side of the internal interconnect via the lower substrate.

20. The electronic device of claim 19, comprising a second external interconnect coupled to a bridging second interconnect via the lower substrate.

21. The electronic device of claim 18, comprising an encapsulation body encapsulating the first electronic component and the upper encapsulation body encapsulating the second electronic component.

22. The electronic device of claim 21, comprising: a bottom filler located between the lower side of the first electronic component and the upper side of the upper substrate; and wherein the upper encapsulation encapsulates and contacts the bottom filler.

23. The electronic device of claim 21, wherein the lower side of the signal redistribution dielectric structure contacts the upper side of the lower substrate.

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