Control circuit and method for reducing reverse recovery charge in switching power converter

Abstract

A control circuit is provided for controlling a switching converter based on a pulse width modulation (PWM) signal. The switching converter includes a first and a second transistor, both coupled to a switching node, for switching an inductor based on the PWM signal to convert the input voltage and generate an output voltage. The control circuit includes: a drive circuit for generating a switching drive signal based on the PWM signal and a switching signal at the switching node to switch the first transistor; and an amplifier circuit for amplifying the difference between the switching signal and a reference signal during a idle time to generate an amplified output signal, and controlling the first transistor through linear negative feedback operation to adjust the voltage of the switching signal to not be lower than a preset negative voltage, thereby preventing the body diode of the first transistor from forward conducting or reducing the reverse recovery charge of the body diode.

Description

Technical Field

[0001] This invention relates to a control circuit, and more particularly to a control circuit for reducing reverse recovery charge in a switching converter. This invention also relates to a control method for reducing reverse recovery charge in a switching converter. Prior Technology

[0002] Figure 1A shows a prior art switching converter. As shown in Figure 1A, control signals SH and SL generate non-overlapping switching drive signals DRVH and DRVL via logic circuitry, which control the switching of the upper-bridge transistor 42 and the lower-bridge transistor 41, respectively. When the upper-bridge transistor 42 is turned on, the input voltage VIN magnetizes the inductor 30 and charges the output capacitor via the switching node LX, thereby generating the output voltage VO. When the upper-bridge transistor 42 is turned off, the lower-bridge transistor 41 is turned on under the control of the switching drive signal DRVL, the inductor 30 is demagnetized, and its current can freewheel through the lower-bridge transistor 41.

[0003] Figure 1B shows the operating waveforms of a prior art switching converter. As shown in Figure 1B, during the dead time DT before the start of the next switching cycle, both the upper bridge transistor 42 and the lower bridge transistor 41 are in the off state, causing the current in the inductor 30 to flow through the body diode 43 inside the lower bridge transistor 41. During the dead time DT, the voltage VLX of the switching node LX drops to the difference between zero voltage and the forward conduction voltage Vf of the body diode 43 (e.g., -0.7V). When the next switching cycle begins, the upper bridge transistor 42 is turned on by the switching drive signal DRVH, at which point the body diode 43 must switch from forward conduction to the off state, generating a large amount of reverse recovery charge (Qrr) during the process. The reverse recovery current and the parasitic inductance together form a resonant circuit, causing a voltage spike on the switching node LX. This voltage spike may even exceed the maximum rated voltage of the upper bridge transistor 42 and the lower bridge transistor 41 or other related components, thus causing system reliability problems or even damaging the devices.

[0004] The prior art switching converter 1001 suppresses voltage spikes at the switching node LX using a filter circuit composed of capacitor 81 and resistor 82. However, although the filter circuit can absorb some parasitic oscillation energy and reduce the spike voltage, power loss occurs because capacitor 81 needs to be charged and discharged during each switching cycle, and its energy is ultimately dissipated as heat by resistor 82. The amount of power loss is related to the capacitance of capacitor 81, the input voltage VIN, and the switching frequency, and it continues to generate power loss even under no-load conditions. In addition, the parasitic inductance 91 also resonates with the filter circuit, affecting the filtering effect, resulting in limited suppression and an inability to effectively eliminate high-frequency noise and voltage spikes generated by the reverse recovery of the body diode.

[0005] In view of the above, to overcome the shortcomings of the prior art, the present invention proposes a control circuit for reducing reverse recovery charge in a switching converter. Compared to the prior art where the inductor current of the lower bridge transistor must flow through the main diode after being disabled during the idle time, leading to the accumulation of reverse recovery charge, the present invention, by having the gate of the lower bridge transistor simultaneously coupled to the driving circuit and the amplification circuit, and by continuously controlling the lower bridge transistor to conduct appropriately during the idle time through the amplification circuit, allows the inductor current to continuously flow through the main channel of the lower bridge transistor (rather than the main diode), thereby avoiding or reducing the accumulation of reverse recovery charge. Summary of the Invention

[0006] From one perspective, the present invention provides a control circuit for controlling a switching converter based on a pulse width modulation (PWM) signal. The switching converter includes a first transistor and a second transistor, both coupled to a switching node, for switching an inductor according to the PWM signal to convert an input voltage and generate an output voltage. The control circuit includes: a drive circuit for generating a switching drive signal based on the PWM signal and a switching signal at the switching node to switch the first transistor; and an amplifier circuit for amplifying the difference between the switching signal and a reference signal during a lag time to generate an amplified output signal. Furthermore, through a linear negative feedback operation, the first transistor is controlled to adjust the voltage of the switching signal to be no lower than a preset negative voltage, thereby preventing the forward conduction of the body diode of the first transistor or reducing the reverse recovery charge of the body diode.

[0007] In a preferred embodiment, the driving circuit is used to generate the switching driving signal according to a first control signal and a second control signal to switch the first transistor; wherein the first control signal is related to the pulse width modulation signal, and the second control signal is related to the switching signal; wherein during the idle time, the switching driving signal has a high output impedance, and the first transistor is dominated by the amplified output signal; wherein during a switching time other than the idle time, the switching driving signal has a low output impedance, and the first transistor is dominated by the switching driving signal.

[0008] In a preferred embodiment, the driving circuit includes a first switch and a second switch; wherein during an on-time of the switching time, the first switch controls the switching driving signal to be enabled according to the first control signal, thereby switching the first transistor to be on; wherein during a non-on-time of the switching time, the second switch controls the switching driving signal to be disabled according to the second control signal, thereby switching the first transistor to be off.

[0009] In a preferred embodiment, when the switching signal exceeds a preset threshold voltage, the second control signal controls the switching drive signal to be disabled, thereby switching the first transistor to be non-conductive.

[0010] In a preferred embodiment, a gate of the second switch is controlled by the second control signal, and the second control signal is coupled to the switching signal, wherein the preset threshold voltage corresponds to a conduction threshold voltage of the second switch.

[0011] In a preferred embodiment, the control circuit further includes: a clamping circuit for generating the second control signal according to the switching signal, and for clamping the second control signal so that it is not greater than a clamping voltage level.

[0012] In a preferred embodiment, the clamping voltage level is lower than the maximum rated voltage of the second switch.

[0013] In a preferred embodiment, the control circuit further includes: a high-pass filter circuit coupled between the clamping circuit and the second control signal, used to filter the switching signal to generate the second control signal, thereby enabling the second switch to disable the switching drive signal when the switching signal has a high-frequency component, thereby switching the first transistor to non-conducting.

[0014] In a preferred embodiment, after the first transistor switches to non-conducting mode, the amplifier circuit controls the amplified output signal to remain disabled based on the difference between the switching signal and the reference signal, so that the first transistor remains non-conducting.

[0015] In a preferred embodiment, the absolute value of the preset negative voltage is less than a forward conduction voltage of the body diode of the first transistor.

[0016] In a preferred embodiment, the amplifier circuit includes a common-base amplifier or a common-gate amplifier and has an input offset voltage, wherein the input offset voltage is related to the preset negative voltage.

[0017] In a preferred embodiment, the amplified output signal is clamped to a level not lower than a preset level, which is higher than a turn-on threshold voltage of the first transistor.

[0018] In a preferred embodiment, the amplification circuit includes a pull-down transistor and a clamping transistor, which are connected in series to the amplified output signal. The pull-down transistor is used to provide a pull-down driving force for the amplified output signal based on the difference between the switching signal and the reference signal. The clamping transistor is configured as a diode-coupled transistor.

[0019] From another perspective, the present invention provides a control method for controlling a switching converter based on a pulse width modulation (PWM) signal. The switching converter includes a first transistor and a second transistor, both coupled to a switching node, for switching an inductor according to the PWM signal to convert an input voltage and generate an output voltage. The control method includes: generating a switching drive signal based on the PWM signal and a switching signal at the switching node to switch the first transistor; and amplifying the difference between the switching signal and a reference signal during a lag time to generate an amplified output signal. The step of generating the amplified output signal includes: controlling the first transistor via a linear negative feedback operation to adjust the voltage of the switching signal to be no lower than a preset negative voltage, thereby preventing the forward conduction of a body diode of the first transistor or reducing the reverse recovery charge of the body diode.

[0020] The following detailed description, through specific embodiments, will make it easier to understand the purpose, technical content, features, and effects achieved by the present invention. Simple Explanation of the Diagram

[0021] Figure 1A shows a prior art switching converter.

[0022] Figure 1B shows the operating waveforms of a prior art switching converter.

[0023] Figures 2A and 2B show block diagrams of the switching converter in two embodiments of the present invention.

[0024] Figures 3A to 3C show schematic diagrams of a switching converter in various specific embodiments of the present invention.

[0025] Figure 4 shows the operation waveform of the switching converter in one embodiment of the present invention.

[0026] Figure 5 shows the operation waveform of the switching converter in another embodiment of the present invention.

[0027] Figure 6 shows a schematic diagram of the amplifier circuit in one specific embodiment of the present invention.

[0028] Figures 7A to 7G show various embodiments of the power stage circuit of the switching converter of the present invention. Implementation

[0029] The diagrams in this invention are illustrative and primarily intended to show the coupling relationships between circuits and the relationships between signal waveforms. The circuits, signal waveforms, and frequencies are not drawn to scale. For clarity, many practical details will be described in the following description, but this is not intended to limit the scope of the patent application.

[0030] Figures 2A and 2B show block diagrams of the switching converter in two embodiments of the present invention. In one embodiment, the switching converter of the present invention can be configured as the switching converter 2002A as shown in Figure 2A, and in another embodiment, the switching converter of the present invention can be configured as the switching converter 2002B as shown in Figure 2B. As shown in Figure 2A, in one embodiment, the switching converter 2002A includes a first transistor ML and a second transistor MH, which are coupled together to a switching node SW to switch the inductor 30 according to the pulse width modulation signal SPW to convert the input voltage VIN and generate the output voltage VO. In one embodiment, the control circuit 3002A is used to control the first transistor ML and the second transistor MH of the switching converter 2002A according to the pulse width modulation signal SPW. In this embodiment, both the first transistor ML and the second transistor MH are N-type metal oxide semiconductor (MOS) transistors.

[0031] In one embodiment, the control circuit 3002A includes a drive circuit 100 and an amplifier circuit 200. The drive circuit 100 generates a switching drive signal DRVL based on the pulse width modulation signal SPW and the switching signal VSW on the switching node SW to switch the first transistor ML. The amplifier circuit 200 amplifies the difference between the switching signal VSW and the reference signal Vref during the idle time to generate an amplified output signal VOA, and controls the first transistor ML through linear negative feedback operation to adjust the voltage of the switching signal VSW to not be lower than a preset negative voltage, thereby preventing the forward conduction of the body diode DL of the first transistor ML, or reducing the reverse recovery charge of the body diode DL. In this embodiment, the switching drive signal DRVL and the amplified output signal VOA are both coupled to the gate GL of the first transistor ML.

[0032] It should be noted that during the aforementioned idle time, the first transistor ML operates in the saturation or linear region under the control of the amplified output signal VOA to adjust the voltage of the switching signal VSW, while the second transistor MH remains non-conductive. It should also be noted that in one embodiment, the absolute value of the aforementioned preset negative voltage is less than the forward conduction voltage of the body diode DL of the first transistor ML (e.g., 0.7V), thereby preventing the body diode DL of the first transistor ML from conducting forward. It is important to note that even if some forward conduction current still occurs in the body diode DL, its reverse recovery charge can still be effectively reduced due to the aforementioned control.

[0033] Please refer to Figure 2A. In one embodiment, the drive circuit 100 generates a switching drive signal DRVL based on a first control signal Ctrl1 and a second control signal Ctrl2 to switch the first transistor ML. In this embodiment, the first control signal Ctrl1 is related to the pulse width modulation signal SPW, and the second control signal Ctrl2 is related to the switching signal VSW.

[0034] It should be noted that the configuration of the switching converter 2002B in Figure 2B is largely the same as that of the switching converter 2002A in Figure 2A. The difference lies in that one input terminal of the amplifier circuit 200 in Figure 2A is directly coupled to the switching signal VSW, while this input terminal of the amplifier circuit 200 in Figure 2B is coupled to one input terminal of the driver circuit 100. Details will be described in detail in subsequent embodiments, and those skilled in the art can infer them from the description of Figure 2A and the following specific embodiments.

[0035] Figures 3A to 3C show schematic diagrams of switching converters in various specific embodiments of the present invention. Figure 4 shows an operational waveform diagram of a switching converter in one embodiment of the present invention. The switching converter 2003A in Figure 3A corresponds to a specific embodiment of the switching converter 2002A in Figure 2A. In one embodiment, as shown in Figure 3A, the control circuit 3003A further includes: a clamping circuit 300 and a non-overlapping circuit 400. In one embodiment, the pulse width modulation signal SPW includes signals SPH and SPL, and the non-overlapping circuit 400 includes complex logic gates to generate a non-overlapping switching drive signal DRVH and a first control signal Ctrl1 (and thus generate a switching drive signal DRVL) according to signals SPH and SPL, respectively, to control the second transistor MH and the first transistor ML.

[0036] In one embodiment, the clamping circuit 300 generates a second control signal Ctrl2 based on the switching signal VSW, and clamps the second control signal Ctrl2 so that it is not greater than a clamping voltage level. In a specific embodiment, the clamping circuit 300 includes a clamping transistor N2, which is an NMOS transistor whose gate is controlled by a DC voltage VDC. In this embodiment, the clamping voltage level is the difference between the DC voltage VDC and the turn-on threshold voltage of the clamping transistor N2. The clamping voltage level is lower than the maximum rated voltage of the second switch N1, thereby preventing the gate voltage of the second switch N1 from exceeding its maximum rated voltage and being damaged.

[0037] Please refer to Figure 3A. In one embodiment, the driving circuit 103 includes a first switch P1 and a second switch N1, which are sequentially connected in series between the driving voltage VDRV and the ground potential. In this embodiment, the first switch P1 is a PMOS transistor and the second switch N1 is an NMOS transistor, and their gates are controlled by the first control signal Ctrl1 and the second control signal Ctrl2, respectively.

[0038] Please refer to Figures 3A and 4 simultaneously. In one embodiment, as shown in Figure 4, during the on-time TON of the switching time, the first switch P1 controls the switching drive signal DRVL to be enabled according to the first control signal Ctrl1, that is, at this time the switching drive signal DRVL has a high level (in this embodiment, for example, the drive voltage VDRV), thereby switching the first transistor ML to be on. In one embodiment, during the off-time TOFF of the switching time, the second switch N1 controls the switching drive signal DRVL to be disabled according to the second control signal Ctrl2, that is, at this time the switching drive signal DRVL has a low level (in this embodiment, for example, the ground potential), thereby switching the first transistor ML to be off.

[0039] It should be noted that the switching time mentioned above refers to the time other than the idle time DT, including the on-time TON and the off-time TOFF. It should also be noted that during the aforementioned switching time, the first transistor ML and the second transistor MH switch complementaryly according to the control circuit 3003A. Furthermore, the on-time TON and off-time TOFF in this paper correspond to the on and off states of the first transistor ML, respectively.

[0040] In one embodiment, when the switching signal VSW exceeds a preset threshold voltage Vth (as shown at time t2 in Figure 4), the second control signal Ctrl2 is enabled to control the second switch N1 to conduct, thereby disabling the switching drive signal DRVL, and thus switching the first transistor ML to non-conducting. In the embodiment shown in Figure 3B, the preset threshold voltage Vth corresponds to the conduction threshold voltage of the second switch N1. When the voltage of the second control signal Ctrl2 exceeds the preset threshold voltage Vth along with the switching signal VSW, the second switch N1 is turned on. In this embodiment, the preset threshold voltage Vth is greater than 0. From one perspective, when the idle time DT ends and the switching drive signal DRVH controls the second transistor MH to turn on (as shown at time t1 in Figure 4), the level of the switching signal VSW gradually increases. When the level of the switching signal VSW increases to exceed the preset threshold voltage Vth, the first transistor ML turns off by the control of the switching drive signal DRVL. Since the body diode DL of the first transistor ML is not forward-biased during the idle time DT, the voltage spike caused by the reverse recovery charge of the body diode DL can be avoided or reduced during this transition process, and the time of this state transition can be greatly shortened.

[0041] In one embodiment, the switching signal VSW is coupled to the negative input terminal of the amplifier circuit 203. In one embodiment, during the idle time DT of FIG4, the amplifier circuit 203 amplifies the difference between the switching signal VSW and the reference signal Vref to generate an amplified output signal VOA, and controls the first transistor ML through linear negative feedback operation to adjust the voltage of the switching signal VSW to be no lower than a preset negative voltage. In this embodiment, the absolute value of the preset negative voltage is less than the forward conduction voltage (e.g., 0.7V) of the body diode DL of the first transistor ML, thereby preventing the body diode DL of the first transistor ML from conducting forward or reducing the reverse recovery charge of the body diode DL.

[0042] It should be noted that, in one embodiment, during the idle time DT, the switching drive signal DRVL has a high output impedance (both the first switch P1 and the second switch N1 are not conducting), and the gate GL of the first transistor ML is controlled by the amplified output signal VOA. In the embodiment of FIG3A, during the switching time other than the idle time DT (including the on time TON and the off time TOFF), the switching drive signal DRVL has a low output impedance (one of the first switch P1 and the second switch N1 is conducting). Therefore, during the switching time other than the idle time DT, the gate GL of the first transistor ML is controlled by the switching drive signal DRVL.

[0043] The switching converter 2003B in Figure 3B is a specific embodiment corresponding to the switching converter 2002B in Figure 2B. The control circuit 3003B is similar to the control circuit 3003A. The difference lies in that, in one embodiment, as shown in Figure 3B, the negative input terminal of the amplifier circuit 203 is coupled together with the second control signal Ctrl2 to the clamping circuit 300. In this embodiment, the clamping circuit 300 is further used to clamp the negative input terminal of the amplifier circuit 203, ensuring it does not exceed the clamping voltage level, thereby preventing the amplifier circuit 203 from exceeding its maximum rated voltage and being damaged. Other operational details of Figure 3B can be deduced from the descriptions of Figures 3A and 4 above.

[0044] The switching converter 2003C in Figure 3C corresponds to another specific embodiment of the switching converter 2002B in Figure 2B. In one embodiment, as shown in Figure 3C, the control circuit 3003C further includes a high-pass filter circuit 500 coupled between the clamping circuit 300 and the second control signal Ctrl2. This filter circuit 500 filters the switching signal VSW to generate the second control signal Ctrl2. This allows a high-pass pulse to be generated in the second control signal Ctrl2 when the switching signal VSW has high-frequency components, rapidly controlling the second switch N1 to turn on, thus disabling the switching drive signal DRVL (e.g., low level). This, in turn, disables the first transistor ML. In one embodiment, the amplifier circuit 203 simultaneously controls the amplified output signal VOA to remain disabled based on the difference between the switching signal VSW and the reference signal Vref, thus keeping the first transistor ML non-conducting.

[0045] Please refer to Figures 3C and 5 simultaneously. Figure 5 shows the operating waveform of the switching converter in another embodiment of the present invention. In a specific embodiment, at time t3 in Figure 5, the level of the switching signal VSW rises rapidly. At this time, the second control signal Ctrl2 generates a pulse to control the second switch N1 to disable the switching drive signal DRVL, thereby switching the first transistor ML to non-conducting. After the first transistor ML is switched to non-conducting, the first transistor ML remains in a non-conducting state according to the control of the amplified output signal VOA.

[0046] It should be noted that, in the embodiment shown in Figure 3C, the second control signal Ctrl2 controls the second switch N1 to turn on in pulse form at time t3, causing the switching drive signal DRVL to turn off, thereby controlling the first transistor ML to turn off. Then, the amplified output signal VOA controls the first transistor ML to remain off. In this embodiment, during the off-time TOFF of the switching time, after the pulse of the aforementioned second control signal Ctrl2 ends, the switching drive signal DRVL has a high output impedance, and then the gate GL of the first transistor ML is mainly controlled by the amplified output signal VOA.

[0047] Figure 6 shows a schematic diagram of an amplifier circuit in one specific embodiment of the present invention. In one embodiment, the amplifier circuit of the present invention includes a common-base amplifier or a common-gate amplifier and has an input offset voltage, wherein the input offset voltage is related to a preset negative voltage. In this embodiment, as shown in Figure 6, the amplifier circuit 205 includes a common-base amplifier 25, which includes transistors B1 and B2 (e.g., both NPN bipolar transistors), whose emitters are respectively coupled to ground potential and switching signal VSW. It should be noted that in this embodiment, the reference signal Vref is physically coupled to ground potential, and the current density of transistor B1 is less than the current density of transistor B2, so that the common-base amplifier 25 has an input offset voltage configured based on the preset negative voltage, thereby adjusting the switching signal VSW to not be lower than the preset negative voltage, so as to avoid the forward conduction of the body diode DL of the first transistor ML, or reduce the reverse recovery charge of the body diode DL.

[0048] It should also be noted that the current density of transistor B1 is lower than that of transistor B2, which can be achieved, for example, through the design of the following specific embodiments. In one embodiment, the area ratio of transistors B1 and B2 is m:n (m and n are greater than 0). When the currents IB1 and IB2 flowing through transistors B1 and B2 are equal, the size ratio of transistors B1 and B2 can be configured such that m is greater than n, making the current density of transistor B1 lower than that of transistor B2. In another embodiment, when the areas of transistors B1 and B2 are the same (i.e., m=n), the current IB1 flowing through transistor B1 can be configured to be less than the current IB2 flowing through transistor B2, making the current density of transistor B1 lower than that of transistor B2. In other embodiments, the above-mentioned area ratio and current ratio relationship can also be combined to achieve a difference in current density.

[0049] In one embodiment, as shown in FIG6, the amplifier circuit 205 includes a pull-down transistor N3 and a clamping transistor D1, which are connected in series from the amplified output signal VOA to ground potential. In this embodiment, the clamping transistor D1 is configured as a diode-coupled transistor. In one embodiment, the pull-down transistor N3 is used to provide a pull-down driving force for the amplified output signal VOA according to the difference between the switching signal VSW and the reference signal Vref, and the clamping transistor D1 is used to clamp the amplified output signal VOA to a level not lower than a preset level. In this embodiment, the preset level is higher than the conduction threshold voltage of the first transistor ML. Specifically, in this embodiment, by clamping the amplified output signal VOA to a level not lower than the conduction threshold voltage of the first transistor ML, the timing when the first transistor ML turns off is controlled by the second switch N1 of the drive circuit 103. It should be noted that this embodiment specifically corresponds to the embodiments of FIG3A and FIG3B.

[0050] Figures 7A to 7G illustrate various embodiments of the power stage circuit of the switching converter of the present invention. The power stage circuit of the switching converter of the present invention includes at least one switch and an inductor coupled to each other, wherein the at least one switch switches the inductor according to a control signal to convert the input power supply into the output power supply. As shown in Figures 7A to 7G, the power stage circuit of the present invention includes, for example, but not limited to, a synchronous buck converter, a synchronous boost converter, a buck-boost converter, a half-bridge flyback converter, or a full-bridge or half-bridge switched resonant converter.

[0051] In summary, according to the present invention, during the switching time, the conduction state of the lower bridge transistor is controlled by the driving circuit; while during the idle time, the switching driving signal switches to a high-impedance state, and the conduction state of the lower bridge transistor is controlled by the amplification circuit, so that the switching signal at the switching node is adjusted to not lower than a preset negative voltage, avoiding forward conduction of the lower bridge transistor's body diode or reducing its reverse recovery charge. Furthermore, when the upper bridge transistor is turned on, the driving circuit turns off the lower bridge transistor to switch it to a non-conducting state, further suppressing voltage spikes and EMI noise. With this design, the present invention can effectively avoid voltage spike problems caused by the reverse recovery of the body diode, and eliminates the need for energy-consuming filtering circuits in the prior art, further improving overall power efficiency.

[0052] The present invention has been described above with reference to preferred embodiments. However, the above description is only for the purpose of enabling those skilled in the art to easily understand the content of the present invention and is not intended to limit the scope of the present invention. The various embodiments described are not limited to individual applications and can also be combined. For example, two or more embodiments can be used in combination, and some components in one embodiment can be used to replace corresponding components in another embodiment. Furthermore, under the same spirit of the present invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the present invention's statement of "processing or calculating based on a signal or generating an output result" is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, under the same spirit of the present invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many combinations, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

[0053] 25: Common-base amplifier 30: Inductor 41: Lower bridge transistor 42: Upper bridge transistor 43: Solid Diode 81: Capacitor 82: Resistor 91: Parasitic inductance 100, 103: Drive circuit 200, 203, 205: Amplifier circuits 300: Clamping circuit 400: Non-overlapping circuit 500: High-pass filter circuit 1001, 2002A, 2002B, 2003A, 2003B, 2003C: Switching converters 3002A, 3002B, 3003A, 3003B, 3003C: Control circuit B1, B2: Transistors Ctrl1, Ctrl2: Control signals D1: Clamping transistor DL: Body Diode DRVH, DRVL: Switching drive signals DT: Lag Time GL: Gate LX: Switch Node MH: Second Transistor ML: First Transistor N1: Second switch N2: Clamping transistor N3: Pull-down transistor P1: First switch SH,SL: Control signals SPH, SPL: Signals SPW: Pulse Width Modulation Signal SW: Switch Node t1, t2, t3: Time points TOFF: Non-conducting time TON: On-time VDC: DC voltage VDRV: Drive voltage Vf: Forward conduction voltage VIN: Input voltage VLX: Switching the voltage of node LX VO: Output voltage VOA: Amplify Output Signal Vref: Reference signal VSW: Switching Signals Vth: Preset threshold voltage

Claims

1. A control circuit for controlling a switching converter according to a pulse width modulation (PWM) signal, wherein the switching converter includes a first transistor and a second transistor, both coupled to a switching node, for switching an inductor according to the PWM signal to convert an input voltage to generate an output voltage, the control circuit comprising: a drive circuit for generating a switching drive signal according to the PWM signal and a switching signal at the switching node to switch the first transistor; and an amplifier circuit for amplifying the difference between the switching signal and a reference signal during a lag time to generate an amplified output signal that dominates the control of a gate of the first transistor, thereby adjusting the voltage of the switching signal to be not lower than a preset negative voltage in a linear negative feedback manner.

2. The control circuit as claimed in claim 1, wherein the drive circuit is configured to generate the switching drive signal according to a first control signal and a second control signal to switch the first transistor; wherein the first control signal is related to the pulse width modulation signal, and the second control signal is related to the switching signal; wherein during the idle time, the switching drive signal has a high output impedance, and the first transistor is dominated by the amplified output signal; wherein during a switching time other than the idle time, the switching drive signal has a low output impedance, and the first transistor is dominated by the switching drive signal.

3. The control circuit as described in claim 2, wherein the drive circuit includes a first switch and a second switch; wherein during an on-time of the switching time, the first switch enables the switching drive signal according to the first control signal, thereby switching the first transistor to be on; wherein during a non-on-time of the switching time, the second switch disables the switching drive signal according to the second control signal, thereby switching the first transistor to be off.

4. The control circuit as described in claim 3, wherein when the switching signal exceeds a preset threshold voltage, the second control signal controls the switching drive signal to be disabled, thereby switching the first transistor to be non-conductive.

5. The control circuit as claimed in claim 4, wherein a gate of the second switch is controlled by the second control signal, and the second control signal is coupled to the switching signal, wherein the preset threshold voltage corresponds to a conduction threshold voltage of the second switch.

6. The control circuit as described in claim 3 further includes: a clamping circuit for generating the second control signal according to the switching signal, and for clamping the second control signal so that it is not greater than a clamping voltage level.

7. The control circuit as described in claim 6, wherein the clamping voltage level is lower than the maximum rated voltage of the second switch.

8. The control circuit as described in claim 6 further includes: a high-pass filter circuit coupled between the clamping circuit and the second control signal, used to high-pass filter the switching signal to generate the second control signal, thereby enabling the second switch to disable the switching drive signal when the switching signal has a high-frequency component, thereby switching the first transistor to non-conducting.

9. The control circuit as described in claim 8, wherein after the first transistor switches to non-conducting, the amplifier circuit controls the amplified output signal to remain disabled based on the difference between the switching signal and the reference signal, so that the first transistor remains non-conducting.

10. The control circuit as claimed in claim 1, wherein the absolute value of the preset negative voltage is less than a forward conduction voltage of a body diode of the first transistor.

11. The control circuit as claimed in claim 1, wherein the amplification circuit includes a common-base amplifier or a common-gate amplifier and has an input offset voltage, wherein the input offset voltage is related to the preset negative voltage.

12. The control circuit as claimed in claim 1, wherein the amplified output signal is clamped at a level not lower than a preset level, the preset level being higher than a turn-on threshold voltage of the first transistor.

13. The control circuit as claimed in claim 12, wherein the amplification circuit includes a pull-down transistor and a clamping transistor connected in series to the amplified output signal, wherein the pull-down transistor is used to provide a pull-down driving force for the amplified output signal based on the difference between the switching signal and the reference signal, wherein the clamping transistor is configured as a diode-coupled transistor.

14. A control method for controlling a switching converter according to a pulse width modulation (PWM) signal, wherein the switching converter includes a first transistor and a second transistor, both coupled to a switching node, for switching an inductor according to the PWM signal to convert an input voltage to generate an output voltage, the control method comprising: generating a switching drive signal based on the PWM signal and a switching signal at the switching node to switch the first transistor; amplifying the difference between the switching signal and a reference signal during a lag time to generate an amplified output signal; and using the amplified output signal to control a gate of the first transistor, adjusting the voltage of the switching signal to be not lower than a preset negative voltage via a linear negative feedback method.

15. The control method as described in claim 14, wherein the step of generating the switching drive signal includes: The switching drive signal is generated based on a first control signal and a second control signal to switch the first transistor; The first control signal is related to the pulse width modulation signal, and the second control signal is related to the switching signal; During the idle time, the switching drive signal has a high output impedance, and the first transistor is controlled by the amplified output signal; during a switching time other than the idle time, the switching drive signal has a low output impedance, and the first transistor is controlled by the switching drive signal.

16. The control method as described in claim 15, wherein the step of generating the switching drive signal includes: During one conduction period of the switching time, the switching drive signal is enabled according to the first control signal, thereby switching the first transistor to conduct. And during a non-conducting period in the switching time, the switching drive signal is disabled according to the second control signal, thereby switching the first transistor to non-conducting.

17. The control method as described in claim 16, wherein the step of generating the switching drive signal includes: When the switching signal exceeds a preset threshold voltage, the switching drive signal is controlled to be disabled, thereby switching the first transistor to be non-conductive.

18. The control method as described in claim 15 further comprises: generating the second control signal based on the switching signal, and clamping the second control signal to a level not exceeding a clamping voltage level.

19. The control method as described in claim 18 further comprises: high-pass filtering the switching signal to generate the second control signal; and when the switching signal has a high-frequency component, controlling the switching drive signal to be disabled, thereby switching the first transistor to be non-conductive.

20. The control method as described in claim 19, wherein the step of generating the amplified output signal includes: After the first transistor turns off, the amplified output signal is controlled to remain disabled based on the difference between the switching signal and the reference signal, so that the first transistor remains off.

21. The control method as described in claim 14, wherein the absolute value of the preset negative voltage is less than a forward conduction voltage of a body diode of the first transistor.

22. The control method as described in claim 14, wherein the step of generating the amplified output signal includes: The amplified output signal is clamped to a level not lower than a preset level, which is higher than a turn-on threshold voltage of the first transistor.

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