Semiconductor structures and methods of fabrication thereof

Abstract

The embodiments of this disclosure provide a method for forming a channel stack of a multichannel device using laser recrystallization technology. By using laser recrystallization, the sacrificial layer in the channel stack can be an oxide layer rather than an epitaxial layer, i.e., a SiGe sacrificial layer. By avoiding the SiGe sacrificial layer, Ge segregation to adjacent semiconductor channel layers during thermal processing can be reduced. The tensile strain caused by the SiGe sacrificial layer to these Si channel layers can also be reduced. Furthermore, the embodiments of this disclosure allow the p-channels and n-channels in these CFETs to have different crystal orientations, thereby improving device performance.

Description

Technical Field

[0001] none Prior Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with circuits that are smaller and more complex than the previous generation. In IC development, functional density (i.e., the number of interconnects per wafer area) typically increases, while geometry (i.e., the smallest components or lines that can be produced using manufacturing processes) decreases. This scaling down process usually yields benefits through increased production efficiency and reduced associated costs.

[0003] The pursuit of higher device density, higher performance, and lower cost has led to manufacturing and design challenges that have driven the development of three-dimensional designs, such as multi-gate field-effect transistors (FETs), including nanosheet FETs. In nanosheet FETs, all sides of the channel are surrounded by gate electrodes, which allows for more complete depletion within the channel, thereby reducing short-channel effects and achieving better gate control. As transistor dimensions continue to shrink, further improvements to nanosheet FETs are needed. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figures 1A through 1P schematically illustrate the various stages of manufacturing vertically stacked complementary field-effect transistors (CFETs) according to some embodiments of this disclosure. Figures 2A and 2B schematically illustrate the cross-channel semiconductor composition profile in a multichannel transistor according to an embodiment of the present disclosure. Figures 3A through 3D schematically illustrate the various stages of fabricating vertically stacked complementary field-effect transistors (CFETs) according to some embodiments of this disclosure. Figures 4A through 4I schematically illustrate the various stages of fabricating vertically stacked complementary field-effect transistors (CFETs) according to some embodiments of this disclosure. Figures 5A through 5E schematically illustrate the various stages of manufacturing a gate-all-around field-effect transistor according to an embodiment of this disclosure. Figures 6A through 6C schematically illustrate the various stages of manufacturing a gate-all-around field-effect transistor according to an embodiment of this disclosure. Implementation

[0006] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0007] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0008] Although the embodiments of this disclosure discuss nanostructured channel FETs, some implementations of this disclosure can be used in other processes and / or other devices, such as planar FETs, FinFETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. Other modifications that may be considered within the scope of this disclosure will be readily understood by those skilled in the art. In the case of a gate all around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern these structures, including dual patterning processes or multiple patterning processes. Typically, dual patterning processes or multiple patterning processes combine lithography processes and self-alignment processes to allow the creation of patterns, for example, patterns with a pitch smaller than that obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along a patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA structure.

[0009] Embodiments of this disclosure provide a method for forming a channel stack, the channel stack including alternating semiconductor channel layers and sacrificial layers, for multi-channel devices, such as vertically stacked complementary field-effect transistors (CFETs), non-stacked CFETs, etc. Specifically, embodiments of this disclosure provide a channel stack including epitaxial semiconductor channel layers formed using solid-state epitaxial recrystallization technology.

[0010] Figures 1A through 1P schematically illustrate various stages of fabricating a semiconductor structure 200 according to some embodiments of the present disclosure, the semiconductor structure 200 including channel stacks for vertically stacked complementary field-effect transistors (CFETs). Figures 1A through 1J are cross-sectional views of the semiconductor structure 200 at various stages.

[0011] Figure 1A is a schematic cross-sectional view of substrate 202, on which channel stacks will be formed. Substrate 202 may be a semiconductor substrate for forming semiconductor devices thereon. Substrate 202 may include single-crystal semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, substrate 202 is made of silicon. In some embodiments, substrate 202 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one embodiment, the insulating layer is an oxygen-containing layer.

[0012] In some embodiments, substrate 202 may comprise a single-crystal semiconductor material, and the front surface 202f of substrate 202 has a crystal orientation selected to achieve a desired mobility in the channel to be formed. In some embodiments, the crystal orientation of substrate 202 is selected to achieve the maximum mobility of the corresponding FET to be formed thereon. For example, the front surface 202f of substrate 202 is located on the (110) plane to achieve improved hole mobility, or on the (100) plane to achieve improved electron mobility. In some embodiments, substrate 202 is a crystalline silicon substrate, and the front surface 202f is located on the (100) plane.

[0013] In some embodiments, the stacked cavity 204 is formed from the front surface 202f of the substrate 202. The stacked cavity 204 is sized to have channel stacking within it. In some embodiments, the stacked cavity 204 may have a rectangular shape in a top view or xy plane. In some embodiments, the stacked cavity 204 may have a length along the x-direction ranging from about 500 nm to about 5000 nm, and a width along the y-direction (into the plane of the paper in Figure 1A) ranging from about 500 nm to about 5000 nm. The stacked cavity 204 may have a depth along the z-direction ranging from about 60 nm to 200 nm.

[0014] The stacked cavity 204 has a bottom surface 204b and sidewalls 204s. The bottom surface 204b has the same crystal orientation as the front surface 202f. As described below, the sidewalls 204s can be used as a seed layer for recrystallization of the channel layer to be formed. In some embodiments, the sidewalls 204s can be oriented so that the channel layer can crystallize in a predetermined crystal orientation. For example, the sidewalls 204s parallel to the xz plane are in a (100) crystal orientation, while the sidewalls 204s parallel to the yz plane are in a (110) crystal orientation.

[0015] In Figure 1B, a first sacrificial layer 205 is formed on the bottom surface 204b of the stacking cavity 204. In some embodiments, the first sacrificial layer 205 may comprise an oxide material, such as silicon oxide (SiO2). The first sacrificial layer 205 is used to define the space around the gate stack around the channel region and is eventually removed. In some embodiments, the thickness of the first sacrificial layer 205 along the z-direction is in the range of about 3 nm to about 10 nm. The first sacrificial layer 205 may be deposited by any suitable process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. In some embodiments, the first sacrificial layer 205 is formed by bottom-up deposition such that the sidewalls 204s above the first sacrificial layer 205 remain exposed to the stacking cavity 204.

[0016] Further, as shown in Figure 1B, a first channel layer 206 is formed on the first sacrificial layer 205. The first channel layer 206 comprises a semiconductor material suitable for use as a channel layer. In some embodiments, the thickness of the first channel layer 206 along the z-direction is in the range of about 3 nm to about 15 nm. The first channel layer 206 comprises a semiconductor material such as Si, SiGe, Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof. In some embodiments, the first channel layer 206 is made of SiGe, wherein the Ge concentration ranges from about 15% to about 35%. The first channel layer 206 may be deposited in an amorphous form. The amorphous semiconductor deposition process can be performed in an LPCVD reactor at a temperature of about 360°C to 560°C, for example, about 400°C.

[0017] In some embodiments, the first channel layer 206 is formed by bottom-up deposition, as shown in Figure 1B. The first channel layer 206 is in contact with the sidewalls 204s of the stacked cavity 204. Therefore, the edge region of the first channel layer 206, which is formed in an amorphous form, is in contact with the crystalline surface of the substrate 202 at the sidewalls 204s.

[0018] After the formation of the amorphous first channel layer 206, a solid-phase epitaxial recrystallization (SPER) process is performed to convert the first channel layer 206 into a crystalline state, as shown in Figure 1C. In some embodiments, the SPER process is performed by a laser annealing process. In some embodiments, a laser source 203 is applied to the first channel layer 206 to rapidly raise the temperature of the first channel layer 206 to a temperature level between approximately 1200°C and approximately 1400°C. In some embodiments, the laser source 203 may pulse for a short duration, for example, in the range of approximately 100 ns to 500 ns, such as approximately 160 ns. By rapidly heating for a short duration, the first channel layer 206 is annealed to a crystalline state while still in a solid phase, denoted as first channel layer 206a.

[0019] Since the first channel layer 206 is in contact with the sidewall 204s, the crystal structure of the substrate 202 on the sidewall 204s serves as a seed layer for the recrystallization of the first channel layer 206a. Therefore, the crystal orientation of the first channel layer 206a can be the same as that of the substrate 202.

[0020] Depending on the number of channels in the device structure, additional pairs of first sacrificial layers 205 and first channel layers 206a may be formed in the stack cavity 204, as shown in Figure 1D. The same process, namely, depositing the first sacrificial layer 205, depositing the first channel layer 206, and recrystallizing SPER, can be repeated to form each pair of first sacrificial layers 205 and first channel layers 206a. These pairs of first sacrificial layers 205 and first channel layers 206a form a first channel stack 212. In Figure 1D, two pairs of first sacrificial layers 205 and first channel layers 206a are shown as an example in the first channel stack 212. In some embodiments, the first channel stack 212 may include two to ten pairs of first sacrificial layers 205 and first channel layers 206a.

[0021] As described above, the semiconductor structure 200 to be formed includes a complementary FET (CFET), wherein two or more nanosheet FETs are vertically stacked together. The first sacrificial layer 205 and the first channel layer 206a are designated for a first type of FET, such as a P-FET.

[0022] In Figure 1E, a first sacrificial layer 205 and an inter-transistor dielectric layer 210 are formed over the first sacrificial layer 205 and the first channel layer 206a. The inter-transistor dielectric layer 210 serves to isolate the gate structure surrounding the first channel layer 206a from the gate structure above it. In some embodiments, the inter-transistor dielectric layer 210 may be a low-k dielectric material with etch selectivity to the first sacrificial layer 205. In some embodiments, the inter-transistor dielectric layer 210 may include silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon oxide, silicon nitride, etc. In some embodiments, the inter-transistor dielectric layer 210 may be formed by a suitable deposition method, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), etc. In some embodiments, the thickness of the inter-transistor dielectric layer 210 along the z-direction is in the range of about 3 nm to about 15 nm.

[0023] After the inter-transistor dielectric layer 210 is formed, two or more pairs of second sacrificial layers 207 and second channel layers 208 may be formed sequentially above the inter-transistor dielectric layer 210, as shown in Figure 1F, Figure 1G and Figure 1H.

[0024] In Figure 1F, a second sacrificial layer 207 is formed on the inter-transistor dielectric layer 210. In some embodiments, the second sacrificial layer 207 may comprise an oxide material, such as silicon oxide (SiO2). In some embodiments, the second sacrificial layer 207 and the first sacrificial layer 205 comprise the same material. The second sacrificial layer 207 is used to define a space for gate stacking around the second channel layer 208 and is eventually removed. In some embodiments, the thickness of the second sacrificial layer 207 along the z-direction is in the range of about 3 nm to about 10 nm. The second sacrificial layer 207 may be deposited by any suitable process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. In some embodiments, the second sacrificial layer 207 is formed by bottom-up deposition such that the sidewalls 204s above the second sacrificial layer 207 remain exposed to the stacking cavity 204.

[0025] Further, as shown in Figure 1F, a second channel layer 208 is formed on the second sacrificial layer 207. The second channel layer 208 comprises a semiconductor material suitable for use as a channel layer. In some embodiments, the thickness of the second channel layer 208 along the z-direction is in the range of about 3 nm to about 15 nm. The second channel layer 208 comprises a semiconductor material such as Si, SiGe, Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof. In some embodiments, the second channel layer 208 is made of silicon. The second channel layer 208 may be deposited in an amorphous form. The amorphous semiconductor deposition process can be performed in an LPCVD reactor at a temperature between about 360°C and 560°C, for example, about 400°C.

[0026] In some embodiments, the second channel layer 208 is formed by bottom-up deposition, as shown in Figure 1F. The second channel layer 208 contacts the sidewalls 204s of the stacked cavity 204. Therefore, the edge region of the second channel layer 208, which is formed in an amorphous form, contacts the crystalline surface of the substrate 202 at the sidewalls 204s.

[0027] After the formation of the amorphous second channel layer 208, a solid-phase epitaxial recrystallization (SPER) process is performed to convert the second channel layer 208 into a crystalline state, as shown in Figure 1G. In some embodiments, the SPER process is performed by a laser annealing process. In some embodiments, a laser source 203 is applied to the second channel layer 208 to rapidly raise the temperature of the second channel layer 208 to a temperature level between approximately 1200°C and approximately 1400°C. In some embodiments, the laser source 203 may pulse for a short duration, for example, in the range of approximately 100 ns to 500 ns, such as approximately 160 ns. By rapidly heating for a short duration, the second channel layer 208 is annealed to a crystalline state while still in a solid phase, denoted as second channel layer 208a.

[0028] Since the second channel layer 208 is in contact with the sidewall 204s, the crystal structure of the substrate 202 on the sidewall 204s serves as a seed layer for the recrystallization of the second channel layer 208a. Therefore, the crystal orientation of the second channel layer 208a can be the same as that of the substrate 202 and the first channel layer 206a.

[0029] Depending on the number of channels in the device structure, additional pairs of second sacrificial layers 207 and second channel layers 208a may be formed in the stack cavity 204, as shown in Figure 1H. The same process, namely depositing the second sacrificial layer 207, depositing the second channel layer 208, and SPER recrystallization, can be repeated to form each pair of second sacrificial layers 207 and second channel layers 208a. These pairs of second sacrificial layers 207 and second channel layers 208a form a second channel stack 213. In Figure 1H, two pairs of second sacrificial layers 207 and second channel layers 208a are shown as an example in the second channel stack 213. In some embodiments, the second channel stack 213 may include two to ten pairs of second sacrificial layers 207 and second channel layers 208a. In some embodiments, the number of first channel layers 206a is the same as the number of second channel layers 208a.

[0030] The sidewall portion of substrate 202 is then removed to form a channel stack 214 above substrate 202, as shown in Figure 1I. The channel stack 214 serves as the channel region for vertically stacked CFETs.

[0031] After the channel stack 214 is formed, a fin structure 216 is formed from the channel stack 214 and the substrate 202, as shown in Figure 1J. Figure 1J is a cross-sectional view of a semiconductor structure along a zy-plane or y-section. Each fin structure 216 has an upper portion including the channel stack 214 and a well portion 218 formed by the substrate 202. The fin structure 216 can be fabricated using suitable processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with, for example, a pitch smaller than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrel can then be used to pattern the fin structure 216 by etching the complementary channel stack 214 and the substrate 202. Etching processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0032] Fin-shaped structures 216 are formed along the channel direction, such that a portion of the fin-shaped structures 216 becomes a channel for the subsequently formed FET. Isolation regions 220 can be formed by depositing insulating material in trenches between the fin-shaped structures 216. The insulating material can be made of: oxygen-containing materials (such as silica or fluorosilicate glass (FSG)); nitrogen-containing materials (such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN); low-k dielectric materials; or any suitable dielectric material. The insulating material can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD). Planarization operations (such as chemical mechanical polishing (CMP) processes and / or etch-back processes) are performed to expose the top of the fin-shaped structures 216 from the insulating material. The insulating material can be recessed to form an isolation region 220 by removing a portion of the insulating material located between adjacent fin structures 216. The isolation region 220 can be shallow trench isolation (STI).

[0033] In Figure 1K, a sacrificial gate structure 222 is formed over the fin structure 216. The sacrificial gate structure 222 is formed over a portion of the fin structure 216. Each sacrificial gate structure 222 may include a sacrificial gate dielectric layer 224, a sacrificial gate electrode layer 226, and a masking layer 228. The sacrificial gate dielectric layer 224, the sacrificial gate electrode layer 226, and the masking layer 228 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 224, the sacrificial gate electrode layer 226, and the masking layer 228, followed by patterning and etching processes. For example, the patterning process includes lithography (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof.

[0034] Sidewall spacers 230 are formed on the sidewalls of the sacrificial gate structure 222. The sidewall spacers 230 can be formed by first depositing a conformal layer, followed by etching the conformal layer to form the sidewall spacers 230. For example, a spacer material layer can be conformally disposed on the exposed surface of the semiconductor structure 200. The conformal spacer material layer can be formed by an ALD process. Subsequently, the spacer material layer is anisotropically etched using, for example, RIE. During the anisotropic etching process, most of the spacer material layer is removed from a horizontal surface (such as the top of the fin structure 216), leaving the sidewall spacers 230 on a vertical surface (such as the sidewalls of the sacrificial gate structure 222). The sidewall spacers 230 can be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0035] In Figure 1L, the fin structure 216 exposed on opposite sides of the sacrificial gate structure 222 and the sidewall spacer 230 is recessed to form a source / drain groove 232. The exposed portions of the fin structure 216 are selectively recessed using one or more suitable etching processes (such as dry etching, wet etching, or a combination thereof). In some embodiments, the exposed portions of the complementary channel stack 214 of the fin structure 216 are removed, thereby exposing a portion of the trap portion 218.

[0036] In Figure 1M, an inner spacer 234 is formed. Edge portions of the first sacrificial layer 205 and the second sacrificial layer 207 of the channel stack 214 are horizontally removed along the X direction. The removal of the edge portions of the first sacrificial layer 205 and the second sacrificial layer 207 creates a cavity in the fin structure 216 below the sidewall spacer 230. A dielectric layer is filled into the cavity to form the inner spacer 234. The inner spacer 234 may be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The formation of the inner spacer 234 may be performed as follows: first, a conformal dielectric layer is formed using a conformal deposition process (such as ALD), and then etching is performed to remove the portion of the conformal dielectric layer except for the inner spacer 234. The etching process may be primarily isotropic etching or a combination of isotropic and anisotropic etching to remove the dielectric layers deposited on the sidewalls and bottom, respectively.

[0037] In Figure 1N, a first source / drain region 236 and a second source / drain region 244 are formed in the source / drain groove 232. The first source / drain region 236 is an epitaxial feature grown from the well portion 218 of the fin structure 216 and the exposed semiconductor surface of the first channel layer 206a.

[0038] For an n-channel FET, the first source / drain region 236 and the second source / drain region 244 may include one or more layers of Si, SiP, SiC, and SiCP; or for a p-channel FET, they may include one or more layers of Si, SiGe, and Ge. In some embodiments, for a p-channel FET, the first source / drain region 236 includes one or more layers of Si, SiGe, and Ge. In some embodiments, for an n-channel FET, the second source / drain region 244 includes one or more layers of Si, SiP, SiC, and SiCP.

[0039] The first source / drain region 236 may be grown from the first channel layer 206a. The first source / drain region 236 may be grown vertically and horizontally to form surfaces that correspond to the crystal surfaces of the material used in the first channel layer 206a. The first source / drain region 236 may be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0040] Source / drain region 236 is formed in the lower portion of source / drain recess 232. A first contact etch stop layer (CESL) 238 and a first interlayer dielectric (ILD) layer 240 are formed above the first source / drain region 236. The first CESL 238 may be formed conformally on the exposed surface of the semiconductor structure 200. The first CESL 238 covers the first source / drain region 236, sidewall spacers 230, isolation region 220, and the exposed surface of channel stack 214. The first CESL 238 may include oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbonitride, silicon oxide, silicon carbide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first ILD layer 240 is formed on the first CESL 238 above the semiconductor structure 200. The material of the first ILD layer 240 may include tetraethoxysilane (TEOS) oxide, undoped silicate glass, or doped silica, such as borosilicate glass (BPSG), fluorosilicone glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials containing Si, O, C, and / or H. The first ILD layer 240 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the first ILD layer 240, the semiconductor structure 200 may undergo a thermal process to anneal the first ILD layer 240.

[0041] In some embodiments, an etch-back process may be performed such that the top surfaces of the first CESL 238 and the first ILD layer 240 are located below the topmost second channel layer 208a, thereby exposing the second channel layer 208a to the source / drain groove 232.

[0042] The second source / drain region 244 is an epitaxial feature grown from the exposed semiconductor surface of the second channel layer 208a. The second source / drain region 244 can be grown vertically and horizontally to form surfaces that correspond to the crystal planes of the material used in the second channel layer 208a. The second source / drain region 244 can be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0043] A second CESL 246 and a second ILD layer 248 are formed over the second source / drain region 244. The second CESL 246 is conformally formed on the exposed surface of the semiconductor structure 200. The second CESL 246 covers the second source / drain region 244, the sidewall spacers 230, and the first ILD layer 240.

[0044] After the formation of the second ILD layer 248, a planarization operation (such as CMP) is performed on the semiconductor structure 200 to remove portions of the second ILD layer 248, the second CESL 246, and the sacrificial gate layer 226. As shown in Figure 10, the sacrificial gate structure 222 and the first sacrificial layer 205 are removed. The removal of the sacrificial gate structure 222 forms a gate recess 250 between the sidewall spacers 230 and exposes the portion of the complementary channel stack 214 located below the sacrificial gate structure 223. The first and second sacrificial layers 205 and 207 can then be selectively removed to expose the first and second channel layers 206a and 208a.

[0045] In Figure 1P, the first replacement gate structure 252 and the second replacement gate structure 258 are formed around the first channel layer 206a and the second semiconductor layer 206b, respectively.

[0046] The first replacement gate structure 252 includes: a first gate dielectric layer 254 formed around the first channel layer 206a; and a first gate electrode layer 256 deposited on the first gate dielectric layer 254. The first replacement gate structure 252, the first channel layer 206a, and the first source / drain region 236 form a first transistor 251. The first channel layer 206a connects the first source / drain regions 236 and serves as a nanosheet channel for the first transistor 251.

[0047] A second replacement gate structure 258 is formed around the second channel layer 208a. The second replacement gate structure 258 includes: a second gate dielectric layer 260 formed around the second channel layer 208a; and a second gate electrode layer 262 deposited above the second gate dielectric layer 260. The second replacement gate structure 258, the second channel layer 208a, and the second source / drain region 244 form a second transistor 257. The second channel layer 208a connects the second source / drain regions 244 and serves as a nanosheet channel for the second transistor 257.

[0048] In some embodiments, a first gate dielectric layer 254 and a second gate dielectric layer 260 are formed simultaneously. The first gate dielectric layer 254 is deposited on the exposed surface of the first channel layer 206a. The second gate dielectric layer 260 is deposited on the exposed surface of the second channel layer 208a. In some embodiments, the first gate dielectric layer 254 and the second gate dielectric layer 260 may comprise a high-k dielectric material. In some embodiments, the first gate dielectric layer 254 and the second gate dielectric layer 260 may be formed by a conformal process.

[0049] A first gate electrode layer 256 is then formed in the gate recess 250 and on the first gate dielectric layer 254. The first gate electrode layer 256 is formed on the first gate dielectric layer 254 to surround the first channel layer 206a. The first gate electrode layer 256 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The first gate electrode layer 256 may be formed by PVD, CVD, ALD, electroplating, or other suitable methods.

[0050] In some embodiments, the first gate electrode layer 256 includes a p-type gate electrode layer, such as TiN, TaN, TiTaN, TiAlN, WCN, W, Ni, Co or other suitable materials, and the first gate electrode layer 256 is the gate electrode layer of a PFET.

[0051] In some embodiments, an etch-back process is performed after the deposition of the first gate electrode layer 256, such that the first replacement gate structure 252 remains in the lower portion of the gate recess 250.

[0052] A second gate electrode layer 262 is formed within the gate recess 250 and on the second gate dielectric layer 260. The second gate electrode layer 262 is formed on the second gate dielectric layer 260 to surround the second channel layer 208a. The second gate electrode layer 262 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the second gate electrode layer 262 includes an n-type gate electrode layer, such as TiAlC, TaAlC, TiSiAlC, TiC, TaSiAlC, or other suitable materials, and the second gate electrode layer 262 is the gate electrode layer of an NFET. The second gate electrode layer 262 can be formed by PVD, CVD, ALD, electroplating, or other suitable methods.

[0053] By using SPER technology to form epitaxial channel layers, the semiconductor device according to this disclosure reduces mixing between the channel layers and sacrificial epitaxial layers (e.g., SiGe layers). Figures 2A and 2B schematically illustrate the semiconductor composition profile across channels in a multichannel transistor according to an embodiment of this disclosure.

[0054] In Figure 2A, contour 261 schematically illustrates the silicon concentration of the second channel layer 208a along the z-direction. Contour 263 schematically illustrates the silicon concentration of the epitaxial silicon channel layer formed between two epitaxial SiGe layers. As shown in contour 263, the silicon concentration decreases near the top and bottom surfaces of the channel. This decrease may be due to Ge from adjacent SiGe layers being incorporated into the channel. Contour 261 of the second channel layer 208a according to this disclosure avoids this decrease near the surface.

[0055] Similarly, in Figure 2B, contour 264 schematically illustrates the silicon concentration along the z-direction of the first channel layer 206a. Contour 266 schematically illustrates the silicon concentration of the epitaxial SiGe channel layer formed between two epitaxial SiGe layers. Contour 268 schematically illustrates the germanium concentration along the z-direction of the first channel layer 206a. Contour 270 schematically illustrates the germanium concentration of the epitaxial SiGe channel layer formed between two epitaxial SiGe layers. As shown in contours 264 and 268, according to this disclosure, there is no silicon or germanium mixture near the surface of the first channel layer 206a.

[0056] In semiconductor structure 200, the first channel layer 206a of the P-FET and the second channel layer 208a of the N-FET have the same crystal orientation. In other embodiments of this disclosure, the channel layers of the P-FET and N-FET may have different crystal orientations, thereby optimizing hole mobility without sacrificing electron mobility.

[0057] Figures 3A through 3D schematically illustrate various stages of fabricating a semiconductor structure 200a having vertically stacked complementary field-effect transistors (CFETs) according to some embodiments of this disclosure.

[0058] In Figure 3A, a first channel stack 212, including a pair of first sacrificial layers 205 and first channel layers 206a, is formed on a first substrate 202a, while a second channel stack 213, including a pair of second sacrificial layers 207 and second channel layers 208a, is formed on a second substrate 202b. The first substrate 202a and the second substrate 202b have different surface orientations. In some embodiments, the first substrate 202a has a (110) crystal orientation, and the second substrate 202b has a (100) crystal orientation.

[0059] After forming the stack of the first sacrificial layer 205 and the first channel layer 206a, a bonding layer 210a is deposited over the first substrate 202a. After forming the stack of the second sacrificial layer 207 and the second channel layer 208a, a bonding layer 210b is deposited over the second substrate 202b. The bonding layers 210a and 210b may include one or more layers of suitable material to bond with and provide isolation therebetween the first sacrificial layer 205 and the second sacrificial layer 207. In some embodiments, the bonding layers 210a and 210b include one or more dielectric layers. For example, bonding layers 210a and 210b may include silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxide, silicon nitride, high-k dielectric materials such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfSiON), hafnium alumina (HfAlO), lanthanum hafnium oxide (HfLaO), zirconium hafnium oxide (HfZrO), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), silicon alumina (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), their compounds, their composites, and combinations thereof. The bonding layer 210a can be formed using appropriate deposition methods, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), spin coating, etc.

[0060] In some embodiments, bonding layers 210a and 210b may be formed symmetrically from the same material and substantially the same thickness. In other embodiments, bonding layers 210a and 210b may be formed asymmetrically from different materials and / or different thicknesses to achieve desired performance or processing efficiency.

[0061] In Figure 3B, the first substrate 202a and the second substrate 202b are bonded together. The first substrate 202a and the second substrate 202b are bonded by connecting the bonding layers 210a and 210b together using a suitable substrate bonding technique.

[0062] In some embodiments, the first substrate 202a and the second substrate 202b may be bonded using a direct bonding process, such as dielectric-dielectric bonding. In some embodiments, surface cleaning is performed to remove particles, contaminants, and native oxides from the surfaces of the first substrate 202a and the second substrate 202b. The surface cleaning process may include one or more cleaning methods, such as cryogenic cleaning, mechanical wiping and scrubbing, etching in gas, plasma, or liquid, ultrasonic and megasonic cleaning, laser cleaning, etc.

[0063] In some embodiments, before performing the bonding operation, the first substrate 202a and the second substrate 202b may be positioned relative to each other such that the intended channel orientations in the first channel layer 206a and the second channel layer 208a are aligned with each other.

[0064] Subsequently, the bonding layers 210a and 210b of the first substrate 202a and the second substrate 202b are brought into solid contact under appropriate bonding pressure and temperature to form a bonding structure therebetween. A complementary channel stack 214a is formed. A thinning process is performed to remove a portion of the second substrate 202b and expose the second channel layer 208a for subsequent processing.

[0065] As shown in Figures 3C and 3D, a semiconductor structure 200a with vertically stacked CFETs is formed. The vertically stacked transistors 251 and 257 include first and second channel layers 206a and 208a with different crystal orientations. In some embodiments, the first channel layer 206a of the P-FET has a (110) crystal orientation, resulting in improved hole mobility, while the second channel layer 208a of the N-FET has a (100) crystal orientation, resulting in optimized electron mobility. Bonding layers 210a and 210b serve as inter-transistor dielectric layers.

[0066] Figures 4A through 4I schematically illustrate various stages of fabricating a semiconductor structure 200b having a vertically stacked complementary field-effect transistor (CFET) according to some embodiments of this disclosure. The semiconductor structure 200b includes a channel stack comprising a sacrificial layer formed of perovskite oxide and a channel layer recrystallized from perovskite oxide as a seed layer.

[0067] In Figure 4A, a first sacrificial layer 205b is formed on substrate 202. In some embodiments, the first sacrificial layer 205b may comprise a perovskite oxide material. In some embodiments, the first sacrificial layer 205b may be a perovskite-type single crystal material having the chemical formula ABO3, wherein A is a rare earth element, including one or more of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, or an alkaline earth element, including one or more of Be, Mg, Ca, Sr, and Ba, and B is a non-rare earth element, including one or more of Ti, Zr, Hf, Al, Ga, In, Tl, Ge, Sn, and Pb, or a rare earth element or transition metal. The first sacrificial layer 205b may be selected to have an ideal crystal orientation for the first channel layer 206a to be formed. In some embodiments, the first sacrificial layer 205b may be YAlO3, LaAlO3, SrTiO3, etc.

[0068] Further, as shown in Figure 4A, a first channel layer 206 is formed on the first sacrificial layer 205b. The first channel layer 206 comprises a semiconductor material suitable for use as a channel layer. The first channel layer 206 comprises a semiconductor material such as Si, SiGe, Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof. In some embodiments, the first channel layer 206 is made of SiGe, with a Ge concentration in the range of about 15% to about 35%. The first channel layer 206 can be deposited in an amorphous form. The amorphous semiconductor deposition process can be performed in an LPCVD reactor at a temperature between about 360°C and 560°C, for example, about 400°C.

[0069] After the formation of the amorphous first channel layer 206, a solid-phase epitaxial recrystallization (SPER) process is performed to convert the first channel layer 206 into a crystalline state, as shown in Figure 4B. In some embodiments, the SPER process is performed by a laser annealing process. In some embodiments, a laser source 203 is applied to the first channel layer 206 to rapidly raise the temperature of the first channel layer 206 to a temperature level between approximately 1200°C and approximately 1400°C. In some embodiments, the laser source 203 may pulse for a short duration, for example, in the range of approximately 100 ns to 500 ns, such as approximately 160 ns. By rapidly heating for a short duration, the first channel layer 206 is annealed to a crystalline state while still in a solid phase, denoted as first channel layer 206a.

[0070] Since the first channel layer 206 is in contact with the perovskite structure of the first sacrificial layer 205b, the crystalline structure of the first sacrificial layer 205b serves as a seed layer for the recrystallization of the first channel layer 206a. Therefore, the crystalline orientation of the first channel layer 206a can be the same as that of the first sacrificial layer 205b.

[0071] Depending on the number of channels in the device structure, additional pairs of first sacrificial layers 205b and first channel layers 206a may be formed on substrate 202, as shown in Figure 4C. The same process, namely depositing the first sacrificial layer 205b, depositing the first channel layer 206a, and recrystallizing with SPER, can be repeated to form each pair of first sacrificial layers 205b and first channel layers 206a. These pairs of first sacrificial layers 205b and first channel layers 206a form a first channel stack 212b. In some embodiments, these pairs of first sacrificial layers 205b and first channel layers 206a are designated for a first type of FET, such as a P-FET. The first channel layer 206a may have a (100) or (110) crystal orientation.

[0072] In Figure 4D, a first sacrificial layer 205b and an inter-transistor dielectric layer 210 are formed above the first sacrificial layer 205b and the first channel layer 206a. The inter-transistor dielectric layer 210 is used to isolate the gate structure around the first channel layer 206a from the gate structure above it.

[0073] After the inter-transistor dielectric layer 210 is formed, two or more pairs of second sacrificial layers 207b and second channel layers 208 may be sequentially formed above the inter-transistor dielectric layer 210, as shown in Figures 4E and 4F.

[0074] In Figure 4E, a second sacrificial layer 207b is formed on the inter-transistor dielectric layer 210. In some embodiments, the second sacrificial layer 207b may be a perovskite-type single-crystal material having the chemical formula ABO3, wherein A is a rare earth element, including one or more of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, or an alkaline earth element, including one or more of Be, Mg, Ca, Sr, and Ba, and B is a non-rare earth element, including one or more of Ti, Zr, Hf, Al, Ga, In, Tl, Ge, Sn, and Pb, or a rare earth element or transition metal. The second sacrificial layer 207b may be selected to have an ideal crystal orientation for the second channel layer 208a to be formed. In some embodiments, the second sacrificial layer 207b may be YAlO3, LaAlO3, SrTiO3, etc.

[0075] In some embodiments, the first sacrificial layer 205b and the second sacrificial layer 207b may comprise different materials or materials with different crystal orientations. In other embodiments, the first sacrificial layer 205b and the second sacrificial layer 207b may comprise the same material or have the same crystal orientation.

[0076] A second channel layer 208 is formed on the second sacrificial layer 207b. The second channel layer 208 comprises a semiconductor material suitable for use as a channel layer. In some embodiments, the thickness of the second channel layer 208 along the z-direction is in the range of about 3 nm to about 15 nm. The second channel layer 208 comprises a semiconductor material such as Si, SiGe, Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof. In some embodiments, the second channel layer 208 is made of silicon. The second channel layer 208 may be deposited in an amorphous form. The amorphous semiconductor deposition process can be performed in an LPCVD reactor at a temperature between about 360°C and 560°C, for example, about 400°C.

[0077] After forming the amorphous second channel layer 208, a solid phase epitaxial recrystallization (SPER) process is performed to convert the second channel layer 208 into a crystalline state, as shown in Figure 4F. In some embodiments, the SPER process is performed by a laser annealing process.

[0078] Because the second channel layer 208 is in contact with the perovskite structure of the second sacrificial layer 207b, the crystalline structure of the second sacrificial layer 207b serves as a seed layer for the recrystallization of the second channel layer 208a. Therefore, the crystalline orientation of the second channel layer 208a can be the same as that of the second sacrificial layer 207b. Subsequently, additional pairs of second sacrificial layers 207b and second channel layers 208b can be formed. The same process, namely, depositing the second sacrificial layer 207b, depositing the second channel layer 208, and SPER recrystallization, can be repeated to form each pair of second sacrificial layers 207b and second channel layers 208a. These pairs of second sacrificial layers 207b and second channel layers 208a form a second channel stack 213b, as shown in Figure 4G.

[0079] The first channel stack 212b, the inter-transistor dielectric layer 210, and the second channel stack 213b form a channel stack 214b, which serves as the channel region for vertically stacked CFETs. After the channel stack 214b is formed, a fin structure 216 is formed from the channel stack 214b and the substrate 202, and a sacrificial gate structure 222 is formed above the fin structure 216, as shown in Figure 4H.

[0080] Subsequently, source / drain regions and a replacement gate structure are formed, resulting in the semiconductor structure 200b shown in Figure 4I. Semiconductor structure 200b includes vertically stacked CFETs. The vertically stacked transistors 251 and 257 have first and second channel layers 206a and 208a with different crystal orientations. In some embodiments, the first channel layer 206a of the P-FET has a (110) crystal orientation, providing improved hole mobility, and the second channel layer 208a of the N-FET has a (100) crystal orientation, providing optimized electron mobility.

[0081] Although the fabrication of vertically stacked CFETs has been discussed above, the embodiments disclosed herein can be used to fabricate any multichannel FET.

[0082] Figures 5A to 5E schematically illustrate the various stages of fabricating a semiconductor structure 200c having a gate-all-around field-effect transistor according to an embodiment of this disclosure. The semiconductor structure 200c is fabricated by a process similar to that of the semiconductor structure 200 in Figures 1A to 1P, except that the N-FETs and P-FETs are arranged side-by-side rather than stacked vertically.

[0083] In Figure 5A, stacked cavities 204P and 204N are formed in different regions of the same substrate 202. Two or more pairs of first sacrificial layers 205 and first channel layers 206a are formed in stacked cavity 204P, and two or more pairs of second sacrificial layers 207 and second channel layers 208a are formed in stacked cavity 204N. According to embodiments of this disclosure, the first channel layers 206a and second channel layers 208a are first deposited in an amorphous form and then recrystallized using a SPER process. In some embodiments, the first channel layers 206a and second channel layers 208a can be formed in separate processes using a suitable mask. The first channel layers 206a and second channel layers 208a have the same crystalline orientation.

[0084] In Figure 5B, the portion of the sidewall 204s of the substrate 202 in Figure 5A that serves as the stacking cavity 204P and 204N is removed. The fin structure is formed by the channel stack 212 and 213 in Figure 5A, and a sacrificial gate structure 222 is formed above the fin structure.

[0085] In Figure 5C, the fin structure not covered by the sacrificial gate structure 222 is recessed to form a source / drain groove 232. In Figure 5D, the first and second epitaxial source / drain regions 236 and 244 are grown from the first channel layer 206a and the second channel layer 208a, respectively. In Figure 5E, a replacement gate process is performed, and a p-type transistor 251 and an n-type transistor 257 are formed side-by-side on the substrate 202.

[0086] Figures 6A to 6C schematically illustrate the various stages of fabricating a semiconductor structure 200d having a gate-all-around field-effect transistor according to an embodiment of this disclosure. The semiconductor structure 200d is fabricated by a process similar to that of the semiconductor structure 200b in Figures 4A to 4I, except that the N-FETs and P-FETs are arranged side-by-side rather than vertically stacked.

[0087] In Figure 6A, two or more pairs of first sacrificial layers 205b and first channel layers 206a, and two or more pairs of second sacrificial layers 207b and second channel layers 208a are formed side-by-side on different regions of the same substrate 202. According to embodiments of this disclosure, the first channel layers 206a and second channel layers 208a are first deposited in an amorphous form and then recrystallized using a SPER process. In some embodiments, the first channel layers 206a and second channel layers 208a can be formed in separate processes using a suitable mask. Depending on the crystal orientation of the first sacrificial layers 205b and second sacrificial layers 207b, the first channel layers 206a and second channel layers 208a may have the same or different crystal orientations.

[0088] In Figure 6B, a fin-shaped structure is formed by channel stacks 212b and 213b, and a sacrificial gate structure 222 is formed above the fin-shaped structure. In Figure 6C, epitaxial first and second source / drain regions 236 and 244 are grown from the first channel layer 206a and the second channel layer 208a, respectively. A replacement gate process is performed to form a p-type transistor 251 and an n-type transistor 257 side by side on the substrate 202.

[0089] The various embodiments or examples described herein offer several advantages over existing technologies. By using laser recrystallization, the sacrificial layer in the channel stack can be an oxide-containing layer, rather than a silicon and germanium-containing epitaxial layer, i.e., a SiGe sacrificial layer. By avoiding the SiGe sacrificial layer, the embodiments reduce Ge segregation to adjacent semiconductor channel layers during thermal processing. The embodiments of this disclosure also reduce the tensile strain caused by the SiGe sacrificial layer on the Si channel layer. Furthermore, the embodiments of this disclosure allow the p-channels and n-channels in a CFET to have different crystal orientations, thereby improving device performance.

[0090] It should be understood that not all advantages are discussed herein, specific advantages are not required for all embodiments or examples, and different advantages may be provided by other embodiments or examples.

[0091] Some embodiments of this disclosure provide a method comprising the steps of: forming a first channel stack on a substrate, comprising: depositing a first sacrificial layer over the substrate; depositing a first channel layer on the first sacrificial layer, wherein the first channel layer is in an amorphous form; and crystallizing the first channel layer; patterning the first channel stack to form a fin structure over the substrate; and forming a first transistor from the fin structure, wherein the first transistor includes: a first source / drain region disposed on a portion of the first channel stack.

[0092] Some embodiments of this disclosure provide a method comprising the following steps: depositing a first sacrificial layer on a first substrate; depositing a first channel layer on the first sacrificial layer, wherein the first channel layer comprises a first semiconductor material in an amorphous form; crystallizing the first channel layer in a first crystalline orientation by rapidly raising the temperature of the first channel layer by applying pulsed laser energy; depositing a second sacrificial layer; depositing a second channel layer on the second sacrificial layer, wherein the second channel layer comprises a second semiconductor material in an amorphous form; crystallizing the second channel layer in a second crystalline orientation by rapidly raising the temperature of the second channel layer by applying pulsed laser energy; forming a fin structure above the first channel layer and the second channel layer; forming a first source / drain region in contact with the first channel layer; and forming a second source / drain region in contact with the second channel layer.

[0093] Some embodiments of this disclosure provide a semiconductor device comprising: a first channel layer having a first crystal orientation; a first gate dielectric layer surrounding the first channel layer; a first gate electrode layer disposed on the first gate dielectric layer; a first source / drain region contacting the first channel layer; a second channel layer stacked above and aligned with the first channel layer, wherein the second channel layer has a second crystal orientation; a second gate dielectric layer surrounding the second channel layer; a second gate electrode layer disposed on the second gate dielectric layer; a second source / drain region contacting the second channel layer; and a dielectric layer disposed between the first gate dielectric layer and the second gate dielectric layer.

[0094] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

[0095] 200, 200a~200d: Semiconductor structure 202:Substrate 202a: First substrate 202b: Second substrate 202f: Front surface 203: Laser source 204: Stacked Cavities 204b: Bottom surface 204N, 204P: Stacked cavities 204s: Sidewall 205,205b: First Sacrificial Layer 206, 206a: First channel layer 207,207b: Second Sacrificial Layer 208, 208a: Second channel layer 210: Inter-transistor dielectric layer 210a, 210b: Bonding layers 212, 212b: First channel stack 213, 213b: Second channel stack 214, 214b: Channel stacking 216: Fin-shaped structure 220: Quarantine Area 222: Sacrificial gate structure 224: Sacrificial gate dielectric layer 226: Sacrificial gate electrode layer 228: Masking layer 230: Sidewall spacers 232: Source / Drain Groove 234: Internal spacer 236: First source / drain region 238: First CESL 240: First ILD layer 244: Second source / drain region 246: Second CESL 248: Second ILD layer 250: Gate groove 251: First Transistor / Transistor 252: First Replacement Gate Structure 254: First gate dielectric layer 256: First gate electrode layer 257: Second transistor / transistor 258: Second Replacement Gate Structure 260: Second gate dielectric layer 262: Second gate electrode layer 261,263,264,266,268,270: Outline x, y, z: Direction

Claims

1. A method for manufacturing a semiconductor structure, comprising the steps of: forming a first channel stack on a substrate, comprising: depositing a first sacrificial layer over the substrate, wherein the first sacrificial layer comprises perovskite oxide; depositing a first channel layer on the first sacrificial layer, wherein the first channel layer is in an amorphous form; and crystallizing the first channel layer; patterning the first channel stack to form a fin structure over the substrate; and forming a first transistor from the fin structure, wherein the first transistor comprises: a plurality of first source / drain regions disposed on a portion of the first channel stack.

2. The method of claim 1, wherein the step of crystallizing the first channel layer comprises the following steps: applying a pulsed laser energy to rapidly raise the temperature of the first channel layer.

3. The method of claim 2, wherein the step of forming the first channel stack further comprises the following steps: forming a stack cavity in the substrate prior to depositing the first sacrificial layer, wherein the first sacrificial layer and the first channel layer are deposited in the stack cavity, and the first channel layer contacts a plurality of sidewalls of the stack cavity.

4. A method for manufacturing a semiconductor structure, comprising the following steps: depositing a first sacrificial layer on a first substrate; depositing a first channel layer on the first sacrificial layer, wherein the first channel layer comprises a first semiconductor material in an amorphous form; crystallizing the first channel layer in a first crystal orientation by rapidly raising the temperature of the first channel layer by applying a pulsed laser energy; depositing a second sacrificial layer; depositing a second channel layer on the second sacrificial layer, wherein the second channel layer comprises a second semiconductor material in an amorphous form; crystallizing the second channel layer in a second crystal orientation by rapidly raising the temperature of the second channel layer by applying a pulsed laser energy; forming a plurality of fin structures on the first channel layer and the second channel layer; forming a plurality of first source / drain regions in contact with the first channel layer; and forming a plurality of second source / drain regions in contact with the second channel layer.

5. The method of claim 4, wherein the first sacrificial layer comprises a first perovskite oxide having the first crystal orientation, and the second sacrificial layer comprises a second perovskite oxide having the second crystal orientation.

6. The method of claim 5 further comprises the following steps: forming a dielectric layer over the first channel layer, wherein the second channel layer is disposed on the dielectric layer and stacked vertically over the first channel layer.

7. The method of claim 5, wherein the first channel layer and the second channel layer are formed side by side on different regions of the first substrate.

8. The method of claim 4, wherein the second sacrificial layer is disposed on a second substrate, the first substrate has the first crystal orientation, and the second substrate has the second crystal orientation, and the method further comprises the steps of: forming a first bonding film over the first channel layer; forming a second bonding film over the second channel layer; bonding the first bonding film to the second bonding film such that the second channel layer is stacked over the first channel layer; and removing the second substrate.

9. A semiconductor device comprising: a first channel layer having a first crystal orientation; a first gate dielectric layer surrounding the first channel layer; a first gate electrode layer disposed on the first gate dielectric layer; a plurality of first source / drain regions contacting the first channel layer; a second channel layer stacked above and aligned with the first channel layer, wherein the second channel layer has a second crystal orientation; a second gate dielectric layer surrounding the second channel layer; a second gate electrode layer disposed on the second gate dielectric layer; a plurality of second source / drain regions contacting the second channel layer; and a dielectric layer disposed between the first gate dielectric layer and the second gate dielectric layer.

10. The semiconductor device of claim 9, wherein the first channel layer and the second channel layer comprise a crystalline semiconductor material formed by solid-state epitaxial recrystallization.

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