Integrated chip and method of forming the same
Patent Information
- Application Number
- TW114116918
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2025-03-19
- Filing Date
- 2025-05-06
- Publication Date
- 2026-10-11
- Estimated Expiration
- 2045-05-05
Smart Images

Figure TWG2TB001915438_001 
Figure TWG2TB001915438_002 
Figure TWG2TB001915438_003
Abstract
Claims
1. A multiphase grain, comprising: A gate structure is located above a substrate; a channel structure is located above the gate structure; a first source / drain contact and a second source / drain contact are disposed above the channel structure and the gate structure, wherein the first source / drain contact is laterally separated from the second source / drain contact along a first direction, the channel structure has a first width below the first source / drain contact and a second width below the second source / drain contact, the first width being different from the second width; a capacitor electrically coupled to the first source / drain contact; and wherein the first source / drain contact has a first length and the second source / drain contact has a second length, the first length and the second length being measured along a second direction substantially perpendicular to the first direction, the first length being different from the second length.
2. The integrated grain as claimed in claim 1, wherein, in a top view, the first source / drain contact extends laterally from the second source / drain contact to a non-zero distance beyond the end of the second source / drain contact.
3. The integrated grain as claimed in claim 1, wherein the channel structure has an inclined sidewall extending between the first source / drain contact and the second source / drain contact, wherein, when viewed in a top view, the inclined sidewall is oriented at an acute angle relative to the sidewall of the first source / drain contact.
4. The integrated die as claimed in claim 1, wherein the channel structure varies between a first width directly below the first source / drain contact and a second width directly below the second source / drain contact, the first width being different from the second width.
5. The integrated grain as described in claim 1, further comprising: Bit lines are coupled to the second source / drain contact, wherein the bit lines have a first width substantially equal to the second length of the second source / drain contact.
6. The integrated grain as described in claim 1, further comprising: Bit lines are coupled to the second source / drain contact, wherein the bit lines have a width smaller than the first length of the first source / drain contact and the second length of the second source / drain contact.
7. The integrated grain as described in claim 1, further comprising: A second gate structure is disposed on the substrate; The second channel structure is arranged on the second gate structure; A third source / drain contact and a fourth source / drain contact are disposed on the second channel structure and the second gate structure; and wherein, viewed from a top view, the channel structure and the second channel structure are separated by a serpentine shape.
8. A method for forming a multiphase grain, comprising: A gate structure is formed on the substrate; A channel structure is formed on the gate structure; A first patterning process is performed on the channel structure to remove a first segment of the channel structure extending along a first direction; a second patterning process is performed on the channel structure to remove a second segment of the channel structure extending along a second direction different from the first direction; A third patterning process is performed on the channel structure to remove a third segment of the channel structure extending along a third direction different from the first and second directions; and a first source / drain contact and a second source / drain contact are formed on the gate structure and the channel structure.
9. A method for forming a multiphase grain, comprising: A gate structure is formed on the substrate; A channel structure is formed on the gate structure, wherein the channel structure has a width that varies between a first width and a second width; A first source / drain contact is formed on a first portion of the channel structure having the first width; and a second source / drain contact is formed on a second portion of the channel structure having the second width.
Citation Information
Patent Citations
Semiconductor device
TW202305952A
