Semiconductor device, diode structure, and method of making same

Abstract

A semiconductor device includes a diode structure comprising a first semiconductor layer stack. The first semiconductor layer stack includes alternating first semiconductor layers and second semiconductor layers. The diode structure further includes a second semiconductor layer stack comprising alternating third semiconductor layers and a plurality of fourth semiconductor layers. The diode structure further includes a fifth semiconductor layer located between the first semiconductor layer stack and the second semiconductor layer stack, wherein the composition of the fifth semiconductor layer is different from each of the first, second, third, and fourth semiconductor layers. The diode structure further includes an n-type doped region located in the first semiconductor layer stack and a p-type doped region located in the second semiconductor layer stack.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] An integrated circuit (IC) includes several IC devices fabricated according to one or more IC layouts. IC devices sometimes include complementary field-effect transistor (CFET) devices. CFET devices typically have an upper FET covering a lower FET in a stacked configuration. The upper and lower FETs in a CFET device are located above conductive lines in the back conductive layer but below conductive lines in the front conductive layer. In addition to active devices (such as CFET devices), IC devices may include passive devices (such as diodes, resistors, capacitors, or inductors) in certain cases. In some methods utilizing fin field-effect transistors (FinFETs) or nanosheet fabrication processes, diodes are formed in a common doped well. These diodes occupy a large amount of space in the IC because both p-type and n-type devices are formed in the common well. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides many different embodiments or examples for implementing different features of the provided object. Specific examples of elements, values, operations, materials, arrangements, etc., described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other elements, values, operations, materials, arrangements, etc., are contemplated. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] With technological advancements, the pressure to reduce the size of integrated circuit (IC) devices is increasing. A promising development for active devices is the complementary field-effect transistor (CFET). CFETs stack transistor elements vertically, reducing the overall device size compared to other methods such as fin field-effect transistors (FinFETs) or nanosheet transistors. While CFET processes offer improvements in transistor size, passive devices (such as diodes) also occupy significant space within the IC due to their size. Diodes used in these methods (such as FinFETs or nanosheet transistors) include p-type and n-type devices. P-type and n-type devices share a common well to form a well diode structure. Because both types of devices (i.e., p-type and n-type) are included, the diode size within the IC is relatively large. To help reduce the diode size in ICs, this disclosure describes stacked PIN diodes compatible with CFET fabrication.

[0008] A stacked PIN diode includes a p-type device, vertically separated from an n-type device. This vertical arrangement helps reduce the footprint of the stacked PIN diode in the IC compared to diodes with horizontally separated p-type and n-type devices. The stacked PIN diode is also compatible with manufacturing processes used to produce CFET devices. In some embodiments, the stacked PIN diode can be manufactured simultaneously with one or more CFET devices to improve manufacturing efficiency and yield. The manufacturing process of the stacked PIN diode shares several operations with the manufacturing process of the CFET device. However, because the structure of the stacked PIN diode is simpler than that of the CFET device, the stacked PIN diode is shielded (e.g., using photoresist) in some process operations used to manufacture CFET devices to avoid interference. The ability to manufacture both stacked PIN diodes and CFET devices simultaneously enhances the integration of the stacked PIN diode in future IC device manufacturing.

[0009] Figure 1 is a cross-sectional view of a stacked PIN diode 100 according to some embodiments. The stacked PIN diode 100 includes an alternating semiconductor layer stack 105. The alternating semiconductor layer stack 105 includes a first semiconductor material layer 107 and a second semiconductor material layer 109 arranged in an alternating manner. The second semiconductor material includes a composition different from that of the first semiconductor layer. The alternating semiconductor layer stack 105 further includes a semiconductor layer 110, which includes a semiconductor material layer and has a composition different from each of the first semiconductor material and the second semiconductor material.

[0010] The stacked PIN diode 100 further includes: p-wells 120 located in an alternating semiconductor layer stack 105. The p-wells 120 are horizontally separated from each other. A first dielectric layer 125 extends through the surface of the alternating semiconductor layer stack 105. The first dielectric layer 125 overlaps with each p-well 120. A contact structure 130 extends vertically through the first dielectric layer 125. Each contact structure 130 is electrically connected to a corresponding p-well 120. Although not shown for clarity, those skilled in the art will understand that the contact structure 130 is electrically connected to an interconnect structure to deliver signals, power, or ground voltage to the p-well 120. A masking material 135 is also located in the first dielectric layer 125. The masking material 135 can be used to determine the location of each p-well 120 in the alternating semiconductor layer stack 105. In some embodiments, the masking material 135 is omitted in the stacked PIN diode 100.

[0011] The stacked PIN diode 100 further includes n-wells 140 in an alternating semiconductor layer stack 105. The n-wells 140 are horizontally separated from each other. A second dielectric layer 145 extends through the surface of the alternating semiconductor layer stack 105. The second dielectric layer 145 overlaps with each n-well 140. A contact structure 150 extends through the second dielectric layer 145 in a vertical direction. Each contact structure 150 is electrically connected to a corresponding n-well 140. Although not shown for clarity, those skilled in the art will understand that the contact structure 150 is electrically connected to an interconnect structure to propagate signals, power, or ground voltage to the n-well 140. A masking material 155 is also located in the second dielectric layer 145. The masking material 155 can be used to determine the location of each n-well 140 in the alternating semiconductor layer stack 105. In some embodiments, the masking material 155 is omitted in the stacked PIN diode 100.

[0012] The alternating semiconductor layer stack 105 includes alternating first semiconductor layers 107 and second semiconductor layers 109. Those skilled in the art will understand that this application is not limited to the number of layers in the alternating semiconductor layer stack 105 shown in Figure 1. The number of layers in the alternating semiconductor layer stack 105 is determined based on a combination of factors, such as sufficient spacing between p-type wells 120 and n-type wells 140 to reduce the risk of short circuits within the stacked PIN diode 100, and the size of the stacked PIN diode 100. Furthermore, those skilled in the art will understand that the number of odd or even layers in the alternating semiconductor layer stack 105 is within the scope of this specification. Each layer of the alternating semiconductor layer stack 105 is grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited using processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). In some embodiments, each layer in the alternating semiconductor layer stack 105 is formed using the same process. In some embodiments, at least one layer in the alternating semiconductor layer stack 105 is formed using a different process than at least another layer in the alternating semiconductor layer stack 105. In some embodiments, each of the first semiconductor layers 107 is formed using a first process, while each of the second semiconductor layers 109 is formed using a second process, which is different from the first process. In some embodiments, semiconductor layer 110 is formed using a process different from the process used to form at least one of the first semiconductor layer 107 or the second semiconductor layer 109.

[0013] The first semiconductor layer 107 comprises silicon. In some embodiments, the first semiconductor layer 107 comprises pure silicon, for example, with a silicon atomic percentage of 95% or higher. In some embodiments, the first semiconductor layer 107 comprises silicon with a low concentration of germanium. In some embodiments, the germanium atomic percentage in the first semiconductor layer 107 is less than about 5%.

[0014] The second semiconductor layer 109 comprises silicon germanium. The germanium concentration in the second semiconductor layer 109 is greater than the germanium concentration in the first semiconductor layer 107. In some embodiments, the percentage of germanium atoms in the second semiconductor layer 109 ranges from about 10% to about 50%.

[0015] Semiconductor layer 110 facilitates gate isolation in a CFET device. Including semiconductor layer 110 in the stacked PIN diode 100 facilitates integration of the stacked PIN diode 100 into a manufacturing process having a CFET device. In some embodiments where the stacked PIN diode 100 is formed independently of the CFET device, the stacked PIN diode 100 does not include semiconductor layer 110. Semiconductor layer 110 is included in the central portion of the alternating semiconductor layer stack 105. In some embodiments, semiconductor layer 110 is the central layer of the alternating semiconductor layer stack 105. In some embodiments, semiconductor layer 110 is not the central layer of the alternating semiconductor layer stack 105. Semiconductor layer 110 replaces one of the second semiconductor layers 109 in an alternating sequence between a first semiconductor layer 107 and a second semiconductor layer 109. Semiconductor layer 110 includes germanium. In some embodiments, semiconductor layer 110 further includes silicon. In some embodiments, semiconductor layer 110 further includes a dopant, such as an n-type dopant or a p-type dopant. Semiconductor layer 110 has a higher germanium concentration than the second semiconductor layer 109. In some embodiments, semiconductor layer 110 comprises pure germanium, for example, germanium having an atomic percentage of at least 95%. In some embodiments, semiconductor layer 110 comprises silicon germanium. In some embodiments, the atomic percentage of germanium in semiconductor layer 110 ranges from about 60% to about 90%.

[0016] A p-type well 120 is formed in the alternating semiconductor layer stack 105. In some embodiments, a semiconductor material is doped, for example, using a planting process, to form a stacked PIN diode 100. By way of example and not limitation, the alternating semiconductor layer stack 105 is doped in a process that forms the source / drain regions in a CFET device. In some embodiments, a sacrificial hard mask layer is formed on the surface of the alternating semiconductor layer stack 105 to modulate the planting depth, thereby modulating the thickness of the p-type well 120. For example, the depth of the resulting p-type well 120 is inversely proportional to or related to the thickness of the sacrificial hard mask layer. In some embodiments, the hard mask layer is, for example, a stack of silicon oxide and silicon nitride. In some embodiments, the depth of the p-type well 120 is modulated via planting process conditions (e.g., planting energy). In some embodiments, the dopant dose for forming the p-type well 120 ranges from 1 × 10¹² cm² to about 5 × 10¹⁶ cm², and the dopant species include boron, indium, gallium, or other suitable p-type dopants.

[0017] In some embodiments, the ion implantation process for forming the p-type well 120 uses an ion beam energy in the range of, for example, about 1 keV to about 15 keV. The dopant is implanted in the alternating semiconductor layer stack 105, for example, in the range of about 5 nm to about 20 nm. In some embodiments, the dopant concentration of the p-type well 120 ranges, for example, from about 1 × 10¹⁹ cm³ to about 1 × 10²¹ cm³. In some embodiments, an annealing process follows the implantation process. In some embodiments, no post-annealing is performed after implanting the dopant into the alternating semiconductor layer stack 105.

[0018] A first dielectric layer 125 extends along the surface of the alternating semiconductor layer stack 105. The first dielectric layer 125 may be used to provide a contact layer to connect an interconnect structure on a first side of the stacked PIN diode 100 to a p-well 120. In some embodiments, the first dielectric layer 125 comprises silicon oxide, silicon carbide, silicon oxynitride, silicon carbide, combinations thereof, or other suitable dielectric materials. In some embodiments, the first dielectric layer 125 is formed using CVD, PECVD, ALD, or other suitable deposition processes.

[0019] The contact structure 130 extends through the first dielectric layer 125 to facilitate electrical connection between the interconnect structure and the p-well 120. Although the stacked PIN diode 100 shown in Figure 1 has a stepped profile of the contact structure 130, those skilled in the art will recognize that the contact structure 130 is not limited to this shape. In some embodiments, the contact structure 130 has a tapered profile or substantially parallel sidewalls. In some embodiments, the contact structure comprises copper, aluminum, tungsten, cobalt, alloys thereof, or other suitable conductive materials. In some embodiments, the contact structure is formed using physical vapor deposition (PVD), CVD, ALD, or other suitable deposition processes. In some embodiments, the contact structure 130 includes a diffusion barrier layer to help prevent conductive material from diffusing into the first dielectric layer 125.

[0020] Masking material 135 can be used to determine the location of p-type wells 120 in the alternating semiconductor layer stack 105. Masking material 135 is deposited along the surface of the alternating semiconductor layer stack 105 and patterned to define openings exposing the alternating semiconductor layer stack 105. The implantation process forming the p-type wells 120 is performed through the openings to implant p-type dopant into the alternating semiconductor layer stack 105. In some embodiments, masking material 135 includes a photoresist, silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, masking material 135 is a single layer. In some embodiments, masking material is multilayered. In some embodiments, masking material 135 includes a hard mask located, for example, beneath a photoresist. In some embodiments, the hard mask includes titanium nitride, cobalt nitride, silicon nitride, or other suitable materials.

[0021] In some embodiments, the masking material 135 is omitted in the stacked PIN diode 100. For example, the masking material 135 is removed after the p-wells 120 are implanted into the alternating semiconductor layer stack 105 and before the first dielectric layer 125 is formed. In some embodiments where the masking material 135 is removed, the first dielectric layer 125 contacts the entire surface of the alternating semiconductor layer stack 105 between the p-wells 120. In some embodiments, the masking material 135 is removed using etching, ashing, or other suitable removal processes.

[0022] An n-type well 140 is formed in an alternating semiconductor layer stack 105. The n-type well 140 is located on the opposite side of the p-type well 120 in the alternating semiconductor layer stack 105 in the vertical direction. In some embodiments, semiconductor material is doped using a planting process, for example, to form a stacked PIN diode 100. By way of example and not limitation, the alternating semiconductor layer stack 105 is doped in a process that forms the source / drain regions in a CFET device. In some embodiments, a sacrificial hard mask layer is formed on the surface of the alternating semiconductor layer stack 105 to modulate the planting depth, thereby modulating the thickness of the n-type well 140. For example, the depth of the resulting n-type well 140 is inversely proportional to or related to the thickness of the sacrificial hard mask layer. In some embodiments, the hard mask layer is, for example, a stack of silicon oxide and silicon nitride. In some embodiments, the depth of the n-type well 140 is modulated via planting process conditions (e.g., planting energy). In some embodiments, the dopant dosage for forming the n-type well 140 ranges from 1 × 10¹² cm² to approximately 5 × 10¹⁶ cm², and the dopant species include phosphorus, arsenic, antimony, or other suitable n-type dopant. In some embodiments, the n-type well 140 has the same depth as the p-type well 120. In some embodiments, the n-type well 140 has a different depth than the p-type well 120.

[0023] In some embodiments, the ion implantation process for forming the n-type well 140 uses an ion beam energy ranging from, for example, from about 1 keV to about 15 keV. Dopant is implanted into the alternating semiconductor layer stack 105, for example, ranging from about 5 nm to about 20 nm. In some embodiments, the dopant concentration of the n-type well 140 ranges from, for example, from about 1 × 10¹⁹ cm³ to about 1 × 10²¹ cm³. In some embodiments, the n-type well 140 has the same dopant concentration as the p-type well 120. In some embodiments, the n-type well 140 has a different dopant concentration than the p-type well 120. In some embodiments, an annealing process follows the implantation process. In some embodiments, no post-annealing is performed after implanting the dopant into the alternating semiconductor layer stack 105.

[0024] A second dielectric layer 145 extends along the surface of the alternating semiconductor layer stack 105. The second dielectric layer 145 may be used to provide a contact layer for connecting interconnect structures on the second side of the stacked PIN diode 100 to the n-well 140. In some embodiments, the second dielectric layer 145 comprises silicon oxide, silicon carbide, silicon oxynitride, silicon carbide, combinations thereof, or other suitable dielectric materials. In some embodiments, the second dielectric layer 145 is formed using CVD, PECVD, ALD, or other suitable deposition processes. In some embodiments, the second dielectric layer 145 comprises the same material as the first dielectric layer 125. In some embodiments, the second dielectric layer 145 comprises a different material from the first dielectric layer 125.

[0025] Contact structure 150 extends through the second dielectric layer 145 to facilitate electrical connection between the interconnect structure and the n-well 140. Although the stacked PIN diode 100 shown in Figure 1 has a stepped profile of contact structure 150, those skilled in the art will recognize that contact structure 150 is not limited to this shape. In some embodiments, contact structure 150 has a tapered profile or substantially parallel sidewalls. In some embodiments, contact structure 150 has a shape similar to contact structure 130. In some embodiments, contact structure 150 has a different shape than contact structure 130. In some embodiments, contact structure includes copper, aluminum, tungsten, cobalt, alloys thereof, or other suitable conductive materials. In some embodiments, contact structure is formed using physical vapor deposition (PVD), CVD, ALD, or other suitable deposition processes. In some embodiments, contact structure 150 has the same material as contact structure 130. In some embodiments, contact structure 150 has a different material than contact structure 130. In some embodiments, contact structure 150 includes a diffusion barrier layer to help prevent conductive material from diffusing into the second dielectric layer 145.

[0026] Masking material 155 can be used to determine the location of n-type wells 140 in the alternating semiconductor layer stack 105. Masking material 155 is deposited along the surface of the alternating semiconductor layer stack 105 and patterned to define openings exposing the alternating semiconductor layer stack 105. The implantation process forming the n-type wells 140 is performed through the openings to implant n-type dopant into the alternating semiconductor layer stack 105. In some embodiments, masking material 155 includes a photoresist, silicon nitride, silicon oxynitride, or other suitable material. In some embodiments, masking material 155 is a single layer. In some embodiments, masking material is a multilayer. In some embodiments, masking material 155 includes a hard mask located, for example, beneath a photoresist. In some embodiments, the hard mask includes titanium nitride, cobalt nitride, silicon nitride, or other suitable material. In some embodiments, masking material 155 includes a dummy gate structure. In some embodiments, the dummy gate structure includes polysilicon. In some embodiments, the dummy gate structure further includes gate spacers along the sidewalls of the dummy gate electrode. In some embodiments, masking material 155 has the same structure and material as masking material 135. In some embodiments, masking material 155 has a different structure or material than masking material 135.

[0027] In some embodiments, the masking material 155 is omitted in the stacked PIN diode 100. For example, the masking material 155 is removed after the n-wells 140 are implanted into the alternating semiconductor layer stack 105 and before the second dielectric layer 145 is formed. In some embodiments where the masking material 155 is removed, the second dielectric layer 145 contacts the entire surface of the alternating semiconductor layer stack 105 between the n-wells 140. In some embodiments, the masking material 155 is removed using etching, ashing, or other suitable removal processes.

[0028] Compared to other diodes, the stacked PIN diode 100 uses vertical separation between the p-well 120 and the n-well 140 to reduce the size of the diode in the IC. The stacked PIN diode 100 can further be integrated into the CFET manufacturing process, thereby improving production efficiency compared to other methods.

[0029] Figure 2 is a flowchart of a method 200 for manufacturing a stacked PIN diode according to some embodiments. In some embodiments, method 200 can be used to form a stacked PIN diode 100 (Figure 1). In some embodiments, method 200 can be used to form diodes other than the stacked PIN diode 100 (Figure 1). Compared with other methods, method 200 can be used to form a diode having an n-type well separated from the p-type well in the vertical direction, thereby reducing the amount of space occupied by the diode in the IC. This helps to further reduce the size of the IC device.

[0030] In operation 205, a semiconductor layer stack is formed on a substrate. Forming the semiconductor layer stack includes forming alternating layers of semiconductor material. Each layer of the semiconductor layer stack has a different composition than each adjacent layer within the semiconductor layer stack. In some embodiments, each layer of the semiconductor layer stack is grown by a process such as VPE or MBE, or deposited by a process such as CVD, ALD, etc. In some embodiments, each layer in the semiconductor layer stack is formed using the same process. In some embodiments, at least one layer of the semiconductor layer stack is formed using a process different from at least another layer of the semiconductor layer stack. In some embodiments, each layer of the semiconductor layer stack having a first composition is formed using a first process, and each layer of the semiconductor layer stack having a second composition is formed using a second process different from the first process.

[0031] The first component comprises silicon. In some embodiments, the first component comprises pure silicon, for example, silicon atomic percentage is 95% or more. In some embodiments, the first component comprises silicon having a low concentration of germanium. In some embodiments, the atomic percentage of germanium in the first component is less than about 5%. The second component comprises silicon-germanium. The germanium concentration in the second component is greater than the germanium concentration in the first component. In some embodiments, the atomic percentage of germanium in the second component ranges from about 10% to about 50%. In some embodiments, operation 205 forms an alternating semiconductor layer stack 105 (Figure 1).

[0032] In operation 210, a semiconductor layer is formed. In some embodiments, operation 210 is integrated into operation 205. For example, in some embodiments, operation 210 is performed after a first execution of operation 205, and then operation 205 is performed a second time after operation 210. In some embodiments, operation 210 is a sub-operation within operation 205, wherein a semiconductor layer is formed using a third component, which has a second component in an alternating sequence. The third component has a higher germanium concentration than the second component. In some embodiments, the semiconductor layer comprises pure germanium, for example, germanium having an atomic percentage of at least 95%. In some embodiments, the semiconductor layer comprises silicon germanium. In some embodiments, the atomic percentage of germanium in the semiconductor layer ranges from about 60% to about 90%. In some embodiments, the semiconductor layer is grown by a process such as VPE or MBE, or deposited by a process such as CVD, ALD, etc. In some embodiments, the semiconductor layer is formed using the same process used to form a semiconductor layer having a second component. In some embodiments, the semiconductor layer is formed using a different process than that used to form a semiconductor layer having a second component. In some embodiments, operation 210 can be used to form semiconductor layer 110 (Figure 1).

[0033] In operation 215, a polycrystalline silicon layer is deposited over a stack of semiconductor layers, including semiconductor layers. In some embodiments, the polycrystalline silicon layer is deposited using CVD, PECVD, ALD, or another suitable deposition process. The polycrystalline silicon layer can be used to form a dummy gate structure.

[0034] In operation 220, the polysilicon layer is patterned to define openings on the surface of the exposed semiconductor layer stack. In some embodiments, the patterning process includes a combination of a lithography process and one or more etching processes. In some embodiments, the combination of operations 215 and 220 may be used to form mask material 155 or mask material 135 (Figure 1).

[0035] In operation 225, a gate spacer is formed along the sidewalls of a patterned polycrystalline silicon layer. The gate spacer is formed by depositing a dielectric material into the opening formed in operation 220 and then etching the dielectric material. In some embodiments, etching includes isotropic etching. In some embodiments, etching includes anisotropic etching. In some embodiments, the gate spacer comprises a monolayer structure. In some embodiments, the gate spacer comprises a multilayer structure. In some embodiments, the gate spacer comprises silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials. In some embodiments, the combination of operations 215 and 220 and operation 225 can be used to form masking material 155 or masking material 135 (Figure 1).

[0036] In some embodiments, operation 225 is omitted. Omitting operation 225 simplifies method 200. However, omitting operation 225 increases the difficulty of integrating stacked PIN diodes with CFET devices. In some embodiments, operation 225 is performed after operation 230 described below.

[0037] In operation 230, a first dopant type is implanted into a semiconductor layer stack. This implantation forms wells in the semiconductor layer stack at locations determined by openings in a patterned polysilicon layer. In some embodiments, the first dopant type is p-type. In some embodiments, the first dopant type is n-type. In some embodiments, the dopant dosage in operation 230 ranges from 1 × 10¹² cm² to approximately 5 × 10¹⁶ cm². In some embodiments, the dopant types used in operation 230 include boron, indium, gallium, or other suitable p-type dopants. In some embodiments, the dopant types used in operation 230 include phosphorus, arsenic, antimony, or other suitable n-type dopants.

[0038] In some embodiments, the implantation process of operation 230 uses ion beam energy, for example, in the range of about 1 keV to about 15 keV. Dopant is implanted into the semiconductor layer stack, for example, in the range of about 5 nm to about 20 nm. In some embodiments, the dopant concentration of the well formed by operation 230 ranges, for example, from about 1 × 10¹⁹ cm³ to about 1 × 10²¹ cm³. In some embodiments, an annealing process follows the implantation process. In some embodiments, no post-annealing is performed after implanting the dopant into the semiconductor layer stack. In some embodiments, operation 230 can be used to form an n-type well 140 or a p-type well 120 (Figure 1).

[0039] Figure 3A is a cross-sectional view of a stacked PIN diode 300A after operation 230 according to some embodiments. The stacked PIN diode 300A includes a substrate 302. A semiconductor layer stack 304 is located above the substrate 302. The semiconductor layer stack 304 includes a semiconductor layer 306. In some embodiments, the semiconductor layer stack 304 corresponds to an alternating semiconductor layer stack 105 (Figure 1). A patterned polysilicon layer 308 is located above the semiconductor layer stack 304. A gate spacer 310 is located along the sidewall of the patterned polysilicon layer 308. In some embodiments, the gate spacer 310 is omitted. In some embodiments, the patterned polysilicon layer 308 corresponds to a masking material 135 or a masking material 155 (Figure 1). In some embodiments, the combination of the patterned polysilicon layer 308 and the gate spacer 310 corresponds to a masking material 135 or a masking material 155 (Figure 1). The implantation process 312 is used to implant a first type of dopant onto the semiconductor layer stack 304. In some embodiments, the implantation process can be used to form a p-type well 120 or an n-type well 140 (Figure 1). In some embodiments, the gate spacer 310 is formed after the implantation process 312.

[0040] Returning to method 200, in operation 235, a first contact structure is formed on the surface of the semiconductor layer stack. A dielectric layer is deposited along the surface of the semiconductor layer stack. In some embodiments, the dielectric layer covers a patterned polysilicon layer. In some embodiments, the top surface of the dielectric layer is substantially coplanar with the top surface of the patterned polysilicon layer. The dielectric layer is patterned to define openings that expose at least a portion of the well formed in operation 230. A conductive material is then deposited into the openings in the dielectric layer to electrically connect to the well formed in operation 230. In some embodiments, a siliconization process is performed to enhance the electrical connection between the contact structure and the well formed in operation 230.

[0041] In some embodiments, the dielectric layer includes silicon oxide, silicon carbide, silicon oxynitride, silicon carbide, and combinations thereof, or other suitable dielectric materials. In some embodiments, the dielectric layer is formed using CVD, PECVD, ALD, or other suitable deposition processes. In some embodiments, the dielectric layer corresponds to a first dielectric layer 125 or a second dielectric layer 145 (Figure 1).

[0042] In some embodiments, the contact structure has a stepped profile, a tapered profile, or substantially parallel sidewalls. In some embodiments, the conductive material includes copper, aluminum, tungsten, cobalt, and their alloys or other suitable conductive materials. In some embodiments, the conductive material is deposited using physical vapor deposition (PVD), CVD, ALD, or other suitable deposition processes. In some embodiments, the formation of the contact structure includes depositing a diffusion barrier layer prior to depositing the conductive material to help prevent the conductive material from diffusing into the dielectric layer. In some embodiments, operation 235 can be used to form contact structure 130 or contact structure 150 (Figure 1).

[0043] In operation 240, the structure is flipped. The flipped structure includes a rotating structure such that the substrate is the uppermost surface of the structure. In some embodiments, a carrier is attached to the dielectric layer formed in operation 235 to facilitate the flipping of the structure. In some embodiments, the carrier is temporarily attached using an adhesive or other suitable attachment method. In some embodiments, the carrier remains attached to the dielectric layer until the formation of the stacked PIN diode is complete. In some embodiments, the carrier is removed from the dielectric layer after flipping. In some embodiments, a solution-dissolving adhesive is used to remove the carrier.

[0044] In operation 245, the substrate is removed. Removing the substrate exposes the surfaces of the semiconductor layer stack opposite to the well formed in operation 230. Exposing this surface of the semiconductor layer stack allows the semiconductor layer stack to be processed to form a stacked arrangement of stacked PIN diodes. In some embodiments, the substrate is removed by polishing, chemical mechanical planarization (CMP), etching, or a combination thereof.

[0045] In operation 250, a implantation mask is formed on the surface of the semiconductor layer stack exposed by removing the substrate. The implantation mask includes openings that expose portions of the semiconductor layer stack to implant doped wells on the surfaces of the semiconductor layer stack opposite the wells formed in operation 230. In some embodiments, the implantation mask includes a deposition or formation process followed by a patterning process. In some embodiments, the implantation mask includes a photoresist, silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the implantation mask is a single layer. In some embodiments, the implantation mask is a multilayer. In some embodiments, the implantation mask includes a hard mask located, for example, beneath a photoresist. In some embodiments, the hard mask includes titanium nitride, cobalt nitride, silicon nitride, or other suitable materials. In some embodiments, the patterning process includes lithography and etching processes.

[0046] In some embodiments, the placement mask is removed from the semiconductor layer stack after placement in operation 255 described below. In some embodiments, the placement mask is held on the semiconductor layer stack after placement in operation 255.

[0047] In operation 255, a second implantation process is performed on the semiconductor layer stack. Implantation is performed using the implantation mask formed in operation 250 to determine the implantation location on the semiconductor layer stack. The implantation process in operation 255 includes implanting a dopant having a dopant type opposite to the dopant implanted in operation 230. In some embodiments, the well formed by implantation operation 255 is aligned vertically with the well formed by implantation operation 230. In some embodiments, the second dopant type is p-type. In some embodiments, the second dopant type is n-type. In some embodiments, the dopant dose in operation 255 ranges from 1 × 10¹² cm² to about 5 × 10¹⁶ cm². In some embodiments, the dopant dose in operation 255 is the same as the dopant dose used in operation 230. In some embodiments, the dopant dose in operation 255 is different from the dopant dose used in operation 230. In some embodiments, the dopant type used in operation 255 includes boron, indium, gallium, or another suitable p-type dopant. In some embodiments, the dopant used in operation 255 includes phosphorus, arsenic, antimony, or another suitable n-type dopant.

[0048] In some embodiments, the implantation process of operation 255 uses ion beam energy, for example, in the range of about 1 keV to about 15 keV. Dopant is implanted into the semiconductor layer stack, for example, in the range of about 5 nm to about 20 nm. In some embodiments, the implantation depth of operation 255 is the same as the implantation depth of operation 230. In some embodiments, the implantation depth of operation 255 is different from the implantation depth of operation 230. In some embodiments, the dopant concentration of the well formed by operation 255 ranges, for example, from about 1 × 10¹⁹ cm³ to about 1 × 10²¹ cm³. In some embodiments, the dopant concentration of the well formed by operation 255 is the same as the dopant concentration of the well formed in operation 230. In some embodiments, the dopant concentration of the well formed by operation 255 is different from the dopant concentration of the well formed in operation 230. In some embodiments, an annealing process follows the implantation process. In some embodiments, post-annealing is not performed after implanting the dopant into the semiconductor layer stack. In some embodiments, operation 255 can be used to form an n-type well 140 or a p-type well 120 (Figure 1).

[0049] Figure 3B is a cross-sectional view of the stacked PIN diode 300B after operation 255 according to some embodiments. For simplicity, only the differences between the stacked PIN diode 300A (Figure 3A) and the stacked PIN diode 300B are described. The stacked PIN diode 300B is rotated 180 degrees relative to the stacked PIN diode 300A (Figure 3A), that is, flipped. Compared to the stacked PIN diode 300A (Figure 3A), a well 314 formed by the placement process 312 (Figure 3A) is included in the stacked PIN diode 300B. In some embodiments, the well 314 corresponds to an n-type well 140 (Figure 1). The stacked PIN diode 300B further includes a contact structure 316 extending through the dielectric layer 318. In some embodiments, the contact structure 316 and the dielectric layer 318 are formed in operation 235 (Figure 2). In some embodiments, contact structure 316 corresponds to contact structure 150 or contact structure 130 (Figure 1). In some embodiments, dielectric layer 318 corresponds to first dielectric layer 125 or second dielectric layer 145 (Figure 1).

[0050] The stacked PIN diode 300B further includes a placement mask 320 located on the surface of the semiconductor layer stack 304 opposite to well 314. In some embodiments, the placement mask 320 includes a photoresist, silicon nitride, silicon oxynitride, or other suitable material. In some embodiments, the placement mask is a single layer. In some embodiments, the placement mask 320 is multilayered. In some embodiments, the placement mask 320 includes a hard mask located, for example, beneath a photoresist. In some embodiments, the hard mask includes titanium nitride, cobalt nitride, silicon nitride, or other suitable material. The stacked PIN diode 300B also does not include a substrate 302 (Figure 3A). A placement process 322 is performed on the portion of the semiconductor layer stack 304 exposed by the placement mask 320. In some embodiments, the placement process 322 can be used to form an n-type well 140 or a p-type well 120 (Figure 1).

[0051] Returning to method 200, in operation 260, a second contact structure is formed on the surface of the semiconductor layer stack deposited during operation 255. A dielectric layer is deposited along the surface of the semiconductor layer stack. In some embodiments, the dielectric layer covers the deposited mask. In some embodiments, the top surface of the dielectric layer is substantially coplanar with the top surface of the deposited mask. The dielectric layer is patterned to define openings exposing at least a portion of the well formed by operation 255. A conductive material is then deposited into the openings in the dielectric layer to electrically connect to the well formed by operation 255. In some embodiments, a siliconization process is performed to enhance the electrical connection between the contact structure and the well formed by operation 255.

[0052] In some embodiments, the dielectric layer includes silicon oxide, silicon carbide, silicon oxynitride, silicon carbide, and combinations thereof, or other suitable dielectric materials. In some embodiments, the dielectric layer is formed using CVD, PECVD, ALD, or other suitable deposition processes. In some embodiments, the dielectric layer corresponds to a first dielectric layer 125 or a second dielectric layer 145 (Figure 1).

[0053] In some embodiments, the contact structure has a stepped profile, a tapered profile, or substantially parallel sidewalls. In some embodiments, the conductive material includes copper, aluminum, tungsten, cobalt, and their alloys or other suitable conductive materials. In some embodiments, the conductive material is deposited using physical vapor deposition (PVD), CVD, ALD, or other suitable deposition processes. In some embodiments, the formation of the contact structure includes depositing a diffusion barrier layer prior to depositing the conductive material to help prevent the conductive material from diffusing into the dielectric layer. In some embodiments, operation 260 can be used to form contact structure 130 or contact structure 150 (Figure 1).

[0054] Figure 3C is a cross-sectional view of a stacked PIN diode 300C after operation 260 according to some embodiments. For simplicity, only the differences between the stacked PIN diode 300B (Figure 3B) and the stacked PIN diode 300C are described. The stacked PIN diode 300C includes a contact structure 326 extending through a dielectric layer 328. In some embodiments, the contact structure 326 and the dielectric layer 328 are formed in operation 260 (Figure 2). In some embodiments, the contact structure 326 corresponds to contact structure 150 or contact structure 130 (Figure 1). In some embodiments, the dielectric layer 328 corresponds to a first dielectric layer 125 or a second dielectric layer 145 (Figure 1).

[0055] Returning to method 200, those skilled in the art will recognize that modifications to method 200 are within the scope of this specification. In some embodiments, at least one additional operation is performed in method 200. For example, in some embodiments, method 200 includes a removal process for removing the fabric mask formed in operation 250. In some embodiments, at least one operation of method 200 is omitted. For example, in some embodiments, the formation of the gate spacer in operation 225 is omitted. In some embodiments, the order of operations of method 200 is modified. For example, in some embodiments, operations 205 and 210 are performed together.

[0056] Figure 4 is a flowchart of a method 400 for simultaneously manufacturing a stacked PIN diode and a complementary field-effect transistor (CFET) according to some embodiments. In some embodiments, method 400 may be used to form a stacked PIN diode 100 (Figure 1). In some embodiments, method 400 produces an intermediate product of any one of the stacked PIN diodes 300A to 300C (Figures 3A to 3C). In some embodiments, method 400 may be used in conjunction with method 200 (Figure 2). During various operations of method 400, the workpiece portion to which the stacked PIN diode is to be formed is partially shielded to allow processing of the CFET device without affecting the structure of the stacked PIN diode. Method 400 facilitates the formation of a stacked PIN diode and one or more CFET devices in a single manufacturing process. This helps to improve the integration of devices in an IC and helps to reduce manufacturing complexity, thereby improving the efficiency of the manufacturing process.

[0057] In operation 405, a semiconductor layer stack is formed on a substrate. Forming the semiconductor layer stack includes forming alternating layers of semiconductor material. Each layer of the semiconductor layer stack has a different composition than each adjacent layer within the semiconductor layer stack. In some embodiments, each layer of the semiconductor layer stack is grown by a process such as VPE or MBE, or deposited by a process such as CVD, ALD, etc. In some embodiments, each layer in the semiconductor layer stack is formed using the same process. In some embodiments, at least one layer of the semiconductor layer stack is formed using a process different from at least another layer of the semiconductor layer stack. In some embodiments, each layer of the semiconductor layer stack having a first composition is formed using a first process, and each layer of the semiconductor layer stack having a second composition is formed using a second process different from the first process.

[0058] The first component comprises silicon. In some embodiments, the first component comprises pure silicon, for example, silicon atomic percentage is 95% or more. In some embodiments, the first component comprises silicon having a low concentration of germanium. In some embodiments, the atomic percentage of germanium in the first component is less than about 5%. The second component comprises silicon-germanium. The germanium concentration in the second component is greater than the germanium concentration in the first component. In some embodiments, the atomic percentage of germanium in the second component ranges from about 10% to about 50%. In some embodiments, operation 205 forms an alternating semiconductor layer stack 105 (Figure 1).

[0059] In operation 410, an active region is patterned. The active region defines the source / drain diffusion regions of the IC device. The active region includes doped portions of the semiconductor layer stack. In some embodiments, doping is performed by ion implantation. In some embodiments, doping is performed by in-situ doping during the formation of the semiconductor layer stack.

[0060] In operation 415, an isolation structure is formed around the patterned active region. The isolation structure can be used to electrically isolate a device from an adjacent device. In some embodiments, the isolation structure includes a shallow trench isolation (STI) structure. In some embodiments, the isolation structure is formed by removing a portion of a semiconductor layer stack to define an opening and depositing a dielectric material into the opening. In some embodiments, the dielectric material includes a single dielectric material. In some embodiments, the dielectric material includes a plurality of layers of one or more dielectric components. In some embodiments, the dielectric material includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0061] In operation 420, a polycrystalline silicon layer is deposited over a stack of semiconductor layers, including semiconductor layers. In some embodiments, the polycrystalline silicon layer is deposited using CVD, PECVD, ALD, or another suitable deposition process. The polycrystalline silicon layer can be used to form a dummy gate structure.

[0062] In operation 425, the polysilicon layer is patterned to define openings on the surface of the exposed semiconductor layer stack. In some embodiments, the patterning process includes a combination of a lithography process and one or more etching processes. In some embodiments, the combination of operations 420 and 425 may be used to form mask material 155 or mask material 135 (Figure 1).

[0063] Up to now, method 400 includes the following steps: processing the CFET device and the workpiece portion of the stacked PIN diode without shielding the stacked PIN diode portion of the workpiece.

[0064] In operation 430, a gate spacer is formed along the sidewalls of a patterned polycrystalline silicon layer. The gate spacer is formed by depositing a dielectric material into an opening formed in operation 425 and then etching the dielectric material. In some embodiments, etching includes isotropic etching. In some embodiments, etching includes anisotropic etching. In some embodiments, the gate spacer comprises a monolayer structure. In some embodiments, the gate spacer comprises a multilayer structure. In some embodiments, the gate spacer comprises silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials. In some embodiments, the combination of operations 420 and 425 and operation 430 can be used to form masking material 155 or masking material 135 (Figure 1).

[0065] In some embodiments, the stacked PIN diode portion of the workpiece is shielded during operation 430. Shielding the stacked PIN diode portion of the workpiece prevents the formation of gate spacers along the sidewalls of the stacked PIN diode portion, but allows the formation of gate spacers in the CFET portion of the workpiece.

[0066] Figure 5A is a cross-sectional view of a stacked PIN diode 500A after operation 430 according to some embodiments. The stacked PIN diode 500A includes a substrate 502. A semiconductor layer stack 504 is located above the substrate. The semiconductor layer stack 504 includes alternating layers of semiconductor material, each layer having a different composition from the adjacent layer. In some embodiments, the semiconductor layer stack 504 corresponds to an alternating semiconductor layer stack 105 (Figure 1). The semiconductor layer stack 504 includes a semiconductor layer 506. The semiconductor layer 506 includes germanium. In some embodiments, the semiconductor layer 506 further includes silicon. In some embodiments, the semiconductor layer 506 further includes a dopant, such as an n-type dopant or a p-type dopant. A patterned polycrystalline silicon layer 508 is located above the semiconductor layer stack 504. A gate spacer layer 510 is located above the patterned polycrystalline silicon layer 508. The stacked PIN diode 500A does not include etching the gate spacer layer 510 to remove the gate spacer layer from the top of the patterned polysilicon layer 508 or along the surface of the semiconductor layer stack 504. The stacked PIN diode 500A includes various other layers, such as a masking layer not labeled for the sake of diagrammatic simplicity.

[0067] Figure 6A is a cross-sectional view of a CFET 600A after operation 430 according to some embodiments. The CFET 600A includes a substrate 602. A semiconductor layer stack 604 is located above the substrate. The semiconductor layer stack 604 includes alternating layers of semiconductor material, each having a different composition from adjacent layers. In some embodiments, the semiconductor layer stack 604 corresponds to an alternating semiconductor layer stack 105 (Figure 1). The semiconductor layer stack 604 includes a semiconductor layer 606. A patterned polysilicon layer 608 is located above the semiconductor layer stack 604. A gate spacer layer 610 is located above the patterned polysilicon layer 608. The CFET 600A does not include etching the gate spacer layer 610 to remove the gate spacer layer from the top of the patterned polysilicon layer 608 or along the surface of the semiconductor layer stack 604. The CFET 600A includes various other layers, such as masking layers not labeled for schematic simplicity.

[0068] Returning to method 400 (Figure 4), in operation 435, etching is performed to define an opening for the source / drain (S / D) feature. The etching is performed on the CFET device while simultaneously masking the stacked PIN diode portion of the workpiece during the etching process. The etching process defines an opening extending through the semiconductor layer stack. In some embodiments, the etching process forms a recess in the substrate. In some embodiments, lithography is used to determine the location of the opening. In some embodiments, the etching includes a wet etching process.

[0069] Figure 5B is a cross-sectional view of a stacked PIN diode 500A after operation 435, according to some embodiments. Compared to the stacked PIN diode 500A (Figure 5A), the stacked PIN diode 500B includes a mask layer 512 located above the top surface of the gate spacer layer 510 to protect the stacked PIN diode 500B during the etching process of operation 435 (Figure 4). In some embodiments, the mask layer 512 includes a photoresist. In some embodiments, the mask layer 512 includes a plurality of layers, such as a hard mask beneath the photoresist.

[0070] Figure 6B is a cross-sectional view of CFET 600B after operation 435 according to some embodiments. Compared to CFET 600A (Figure 6A), CFET 600B includes an opening 612 extending through semiconductor layer stack 604. The opening 612 defines a recess in substrate 602. In some embodiments, the opening 612 does not form a recess in substrate 602.

[0071] Returning to method 400 (Figure 4), in operation 440, an inner spacer is formed. The inner spacer is formed along the sidewalls of the silicon-germanium layer of the semiconductor layer stack and separates the silicon-germanium layer of the semiconductor layer stack from the opening formed in operation 435. The inner spacer is also located between the lower portion of the subsequently formed active gate structure and the subsequently formed S / D structure. In some embodiments, the inner spacer comprises an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, or another suitable dielectric material.

[0072] In addition to forming the inner spacer, a semiconductor layer is formed in operation 440. The semiconductor layer is formed by removing the entire stacked semiconductor layer and replacing it with the dielectric material of the inner spacer. Since the stacked PIN diode portion of the workpiece is shielded during operation 440, the semiconductor layer in the stacked PIN diode portion of the workpiece is not replaced during operation 440.

[0073] In operation 445, a first S / D structure is formed in the opening formed by operation 435. The first S / D structure is closest to the substrate. In some embodiments, the first S / D structure is located within a recess in the substrate formed in operation 435. In some embodiments, the first S / D structure is formed by epitaxial growth of a semiconductor material (such as silicon or silicon-germanium). The semiconductor material is doped using a first type of dopant (e.g., a p-type dopant or an n-type dopant). In some embodiments, the semiconductor material is doped using an ion implantation process. In some embodiments, the semiconductor material is doped using an in-situ doping process. In some embodiments, an annealing process is performed after doping the semiconductor material.

[0074] In operation 450, an isolation structure is formed over the first S / D structure. The isolation structure is a dielectric material used to electrically isolate the first S / D structure formed in operation 445 from a second S / D structure formed subsequently. In some embodiments, the isolation structure includes silicon oxide, silicon nitride, silicon oxynitride, or another suitable dielectric material. In some embodiments, the isolation structure is formed by CVD, ALD, or another suitable deposition process. In some embodiments, the isolation structure is a single material. In some embodiments, the isolation structure includes a plurality of material layers, for example, with different compositions.

[0075] In operation 455, a second S / D structure is formed on the isolation structure in the opening formed in operation 435. The second S / D structure is furthest from the substrate. In some embodiments, the second S / D structure is formed by epitaxial growth of a semiconductor material (such as silicon or silicon-germanium). The semiconductor material is doped using a second type of dopant (e.g., a p-type dopant or an n-type dopant). The second type of dopant is the opposite of the first type of dopant. In some embodiments, the semiconductor material is doped using an ion implantation process. In some embodiments, the semiconductor material is doped using an in-situ doping process. In some embodiments, an annealing process is performed after doping the semiconductor material. In some embodiments, a single annealing process is performed after doping each of the first S / D structure and the second S / D structure.

[0076] Furthermore, during operation 455, a first doped well is formed in the stacked PIN diode portion of the workpiece. In some embodiments, the first doped well may be used to form an n-type well 140 or a p-type well 120 (Figure 1). In some embodiments, the ion implantation process in operation 455 is similar to operation 230 of method 200 (Figure 2). In some embodiments, the first doped well is formed simultaneously with the doping of the second S / D structure. In some embodiments, the first doped well is formed by a doping process different from the doping process used to form the second S / D structure.

[0077] During operations 435-450, the stacked PIN diode portion of the workpiece remains shielded. In some embodiments, during the doping process performed in operation 455, i.e., when the doping process forming the first well is performed simultaneously with the doping of the second S / D structure, the shielding layer above the stacked PIN diode portion of the workpiece is removed. In some embodiments, the shielding layer above the stacked PIN diode is removed after the doping of the second S / D structure. The first well is formed after the shielding layer is removed. In some embodiments, during the formation of the first well, i.e., when the doping process forming the first well is performed after the doping of the second S / D structure, the CFET portion of the workpiece is shielded.

[0078] Figure 5C is a cross-sectional view of a stacked PIN diode 500C after operation 455, according to some embodiments. Compared to a stacked PIN diode 500B (Figure 5B), the stacked PIN diode 500C does not include a masking layer 512 located on the top surface of the gate spacer layer 510. In some embodiments, the masking layer 512 is removed using an etching process, a dissolution process, an ashing process, or other suitable removal process. An ion implantation process 514 is performed to implant a first well in the stacked PIN diode 500C. In some embodiments, the ion implantation process 514 can be used to form an n-type well 140 or a p-type well 120 (Figure 1). The depth of the well formed by the implantation process 514 can be controlled based on the duration and energy of the implantation process 514. The maximum depth of the well produced by the implantation process 514 is less than the distance from the surface of the semiconductor layer stack 504 to the semiconductor layer 506.

[0079] Figure 6C is a cross-sectional view of CFET 600C after operation 455 according to some embodiments. Compared to CFET 600B (Figure 6B), CFET 600C includes an S / D structure 618 in opening 612. S / D structure 618 includes a first S / D structure (e.g., formed by operation 445 (Figure 4)), an isolation structure (e.g., formed by operation 450 (Figure 4)) and a second S / D structure (e.g., formed by operation 455 (Figure 4)). For the sake of simplicity, the various components of S / D structure 618 are not labeled. CFET 600C further includes an inner spacer 614 along the sidewalls of alternating layers of semiconductor layer stack 604. The inner spacer 614 separates S / D structure 618 from alternating layers of semiconductor layer stack 604. CFET 600C further includes an isolation layer 616. The isolation layer 616 comprises a material similar to that of the inner spacer 614; however, the entire corresponding semiconductor layer of the semiconductor layer stack 604 is replaced by a dielectric material to form the isolation layer 616.

[0080] Returning to method 400 (Figure 4), in operation 460, a contact etch stop layer (CESL) is formed. An inter-layer dielectric (ILD) layer is also formed over the CESL; and a planarization process is performed. The CESL and ILD are formed in the space between adjacent polysilicon structures. Each of the CESL and ILD includes a dielectric material; however, the dielectric material of the CESL is different from the dielectric material of the ILD. In some embodiments, the CESL and ILD independently include silicon oxide, silicon nitride, silicon oxynitride, or another suitable dielectric material. In some embodiments, the CESL is formed over a portion of a gate spacer layer that extends along the surface of the semiconductor layer stack. In some embodiments, a portion of the gate spacer layer that extends along the surface of the semiconductor layer stack is removed before the CESL is formed. In some embodiments, the CESL and ILD are formed independently by CVD, ALD, or another suitable deposition process.

[0081] A planarization process is used to planarize the top surface of the workpiece. In some embodiments, the planarization process includes a CMP process, an etching process, a combination thereof, or another suitable removal process. The stacked pin diode portion of the workpiece is not masked during operation 460.

[0082] Figure 5D is a cross-sectional view of a stacked PIN diode 500D after operation 460 according to some embodiments. Compared to a stacked PIN diode 500C (Figure 5C), the stacked PIN diode 500D includes a dielectric region 516. The dielectric region 516 includes CESL and ILD. For the sake of simplicity, the components of the dielectric region 516 are not labeled. A gate spacer layer 510 is retained between the dielectric region 516 and the semiconductor layer stack 504. In some embodiments, the gate spacer layer 510 is removed, and the dielectric region 516 directly contacts the semiconductor layer stack 504. The top surface of the stacked PIN diode 500D is planarized due to a planarization process.

[0083] Figure 6D is a cross-sectional view of the CFET 600D after operation 460 according to some embodiments. Compared to CFET 600C (Figure 6C), CFET 600D includes a dielectric region 620. The dielectric region 620 includes CESL and ILD. For the sake of simplicity, the components of the dielectric region 620 are not labeled. A gate spacer layer 610 is retained between the dielectric region 620 and the semiconductor layer stack 604. In some embodiments, the gate spacer layer 610 is removed, and the dielectric region 620 directly contacts the semiconductor layer stack 604. Due to the planarization process, the top surface of CFET 600D is flat.

[0084] Returning to method 400 (Figure 4), in operation 465, the patterned polysilicon is removed. In some embodiments, the patterned polysilicon is removed using a wet etching process, an oxidation process, or another suitable removal process. In some embodiments, removing the patterned polysilicon exposes a portion of the semiconductor layer stack. In some embodiments where the dummy gate structure includes a gate dielectric layer, removing the patterned polysilicon exposes the gate dielectric layer. In some embodiments where the dummy gate structure includes a gate dielectric layer, the gate dielectric layer is also removed in operation 465. In some embodiments, during the removal of the patterned polysilicon, the stacked PIN diode portion of the workpiece is masked. In some embodiments, the stacked PIN diode portion of the workpiece is not masked, and the patterned polysilicon on the stacked PIN diode portion is removed by operation 465.

[0085] Figure 5E is a cross-sectional view of the stacked PIN diode 500E after operation 465 according to some embodiments. Compared with the stacked PIN diode 500D (Figure 5D), the patterned polysilicon layer 508 is removed from the stacked PIN diode 500E.

[0086] Figure 6E is a cross-sectional view of CFET 600E after operation 465 according to some embodiments. Compared with CFET 600D (Figure 6D), the patterned polysilicon layer 608 is removed from CFET 600E.

[0087] Returning to method 400 (Figure 4), in operation 470, the silicon-germanium layer of the semiconductor layer stack is removed. Removal of the silicon-germanium layer of the semiconductor layer stack defines openings between the inner spacers formed in operation 440 and exposes the surface of the silicon layer of the semiconductor layer stack. In some embodiments, the etching process selectively removes the silicon layer or the silicon-germanium layer of various dielectric layers relative to the CFET portion of the workpiece. For example, the etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, a patterned masking layer, such as an etch mask, is formed to protect the CESL, ILD, and the top surface of the semiconductor layer stack during the etching process. The stacked PIN diode portion of the workpiece is masked during operation 470, so that the silicon-germanium layer in the semiconductor layer stack of the stacked PIN diode portion of the workpiece remains after operation 470.

[0088] Figure 5F is a cross-sectional view of a stacked PIN diode 500F after operation 470, according to some embodiments. Compared to a stacked PIN diode 500E (Figure 5E), the stacked PIN diode 500F includes a masking layer 518. In some embodiments, the masking layer 518 comprises the same material as the masking layer 512 (Figure 5B). In some embodiments, the masking layer 518 comprises a different material than the masking layer 512 (Figure 5B).

[0089] Figure 6F is a cross-sectional view of the CFET 600F after operation 470 according to some embodiments. Compared with CFET 600E (Figure 6E), the silicon-germanium layer of the semiconductor layer stack 604 is removed, thereby forming a gap within the semiconductor layer stack 604 of the CFET 600F.

[0090] Returning to method 400 (Figure 4), in operation 475, a gate structure is formed in the opening defined in operation 470. The gate structure includes a gate dielectric layer, such as a high-k gate dielectric layer, and a conductive material. In some embodiments, the gate structure includes additional layers, such as a work function layer, a barrier layer, or other suitable layers. In some embodiments, the gate dielectric layer is formed by CVD, ALD, PVD, or other suitable deposition processes. In some embodiments, the conductive material is formed by CVD, ALD, PVD, plating, or other suitable deposition processes. Operation 475 also forms the gate structure in the opening defined by the removal of patterned polysilicon in operation 465. In some embodiments, the stacked PIN diode portion of the workpiece is shielded throughout the process of performing operation 475. In some embodiments, during the formation of a gate structure within a semiconductor layer stack, the stacked PIN diode portion of the workpiece is shielded, and then during the formation of the gate structure in an opening defined by the removal of patterned polysilicon in operation 465, the stacked PIN diode portion of the workpiece is not shielded.

[0091] Figure 5G is a cross-sectional view of a stacked PIN diode 500G after operation 475, according to some embodiments. Compared to a stacked PIN diode 500F (Figure 5F), the stacked PIN diode 500G includes a gate structure 520 that fills an opening defined by removing a patterned polysilicon layer 508. For the sake of brevity, the individual components of the gate structure 520 are not labeled.

[0092] Figure 6G is a cross-sectional view of the CFET 600G after operation 475 according to some embodiments. Compared to CFET 600F (Figure 6F), CFET 600G includes a gate structure 624 that fills an opening defined by removing a patterned polysilicon layer 608. For the sake of simplicity, the individual component of the gate structure 624 is not labeled. CFET 600G further includes a gate structure 626 that fills an opening defined by removing a silicon-germanium portion of the semiconductor layer stack 604.

[0093] Returning to method 400 (Figure 4), in operation 480, a first interconnect structure is formed. The first interconnect structure is electrically connected to a first well in the stacked PIN diode portion of the workpiece. The first interconnect structure is electrically connected to a second S / D structure in the CFET portion of the workpiece. Those skilled in the art will understand that although the first interconnect structure is electrically connected as a whole to the first well and the second S / D structure, the first interconnect structure does not necessarily electrically connect the first well to the second S / D structure. The first interconnect structure is formed by removing the CESL and ILD formed in operation 460 to expose the first well in the stacked PIN diode portion of the workpiece and the second S / D structure in the CFET portion of the workpiece. A contact structure is then formed in the opening defined by removing the CESL and ILD. In some embodiments, the formation of the contact structure is similar to operation 235 (Figure 2). The formation of the first interconnect structure continues, depositing one or more dielectric layers, removing portions of the dielectric layers, and forming a conductive material in the resulting openings in the dielectric layers. For simplicity, details of the formation of the interconnect structure are not provided.

[0094] Figure 5H is a cross-sectional view of a stacked PIN diode 500H during operation 480 according to some embodiments. Compared with the stacked PIN diode 500G (Figure 5G), the dielectric region 516 in the stacked PIN diode 500H is removed to expose a portion of the semiconductor layer stack 504.

[0095] Figure 6H is a cross-sectional view of CFET 600H during operation 480 according to some embodiments. Compared with CFET 600G (Figure 6G), dielectric region 620 in CFET 600H is removed to expose a portion of S / D structure 618.

[0096] Figure 5I is a cross-sectional view of a stacked PIN diode 500I after operation 480 according to some embodiments. Compared with a stacked PIN diode 500H (Figure 5H), the stacked PIN diode 500I includes a contact structure 522 electrically connected to a first well; and an interconnect structure 524 electrically connected to the contact structure 522.

[0097] Figure 61 is a cross-sectional view of CFET 600I after operation 480 according to some embodiments. Compared with CFET 600H (Figure 6H), CFET 600I includes a contact structure 628 and a second S / D structure electrically connected to S / D structure 618. Interconnect structure 630 is electrically connected to contact structure 628.

[0098] Returning to method 400 (Figure 4), in operation 485, a second well is implanted in the stacked PIN diode portion of the workpiece. Operation 485 further includes flipping the workpiece and removing the substrate from the workpiece to expose the surface of the semiconductor layer stack opposite to the first interconnect structure formed in operation 480. In some embodiments, the flipping of the workpiece is similar to operation 240 (Figure 2). In some embodiments, the removal of the substrate is similar to operation 245 (Figure 2).

[0099] The second well placement includes forming a placement mask, for example, operation 250 (Figure 2). A second dopant is then placed into the semiconductor layer stack in the stacked PIN diode portion of the workpiece. In some embodiments, the placement process is similar to operation 255 (Figure 2). In some embodiments, the CFET portion of the workpiece is masked throughout operation 485. In some embodiments, the CFET portion of the workpiece is not masked to form a placement mask, and then masked for the placement process.

[0100] Figure 5J is a cross-sectional view of a stacked PIN diode 500J after operation 485 according to some embodiments. Compared to a stacked PIN diode 500I (Figure 5I), the stacked PIN diode 500J includes a placement mask 526 located on the surface of the semiconductor layer stack 504 opposite to the interconnect structure 524. A placement process 528 is performed on the portion of the semiconductor layer stack 504 exposed by the placement mask 526. The stacked PN diode 500J does not include a substrate 502. The depth of the well formed using the placement process 528 can be controlled based on the duration and energy of the placement process 528. The maximum depth of the well formed by the placement process 528 is less than the distance from the surface of the semiconductor layer stack 504 to the semiconductor layer 506.

[0101] Figure 6J is a cross-sectional view of CFET 600J after operation 485 according to some embodiments. Compared to CFET 600I (Figure 6I), CFET 600J includes a placement mask 632. An opening in the placement mask 632 exposes the S / D structure 618. CFET 600J does not include a substrate 602. In some embodiments, the placement mask 632 includes a dummy gate structure.

[0102] Returning to method 400 (Figure 4), in operation 490, a second interconnect structure is formed. The second interconnect structure is electrically connected to a second well in the stacked PIN diode portion of the workpiece. The second interconnect structure is electrically connected to a first S / D structure in the CFET portion of the workpiece. Those skilled in the art will understand that although the second interconnect structure is electrically connected as a whole to the second well and the first S / D structure, the second interconnect structure does not necessarily electrically connect the second well to the first S / D structure. A contact structure is then formed in the opening defined by the planting mask. In some embodiments, the formation of the contact structure is similar to operation 260 (Figure 2). The formation of the second structure continues, depositing one or more dielectric layers, removing portions of the dielectric layers, and forming a conductive material in the resulting openings of the dielectric layers. For simplicity, details of the formation of the interconnect structure are not provided.

[0103] Figure 5K is a cross-sectional view of a stacked PIN diode 500K after operation 490 according to some embodiments. Compared with a stacked PIN diode 500J (Figure 5J), the stacked PIN diode 500K includes a contact structure 530 electrically connected to a second well; and an interconnect structure 532 electrically connected to the contact structure 530.

[0104] Figure 6K is a cross-sectional view of CFET 600K after operation 490 according to some embodiments. Compared with CFET 600J (Figure 6J), CFET 600K includes a contact structure 634, a first S / D structure electrically connected to S / D structure 618. Interconnect structure 636 is electrically connected to contact structure 634.

[0105] Method 400 can be used to simultaneously form a CFET device and a stacked PIN diode. Those skilled in the art will understand that modifications to method 400 are within the scope of their skill. In some embodiments, at least one operation is added to method 400. For example, in some embodiments, method 400 includes a workpiece flipping and / or substrate removal operation. In some embodiments, at least one operation is omitted from method 400. For example, in some embodiments, operation 430 is omitted from method 400. In some embodiments, the order of operations of method 400 is adjusted. For example, in some embodiments, the formation of the S / D structure is divided into: a first process performed from a first surface of the semiconductor layer stack (e.g., before flipping the workpiece) and a second process performed from a second surface of the semiconductor layer stack (e.g., after flipping the workpiece).

[0106] Figure 7 is a schematic diagram of an integrated circuit (IC) 700 including stacked PIN diodes according to some embodiments. IC 700 includes a header switch 702 connected to a memory cell 704. Those skilled in the art will understand that this specification is not limited to the use of stacked PIN diodes in the header switch 702, and other implementations of stacked PIN diodes in IC devices are also within the scope of this specification. Other implementations of stacked PIN diodes in this specification include bipolar transistors (BJTs) or other passive devices.

[0107] According to some embodiments, a header switch 702 is electrically located between power line 710 and memory power line 712. In some embodiments, power line 710 is maintained at an upper power supply voltage VCC, while memory power line 712 (used as a dummy power line) is connected to one or more memory cells 704. The header switch 702 is in an on or off state under the control of a power control signal PG. When the header switch 702 is in the on state, memory power line 712 is connected to power line 710, so the upper power supply voltage VCC on power line 710 is applied to memory cell 704. When the header switch 702 is in the off state, the power connection between memory power line 712 and power line 710 is broken, thus preventing the upper power supply voltage VCC on power line 710 from being applied to memory cell 704. The header switch 702 provides a power management scheme that allows memory cell 704 to receive power as needed.

[0108] The header switch 703 includes a CFET transistor 706 and a stacked PIN diode 708. In some embodiments, the CFET transistor 706 is a p-type CFET transistor. The source terminal of the CFET transistor 706 is connected to the power line 710. The first terminal of the stacked PIN diode 708 is connected to the memory power line 712. The drain terminal of the CFET transistor 706 is connected to the second terminal of the stacked PIN diode 708. The gate terminal of the CFET transistor 706 is used to receive a power control signal PG. When the power control signal PG is at a logic low voltage level, the header switch 703 is set to the ON state. When the power control signal PG is at a logic high voltage level, the header switch 703 is set to the OFF state.

[0109] This specification relates to a diode structure. The diode structure includes: a first semiconductor layer stack, wherein the first semiconductor layer stack includes alternating arrangements of a plurality of first semiconductor layers and a plurality of second semiconductor layers, and each of the first semiconductor layers has a different composition than each of the second semiconductor layers. The diode structure further includes: a second semiconductor layer stack, wherein the second semiconductor layer stack includes alternating arrangements of a plurality of third semiconductor layers and a plurality of fourth semiconductor layers, and each of the third semiconductor layers has a different composition than each of the fourth semiconductor layers. The diode structure further includes: a fifth semiconductor layer, located between the first semiconductor layer stack and the second semiconductor layer stack, wherein the composition of the fifth semiconductor layer is different from each of the first semiconductor layer, each of the second semiconductor layer, each of the third semiconductor layer, and each of the fourth semiconductor layer. The diode structure further includes: an n-type doped region located in the first semiconductor layer stack. The diode structure further includes: a p-type doped region located in the second semiconductor layer stack. In some embodiments, each of the first semiconductor layers has the same composition as each of the third semiconductor layers. In some embodiments, each of the second semiconductor layers has the same composition as each of the fourth semiconductor layers. In some embodiments, each of the first semiconductor layers and each of the third semiconductor layers comprises silicon. In some embodiments, each of the second semiconductor layers and each of the fourth semiconductor layers comprises silicon germanium, and the germanium concentration of each of the second semiconductor layers is higher than the germanium concentration of each of the first semiconductor layers. In some embodiments, the fifth semiconductor layer comprises silicon germanium, and the germanium concentration of the fifth semiconductor layer is greater than the germanium concentration of each of the second semiconductor layers. In some embodiments, the n-type doped regions are vertically aligned with the p-type doped regions.

[0110] This specification relates to a semiconductor device. The semiconductor device includes a complementary field-effect transistor (CFET) device. The semiconductor device further includes a stacked PIN diode connected to the CFET device. The stacked PIN diode includes a first semiconductor layer stack, wherein the first semiconductor layer stack includes alternating layers having a first component and a second component, and the first component is different from the second component. The stacked PIN diode further includes a second semiconductor layer stack, wherein the second semiconductor layer stack includes alternating layers having a first component and a second component. The stacked PIN diode further includes an intermediate semiconductor layer located between the first semiconductor layer stack and the second semiconductor layer stack, wherein the composition of the intermediate semiconductor layer is different from the first component and the second component. The stacked PIN diode further includes a plurality of n-type doped regions located in the first semiconductor layer stack. The stacked PIN diode further includes a plurality of p-type doped regions located in the second semiconductor layer stack. In some embodiments, each of the n-type doped regions is vertically aligned with a corresponding p-type doped region among the p-type doped regions. In some embodiments, a CFET device includes: a plurality of first channel layers; a plurality of second channel layers; and an isolation layer located between the first channel layers and the second channel layers. In some embodiments, the intermediate semiconductor layer and the isolation layer are horizontally aligned. In some embodiments, the number of the first channel layers is equal to the number of layers having a first component in the first semiconductor layer stack. In some embodiments, the first component comprises silicon, the second component comprises silicon germanium, and the germanium concentration of the second component is greater than the germanium concentration of the first component. In some embodiments, the first component does not contain germanium. In some embodiments, the germanium concentration of the first component is greater than the germanium concentration of the second component. In some embodiments, the CFET device is connected in parallel with a stacked PIN diode. In some embodiments, the stacked PIN diode further includes: a dummy gate structure disposed along the surface of the first semiconductor layer stack, wherein the dummy gate structure includes a first gate spacer. In some embodiments, the CFET device further includes a gate structure, wherein the gate structure includes a second gate spacer. In some embodiments, the top surface of the first gate spacer and the top surface of the second gate spacer are coplanar.

[0111] This specification relates to a method for manufacturing a diode structure. The method includes the steps of: forming a semiconductor layer stack, wherein the semiconductor layer stack comprises alternating layers with different compositions, and a central semiconductor layer of the semiconductor layer stack has a composition different from all other layers in the semiconductor layer stack. The method further includes the step of: forming a first implantation mask on a first surface of the semiconductor layer stack. The method further includes the step of: implanting a dopant of a first doping type into the first surface of the semiconductor layer stack using the first implantation mask. The method further includes the step of: forming a second implantation mask on a second surface of the semiconductor layer stack, wherein the second implantation mask is perpendicularly aligned with the first implantation mask. The method further includes the step of: implanting a dopant of a second doping type into the second surface of the semiconductor layer stack using the second implantation mask, wherein the second doping type is opposite to the first doping type.

[0112] The foregoing has summarized the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The various aspects of this disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 is a cross-sectional view of a stacked PIN diode according to some embodiments. Figure 2 is a flowchart of a method for manufacturing a stacked PIN diode according to some embodiments. Figures 3A to 3C are cross-sectional views of a stacked PIN diode at various manufacturing stages according to some embodiments. Figure 4 is a flowchart of a method for simultaneously manufacturing a stacked PIN diode and a complementary field-effect transistor (CFET) according to some embodiments. Figures 5A to 5K are cross-sectional views of a stacked PIN diode manufactured simultaneously with a CFET according to some embodiments. Figures 6A to 6K are cross-sectional views of a CFET manufactured simultaneously with a stacked PIN diode according to some embodiments. Figure 7 is a schematic diagram of an integrated circuit (IC) including stacked PIN diodes according to some embodiments. [Biomaterial Storage]

[0114] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A diode structure comprising: a first semiconductor layer stack, wherein the first semiconductor layer stack comprises: a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged in an alternating manner, and each of the first semiconductor layers has a different composition from each of the second semiconductor layers, wherein at least one of the second semiconductor layers has a higher germanium concentration than the germanium concentration of at least one of the first semiconductor layers; a second semiconductor layer stack, wherein the second semiconductor layer stack comprises: a plurality of third semiconductor layers and a plurality of fourth semiconductor layers arranged in an alternating manner, and each of the third semiconductor layers has a different composition from each of the fourth semiconductor layers, wherein each of the second semiconductor layers and each of the fourth semiconductor layers comprises silicon germanium; a fifth semiconductor layer located between the first semiconductor layer stack and the second semiconductor layer stack, wherein a composition of the fifth semiconductor layer is different from each of the first semiconductor layers, each of the second semiconductor layers, each of the third semiconductor layers and each of the fourth semiconductor layers; An n-type doped region is located in the first semiconductor layer stack; and a p-type doped region is located in the second semiconductor layer stack.

2. The diode structure as claimed in claim 1, wherein each of the first semiconductor layers and each of the third semiconductor layers comprises silicon.

3. The diode structure as claimed in claim 1, wherein the fifth semiconductor layer comprises silicon germanium, and the germanium concentration of the fifth semiconductor layer is greater than the germanium concentration of each of the second semiconductor layers.

4. A semiconductor device comprising: a complementary field-effect transistor (FET) device; and a stacked PIN diode connected to the complementary field-effect transistor device, wherein the stacked PIN diode comprises: a first semiconductor layer stack, wherein the first semiconductor layer stack comprises a plurality of alternating layers having a first component and a second component, and the first component is different from the second component, wherein the first component comprises silicon and does not contain germanium, and the second component comprises silicon-germanium; a second semiconductor layer stack, wherein the second semiconductor layer stack comprises a plurality of alternating layers having the first component and the second component; an intermediate semiconductor layer located between the first semiconductor layer stack and the second semiconductor layer stack, wherein a component of the intermediate semiconductor layer is different from the first component and the second component; a plurality of n-type doped regions located in the first semiconductor layer stack; and a plurality of p-type doped regions located in the second semiconductor layer stack.

5. The semiconductor device of claim 4, wherein each of the n-type doped regions is perpendicularly aligned with a corresponding p-type doped region of the p-type doped regions.

6. The semiconductor device of claim 4, wherein the complementary field-effect transistor device comprises: a plurality of first channel layers; a plurality of second channel layers; and an isolation layer located between the first channel layers and the second channel layers.

7. The semiconductor device as claimed in claim 6, wherein the intermediate semiconductor layer is horizontally aligned with the isolation layer.

8. The semiconductor device as claimed in claim 4, wherein the complementary field-effect transistor device is connected in parallel with the stacked PIN diode.

9. The semiconductor device of claim 4, wherein the stacked PIN diode further comprises: a dummy gate structure stacked along a surface of the first semiconductor layer, wherein the dummy gate structure includes a first gate spacer.

10. A method of manufacturing a diode structure, comprising: forming a semiconductor layer stack, wherein the semiconductor layer stack includes a plurality of alternating layers having a first component and a second component, wherein the first component is different from the second component, wherein the first component and the second component include silicon and germanium, and the germanium concentration of the second component is greater than the germanium concentration of the first component, and a central semiconductor layer of the semiconductor layer stack has a component different from all other layers in the semiconductor layer stack; forming a first implantation mask on a first surface of the semiconductor layer stack; implanting a dopant of a first doping type into the first surface of the semiconductor layer stack using the first implantation mask; forming a second implantation mask on a second surface of the semiconductor layer stack, wherein the second implantation mask is perpendicularly aligned with the first implantation mask; and implanting a dopant of a second doping type into the second surface of the semiconductor layer stack using the second implantation mask, wherein the second doping type is opposite to the first doping type.

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