Semiconductor device and method of manufacturing semiconductor device

Abstract

One embodiment of a semiconductor device includes a memory cell array, a first conductive structure for carrying a first control signal for operating a group of memory cells in the memory cell array, and a second conductive structure electrically coupled to the first conductive structure and for carrying the first control signal for operating the group of memory cells in the memory cell array. The memory cells in the group of memory cells are arranged along a first horizontal direction. The first conductive structure and the second conductive structure extend along the first horizontal direction. The first conductive structure and the second conductive structure are spaced apart in a second horizontal direction, in a vertical direction, or in both the second horizontal direction and the vertical direction.

Description

Technical Field

[0001] none Prior Technology

[0002] Modern integrated circuit (IC) manufacturing technology has enabled faster, smaller, and more efficient devices. In many applications, the size of electronic components and transistors has been reduced to include more components, and even more layers of components, within a semiconductor die. These advancements in IC manufacturing technology support the development of a wide variety of digital devices, such as semiconductor devices that include memory cell arrays for storing data.

[0003] In some applications, semiconductor devices including memory cell arrays further include conductive structures for carrying control signals for operations on the memory cell array, such as read operations, write operations, erase operations, combinations thereof, or the like. As the size of electronic components and transistors becomes smaller, the area used to implement the conductive structures for carrying control signals also becomes smaller. In some applications, the resistance level of the conductive structure increases as its linewidth decreases. In some applications, the drive load and corresponding signal delay of the signal lines increase with the resistance level of the signal lines. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a schematic block diagram of a memory device according to some embodiments. Figure 2 is a cross-sectional view of a semiconductor device according to some embodiments. Figures 3A to 3B are layout diagrams of a first layout example according to some embodiments. Figures 3C to 3D are cross-sectional views of a semiconductor device based on a first layout example in Figures 3A to 3B, according to some embodiments. Figure 4A is a layout diagram of a second layout example according to some embodiments. Figures 4B to 4C are cross-sectional views of a semiconductor device based on a second layout example in Figure 4A, according to some embodiments. Figure 5A is a layout diagram of a third layout example according to some embodiments. Figures 5B to 5C are cross-sectional views of a semiconductor device based on a third layout example in Figure 5A, according to some embodiments. Figure 6A is a layout diagram of a fourth layout example according to some embodiments. Figures 6B to 6C are cross-sectional views of a semiconductor device based on the fourth layout example in Figure 6A, according to some embodiments. Figure 7A is a layout diagram of a fifth layout example according to some embodiments. Figures 7B to 7C are cross-sectional views of a semiconductor device based on the fifth layout example in Figure 7A, according to some embodiments. Figure 8A is a layout diagram of a sixth layout example according to some embodiments. Figures 8B to 8C are cross-sectional views of a semiconductor device based on the sixth layout example in Figure 8A, according to some embodiments. Figures 9A to 9C are schematic diagrams of layout planning examples of semiconductor devices including memory devices according to some embodiments. Figures 10A to 10B are cross-sectional views of examples of semiconductor devices according to some embodiments. Figure 11 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments. Figure 12 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Figure 13 is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments. Implementation

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to digits and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s) or feature(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted similarly accordingly. Additionally, the term "made of" may mean "including" or "consisting of." In this disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and unless otherwise stated, does not mean an element from A, an element from B, and an element from C.

[0008] Figure 1 is a schematic block diagram of a memory device 100 according to some embodiments. In some embodiments, the memory device 100 is included in a semiconductor device. In some embodiments, the semiconductor device including the memory device 100 further includes other components and / or circuit systems for other functionalities.

[0009] In Figure 1, the memory device 100 includes a memory cell array 110 and a control circuitry system 120 coupled to the memory cell array 110. The memory cell array 110 includes memory cells (labeled "MC" in Figure 1) arranged in columns and rows. In some embodiments, the control circuitry system 120 is used to control the operation of the memory cells in the memory cell array 110. In Figure 1, as a non-limiting example, the memory device 100 further includes a plurality of word lines WL_0 to WL_m-1 extending along the column direction, a plurality of bit lines (also referred to as "data lines") BL_0 to BL_k-1 extending along the row direction, and a plurality of source lines SL_0 to SL_k-1 extending along the row direction of the memory cell array 110. Each of the memory cells MC is coupled to the control circuitry system 120 by at least one of the word lines, at least one of the bit lines, and at least one of the source lines.

[0010] Examples of word lines include, but are not limited to, read word lines for carrying read word line signals based on the address of a memory cell MC to be read, write word lines for carrying the address of a memory cell MC to be written, or the like. In at least one embodiment, a set of word lines is used as both read word lines and write word lines. Examples of bit lines include read bit lines for carrying data signals read from a memory cell MC initiated by a corresponding word line, data signals to be written to a memory cell MC initiated by a corresponding word line, or the like. In at least one embodiment, a set of bit lines is used as both read bit lines and write bit lines. In one or more embodiments, each memory cell MC is coupled to a pair of bit lines referred to as a bit line and a bit line bar (or complementary bit line). In some embodiments, a source line is used to carry a source line signal corresponding to a current path that establishes a selected subset of memory cells MC based on the address of the memory cell MC.

[0011] In this disclosure, word lines are also referred to as WL, bit lines as BL, and source lines as SL. Various numbers of word lines, bit lines, and / or source lines in the memory device 100 are also within the scope of various embodiments. In Figure 1, which is a non-limiting example, the source lines extend along the row direction. In some other embodiments, the source lines extend along the column direction. In some other embodiments, the source lines are omitted.

[0012] In Figure 1, as a non-limiting example, the control circuitry system 120 includes a decoder 122, a plurality of word line drivers 124, a plurality of sense amplifiers and / or bit line drivers 126, and a plurality of source line drivers 128. In some embodiments, the decoder 122 interprets at least a portion of an address to be accessed during a read or write operation and activates a corresponding one of the word line drivers 124 to activate one of the word lines corresponding to that address. In some embodiments, the selected word line driver 124 activates a specific column based on activating the corresponding word line, thereby enabling access to memory cells in that column. In some embodiments, the decoder 122 interprets at least another portion of an address and selects one of the sense amplifiers and / or bit line drivers 126 coupled to one of the bit lines corresponding to that address. In some embodiments, the selected sense amplifier and / or bit line driver 126 is used to read binary values ​​stored in memory cells specified by the decoded columns and rows via the corresponding bit lines. In some embodiments, a selected sense amplifier and / or bit line driver 126 is used to write a binary value to be stored in a memory cell specified by the decoded column and row through a corresponding bit line. In some embodiments, the decoder 122 further selectively activates one of the source line drivers 128 to supply voltage to the selected source line and supply different voltages to the unselected source line. In some embodiments, the source lines and source line drivers 128 are omitted.

[0013] In some embodiments, the control circuit system 120 further includes one or more clock generators for providing clock signals to various components in the memory device 100, one or more input / output (I / O) circuits for exchanging data with external devices, and / or one or more control circuit blocks for controlling various operations in the memory device 100. In some embodiments, the configuration of the memory device 100 is available and / or modifiable to implement a read-only memory device, a write-once memory device, an erasable memory device, a reprogrammable memory device, or a read-write memory device. In some embodiments, a memory cell MC corresponds to a volatile memory cell, such as a dynamic random access memory (DRAM) cell or a static random access memory (SRAM) cell. In some embodiments, the memory cell MC corresponds to a non-volatile memory cell, such as a floating gate memory cell, a ferroelectric random access memory (FRAM) cell, a magnetic random access memory (MRAM) cell, a phase-change memory (PCM) cell, or a resistive random access memory (RRAM) cell.

[0014] In Figure 1, as a non-limiting example, memory device 100 includes a memory cell array 110. In some embodiments, the memory device includes one or more memory cell arrays controllable by a control circuitry system.

[0015] Figure 2 is a cross-sectional view of a semiconductor device 200 according to some embodiments. In some embodiments, the semiconductor device 200 includes a memory device configured based on the example shown in Figure 1. In some embodiments, the cross-sectional view is a simplified cross-sectional view, in which many features are simplified or not depicted.

[0016] The semiconductor device 200 in Figure 2 includes a substrate 210 having an active region 212 and a gate structure 214 formed on or partially formed in the substrate 210. In this example, the semiconductor device 200 includes a metal-to-drain / source (MD) structure 222 coupled to the active region 212. In this example, the semiconductor device 200 includes a via-to-drain / source (VD) structure coupled to the MD structure 222 at a VD / VG layer above the substrate 210 (relative to direction Z) and a via-to-gate (VG) structure coupled to the gate structure 214. In some embodiments, the semiconductor device 200 further includes a VD / VG layer and a plurality of metallization layers (e.g., M0, M1, M2, ..., Mn-1, and Mn layers) and a plurality of via layers (e.g., V0, V1, V2, ..., Vn-2, and Vn-1 layers) above the substrate 210 (n is a positive integer). In some embodiments, the number of metallization layers above the substrate 210 is in the range of 8 to 14. In some embodiments, the Vn-1 layer represents a via structure between the Mn-1 layer and the Mn layer and connecting the wires therethrough. In some embodiments, the M0 layer represents a first metallization layer above the substrate 210. In some embodiments, the plurality of metallization layers and the plurality of via layers comprise a conductive material, which includes copper, aluminum, gold, tungsten, combinations thereof, or the like.

[0017] As a non-limiting example, the semiconductor device 200 in Figure 2 further includes conductive structures disposed beneath the substrate 210. For example, the semiconductor device 200 further includes rear-side metallization layers BMO and BM1, and rear-side via layers BVD and BVO. In this example, the BVD layer represents a rear-side via structure connecting the active region 212 and the rear-side conductors in the BMO layer; the BVO layer represents a rear-side via structure connecting the rear-side conductors in the BMO and BM1 layers. In some embodiments, the BMO layer represents a first metallization layer beneath the substrate 210. In this example, the semiconductor device 200 includes two rear-side metallization layers and corresponding via layers. In some embodiments, the number of rear-side metallization layers beneath the substrate 210 is in the range of 2 to 6. In some embodiments, one or more of the rear-side conductive structures (e.g., rear-side metallization layers BMO and BM1, and rear-side via layers BVD and BVO) are partially or entirely embedded in the substrate 210. In some embodiments, the back metallization layers BMO and BM1, and the back via layers BVD and BVO, comprise a conductive material, including copper, aluminum, gold, tungsten, combinations thereof, or the like. In some other embodiments, the semiconductor device does not include any back conductive structure.

[0018] In some embodiments, the semiconductor device 200 includes one or more redistribution layers and conductive pad structures (not shown in Figure 2) above the one or more redistribution layers. In some embodiments, the semiconductor device 200 further includes conductive terminal structures (e.g., conductive bumps, copper pillar bumps, solder bumps, or similar, not shown in Figure 2) above the conductive pad structures. In some embodiments, the semiconductor device 200 also includes one or more rear-side redistribution layers and rear-side conductive pad structures (not shown in Figure 2) below the one or more rear-side redistribution layers. In some embodiments, the semiconductor device 200 also includes rear-side conductive terminal structures (e.g., conductive bumps, copper pillar bumps, solder bumps, or similar, not shown in Figure 2) below the rear-side conductive pad structures.

[0019] In some embodiments, the semiconductor device 200 includes a transistor formed based on an active region 212 and a gate structure 214 in a front-end-of-line (FEOL) portion of the semiconductor device 200. In some embodiments, memory cells in a memory device (e.g., memory cells MC in memory device 100 in Figure 1) are formed based on transistors electrically connected to the FEOL portion of the semiconductor device 200. In some embodiments, the portion of the semiconductor device 200 at and above a given metallization layer (e.g., M5 layer and above) corresponds to a back-end-of-line (BEOL) portion of the semiconductor device 200. In some embodiments, memory cells in a memory device (e.g., memory cells MC in memory device 100 in Figure 1) are formed based on transistors, capacitors, and / or resistors electrically connected to the BEOL portion of the semiconductor device 200. Furthermore, in some embodiments, the control circuitry of the memory device (e.g., the control circuitry 120 of the memory device 100 in Figure 1) is formed based on transistors electrically connected to the FEOL portion of the semiconductor device 200.

[0020] According to one or more embodiments of this disclosure, in order to reduce the resistance of signal lines (e.g., bit lines, word lines, or source lines) in a memory device, the signal lines are implemented based on a plurality of parallel electrically coupled conductive structures. In some embodiments, the plurality of conductive structures corresponding to the same signal line are spaced apart in a horizontal direction, a vertical direction, or a combination thereof. In some embodiments, the plurality of conductive structures reduce the effective resistance of the corresponding signal line. In some embodiments, a portion of the plurality of conductive structures has an enlarged linewidth, which further reduces the effective resistance of the corresponding signal line.

[0021] Figure 3A is a layout diagram of a first portion of a first layout example 300A according to some embodiments. Figure 3B is a layout diagram of a second portion of the first layout example 300A according to some embodiments, indicating the layout pattern above the first portion of Figure 3A. As a non-limiting example, Figures 3A to 3B correspond to a portion of the first layout example 300A. In this example, the first layout example 300A is used to form a memory device. In Figures 3A to 3B, the first layout example 300A corresponds to two dual-unit cells 302 and 304. In Figures 3A to 3B, as a non-limiting example, each of the dual-unit cells 302 and 304 corresponds to two memory cells (e.g., configuring the dual-unit cells 302 and 304 as four memory cells).

[0022] Figure 3A includes illustrations of various layout patterns used in Figure 3A. In Figure 3A, the layout pattern of the first layout example 300A includes an oxide diffusion (OD) pattern (corresponding to "OD" in the illustration) indicating the active region of the transistor. In some embodiments, the active region includes a doped semiconductor material suitable for forming a drain / source structure of the transistor and defines a region suitable for forming a channel structure of the transistor. In this non-limiting example, the OD pattern extends along a first direction (e.g., the X direction). In Figure 3A, the layout pattern of the first layout example 300A includes a polysilicon gate pattern (corresponding to "PO" in the illustration) indicating a polysilicon gate structure. In some embodiments, the polysilicon gate structure serves as a functional gate structure, a dummy gate structure, or a placeholder structure on which functional and dummy structures are formed. In Figure 3A, the layout pattern of the first layout example 300A further includes metal-to-drain / source (MD) patterns 312, 314, 316, 322, and 324 (corresponding to "MD" in the illustration) and a cut MD pattern (corresponding to "CMD" in the illustration), collectively indicating the MD structure. In this non-limiting example, the PO pattern and the MD pattern extend along a second direction (e.g., the Y direction). In some embodiments, the transistors in the dual-unit cells 302 and 304 are configured as four memory cells.

[0023] Furthermore, Figure 3B includes illustrations of various types of layout patterns used in Figure 3B. In Figure 3B, MD patterns 312, 314, 316, 322, and 324 (corresponding to "MD" in the illustration) are the same as the MD patterns in Figure 3A, but are shaded differently in the illustration for clarity. In Figure 3B, the first layout example 300A includes a first group of MO patterns 332, 334, 336, and 338 (corresponding to "MOA" in the illustration) and a cut MOA pattern (corresponding to "CM0A" in the illustration), collectively indicating the first set of conductive structures in the MO metallization layer. In Figure 3B, the first layout example 300A includes a second group of MO patterns 342, 344, and 346 (corresponding to "MOB" in the illustration), indicating the second set of conductive structures in the MO metallization layer. Additionally, in Figure 3B, the first layout example 300A includes a VD pattern (corresponding to "VD" in the illustration) indicating a VD structure. In this non-limiting example, the first layout example 300A includes five M0 patterns 334, 336, 342, 344, and 346 within the cell boundaries, and two M0 patterns 332 and 338 overlapping the cell boundaries above and below the dual-unit cells 302 and / or 304. In this example, the dual-unit cells 302 and 304 have a cell height along a second direction (e.g., the Y direction) with a pitch greater than six track pitches and less than seven track pitches of the M0 layer.

[0024] In Figure 3B, M0 pattern 334 represents a conductive structure corresponding to the first bit line electrically coupled to the memory cell represented by the upper portions of dual-unit cells 302 and 304. Similarly, M0 pattern 336 represents a conductive structure corresponding to the second bit line electrically coupled to the memory cell represented by the lower portions of dual-unit cells 302 and 304. In this example, the first bit line indicated by M0 pattern 334 is electrically coupled to the metal-to-drain / source structure indicated by MD patterns 314 and 322 via a via structure indicated by the corresponding VD pattern. Similarly, the second bit line indicated by M0 pattern 336 is electrically coupled to the metal-to-drain / source structure indicated by MD patterns 314 and 322 via a via structure indicated by the corresponding VD pattern.

[0025] In Figure 3B, M0 patterns 342, 344, and 346 indicate conductive structures corresponding to source lines electrically coupled to memory cells represented by dual-unit cells 302 and 304. In this example, the source lines indicated by M0 patterns 342, 344, and 346 are electrically coupled to metal-to-drain / source terminals indicated by MD patterns 312, 316, and 324 via via structures indicated by corresponding VD patterns. In Figure 3B, the conductive structures indicated by M0 patterns 342, 344, and 346 are contained within the same metallization layer (e.g., the M0 layer) and spaced apart in a second direction (e.g., the Y direction). In some embodiments, the distance between adjacent MO patterns 342, 344, and 346 is greater than the minimum pitch of the VD pattern, so as to accommodate multiple via structures between the source line (e.g., indicated by MO patterns 342, 344, and 346) and the corresponding metal-to-drain / source structure (e.g., indicated by MD patterns 312, 316, and 324).

[0026] Figures 3C to 3D are cross-sectional views of a semiconductor device 300B including a memory device based on a first layout example 300A in Figures 3A to 3B, according to some embodiments. Figure 3C corresponds to a cross-sectional view taken along the first reference line A-A' in Figures 3A to 3B. Figure 3D corresponds to a cross-sectional view taken along the second reference line B-B' in Figures 3A to 3B. In Figures 3C to 3D, various structures are represented using the same legends as the corresponding layout patterns in Figures 3A to 3B, and their descriptions are simplified or omitted. Similarly, Figures 3C to 3D are simplified cross-sectional views, and various features of the semiconductor device 300B are simplified or omitted in Figures 3C to 3D.

[0027] In Figure 3C, the semiconductor device 300B includes an OD structure (corresponding to "OD" in the legend) above the substrate of the semiconductor device 300B (e.g., substrate 210 in Figure 2), a metal-to-drain / source structure 352 (corresponding to "MD" in the legend, as shown in MD pattern 312) above the OD structure, and MO conductive structures 372, 374, 376, and 378 (corresponding to "MOA" in the legend, as shown in MOA patterns 332, 334, 336, and 338) above the metal-to-drain / source structure 356, and MO conductive structures 382, ​​384, and 386 (corresponding to "MOB" in the legend, as shown in MOB patterns 342, 344, and 346). In Figure 3C, the M0 conductive structures 382, ​​384, and 386 correspond to the source line and are electrically coupled to the metal-to-drain / source structure 356 via three via structures (corresponding to "VD" in the illustration).

[0028] In the 3D diagram, the semiconductor device 300B includes an OD structure (corresponding to "OD" in the legend) above the substrate of the semiconductor device 300B (e.g., substrate 210 in the second diagram), metal-to-drain / source structures 352, 354, 356, 362, and 364 above the OD structure (corresponding to "MD" in the legend, as shown in MD patterns 312, 314, 316, 322, and 324), and an MO conductive structure 382 (corresponding to "MOB" in the legend, as shown in MOB pattern 342) above the metal-to-drain / source structures 352, 354, 356, 362, and 364. In the 3D diagram, the MO conductive structure 382 corresponds to a portion of the source line and is electrically coupled to the metal-to-drain / source structures 352, 356, and 364 via three via structures (corresponding to "VD" in the legend).

[0029] Based on the examples in Figures 3A to 3D, in some embodiments, a semiconductor device (e.g., semiconductor device 300B) includes a memory cell array, a first conductive structure (e.g., MO conductive structure 382) for carrying a first control signal (e.g., a source line signal) for operation of a group of memory cells in the memory cell array, and a second conductive structure (e.g., MO conductive structure 384 and / or MO conductive structure 386) electrically coupled to the first conductive structure and for carrying the first control signal for operation of the group of memory cells. In some embodiments, the memory cells in the group of memory cells are arranged along a first horizontal direction (e.g., the X direction), and the first conductive structure and the second conductive structure extend along the first horizontal direction.

[0030] Based on the examples in Figures 3A to 3D, in some embodiments, the first conductive structure and the second conductive structure are spaced apart in a second horizontal direction (e.g., the Y direction). In some embodiments, the first conductive structure and the second conductive structure are included in the same metallization layer (e.g., the MO layer). In some embodiments, the semiconductor device (e.g., semiconductor device 300B) further includes a third conductive structure (e.g., a metal-to-drain / source structure 356) extending along the second horizontal direction. In some embodiments, the semiconductor device includes a plurality of via structures connecting the third conductive structure to the first and second conductive structures. In some embodiments, the additional conductive structures and via structures further reduce the resistance of the corresponding signal lines (e.g., the source line in this example).

[0031] Figure 4A is a layout diagram of a portion of a second layout example 400A according to some embodiments. In some embodiments, the second layout example 400A is based on a first layout example 300A or a variation thereof, and incorporates portions of Figures 3A to 3B. In Figure 4A, the same legends are used to represent various layout patterns that are the same or similar to those in Figures 3A to 3B, and the same reference numerals are given, and their descriptions are simplified or omitted.

[0032] Compared to the layout diagrams in Figures 3A to 3B, the second layout example 400A in Figure 4A further includes M1 patterns 412, 414, 416, 422, 424, 426, and 428 (corresponding to "M1" in the legend) indicating conductive structures in the M1 layer. In Figure 4A, the second layout example 400A further includes V0 patterns (corresponding to "V0" in the legend) representing V0 structures. In Figure 4A, M1 pattern 412 represents a conductive structure corresponding to a first word line electrically coupled to a memory cell represented by dual-unit cell 302; M1 pattern 414 represents a conductive structure corresponding to a second word line electrically coupled to a memory cell represented by dual-unit cell 304. In Figure 4A, M1 patterns 422, 424, 426, and 428 represent conductive structures corresponding to various bit lines electrically coupled to different M0 conductive structures below them via via structures indicated by the V0 patterns.

[0033] Figures 4B to 4C are cross-sectional views of a semiconductor device 400B comprising a memory device based on a second layout example 400A in Figure 4A (which is further based on a first layout example 300A in Figures 3A to 3B) according to some embodiments. Figure 4B corresponds to a cross-sectional view taken along the first reference line A-A' in Figures 3A to 3B and Figure 4A. Figure 4C corresponds to a cross-sectional view taken along the second reference line B-B' in Figures 3A to 3B and Figure 4A. In Figures 4B to 4C, various structures are represented using the same legends as the corresponding layout patterns in Figures 3A to 3B and Figure 4A, and their descriptions are simplified or omitted. Similarly, Figures 4B to 4C are simplified cross-sectional views, and various features of the semiconductor device 400B are simplified or omitted in Figures 4B to 4C.

[0034] In Figure 4B, compared to semiconductor device 300B in Figure 3C, semiconductor device 400B further includes a conductive structure 432 (corresponding to "M1" in the legend, as shown in M1 pattern 412) above M0 conductive structures 372, 374, 376, 378, 382, ​​384, and 386. In this example, conductive structure 432 corresponds to a word line electrically coupled to the gate structure of the corresponding memory cell. In Figure 4C, semiconductor device 400B includes gate structures 452, 454, 456, and 458 corresponding to the PO pattern in Figure 3A. Similarly, in Figure 4C, semiconductor device 400B includes conductive structures 432, 434, 436, 444, and 448 (corresponding to "M1" in the legend, as shown in M1 patterns 412, 414, 416, 424, and 428) above M0 conductive structures (e.g., M0 conductive structure 382). In this example, conductive structure 432 corresponds to a first word line electrically coupled to gate structures 452 and 454 via one or more via structures in the peripheral area outside the corresponding memory cell, and conductive structure 434 corresponds to a second word line electrically coupled to gate structures 456 and 458 via one or more other via structures in the peripheral area outside the corresponding memory cell. In this example, gate structures 452 and 454 are also used as first word lines, and gate structures 456 and 458 are also used as second word lines. In this example, conductive structure 436 corresponds to yet another word line of another set of memory cells, and conductive structures 444 and 448 correspond to different bit lines.

[0035] Based on the examples in Figures 4A to 4C, in some embodiments, a semiconductor device (e.g., semiconductor device 400B) includes a memory cell array, a first conductive structure (e.g., gate structures 452 and / or 454) for carrying a first control signal (e.g., word line signal) for operation of a group of memory cells in the memory cell array, and a second conductive structure (e.g., M1 conductive structure 432) electrically coupled to the first conductive structure and for carrying the first control signal for operation of the group of memory cells. In some embodiments, the memory cells in the group of memory cells are arranged along a first horizontal direction (e.g., the Y direction), and the first conductive structure and the second conductive structure extend along the first horizontal direction.

[0036] Given the examples in Figures 4A to 4C, in some embodiments, the first conductive structure and the second conductive structure are spaced apart in the vertical direction (e.g., the Z direction). In some embodiments, the first conductive structure corresponds to a gate structure above the substrate of the semiconductor device, and the second conductive structure is included in a metallization layer (e.g., layer M1) above the first conductive structure and above the substrate of the semiconductor device. In some embodiments, based on having multiple conductive structures for carrying the same control signal (e.g., word line signal in this example), the resistance of the corresponding signal line (e.g., word line in this example) is further reduced. In some embodiments, the area occupied by each of the conductive structures of the corresponding bit lines indicated by M1 patterns 422, 424, 426, and 428 can be reduced to further reduce their capacitance.

[0037] Figure 5A is a layout diagram of a portion of a third layout example 500A according to some embodiments. In some embodiments, the third layout example 500A is a variation of the second layout example 400A and incorporates portions of Figures 3A to 3B and Figure 4A. In Figure 5A, the same legends are used to represent various layout patterns that are the same or similar to those in Figures 3A to 3B and Figure 4A, and the same reference numerals are given, and their descriptions are simplified or omitted.

[0038] Compared to the example in Figure 4A, the third layout example 500A includes M1 patterns 512, 514, and 516 (corresponding to "M1" in the legend) to replace M1 patterns 412, 414, and 416. In Figure 5A, M1 pattern 512 represents a conductive structure corresponding to a first word line electrically coupled to a memory cell represented by dual-unit cell 302; M1 pattern 514 represents a conductive structure corresponding to a second word line electrically coupled to a memory cell represented by dual-unit cell 304. In Figure 5A, M1 patterns 512 and 516 have the same shape as M1 pattern 514, wherein the dashed lines indicate portions outside dual-unit cells 302 and 304.

[0039] Taking M1 pattern 512 as an example, M1 pattern 512 includes at least a portion of a first linewidth W1 having a preset linewidth equal to or greater than that associated with a metallization layer (e.g., M1 layer) along the X direction (e.g., a central portion along the Y direction). M1 pattern 512 further includes at least a portion of a second linewidth W2 having a second linewidth W2 along the X direction and greater than the first linewidth W1 (e.g., an end portion above or below the central portion relative to the Y direction).

[0040] Figures 5B to 5C are cross-sectional views of a semiconductor device 500B comprising a memory device based on a third layout example 500A in Figure 5A (which is further based on examples in Figures 3A to 3B and Figure 4A) according to some embodiments. Figure 5B corresponds to a cross-sectional view taken along the third reference line C-C' in Figure 5A. Figure 5C corresponds to a cross-sectional view taken along the second reference line B-B' in Figures 3A to 3B and Figure 5A. In Figures 5B to 5C, various structures are represented using the same legends as the corresponding layout patterns in Figures 3A to 3B, Figure 4A, and Figure 5A, and their descriptions are simplified or omitted. Similarly, Figures 5B to 5C are simplified cross-sectional views, and various features of the semiconductor device 500B are simplified or omitted in Figures 5B to 5C.

[0041] In Figure 5B, semiconductor device 500B includes conductive structures 444 and 534 (corresponding to "M1" in the legend, as shown in M1 patterns 424 and 514). In this example, conductive structure 444 corresponds to a bit line, and conductive structure 534 corresponds to a word line. In Figure 5C, semiconductor device 500B includes conductive structures 532, 534, 536, 444, and 448 (corresponding to "M1" in the legend, as shown in M1 patterns 512, 514, 516, 424, and 428) above an M0 conductive structure (e.g., M0 conductive structure 382). In Figures 5C and 5A, the end portion of conductive structure 534 extends along the X direction through the two M1 tracks and the space between them. Therefore, the end portions of conductive structures 532, 534, and 536 have an increased linewidth (e.g., a second linewidth W2) along the X direction.

[0042] In view of the examples in Figures 5A to 5C, in some embodiments, a semiconductor device (e.g., semiconductor device 500B) includes a memory cell array, a first conductive structure (e.g., gate structure 452 and / or 454) for carrying a first control signal (e.g., word line signal) for operation of a group of memory cells in the memory cell array, and a second conductive structure (e.g., M1 conductive structure 532) electrically coupled to the first conductive structure and for carrying the first control signal for operation of the group of memory cells.

[0043] Based on the examples in Figures 5A to 5C, in some embodiments, the second conductive structure (e.g., conductive structure M1 532) includes a first portion (e.g., its central portion) and a second portion (e.g., its end portion). The first portion has a first linewidth (e.g., a first width W1) along a second horizontal direction that is equal to or greater than a preset linewidth associated with the metallization layer, and the second portion has a second linewidth (e.g., a first width W2) along the second horizontal direction that is greater than the first linewidth. In some embodiments, based on the conductive structure used to carry control signals (e.g., word line signals in this example) having a widened linewidth at a portion (e.g., the end portion), the resistance of the corresponding signal line (e.g., the word line in this example) is further reduced.

[0044] Figure 6A is a layout diagram of a portion of a fourth layout example 600A according to some embodiments. In some embodiments, the fourth layout example 600A is a variation of the second layout example 400A and incorporates portions of Figures 3A to 3B and Figure 4A. In Figure 6A, the same legends are used to represent various layout patterns that are the same or similar to those in Figures 3A to 3B and Figure 4A, and the same reference numerals are given, and their descriptions are simplified or omitted.

[0045] Compared to the example in Figure 4A, the fourth layout example 600A includes M2 patterns 612, 614, 616, and 618 (corresponding to "M2" in the legend) indicating conductive structures corresponding to various bit lines. In Figure 5A, the fourth layout example 600A further includes M3 patterns 622, 624, and 626 (corresponding to "M3" in the legend) indicating conductive structures corresponding to various character lines, and M3 patterns 632, 634, 636, and 638 (corresponding to "M3" in the legend) indicating conductive structures corresponding to various bit lines.

[0046] In Figure 6A, pattern M3 622 indicates a conductive structure corresponding to a first word line electrically coupled to a memory cell represented by dual-unit cell 302; pattern M3 624 indicates a conductive structure corresponding to a second word line electrically coupled to a memory cell represented by dual-unit cell 304. In some embodiments, pattern M3 626 indicates a conductive structure corresponding to yet another word line electrically coupled to a memory cell of another dual-unit cell. Similarly, in this example, the conductive structures indicated by patterns M3 632, M2 612, and M1 422 are electrically coupled by via structures indicated by corresponding patterns V2 and V1; the conductive structures indicated by patterns M3 634, M2 614, and M1 424 are electrically coupled by via structures indicated by corresponding patterns V2 and V1; the conductive structures indicated by patterns M3 636, M2 616, and M1 426 are electrically coupled by via structures indicated by corresponding patterns V2 and V1; and the conductive structures indicated by patterns M3 638, M2 618, and M1 428 are electrically coupled by via structures indicated by corresponding patterns V2 and V1.

[0047] Figures 6B to 6C are cross-sectional views of a semiconductor device 600B comprising a memory device based on a fourth layout example 600A in Figure 6A (which is further based on examples in Figures 3A to 3B and 4A) according to some embodiments. Figure 6B corresponds to a cross-sectional view taken along the first reference line A-A' in Figures 3A to 3B and 6A. Figure 6C corresponds to a cross-sectional view taken along the second reference line B-B' in Figures 3A to 3B and 6A. In Figures 6B to 6C, various structures are represented using the same legends as the corresponding layout patterns in Figures 3A to 3B, 4A, and 6A, and their descriptions are simplified or omitted. Similarly, Figures 6B to 6C are simplified cross-sectional views, and various structures of the semiconductor device 600B are simplified or omitted in Figures 6B to 6C.

[0048] In Figure 6B, compared to semiconductor device 400B in Figures 4B to 4C, semiconductor device 600B further includes a conductive structure 642 (corresponding to "M3" in the legend, as shown in M3 pattern 622). In this example, conductive structure 642 is electrically coupled to conductive structure 432 and corresponds to the same character line as conductive structure 432, as shown in Figures 4B to 4C. In Figure 6C, compared to semiconductor device 400B in Figures 4B to 4C, semiconductor device 600B includes conductive structures 642, 644, 646, 654, and 658 (corresponding to "M3" in the legend, as shown in M3 patterns 622, 624, 626, 634, and 638) and conductive structure 674 (corresponding to "M2" in the legend, as shown in M2 pattern 614).

[0049] In this example, conductive structure 674 is electrically coupled to structure 444 via structure V1 (corresponding to "V1" in the illustration), and conductive structure 654 is electrically coupled to structure 674 via structure V2 (corresponding to "V2" in the illustration). In this example, conductive structures 444, 674, and 654 correspond to the bit lines of conductive structure 374 as shown in Figure 5B. In this example, conductive structures 642 and 432 correspond to the first word lines electrically coupled to gate structures 452 and 454 via one or more via structures in the peripheral area outside the corresponding memory cell, and conductive structures 644 and 434 correspond to the second word lines electrically coupled to gate structures 456 and 458 via one or more other via structures in the peripheral area outside the corresponding memory cell. In this example, conductive structures 646 and 436 correspond to yet another word line of another set of memory cells.

[0050] Based on the examples in Figures 6A to 6C and Figures 4A to 4C, in some embodiments, the semiconductor device includes one or more other conductive structures (e.g., conductive structure 642) electrically coupled to a first conductive structure (e.g., gate structures 456 and 458) and a second conductive structure (e.g., conductive structure 432), and extending along a first horizontal direction (e.g., the Y direction). In this example, the second conductive structure and the one or more other conductive structures are located in different metallization layers above the substrate of the semiconductor device. In some embodiments, the resistance of the corresponding signal lines (e.g., word lines in this example) is further reduced based on multiple parallel conductive structures electrically coupled together and used to carry the same control signal (e.g., word line signals in this example).

[0051] In some embodiments, various parallel conductive structures electrically coupled together and corresponding to the same control signal (e.g., word line signal, source line signal, or bit line signal) are not limited to those located in layers M1, M2, and / or M3. In some embodiments, these parallel conductive structures disposed in different metallization layers are also within the scope of this disclosure.

[0052] Figure 7A is a layout diagram of a portion of a fifth layout example 700A according to some embodiments. In some embodiments, the fifth layout example 700A is a variation of the fourth layout example 600A and incorporates portions of Figures 3A to 3B, 4A, and 6A. In Figure 7A, various layout patterns that are the same or similar to those in Figures 3A to 3B, 4A, and 6A are represented using the same legends and given the same reference numerals, and their descriptions are simplified or omitted.

[0053] Compared to the example in Figure 6A, the fifth layout example 700A further includes Mx patterns 712 and 714 (corresponding to "Mx" in the legend) indicating conductive structures corresponding to various word lines at the Mx layer. In this example, the subscript "x" indicates any of the metallization layers of the semiconductor device. In Figures 7A to 7C, as a non-limiting example, the subscript "x" is greater than 3. In Figure 7A, Mx pattern 712 indicates a conductive structure corresponding to a first word line electrically coupled to a memory cell represented by dual-unit cell 302; Mx pattern 714 indicates a conductive structure corresponding to a second word line electrically coupled to a memory cell represented by dual-unit cell 304. In view of the examples in Figures 6A to 6C, the conductive structures indicated by Mx pattern 712 and M3 pattern 622 are electrically coupled via corresponding via structures; and the conductive structures indicated by Mx pattern 714 and M3 pattern 624 are electrically coupled via corresponding via structures.

[0054] In some embodiments, each memory cell has a cell width Wcell along the horizontal X direction. Furthermore, the conductive structure indicated by Mx pattern 712 has a linewidth W3 along the X direction. In this example, in response to an adjacent conductive structure (e.g., indicated by Mx pattern 714) carrying another control signal of the same type (e.g., another word line signal) and the adjacent conductive structure (e.g., indicated by Mx pattern 714) being in the same metallization layer (e.g., Mx layer) as the conductive structure indicated by Mx pattern 712, the linewidth W3 ranges from a preset linewidth (as associated with the metallization layer) to the difference between the cell width Wcell and the minimum linespace (as associated with the metallization layer), such that each memory cell can have a correspondingly widened signal line (e.g., word line) conductive structure in the metallization layer. In some embodiments, the linewidth W3 is set to half the cell width Wcell.

[0055] Figures 7B to 7C are cross-sectional views of a semiconductor device 700B, including a memory device based on the fifth layout example 700A in Figure 7A (which is further based on examples in Figures 3A to 3B, 4A, and 6A), according to some embodiments. Figure 7B corresponds to a cross-sectional view taken along the fourth reference line D-D' in Figure 7A. Figure 7C corresponds to a cross-sectional view taken along the second reference line B-B' in Figures 3A to 3B and Figure 7A. In Figures 7B to 7C, various structures are represented using the same legends as the corresponding layout patterns in Figures 3A to 3B, 4A, and 6A, and their descriptions are simplified or omitted. Similarly, Figures 7B to 7C are simplified cross-sectional views, and various structures of the semiconductor device 700B are simplified or omitted in Figures 7B to 7C.

[0056] In Figure 7B, compared to semiconductor device 600B in Figures 6B to 6C, semiconductor device 700B further includes conductive structure 722 (corresponding to "Mx" in the legend, as shown in Mx pattern 712). In Figure 7C, compared to semiconductor device 600B in Figures 6B to 6C, semiconductor device 700B includes conductive structures 722 and 724 (corresponding to "Mx" in the legend, as shown in Mx patterns 712 and 714). In this example, conductive structures 722, 642, and 432 correspond to first word lines electrically coupled to gate structures 452 and 454 via one or more via structures in the peripheral area outside the corresponding memory cell; conductive structures 724, 644, and 434 correspond to second word lines electrically coupled to gate structures 456 and 458 via one or more other via structures in the peripheral area outside the corresponding memory cell.

[0057] Based on the examples in Figures 7A to 7C, 6A to 6C, and 4A to 4C, the metallization layer can be used for additional widened conductive structures to carry the same type of control signals (e.g., word line signals in this example). In some embodiments, the linewidth of these additional conductive structures is widened, as long as they remain suitable for configuration within the same metallization layer. In some embodiments, based on multiple parallel conductive structures electrically coupled together to carry the same control signals (e.g., word line signals in this example), and based on the additional widened conductive structures based on the examples in Figures 7A to 7C, the resistance of the corresponding signal lines (e.g., word lines in this example) is further reduced.

[0058] Figure 8A is a layout diagram of a portion of a sixth layout example 800A according to some embodiments. In some embodiments, the sixth layout example 800A is another variation of the fourth layout example 600A and incorporates portions of Figures 3A to 3B, Figure 4A, and Figure 6A. In Figure 8A, various layout patterns that are the same or similar to those in Figures 3A to 3B, Figure 4A, and Figure 6A are represented using the same legends and given the same reference numerals, and their descriptions are simplified or omitted.

[0059] Compared to the example in Figure 6A, the sixth layout example 800A further includes an Mx pattern 812 (corresponding to "Mx" in the legend) indicating a conductive structure corresponding to a word line at the Mx metallization layer; and an Mx+a pattern 814 (corresponding to "Mx+a" in the legend) indicating a conductive structure corresponding to another word line at the Mx+a metallization layer. In this example, the subscript "x" indicates any of the metallization layers of the semiconductor device, and the subscript "x+a" indicates any of the metallization layers of the semiconductor device above the Mx layer. As a non-limiting example, in Figures 8A to 8C, the subscript "x" is greater than 3, and "a" is a positive even number. In Figure 8A, the Mx pattern 812 indicates a conductive structure corresponding to a first word line electrically coupled to a memory cell represented by the dual-unit cell 302; the Mx+a pattern 814 indicates a conductive structure corresponding to a second word line electrically coupled to a memory cell represented by the dual-unit cell 304. In view of the examples in Figures 6A to 6C, the conductive structures indicated by Mx pattern 812 and M3 pattern 622 are electrically coupled by a via structure; and the conductive structures indicated by Mx+a pattern 814 and M3 pattern 624 are electrically coupled by a via structure.

[0060] In some embodiments, each memory cell has a cell width Wcell along the X horizontal direction. Furthermore, the conductive structure indicated by Mx pattern 812 has a linewidth W4 along the X direction. In this example, in response to an adjacent conductive structure (e.g., indicated by Mx+a pattern 814) carrying another control signal of the same type (e.g., another character line signal) and this adjacent conductive structure being in a different metallization layer (e.g., Mx layer and Mx+a layer) from the conductive structure indicated by Mx pattern 812, the linewidth W4 is equal to or greater than the cell width Wcell. In some embodiments, the linewidth W4 is set to at least 1.2 times the cell width Wcell.

[0061] Figures 8B to 8C are cross-sectional views of a semiconductor device 800B, including a memory device based on the sixth layout example 800A in Figure 8A (which is further based on examples in Figures 3A to 3B, 4A, and 6A), according to some embodiments. Figure 8B corresponds to a cross-sectional view taken along the fourth reference line D-D' in Figure 8A. Figure 8C corresponds to a cross-sectional view taken along the second reference line B-B' in Figures 3A to 3B and Figure 8A. In Figures 8B to 8C, various structures are represented using the same legends as the corresponding layout patterns in Figures 3A to 3B, 4A, and 6A, and their descriptions are simplified or omitted. Similarly, Figures 8B to 8C are simplified cross-sectional views, and various structures of the semiconductor device 800B are simplified or omitted in Figures 8B to 8C.

[0062] In Figures 8B to 8C, compared to the semiconductor device 600B in Figures 6B to 6C, the semiconductor device 800B further includes a conductive structure 822 (corresponding to "Mx" in the legend, as shown in Mx pattern 812) and a conductive structure 824 (corresponding to "Mx+a" in the legend, as shown in Mx+a pattern 814). In this example, conductive structures 822, 642, and 432 correspond to first word lines electrically coupled to gate structures 452 and 454 via one or more via structures in the peripheral area outside the corresponding memory cell; conductive structures 824, 644, and 434 correspond to second word lines electrically coupled to gate structures 456 and 458 via one or more other via structures in the peripheral area outside the corresponding memory cell.

[0063] Based on the examples in Figures 8A to 8C, 6A to 6C, and 4A to 4C, two or more metallization layers can be used for additional conductive structures to carry the same type of control signal (e.g., the word line signal in this example). In some embodiments, the linewidth of these additional conductive structures is widened to be equal to or greater than the cell width. In some embodiments, based on multiple parallel conductive structures electrically coupled together to carry the same control signal (e.g., the word line signal in this example), and based on the additional widened conductive structures in the examples in Figures 8A to 8C, the resistance of the corresponding signal line (e.g., the word line in this example) is further reduced.

[0064] In some embodiments, various parallel conductive structures electrically coupled together and corresponding to the same control signal (e.g., word line signal, source line signal, or bit line signal) are implemented individually or in combination based on the examples in Figures 3A through 8C.

[0065] Figure 9A is a schematic diagram of a layout planning example 900A of a semiconductor device including a memory device according to some embodiments. Layout planning example 900A is a simplified layout planning that indicates how to reduce the resistance of a specific signal line (e.g., a word line in this example) in the memory device based on one or more of the examples in Figures 3A and 8C.

[0066] Layout planning example 900A includes memory cell regions 911-918 in which memory cells are placed and peripheral regions 921-928 in which electrical components for peripheral circuitry are placed. Furthermore, layout planning example 900A includes a buffer zone 932 surrounding the memory cell regions 911-918 and the peripheral regions 921-928. In some embodiments, the memory cells placed in the memory cell regions 911-918 correspond to volatile memory cells, such as DRAM cells or SRAM cells. In some embodiments, the memory cells placed in the memory cell regions 911-918 correspond to non-volatile memory cells, such as floating-gate memory cells, FRAM cells, MRAM cells, PCM cells, or RRAM cells. In some embodiments, the memory cells are formed in the FEOL portion of the resulting semiconductor device. In some embodiments, the memory cells are formed in the BEOL portion of the resulting semiconductor device.

[0067] In Figure 9A, the word line includes conductive structures 941, 942, 944, 946, and 948 extending along the Y direction. In this example, conductive structures 941, 942, 944, 946, and 948 are electrically coupled together based on via structures and / or other conductive structures in peripheral regions 922, 924, 926, and 928 and / or buffer zone 932. In some embodiments, in response to a memory cell being formed in the FEOL portion, conductive structure 941 corresponds to the gate structure of the associated memory cell, and conductive structures 942, 944, 946, and 948 are located in different metallization layers. In some embodiments, in response to a memory cell being formed in the BEOL portion, conductive structures 941, 942, 944, 946, and 948 are located in different metallization layers. Thus, the word line in this example includes parallel conductive structures in at least four different metallization layers. In some embodiments, the word line includes parallel conductive structures in at least two different metallization layers. In some embodiments, the resistance of the corresponding signal lines (e.g., word lines in this example) is further reduced by using multiple parallel conductive structures electrically coupled together to carry the same control signal (e.g., word line signals in this example).

[0068] Figure 9B is a schematic diagram of a layout plan example 900B of a semiconductor device including a memory device according to some embodiments. Layout plan example 900B is a simplified layout plan that indicates how to reduce the resistance of a specific signal line (e.g., the source line in this example) in the memory device based on one or more of the examples in Figures 3A to 8C. Furthermore, components in Figure 9B that are the same or similar to those in Figure 9A are given the same reference numerals, and their descriptions are simplified or omitted.

[0069] In Figure 9B, the source line includes conductive structures 952, 954, and 956 extending along the X direction. In this example, conductive structures 952, 954, and 956 are electrically coupled together based on via structures and / or other conductive structures in memory cell regions 913 and 914 and / or buffer 932. In some embodiments, conductive structures 952, 954, and 956 are located in different metallization layers. Thus, the source line in this example includes parallel conductive structures in at least three different metallization layers. In some embodiments, the source line includes parallel conductive structures in at least two different metallization layers. In some embodiments, the electrical coupling of multiple parallel conductive structures to carry the same control signal (e.g., the source line signal in this example) further reduces the resistance of the corresponding signal line (e.g., the source line in this example).

[0070] Figure 9C is a schematic diagram of a layout plan example 900C of a semiconductor device including a memory device according to some embodiments. Layout plan example 900C is a simplified layout plan that indicates how to reduce the resistance of a specific signal line (e.g., a bit line in this example) in the memory device based on one or more of the examples in Figures 3A to 8C. Furthermore, components in Figure 9C that are the same or similar to those in Figure 9A are given the same reference numerals, and their descriptions are simplified or omitted.

[0071] In Figure 9C, the bit line includes conductive structures 962, 964, and 966 extending along the X direction. In this example, conductive structures 962, 964, and 966 are electrically coupled together based on via structures and / or other conductive structures in memory cell regions 913 and 914 and / or buffer 932. In some embodiments, conductive structures 962, 964, and 966 are located in different metallization layers. Thus, the bit line in this example includes parallel conductive structures in at least three different metallization layers. In some embodiments, the bit line includes parallel conductive structures in at least two different metallization layers. In some embodiments, the electrical coupling of multiple parallel conductive structures to carry the same control signal (e.g., the bit line signal in this example) further reduces the resistance of the corresponding signal line (e.g., the bit line in this example).

[0072] Figure 10A is a cross-sectional view of an example of a semiconductor device 1000A, including parallel conductive structures at different metallization layers for a memory device, according to some embodiments. In this example, the semiconductor device 1000A includes memory cell regions 1002 and 1004 in which memory cells are disposed, and a buffer zone 1008 surrounding the memory cell regions 1002 and 1004. In Figure 10A, the semiconductor device 1000A includes a substrate 1010 corresponding to substrate 210 in Figure 2, a metal-to-drain / source (MD) structure layer corresponding to the MD layer in Figure 2, and metallization layers M0~M5, Mx, Mx+a, My, My+b, Mz, and Mz+c corresponding to various metallization layers in Figure 2. In this example, the subscripts x, x+a, y, y+b, z, and z+c correspond to positive integers.

[0073] In Figure 10A, RRAM memory cells 1022 and 1024 are formed between layers M4 and M5 within memory cell regions 1002 and 1004. In this example, conductive structure 1032 at layer Mx is electrically coupled to conductive structure 1034 at layer Mx+a and is used to carry bit line signals. In this example, conductive structure 1042 at layer My is electrically coupled to conductive structure 1044 at layer My+b and is used to carry first word line signals; conductive structure 1046 at layer My is electrically coupled to conductive structure 1048 at layer My+b and is used to carry second word line signals. Similarly, in this example, conductive structure 1052 at layer Mz is electrically coupled to conductive structure 1054 at layer Mz+c and is used to carry source line signals.

[0074] In Figure 10A, layers Mz+c and Mz are above layers My+b and My, and layers My+b and My are above layers Mx+a and Mx. In some embodiments, since the subscripts x, x+a, y, y+b, z, and z+c correspond to positive integers and are not limited to any given order, the order of layers Mx, Mx+a, My, My+b, Mz, and Mz+c is not limited to the instances in Figure 10A.

[0075] For example, Figure 10B is a cross-sectional view of another semiconductor device example 1000B, which includes parallel conductive structures at different metallization layers of a memory device according to some embodiments. Components in Figure 10B that are identical or similar to those in Figure 10A are given the same reference numerals, and their descriptions are simplified or omitted. In Figure 10B, compared to semiconductor device example 1000A, semiconductor device example 1000B includes Mx, Mx+a, My, My+b, Mz, and Mz+c layers arranged in a different order. In this example, the My+b layer is above the Mx+a layer, the Mx+a layer is above the My layer, and the My layer is above the Mx layer.

[0076] In view of the above one or more examples, in some embodiments, the semiconductor device includes a memory cell array (e.g., memory cell array 110 in Figure 1), a first conductive structure for carrying a first control signal (e.g., word line signal, bit line signal, or source line signal) for operation of a group of memory cells in the memory cell array, and a second conductive structure electrically coupled to the first conductive structure for carrying the first control signal for operation of the group of memory cells in the memory cell array. In some embodiments, the memory cells in the group of memory cells are arranged along a first horizontal direction (e.g., one of the X direction or the Y direction). In some embodiments, the first conductive structure and the second conductive structure extend along the first horizontal direction, and the first conductive structure and the second conductive structure are spaced apart in the second horizontal direction (e.g., the other of the X direction or the Y direction), in the vertical direction (e.g., the Z direction), or in both the second horizontal direction and the vertical direction.

[0077] In some embodiments, as discussed based on the non-limiting examples in Figures 3A to 3D, the semiconductor device further includes a third conductive structure (e.g., drain / source structure 352) extending along a second horizontal direction and a plurality of via structures connecting the third conductive structure to the first and second conductive structures (e.g., conductive structures 382, ​​384, and / or 386). In some embodiments, the first and second conductive structures are included in the same metallization layer (e.g., MO layer). In some embodiments, the third conductive structure corresponds to a drain / source terminal substructure (e.g., MD layer) above the substrate of the semiconductor device (e.g., substrate 210 in Figure 2).

[0078] In some embodiments, as discussed based on the non-limiting examples in Figures 4A to 4C, the first conductive structure corresponds to a gate structure (e.g., gate structure 452 and / or gate structure 454) above the substrate of the semiconductor device. In some embodiments, the second conductive structure (e.g., conductive structure 432) is included in a metallization layer (e.g., M1 layer) above the first conductive structure and above the substrate of the semiconductor device.

[0079] In some embodiments, such as those discussed based on non-limiting examples in Figures 5A to 5C, the second conductive structure (e.g., conductive structure 532) includes a first portion and a second portion, the first portion having a first linewidth (e.g., linewidth W1) along a second horizontal direction (e.g., the X direction) equal to or greater than a preset linewidth associated with the metallization layer, and the second portion having a second linewidth (e.g., linewidth W2) along the second horizontal direction and greater than the first linewidth.

[0080] In some embodiments, each memory cell in the memory cell array has a cell width (e.g., cell width Wcell in Figures 7A and 8A) along a second horizontal direction (e.g., the X direction). In some embodiments, as discussed based on non-limiting examples in Figures 7A to 7C, a second conductive structure (e.g., conductive structure 722) has a linewidth (e.g., linewidth W3) along the second horizontal direction. In some embodiments, in response to an adjacent conductive structure (e.g., conductive structure 724) carrying a second control signal of the same type as the first control signal and the adjacent conductive structure being in the same metallization layer as the second conductive structure, the linewidth (e.g., linewidth W3) ranges from a preset linewidth (as associated with the metallization layer) to the difference between the cell width and the minimum line spacing (as associated with the metallization layer). In some embodiments, as discussed based on non-limiting examples in Figures 8A to 8C, a second conductive structure (e.g., conductive structure 822) has a linewidth (e.g., linewidth W4) along the second horizontal direction. In some embodiments, in response to adjacent conductive structures (e.g., conductive structure 824) and second conductive structures being in different metallization layers, the linewidth (e.g., linewidth W4) is equal to or greater than the cell width (e.g., cell width Wcell).

[0081] In some embodiments, as discussed based on the non-limiting examples in Figures 4A to 10B, the first conductive structure and the second conductive structure are different metallization layers above the substrate of the semiconductor device. In some embodiments, as discussed based on the non-limiting examples in Figures 6A to 9C, the semiconductor device further includes one or more other conductive structures electrically coupled to the first conductive structure and extending along a first horizontal direction. In some embodiments, the first conductive structure, the second conductive structure, and one or more other conductive structures are different metallization layers above the substrate of the semiconductor device.

[0082] In some embodiments, the first conductive structure and the second conductive structure correspond to the source line, bit line, or word line of the memory cell array. In some embodiments, the memory cell array includes memory cells, which are volatile memory cells including DRAM cells or SRAM cells, or non-volatile memory cells including floating gate memory cells, FRAM cells, MRAM cells, PCM cells, or RRAM cells.

[0083] In some embodiments, as discussed based on the non-limiting examples in Figures 10A to 10B, in addition to the first conductive structure (e.g., conductive structure 1032) and the second conductive structure (e.g., conductive structure 1034) for carrying the first control signal (e.g., bit line signal), the memory device further includes a third conductive structure (e.g., conductive structure 1042) for carrying the second control signal (e.g., word line signal) for the operation of the second group of memory cells in the memory cell array, and a fourth conductive structure (e.g., conductive structure 1044) electrically coupled to the third conductive structure and for carrying the second control signal for the operation of the second group of memory cells in the memory cell array. In some embodiments, the third conductive structure and the fourth second conductive structure extend along a second horizontal direction and are spaced apart in the first horizontal direction, in the vertical direction, or in both the first horizontal direction and the vertical direction. In some embodiments, the first conductive structure includes a first metallization layer (e.g., the Mx layer in Figures 10A to 10B) above the memory cell array, the second conductive structure includes a second metallization layer (e.g., the Mx+a layer in Figures 10A to 10B) above the first metallization layer, the third conductive structure includes a third metallization layer (e.g., the My layer in Figures 10A to 10B) above the first conductive structure, and the fourth conductive structure includes a fourth metallization layer (e.g., the My+b layer in Figures 10A to 10B) above the third conductive structure. In some embodiments, as discussed based on the non-limiting example in Figure 10A, the third conductive structure is above the second conductive structure. In some embodiments, as discussed based on the non-limiting example in Figure 10B, the third conductive structure is below the second conductive structure.

[0084] Similarly, in view of one or more of the above examples, in some embodiments, the semiconductor device includes a memory cell array (e.g., memory cell array 110 in Figure 1) and a first plurality of conductive structures (e.g., conductive structures 1032 and 1034) included in a first plurality of metallization layers above the memory cell array. In some embodiments, the first plurality of conductive structures are electrically coupled to each other and are used to carry a first control signal (e.g., a bit line signal) for operation of a first group of memory cells in the memory cell array. In some embodiments, the memory cells in the first group of memory cells are arranged along a first horizontal direction, and each of the first plurality of conductive structures extends along the first horizontal direction and overlaps with the first group of memory cells.

[0085] In some embodiments, the semiconductor device further includes a second plurality of conductive structures (e.g., conductive structures 1042 and 1044) in a second plurality of metallization layers above the memory cell array. In some embodiments, the second plurality of conductive structures are electrically coupled to each other and are used to carry a second control signal for operation of a second group of memory cells in the memory cell array. In some embodiments, the memory cells in the second group of memory cells are arranged along a second horizontal direction, and each of the second plurality of conductive structures extends along the second horizontal direction.

[0086] In some embodiments, the semiconductor device further includes a third plurality of conductive structures (e.g., conductive structures 1052 and 1054) in a third plurality of metallization layers above the memory cell array. In some embodiments, the third plurality of conductive structures are electrically coupled to each other and are used to carry a third control signal for operation of a first group of memory cells of the memory cell array. In some embodiments, each of the third plurality of conductive structures extends along a first horizontal direction.

[0087] In some embodiments, a first plurality of conductive structures correspond to bit lines of the memory cell array, a second plurality of conductive structures correspond to word lines of the memory cell array, and a third plurality of conductive structures correspond to source lines of the memory cell array. In some other embodiments, a first plurality of conductive structures correspond to source lines of the memory cell array, a second plurality of conductive structures correspond to word lines of the memory cell array, and a third plurality of conductive structures correspond to bit lines of the memory cell array.

[0088] In some embodiments, as discussed based on a non-limiting example in Figure 10A, the first plurality of conductive structures, the second plurality of conductive structures, and the third plurality of conductive structures are stacked on top of each other in a vertical direction. In some embodiments, as discussed based on a non-limiting example in Figure 10B, at least one of the first plurality of conductive structures is positioned vertically between two of the second plurality of conductive structures, and / or at least one of the second plurality of conductive structures is positioned vertically between two of the third plurality of conductive structures.

[0089] Figure 11 is a flowchart of a method 1100 for manufacturing a semiconductor device according to some embodiments. In some embodiments, given the configurations in Figures 1 to 2, the semiconductor device based on method 1100 corresponds to the instances in Figures 3A to 10B. In some embodiments, method 1100 is performed in conjunction with an IC manufacturing system as described with respect to IC manufacturing system 1300 in Figure 13. In some embodiments, the semiconductor device is designed based on an EDA system, as described with respect to the EDA system in Figure 12. Method 1100 includes blocks 1110 to 1130.

[0090] At block 1110, a memory cell array is formed above the substrate. In some embodiments, block 1110 includes the formation of volatile memory cells comprising DRAM cells or SRAM cells. In some embodiments, block 1110 includes the formation of non-volatile memory cells comprising floating gate memory cells, FRAM cells, MRAM cells, PCM cells, or RRAM cells.

[0091] At block 1120, a first conductive structure is disposed above the substrate. In some embodiments, the first conductive structure is used to carry a first control signal for the operation of a group of memory cells of the memory cell array.

[0092] At block 1130, a second conductive structure is disposed above the substrate. In some embodiments, the second conductive structure is electrically coupled to the first conductive structure and is used to carry a first control signal for the operation of the group of memory cells of the memory cell array.

[0093] In some embodiments, the memory cells in the group of memory cells are arranged along a first horizontal direction. In some embodiments, a first conductive structure and a second conductive structure extend along the first horizontal direction, and the first conductive structure and the second conductive structure are spaced apart in a second horizontal direction, in a vertical direction, or in both the second horizontal direction and the vertical direction. In some embodiments, the first control signal corresponds to a bit line signal, a word line signal, or a source line signal.

[0094] In some embodiments, given the non-limiting examples in Figures 3A to 3D, method 1100 further includes forming a metallization layer including a first conductive structure and a second conductive structure, a third conductive structure disposed above a substrate and extending along a second horizontal direction, and forming a plurality of via structures connecting the third conductive structure to the first conductive structure and the second conductive structure. In some embodiments, forming the third conductive structure includes forming a metal-to-drain / source (MD) structure as the third conductive structure.

[0095] In some embodiments, given the non-limiting examples in Figures 4A to 4C, setting the first conductive structure includes forming a gate structure as the first conductive structure, and setting the second conductive structure includes forming a metallization layer above the first conductive structure and including the second conductive structure.

[0096] In some embodiments, given the non-limiting examples in Figures 5A to 5C, the provision of the second conductive structure includes forming a first portion of the second conductive structure having a first linewidth (e.g., linewidth W1) along a second horizontal direction that is equal to or greater than a preset linewidth associated with the metallization layer, and forming a second portion of the second conductive structure having a second linewidth (e.g., linewidth W2) along a second horizontal direction that is greater than the first linewidth.

[0097] In some embodiments, each memory cell in the memory cell array has a cell width (e.g., linewidth Wcell) along a second horizontal direction. In some embodiments, given the non-limiting examples in Figures 7A to 7C, in response to an adjacent conductive structure carrying a second control signal of the same type as the first control signal and the adjacent conductive structure being in the same metallization layer as the second conductive structure, setting the second conductive structure includes forming a second conductive structure having a linewidth (e.g., linewidth W3) along the second horizontal direction, the linewidth ranging from a preset linewidth (associated with the metallization layer) to the difference between the cell width and the minimum line spacing (associated with the metallization layer). In some embodiments, given the non-limiting examples in Figures 8A to 8C, in response to an adjacent conductive structure being in a different metallization layer as the second conductive structure, setting the second conductive structure includes forming a second conductive structure having a linewidth (e.g., linewidth W4) equal to or greater than the cell width.

[0098] In some embodiments, method 1100 includes forming two different metallization layers including a first conductive structure and a second conductive structure. In some embodiments, method 1100 further includes forming one or more other metallization layers including one or more other corresponding conductive structures. In some embodiments, one or more other conductive structures are electrically coupled to the first conductive structure and extend along a first horizontal direction.

[0099] Figure 12 is a block diagram of an electronic design automation (EDA) system 1200 according to some embodiments. In some embodiments, the EDA system 1200 includes an automatic placement and routing (APR) system. The methods described herein are implementable according to one or more embodiments, for example, using the EDA system 1200 according to some embodiments.

[0100] In some embodiments, the EDA system 1200 is a general-purpose computing device including a hardware processor 1202 and a computer-readable storage medium 1204. Among other things, the storage medium 1204 is encoded (i.e., stored) with computer program code 1206, i.e., a set of executable instructions. Execution of the instructions 1206 by the hardware processor 1202 represents (at least partially) an EDA tool that implements some or all of the methods described herein (hereinafter referred to as the processes and / or methods mentioned) according to one or more embodiments.

[0101] Processor 1202 is electrically coupled to computer-readable storage medium 1204 via bus 1208. Processor 1202 is also electrically coupled to I / O interface 1210 via bus 1208. Network interface 1212 is also electrically connected to processor 1202 via bus 1208. Network interface 1212 is connected to network 1214, enabling processor 1202 and computer-readable storage medium 1204 to be connected to external components via network 1214. Processor 1202 is used to execute computer program code 1206 encoded in computer-readable storage medium 1204 to enable system 1200 to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 1202 is a CPU, a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0102] In one or more embodiments, the computer-readable storage medium 1204 is a non-transitory computer-readable storage medium including electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor systems (or devices or apparatuses). For example, the computer-readable storage medium 1204 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 1204 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0103] In one or more embodiments, storage medium 1204 stores computer program code 1206 that enables system 1200 (wherein such execution (at least partially) represents an EDA tool) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1204 also stores information that facilitates the execution of part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1204 stores a cell library 1207 comprising standard cells including such standard cells as disclosed herein. In one or more embodiments, storage medium 1204 stores one or more layout schemes 1209 corresponding to one or more layout schemes disclosed herein.

[0104] EDA system 1200 includes an I / O interface 1210. The I / O interface 1210 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1210 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or directional keys for transmitting information and commands to processor 1202.

[0105] EDA system 1200 also includes a network interface 1212 coupled to processor 1202. Network interface 1212 allows system 1200 to communicate with a network 1214 to which one or more other computer systems are connected. Network interface 1212 includes wireless network interfaces such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more systems 1200.

[0106] System 1200 receives information via I / O interface 1210. The information received via I / O interface 1210 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 1202. Information is transferred to processor 1202 via bus 1208. EDA system 1200 receives UI-related information via I / O interface 1210. This information is stored as a user interface (UI) 1242 in computer-readable media 1204.

[0107] In some embodiments, one or more of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, one or more of the mentioned processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, one or more of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, one or more of the mentioned processes and / or methods are implemented as a software application used by EDA system 1200. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0108] In some embodiments, these processes are implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memory (e.g., ROM, RAM, memory cards), and one or more of the like.

[0109] Figure 13 is a block diagram of an IC manufacturing system 1300 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1300 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of semiconductor integrated circuits.

[0110] In Figure 13, the IC manufacturing system 1300 includes entities that interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacturing of IC devices 1360, such as design room 1320, mask room 1330, and IC manufacturer / fab 1350. The entities in system 1300 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet or the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1320, mask room 1330, and IC fab 1350 are owned by a single larger company. In some embodiments, two or more of the design room 1320, the shielding room 1330, and the IC wafer fab 1350 coexist in a common facility and use common resources.

[0111] Design studio (or design team) 1320 generates IC design layout 1322 (e.g., layout plan). IC design layout 1322 includes various geometric patterns designed for IC device 1360. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1360 to be manufactured. Various layers are combined to form various IC features. For example, a portion of IC design layout 1322 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 1320 implements appropriate design procedures to form IC design layout 1322. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 1322 is presented in the form of one or more data files containing information on geometric patterns. For example, IC design layout diagram 1322 can be expressed in GDSII file format or DFII file format.

[0112] Masking chamber 1330 includes data preparation 1332 and mask fabrication 1344. Masking chamber 1330 uses an IC design layout 1322 to fabricate one or more masks 1345 for use in fabricating various layers in an IC device 1360 according to the IC design layout 1322. Masking chamber 1330 performs mask data preparation 1332, in which the IC design layout 1322 is translated into a representative data file (RDF). Mask data preparation 1332 provides the RDF to mask fabrication 1344. Mask fabrication 1344 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 1345 or a semiconductor wafer 1353. The design layout 1322 is controlled by mask data preparation 1332 to conform to the specific characteristics of the mask writer and / or the requirements of the IC wafer fab 1350. In Figure 13, mask data preparation 1332 and mask manufacturing 1344 are shown as separate elements. In some embodiments, mask data preparation 1332 and mask manufacturing 1344 may be collectively referred to as mask data preparation.

[0113] In some embodiments, mask data preparation 1332 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as those that can produce self-diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout diagram 1322. In some embodiments, mask data preparation 1332 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0114] In some embodiments, mask data preparation 1332 includes checking the IC design layout 1322 with a mask rule checker (MRC) that has undergone processing in an OPC using a set of mask generation rules containing certain geometric and / or connectivity constraints to ensure sufficient margin, take into account variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 1322 to compensate for optical lithography effects during mask manufacturing 1344, where modifications performed by the OPC can be reversed to satisfy the mask generation rules.

[0115] In some embodiments, mask data preparation 1332 includes lithography process checking (LPC), which simulates the process implemented by IC wafer fab 1350 to manufacture IC device 1360. LPC simulates this process based on IC design layout 1322 to produce a simulated manufactured device, such as IC device 1360. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after the simulated manufactured device has been produced by LPC, if the simulated device does not sufficiently approximate the shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1322.

[0116] It should be understood that the above description of mask data preparation 1332 has been simplified for clarity. In some embodiments, data preparation 1332 includes additional features, such as logic operations (LOPs), to modify the IC design layout 1322 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1322 during data preparation 1332 can be performed in a variety of different sequences.

[0117] After mask data preparation 1332 and during mask manufacturing 1344, mask 1345 or a group of masks 1345 is manufactured based on a modified IC design layout 1322. In some embodiments, mask manufacturing 1344 includes performing one or more lithography exposures based on IC design layout 1322. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to pattern the mask (photomask or master photomask) 1345 based on the modified IC design layout 1322. Mask 1345 can be formed using various techniques. In some embodiments, mask 1345 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., a photoresist layer) coated on the wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary mask version of mask 1345 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1345 is formed using a phase shift mask (PSM) technique. In the phase shift mask (PSM) version of mask 1345, various features in the pattern formed on the phase shift mask are used to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1344 is used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1353, in etching processes to form various etched regions in semiconductor wafer 1353, and / or in other suitable processes.

[0118] IC wafer fab 1350 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC wafer fab 1350 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end-of-line (FEOL) manufacturing of a plurality of IC products, a second manufacturing facility that provides back-end-of-line (BEOL) manufacturing for interconnecting and packaging of IC products, and a third manufacturing facility that provides other services for the foundry business.

[0119] IC wafer fab 1350 includes manufacturing tools 1352 for performing various manufacturing operations on semiconductor wafers 1353 to manufacture IC devices 1360 according to masks (e.g., mask 1345). In various embodiments, manufacturing tools 1352 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD manufacturing tool chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0120] IC wafer fab 1350 uses multiple masks 1345 manufactured by mask chamber 1330 to manufacture IC device 1360. Therefore, IC wafer fab 1350 uses IC design layout 1322 at least indirectly to manufacture IC device 1360. In some embodiments, semiconductor wafer 1353 is manufactured by IC wafer fab 1350 using multiple masks 1345 to form IC device 1360. In some embodiments, IC manufacturing includes performing one or more optical lithography exposures at least indirectly based on IC design layout 1322. Semiconductor wafer 1353 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1353 further includes various doped regions, dielectric features, multilayer interconnects, and one or more of the like (formed in subsequent manufacturing steps).

[0121] In some embodiments, a semiconductor device includes a memory cell array, a first conductive structure, and a second conductive structure. The first conductive structure carries a first control signal for operating a group of memory cells in the memory cell array. The second conductive structure is electrically coupled to the first conductive structure and also carries the first control signal for operating the group of memory cells in the memory cell array. The memory cells in the group of memory cells are arranged along a first horizontal direction. The first conductive structure and the second conductive structure extend along the first horizontal direction. The first conductive structure and the second conductive structure are spaced apart in a second horizontal direction, in a vertical direction, or in both the second horizontal direction and the vertical direction.

[0122] In some embodiments, a method of manufacturing a semiconductor device includes forming a memory cell array over a substrate, disposing a first conductive structure over the substrate, and disposing a second conductive structure over the substrate. The first conductive structure carries a first control signal for operating a group of memory cells in the memory cell array. The second conductive structure is electrically coupled to the first conductive structure and carries the first control signal for operating the group of memory cells in the memory cell array. The memory cells in the group of memory cells are arranged along a first horizontal direction. The first conductive structure and the second conductive structure extend along the first horizontal direction. The first conductive structure and the second conductive structure are spaced apart in a second horizontal direction, in a vertical direction, or in both the second horizontal and vertical directions.

[0123] In some embodiments, the semiconductor device includes a memory cell array above a substrate and a first plurality of conductive structures included in a first plurality of metallization layers above the memory cell array. The first plurality of conductive structures are electrically coupled to each other and are used to carry a first control signal for operation of a first group of memory cells in the memory cell array. The memory cells in the first group of memory cells are arranged along a first horizontal direction. Each of the first plurality of conductive structures extends along the first horizontal direction and overlaps with the first group of memory cells.

[0124] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0125] 100: Memory Device 110: Memory Cell Array 120: Control circuit system 122: Decoder 124: Character Line Driver 126: Sensing amplifier and / or bit line driver 128: Source Line Driver 200: Semiconductor devices 210:Substrate 212: Activity Area 214: Gate Structure 222:MD structure 300A: First Layout Example 300B: Semiconductor Device 302: Two-unit unit 304: Double unit 312:MD pattern 314:MD pattern 316:MD pattern 322:MD pattern 324:MD pattern 332:M0 pattern 334:M0 pattern 336:M0 pattern 338:M0 pattern 342:M0 pattern 344:M0 pattern 346:M0 pattern 352: Metal-to-Drain / Source Structure 354: Metal-to-Drain / Source Structure 356: Metal-to-Drain / Source Structure 362: Metal-to-Drain / Source Structure 364: Metal-to-Drain / Source Structure 372:M0 conductive structure 374:M0 conductive structure 376:M0 conductive structure 378:M0 conductive structure 382:M0 conductive structure 384:M0 conductive structure 386:M0 conductive structure 400A: Second Layout Example 400B: Semiconductor Device 412:M1 pattern 414:M1 pattern 416:M1 pattern 422:M1 pattern 424:M1 pattern 426:M1 pattern 428:M1 pattern 432: Conductive Structure 434: Conductive Structure 436: Conductive Structure 444: Conductive structure 448: Conductive Structure 452: Gate structure 454: Gate structure 456: Gate structure 458: Gate structure 500A: Third Layout Example 500B: Semiconductor Device 512:M1 pattern 514:M1 pattern 516:M1 pattern 532: Conductive Structure 534: Conductive Structure 536: Conductive Structure 600A: Fourth Layout Example 600B: Semiconductor Device 612:M2 pattern 614:M2 pattern 616:M2 pattern 618: M2 pattern 622:M3 pattern 624:M3 pattern 626:M3 pattern 632:M3 pattern 634:M3 pattern 636: M3 pattern 638: M3 pattern 642: Conductive structure 644: Conductive structure 646: Conductive structure 654: Conductive Structure 658: Conductive Structure 674: Conductive Structure 700A: Fifth Layout Example 700B: Semiconductor Device 712:Mx pattern 714:Mx pattern 722: Conductive Structure 724: Conductive Structure 800A: Sixth Layout Example 800B: Semiconductor Device 812:Mx pattern 814:Mx+a pattern 822: Conductive structure 824: Conductive Structure 900A: Layout Planning Example 900B: Layout Planning Example 900C: Layout Planning Example 911~918: Memory cell area 921~928: Surrounding Area 932: Buffer 941: Conductive Structure 942: Conductive Structure 944: Conductive Structure 946: Conductive Structure 948: Conductive Structure 952: Conductive Structure 954: Conductive Structure 956: Conductive Structure 962: Conductive Structure 964: Conductive Structure 966: Conductive structure 1000A: Examples of Semiconductor Devices 1000B: Examples of Semiconductor Devices 1002: Memory cell area 1004: Memory Cell Area 1008: Buffer 1010:Substrate 1022: RRAM memory unit 1024: RRAM memory unit 1032: Conductive Structure 1034: Conductive Structure 1042: Conductive Structure 1044: Conductive Structure 1046: Conductive Structure 1048: Conductive Structure 1052: Conductive Structure 1054: Conductive Structure 1100: Method 1110, 1120, 1130: Square 1200: EDA System 1202: Hardware Processor 1204: Computer-readable storage media 1206: Computer program code 1207: Unit Library 1208: Busbar 1209: Layout Plan 1210:I / O interface 1212: Network Interface 1214: Internet 1242: User Interface 1300: IC Manufacturing System 1320: Design Studio 1322: IC Design Layout Diagram 1330: Shielded Room 1332: Data Preparation 1344: Mask Manufacturing 1345: Mask 1350: IC wafer fab 1352: Manufacturing Tools 1353: Semiconductor wafer 1360: IC device

Claims

1. A semiconductor device comprising: a memory cell array; a first conductive structure for carrying a first control signal for operating one of a group of memory cells in the memory cell array; and a second conductive structure electrically coupled to the first conductive structure and for carrying the first control signal for operating the group of memory cells in the memory cell array, wherein a plurality of memory cells in the group of memory cells are arranged along a first horizontal direction, the first conductive structure and the second conductive structure extend along the first horizontal direction, and the first conductive structure and the second conductive structure are spaced apart in a second horizontal direction, in a vertical direction, or in both the second horizontal direction and the vertical direction, wherein a first portion of the second conductive structure has a first linewidth along the second horizontal direction, and a second portion of the second conductive structure has a second linewidth along the second horizontal direction that is greater than the first linewidth.

2. The semiconductor device as claimed in claim 1, further comprising: a third conductive structure extending along the second horizontal direction and overlapping the second conductive structure.

3. The semiconductor device as claimed in claim 1, wherein the first conductive structure corresponds to a gate structure above a substrate of the semiconductor device, and the second conductive structure is included in a metallization layer above the first conductive structure and above the substrate of the semiconductor device.

4. The semiconductor device as claimed in claim 1, further comprising: a third conductive structure for carrying a second control signal for operating one of a second group of memory cells in the memory cell array; and a fourth conductive structure electrically coupled to the third conductive structure and for carrying the second control signal for operating the second group of memory cells in the memory cell array, wherein a plurality of memory cells in the second group of memory cells are arranged along the second horizontal direction, the third conductive structure and the fourth conductive structure extend in the second horizontal direction, and the third conductive structure and the fourth conductive structure are spaced apart in the first horizontal direction, in the vertical direction, or in both the first horizontal direction and the vertical direction.

5. A method of manufacturing a semiconductor device, comprising: forming a memory cell array above a substrate; disposing a first conductive structure above the substrate, the first conductive structure being used to carry a first control signal for operation of one of a group of memory cells in the memory cell array; and disposing a second conductive structure above the substrate, the second conductive structure being electrically coupled to the first conductive structure and used to carry the first control signal for operation of the group of memory cells in the memory cell array, wherein a plurality of memory cells in the group of memory cells are arranged along a first horizontal direction, the first conductive structure and the second conductive structure extend along the first horizontal direction, and the first conductive structure and the second conductive structure are spaced apart in a second horizontal direction, in a vertical direction, or in both the second horizontal direction and the vertical direction. Each memory cell in the memory cell array has a cell width along the second horizontal direction and responds to an adjacent conductive structure for carrying a second control signal of the same type as the first control signal, and the adjacent conductive structure and the second conductive structure are in the same metallization layer. The setting of the second conductive structure includes: forming the second conductive structure having a line width along the second horizontal direction, and the line width ranges from a preset line width associated with the metallization layer to a difference between the cell width and a minimum line spacing associated with the metallization layer.

6. The method as described in claim 5, further comprising: forming the metallization layer including the second conductive structure.

7. The method as described in claim 5, wherein setting the second conductive structure comprises: forming the metallization layer above the first conductive structure and including the second conductive structure.

8. The method as described in claim 5, wherein in response to the adjacent conductive structure and the second conductive structure being in multiple different metallization layers, setting the second conductive structure comprises: forming the second conductive structure having a linewidth equal to or greater than the cell width.

9. The method as described in claim 5, further comprising: forming two different metallization layers including the first conductive structure and the second conductive structure; forming one or more other metallization layers including corresponding one or more other conductive structures, wherein the one or more other conductive structures are electrically coupled to the first conductive structure and extend along the first horizontal direction.

10. A semiconductor device comprising: a memory cell array above a substrate; and a first plurality of conductive structures included in a first plurality of metallization layers above the memory cell array, the first plurality of conductive structures being electrically coupled to each other and configured to carry a first control signal for operation of one of a first group of memory cells in the memory cell array, wherein a plurality of memory cells in the first group of memory cells are arranged along a first horizontal direction, each of the first plurality of conductive structures extending along the first horizontal direction and overlapping the first group of memory cells, the first plurality of conductive structures including a first conductive structure and a second conductive structure, each of the first conductive structure and the second conductive structure being configured to carry the first control signal, the second conductive structure including a metal layer above the first conductive structure, a first portion of the second conductive structure having a first linewidth along a second horizontal direction equal to or greater than a preset linewidth associated with the metallization layer, and a second portion of the second conductive structure having a second linewidth along the second horizontal direction and greater than the first linewidth.

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