Memory device and memory system

Abstract

A memory system includes a memory device, a memory controller, and configuration circuitry. The memory controller has logic to perform: (i) programming the memory device to store data; (ii) providing one or more search voltages to the memory device based on input data; and (iii) determining the similarity between the stored data and the input data based on an output current from the memory device. The output current represents the Euclidean distance between a stored logic value representing the stored data and an input logic value representing the input data. The configuration circuitry has logic to determine a reference threshold voltage based on the memory controller's actions of: (i) programming the memory device; and (ii) providing the one or more search voltages.

Description

Technical Field

[0001] This disclosure relates to memory, and in particular to a memory device and memory system. Prior Technology

[0002] The growth of big data and artificial intelligence (AI), such as AI hardware accelerators, has increased the importance of searching, comparing, and / or ranking data (e.g., intra-memory search, IMS). Systems performing IMS can use ternary content addressable memory (TCAM) technology or other technologies that indicate whether there is a match between stored and input data to perform the search.

[0003] For example, traditional TCAM is implemented using static randomly accessible memory (SRAM) technology and non-volatile memory technologies (such as 2T2R-based dual-transistor dual-resistor and 2FeFET-based biferroelectric field-effect transistors). Typically, the search in this type of TCAM only indicates whether there is a match between stored and input data, or whether there is a mismatch. Alternatively, for example, traditional IMS can be performed using NAND flash memory. However, this type of NAND flash memory technology also only indicates whether there is a match between stored and input data, or whether there is a mismatch.

[0004] Some applications of IMS benefit from the ability to determine the similarity or dissimilarity between input and stored data. In other words, it is helpful to understand how close the input and stored data are if they do not match. Therefore, in addition to performing IMS to indicate whether the input and stored data match or do not match, an IMS technology is needed to indicate the similarity or dissimilarity between the input and stored data when a mismatch exists. Summary of the Invention

[0005] This disclosure pertains to in-memory searching (IMS), such as using flash memory. Specifically, the IMS described herein uses Euclidean distance calculation to determine the difference between stored logical values ​​(e.g., stored data) and input logical values ​​(e.g., input data) to ascertain the similarity or dissimilarity between the input and stored values.

[0006] This disclosure relates to a memory system comprising a memory device, a memory controller, and configuration circuitry. The memory device is used to store data for searching within the memory. The memory controller has logic to perform: (i) programming the memory device to store stored data according to one or more programming voltages; (ii) providing one or more search voltages to the memory device according to input data; and (iii) determining the similarity between the stored data and the input data based on an output current from the memory device. The output current represents the Euclidean distance between a stored logic value representing the stored data and an input logic value representing the input data. The configuration circuitry has logic to determine a reference threshold voltage, wherein the determination is based on the following actions of the memory controller: (i) programming the memory device using the one or more programming voltages to set one or more threshold voltages; and (ii) providing the one or more search voltages; wherein the reference threshold voltage is determined to cause the output current to be such that the stored logic value is such that the Euclidean distance between the stored logic value and the input ...

[0007] In one embodiment, the reference threshold voltage is determined based on an ideal reference threshold voltage, which is calculated by extrapolation of a characteristic line with known or confirmed characteristics, and the characteristic line is derived from... The relationship between the gate voltage and the current is represented by a curve. Id represents the drain current provided by the memory device in response to the gate voltage.

[0008] In one embodiment, the logic of the configuration circuit for determining the reference threshold voltage includes: calculating a partial derivative curve for the known or confirmed characteristics of the memory device; and identifying the value of the gate voltage as an ideal reference threshold voltage, wherein the value of the gate voltage is confirmed based on the peak point and tangent of the partial derivative curve, and the tangent is tangent to the confirmation point on the relationship curve corresponding to the peak point; wherein the reference threshold voltage is set based on the calculated ideal reference threshold voltage.

[0009] In one embodiment, the logic of the configuration circuit for determining a reference threshold voltage includes: determining the peak value of the gate voltage, wherein the peak value is aligned with the voltage at the peak point of the partial derivative curve; determining a point on the relationship curve aligned with the peak value; calculating the tangent line tangent to the confirmation point on the relationship curve, wherein the slope of the tangent line is defined by the peak point of the partial derivative curve; and determining the value of the ideal reference threshold voltage such that the value of the gate voltage corresponds to a point on the tangent line, wherein the point meets the following conditions: =0.

[0010] In one embodiment, the reference threshold voltage is determined based on an extracted reference threshold voltage, which is calculated by applying an ideal reference threshold voltage to a group of memory cells in the memory device.

[0011] In one embodiment, the extraction reference threshold voltage is determined by: determining an actual mid-current drain of the memory cell group of the memory device as an ideal reference threshold voltage, and defining the actual mid-current drain as current Ith; and determining the extraction reference threshold voltage from the relationship curve, and using the extraction reference threshold voltage as the voltage corresponding to the current Ith on the relationship curve, so that the extraction reference threshold voltage is an improved version of the ideal reference threshold voltage adjusted according to the actual changes of the memory cell group.

[0012] In one embodiment, the memory controller is configured to configure logic to store one of n logic values ​​as a stored logic value, wherein the stored logic value is represented by stored data of each cell of the memory device, and n is an integer greater than zero.

[0013] In one embodiment, n is a value between 1 and 8.

[0014] In one embodiment, the configuration circuit also has logic to perform: setting a voltage value ΔV based on a reference threshold voltage being adjusted to a different logic value among n stored logic values.

[0015] In one embodiment, the configuration circuit also has logic to perform: minimizing an error in the Euclidean distance, wherein the error is calculated between the stored logic value and the input logic value by defining an adjustment current Iref, and the output current is divided according to the adjustment current.

[0016] In one embodiment, the adjustment current Iref is calculated based on the voltage value ΔV, n, and the reference threshold voltage.

[0017] In one embodiment, the configuration circuit has logic to perform: minimizing the error of the Euclidean distance, wherein the error is calculated between the stored logic value and the input logic value by defining an adjustment current Iref, and the output current is divided according to the adjustment current before determining the Euclidean distance.

[0018] In one embodiment, the memory device is a multi-layer content-addressable memory.

[0019] In one embodiment, the memory device is a two-dimensional NOR flash memory. A pair of rows in a specific row of the two-dimensional NOR flash memory is used to store data. A plurality of character lines in the two-dimensional NOR flash memory are used to input data corresponding to the stored data, and these character lines are connected to the pair of rows in the specific row. A row of the two-dimensional NOR flash memory is used to store one or more data characters.

[0020] In one embodiment, the two-dimensional NOR flash memory is configured as a dual-transistor NOR flash memory, and one transistor of each dual-transistor pair is used to enable or disable the search for a particular transistor array.

[0021] In one embodiment, the two-dimensional NOR flash memory is configured as a discrete-gate NOR flash memory, and the gate of each transistor is used to enable or disable the search for a particular transistor array.

[0022] In one embodiment, the memory device is a three-dimensional NOR flash memory.

[0023] This disclosure also includes a memory device comprising a plurality of memory cells and a memory controller. The memory cells are used to store data for searching within the memory. The memory controller is configured to perform logic to: program the memory device to store stored data according to one or more programming voltages, wherein the one or more programming voltages are set based on a reference threshold voltage; provide one or more search voltages to the memory device according to input data, wherein the one or more search voltages are set based on a reference threshold voltage; and determine the similarity between the stored data and the input data based on an output current from the memory device, wherein the output current is used to represent the Euclidean distance between a stored logic value representing the stored data and an input logic value representing the input data; wherein the reference threshold voltage is determined such that the output current represents the Euclidean distance between the stored logic value and the input logic value.

[0024] In one embodiment, the reference threshold voltage is determined based on an ideal reference threshold voltage, which is calculated by extrapolation of a characteristic line with known or confirmed characteristics, and the characteristic line is derived from... The relationship between the gate voltage and the memory device is represented by a curve. Here, Id represents the drain current supplied by the memory device in response to the gate voltage.

[0025] In one embodiment, the logic of the configuration circuit for determining the reference threshold voltage includes: calculating a partial derivative curve for the known or confirmed characteristic of the memory device; and identifying the value of the gate voltage as an ideal reference threshold voltage, wherein the value of the gate voltage is confirmed based on the peak point and tangent of the partial derivative curve, and the tangent is tangent to the confirmation point on the relationship curve corresponding to the peak point; wherein the reference threshold voltage is set based on the calculated ideal reference threshold voltage.

[0026] In addition, methods can be provided to perform the operations and functions of the aforementioned memory system.

[0027] For example, a method for use in a memory system may be provided, wherein the memory system includes a memory device, a memory controller, and configuration circuitry. The method includes: the memory device storing data for searching within the memory, and the memory controller configuring logic to perform: (i) programming the memory device to store stored data according to one or more programming voltages; (ii) providing one or more search voltages to the memory device according to input data; and (iii) determining a similarity between the stored data and the input data based on an output current from the memory device. The output current is used to represent the Euclidean distance between a stored logic value representing the stored data and an input logic value representing the input data. The configuration circuitry has logic to determine a reference threshold voltage, wherein the determination is based on the following actions of the memory controller: (i) programming the memory device using the one or more programming voltages to set one or more threshold voltages; and (ii) providing the one or more search voltages; wherein the reference threshold voltage is determined to result in the Euclidean distance between the output current, the stored logic value, and the input logic value.

[0028] Furthermore, a method for operating a memory device is also provided, wherein the memory device includes a plurality of memory cells and a memory controller. The method includes storing data to the memory cells for memory searching. The method further includes causing the memory controller to: program the memory device to store stored data according to one or more programming voltages, wherein the one or more programming voltages are set based on a reference threshold voltage; provide one or more search voltages to the memory device according to input data, wherein the one or more search voltages are set based on a reference threshold voltage; and determine the similarity between the stored data and the input data based on an output current from the memory device, wherein the output current is used to represent the Euclidean distance between a stored logic value representing the stored data and an input logic value representing the input data; wherein the reference threshold voltage is determined such that the output current represents the Euclidean distance between the stored logic value and the input logic value.

[0029] The various forms and advantages of this disclosure will be explained through the following figures, implementation methods and patent claims. Simple Explanation of the Diagram

[0030] Figure 1 shows a schematic diagram of a two-dimensional search memory used to perform a search within the memory. Figure 2 shows a schematic diagram of a three-dimensional search of memory. Figure 3A shows a schematic diagram of the relationship between the drain current (Id) and the gate voltage (Vg) of the transistor used for searching within the memory cell. Figure 3B shows a schematic diagram of the relationship between the square root of the drain current (Id) and the gate voltage (Vg) of the transistor used for searching within the memory cell. Figure 3C shows a schematic diagram of the square root of the drain current (Id) divided by the calculated reference current (Iref) and (Vg-Vt) / (Vg-Vt)ref. Figure 3D shows a schematic diagram of the relationship between Euclidean distance (L2) and n. Figure 4A shows the use A schematic diagram illustrating the relationship curve between V and Vg for calculating the ideal Vt. Figure 4B shows the results using the calculated ideal Vt and... A schematic diagram illustrating the relationship curve between V and Vg to calculate the extracted Vt. Figure 4C shows a schematic diagram of the Euclidean distance (L2) and the Iref curves corresponding to different n values. Figure 5A shows a schematic diagram of a multi-level content addressable memory (MCAM) based on NOR flash memory, which can be used to calculate the Euclidean distance between stored data and input data. Figure 5B shows a schematic diagram of eight threshold levels used for data storage and eight voltages representing different search or input values. Figure 5C shows a table representing different floating raster values ​​for stored data and different character line values ​​for input (search) data. Figure 6 shows a table of different drain current values ​​based on the difference between the stored value and the input value. Figure 7 shows... The relationship between Vg and the current (distance) increases as the difference between the stored value and the input value increases. Figure 8 shows a memory based on two-dimensional NOR, where the output current increases as the difference between the stored value and the input value increases. Figure 9 shows a memory arithmetic array based on two-dimensional NOR, used to compare input data with stored data and provide the current output representing the Euclidean distance between the input data and the stored data. Figure 10 shows the flash memory architecture of a two-dimensional NOR. According to this architecture, a search character is input on each character line to compare the search character with the stored data character stored in a row. Furthermore, Euclidean distance technology can be applied to determine the distance between the search character and the stored data character based on this architecture. Figure 11 shows the 2T-NOR flash memory architecture. According to this architecture, a search character is input on each MG line to compare the search character with the stored data character stored in a row. Furthermore, Euclidean distance technology can be applied to determine the distance between the search character and the stored data character based on this architecture. Figure 12 shows the architecture of a split-gate NOR flash memory. According to this architecture, a search character is input on each MG line to compare the search character with the stored data character stored in a row. Furthermore, Euclidean distance technology can be applied to determine the distance between the search character and the stored data character based on this architecture. Figure 13 shows a two-dimensional NOR flash memory architecture. According to this architecture, two search characters are input on each character line to compare these two search characters with two stored data characters stored in a row. Furthermore, Euclidean distance technology can be applied to determine the distance between the search characters and the stored data characters based on this architecture. Figure 14 shows the 2T-NOR flash memory architecture. According to this architecture, two search characters are input on each character line to compare these two search characters with two stored data characters stored in a row. Furthermore, Euclidean distance technology can be applied to determine the distance between the search characters and the stored data characters based on this architecture. Figure 15 shows the architecture of a split-gate NOR flash memory. According to this architecture, two search characters are input on each character line to compare the two search characters with two stored data characters stored in a row. Furthermore, Euclidean distance technology can be applied to determine the distance between the search characters and the stored data characters based on this architecture. Figure 16 shows a split-gate NOR flash memory architecture. According to this architecture, two search characters are input on different character lines to compare the two search characters with two stored data characters stored in the same row. According to this architecture, each column in the NOR flash memory architecture is disabled for searching, and Euclidean distance technology can be applied to determine the distance between the search characters and the stored data characters. Figure 17 shows a three-dimensional NOR flash memory architecture. According to this architecture, a search character is input on each character line of a row of transistors in a block to compare the search character with the stored data characters stored in the columns of transistors in that block. According to this architecture, Euclidean distance technology can be applied to determine the distance between the search character and the stored data characters. Figure 18 shows a three-dimensional NOR flash memory architecture. According to this architecture, a search character is input on a character line of each different block to compare the search character with the stored data character stored on a character line of each different block. According to this architecture, Euclidean distance technology can be applied to determine the distance between the search character and the stored data character. Figure 19 shows a three-dimensional NOR flash memory architecture. According to this architecture, a search character is input on multiple character lines in each different block to compare the search character with the stored data characters stored on multiple character lines in each different block. According to this architecture, Euclidean distance technology can be applied to determine the distance between the search character and the stored data characters. Figure 20 shows a simplified schematic diagram of a storage system, including memory that uses an IMS to search for character sequences in order to implement the various Euclidean distance techniques described in this disclosure. Implementation

[0031] The techniques disclosed herein are used to determine the similarity or degree of similarity between data stored in memory (such as stored data characters, stored logical values, etc.) and input data (such as input search characters, input logical values, etc.). Specifically, these techniques can be applied to memory architectures that implement Memory Search (IMS).

[0032] These techniques include determining distances, such as the Euclidean distance between stored data characters (e.g., stored logical values) and input search characters (e.g., input logical values). The Euclidean distance is zero if the stored data characters and the input search characters match perfectly. The calculated Euclidean distance increases as the difference between the stored data characters and the input search characters increases. The determined Euclidean distance, based on the proximity of the input search characters to the stored data characters, can be used to make decisions.

[0033] In mathematics, the Euclidean distance (L²) is the shortest distance between two points in N-dimensional space (such as Euclidean space), and it is a commonly used metric to measure the similarity between two data points. The Euclidean distance can be calculated as the difference between the square roots of the sum of the squares of the corresponding targets. The formula for calculating the N-dimensional Euclidean distance is as follows:

[0034] The calculation of Euclidean distance can be applied to a new purpose as a new technique to determine the similarity (or dissimilarity) between input search characters and stored data characters.

[0035] This technology may include determining a reference threshold voltage Vt for programming or writing to the memory cell, and defining a technique for measuring the current output from the memory cell when an input search word is provided, such that the output current represents the Euclidean distance between the stored data word and the input search word. When the similarity between the stored data word and the input search word is high, the Euclidean distance is small, and the output current is low; when the similarity between the stored data word and the input search word is low, the Euclidean distance is large, and the output current is high. This technology can be applied to two-dimensional and three-dimensional NOR flash memory, including multi-level content-addressed memory (MCAM), standard NOR architecture, two-transistor (2T) NOR flash memory architecture, split-gate NOR architecture, and other types of NOR architecture.

[0036] To facilitate understanding, before explaining the techniques for determining the similarity or dissimilarity of input search characters relative to stored data characters, we will first describe the two-dimensional and three-dimensional memory systems that implement these techniques as follows.

[0037] Figure 1 shows a schematic diagram of a two-dimensional search memory used to perform In-Memory Search (IMS).

[0038] Specifically, the two-dimensional search memory 100 shown in Figure 1 includes encoding resources, which include a data encoder 160 (e.g., a data encoding circuit) capable of receiving data 110 and, in response, providing encoded data 111 (e.g., programming data, stored data characters to be stored) on bit lines (BLs) 180 to the memory array 150. In one embodiment, the memory array 150 may be a NOR flash memory architecture. The encoding resources also include a search encoder 170 for receiving search 120 (e.g., input data characters) and, in response, providing string search lines (e.g., string selection lines (SSLs) 171 as shown) and paired character lines (e.g., character lines (WLs~) 172 as shown). The encoding performed by the encoding resources is based on a specific encoding technique, such as encoding 140 shown in the dashed box in the figure. This encoding 140 and the operation of other memory components can be performed by a memory controller, as detailed in Figure 20 below. The search results on source lines (SLs) 182 (e.g., the result of comparing a stored data character with an input search character) are provided to the common source line (CSL) 184. The search results include the current generated by the voltage applied to bit line 172 and the threshold voltage of the transistors (or switches) included in the memory array 150. The output resources of the two-dimensional search memory 100 may include sense amplifiers, etc., connected to source lines 182 and / or common source line 184.

[0039] To clearly illustrate the features, some details have been omitted from the diagram, such as the description of a programmable memory device for programming and erasing a two-dimensional memory array.

[0040] Figure 2 shows a schematic diagram of the three-dimensional memory search used to perform IMS.

[0041] The three-dimensional search memory 200 shown in Figure 2 is implemented in three-dimensional space (X, Y, and Z) and includes encoding resources. The encoding resources include a data encoder 260 (e.g., a data encoding circuit) that receives data 210 and, in response, provides encoded data 211 (e.g., programming data, stored data characters to be stored) on bit lines (BLs) 280 to the three-dimensional memory array 250. In one embodiment, the memory array 250 may be a NOR flash memory architecture. The encoding resources also include a search encoder 270 for receiving a search 220 (e.g., input data characters) and, in response, providing string search lines (e.g., string selection lines (SSLs) 271 as shown) and paired character lines (e.g., character lines (WLs~WL's) 272 as shown). The encoding performed by the encoding resources is based on a specific encoding technique, such as encoding 240 shown in the dashed box in the figure. The operation of this code 240 and other memories can be performed by the memory controller, as detailed in Figure 20 below. The search results on source lines (SLs) 282 (e.g., the result of comparing a stored data character with an input search character) are provided to the common source line (CSL) 284. The search results include the current generated by the voltage applied to bit line 272 and the threshold voltage of the transistors (or switches) included in the three-dimensional memory array 250. The three-dimensional memory array 250 may include multiple two-dimensional memory arrays, one of which is labeled as two-dimensional memory array (2D) 299 in the figure. The output resources of the three-dimensional search memory 200 may include sense amplifiers, etc., connected to source line 282 and / or common source line 284.

[0042] Figure 3A shows the relationship between the drain current (Id) and gate voltage (Vg) of a transistor used in IMS.

[0043] Specifically, the drain current (Id) versus gate voltage (Vg) curve 302 shown in Figure 3A can be applied to any type of cell (e.g., transistor or switch) used in a memory device. In this disclosure, the term "transistor" can refer to any cell in a memory device, including basic switching elements. Furthermore, the term "transistor" can refer to any type of transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), including NMOS and PMOS. This drain current (Id) versus gate voltage (Vg) curve 302 can be the result of measuring the characteristics of a specific transistor based on various voltages and / or currents applied to the gate, source, and / or drain. The drain current (Id) versus gate voltage (Vg) curve 302 can be provided by the transistor manufacturer and / or can be actually measured at any given point in time during the transistor's lifespan.

[0044] As shown in the figure, the Y-axis represents the drain current (Id), and the X-axis represents the gate voltage (Vg). Most transistors behave in a way that when the gate voltage (Vg) increases sufficiently to put the transistor in its saturation operating region, the relationship curve 302 flattens out (e.g., even if the gate voltage (Vg) continues to increase, the drain current (Id) remains constant). This saturation operating region is not shown in the relationship curve 302.

[0045] Figure 3B shows the relationship between the square root of the drain current (Id) of the transistor used in IMS and the voltage curve (Figure 304).

[0046] Specifically, Figure 3B presents The relationship curve between the gate voltage (Vg) and curve 306, and Curve 308 shows the relationship between the gate voltage (Vg) and the threshold voltage (Vt). The relationship curve 306 between the gate voltage (Vg) and the gate voltage (Vg) can be derived from the relationship curve 302 shown in Figure 3A. The relationship curve 308 is essentially the same as the relationship curve 306, except that it is shifted to the right by an amount equivalent to the threshold voltage (Vt) of the specific transistor.

[0047] One technique for determining the similarity between stored data characters and input search characters is to determine a reference threshold voltage (Vt) to be implemented when storing and inputting IMS logic values. The reference threshold voltage (Vt) can be the lowest threshold voltage for storing a certain value in a single transistor or a pair of transistors. For example, if a floating-gate transistor is used to store one of eight values ​​(e.g., eight possible logic values), the threshold voltage of the floating-gate transistor can be programmed to be any one of eight different voltages. These eight different voltages can be described as Vt0, Vt1, Vt2, Vt3, Vt4, Vt5, Vt6, and Vt7, or as Vt0 through Vt7. One reference threshold voltage (Vt) can be set to be equal to Vt0, and then the other voltages Vt1 through Vt7 are set to progressively higher than Vt0. In some embodiments, the increment between each voltage can be the same, while in other embodiments, the increment between each voltage in the range can be different.

[0048] In one embodiment, the voltage set by the reference threshold voltage (Vt, or ideal reference threshold voltage, extracted reference threshold voltage) makes... It is proportional to (Vg-Vt). As shown in the figure, the reference threshold voltage (Vt) 309 is shown in the figure. The starting point is proportional to (Vg-Vt). In other words, the base threshold voltage (Vt) can be defined as the voltage at which the drain current (Id) can be obtained through a square ratio. Other techniques for determining the reference threshold voltage (Vt) will be explained below.

[0049] Figure 3C, or diagram 310, shows a schematic of the relationship between the drain current (Id) divided by the square root of the calculated reference current (Iref) and (Vg-Vt) / (Vg-Vt)ref.

[0050] Specifically, the Y-axis of Figure 3C represents the drain current (Id) divided by the square root of the calculated adjustment current (Iref). The calculation of the adjustment current (Iref) will be explained in detail below. The purpose of the adjustment current (Iref) is to adjust the drain current (Id) so that it can more accurately represent the Euclidean distance between the stored data and the input data.

[0051] The X-axis represents (Vg – Vt) / (Vg – Vt)ref, where (Vg – Vt)ref equals ∆V, and ∆V represents the incremental change in voltage, such as the change between Vt0 and Vt1, between Vt1 and Vt2, and so on. The magnitude of ∆V can be selected from a range of selectable voltages. For example, ∆V can be between 0.05V and 0.3V. If ∆V is close to the lower limit of the 0.05V to 0.3V range, the L2 result may be more accurate at higher values ​​of n. If ∆V is close to the upper limit of the range or exceeds the range, the transistor will enter the saturation region when the value of n is high. The first "n" is the ratio of (Vg – Vt) / ∆V. That is, if it is desired to support L2 calculations up to n=X, then the applied Vg is "Vt + X * ∆V", and this applied Vg cannot cause the transistor to enter the saturation region.

[0052] As shown in Figure 3C, n (i.e., the possible number of logic values ​​stored in the transistor) is equal to the ratio of (Vg – Vt) / (Vg – Vt)ref, and under a given drain current (Id), it can also be equal to As shown in curve 312, when the value of ∆V is selected, Iref is determined, and the device's Vt is determined or known, Vg can be applied to the device and n can be defined as (Vg-Vt) / ∆V. Then, the transistor's drain current Id can be determined based on the applied Vg, and the Euclidean distance L2 can be obtained through Id / Iref.

[0053] Figure 3D shows a schematic diagram of the relationship between Euclidean distance (L2) and n.

[0054] Specifically, the relationship curve 316 shown in Figure 3D represents the Euclidean distance L2 based on the square of n. This means that the greater the distance between the input and stored values, the larger the Euclidean distance. For example, if the stored (logical) value is 0 and the input (logical) value is 5, the Euclidean distance between the logical values ​​is 25, since n=5 in this example. In relationship graph 314, the dashed or dotted lines represent the ideal L2 distance of n squared, while the dots represent actual experimental results.

[0055] Figure 4A shows the use A schematic diagram illustrating the relationship curve between V and Vg for calculating the ideal Vt.

[0056] Specifically, Figure 4A, diagram 400, illustrates how to calculate the ideal reference threshold voltage Vt (ideal Vt). First, the transistor's... The relationship curve between Vg and curve 402 is shown in Figure 3B. Curve 306 is also shown in Figure 3B. An example of the relationship curve 402 between Vg and εg. As mentioned above, relationship curve 402 can be obtained in various ways. Next, the partial derivatives of relationship curve 402 are calculated (see curve 404). As shown in the figure, curve 404 is obtained by calculating... / The peak value of curve 404 is identified, and the voltage value Vg is then obtained from curve 404. Specifically, the vertical dashed line 406 is located at the peak value of curve 404, and the voltage (Vg_peak) 408 is identified at the intersection of the vertical dashed line 406 and the X-axis. The value of voltage (Vg_peak) 408 is based on the peak value obtained from the partial derivative curve 404. Value. In other words, the voltage (Vg_peak) 408 is aligned with the peak point of the calculated partial derivative curve 404.

[0057] Voltage (Vg_peak) 408 is used for identification A point 409 on the curve 402 relating Vg to Vg. In other words, identifying... Point 409 on the curve 402 relating Vg and voltage (Vg_peak) corresponds to voltage (Vg_peak) 408. Next, based on the slope of the partial derivative curve 404, the tangent line 410 tangent to point 409 is calculated from point 409. For example, the direction of the tangent at point 409 can be inferred through extrapolation, thus obtaining the tangent line 410. In other words, the slope of the peak value of the partial derivative curve 404 can be used to calculate the slope of the tangent line 410 tangent to point 409. The slope of the tangent line 410 can be determined from other values ​​derived from curve 404 or through calculation.

[0058] The intersection point 412 of the tangent 410 and the X-axis is determined to be the ideal reference threshold voltage Vt (hereinafter referred to as ideal Vt). In other words, ideal Vt can be expressed as the voltage value on the tangent 410, where =0. The ideal Vt can be represented as a minimum threshold voltage used for storing values ​​and input data to determine the Euclidean distance between the stored value (e.g., stored data, stored data character, etc.) and the input data (e.g., input search character). As will be explained in more detail later, the calculated ideal Vt value can serve as both the minimum programming threshold voltage for the transistor and the minimum voltage representing the input search character. The ideal Vt can be represented as voltage Vtn, where n=0. For example, if it is determined that the transistor can store eight values, the voltages used to store these eight values ​​are represented as voltages Vt0~Vt7, and the difference between each voltage (e.g., voltages Vt0, Vt1) is expressed as ∆V, representing the voltage increment. The range of voltage Vtn can be the threshold voltage range used to program the transistor. More embodiments will be provided in subsequent paragraphs. Even if voltage Vt0 is close to the ideal Vt, voltage Vt0 does not necessarily need to be equal to the ideal Vt. Vt0 can be either extracted Vt or ideal Vt.

[0059] Figure 4B shows the results using the calculated ideal Vt and... A schematic diagram illustrating the relationship curve between V and Vg to calculate the extracted Vt.

[0060] The technique of this elucidation of the contents can be applied to the calculation of the extracted Vt (or referred to as the extracted datum threshold reference voltage Vt) based on the ideal Vt discussed in Figure 4A . The process of calculating the extraction of Vt may include the following operations: (i) Obtaining a curve 416 between Id and Vg of a known transistor, as discussed previously in Figure 3A 302 . (ii) Determine the current value Id corresponding to the ideal Vt on the curve 416. In the 4B diagram, the point 418 on the X-axis indicates the ideal Vt and intersects with the vertical dashed line 420 , where the intersection points indicate the current value Id that is discerned. (iii) Use a selected set of transistors based on the transistors of the acquired curve 416 to judge the median draw current value Id corresponding to the ideal Vt (in other words, using a set of actual or simulated transistors, the calculated ideal Vt will be used to judge the median draw current value Id). (iv) Define the judged median draw current value Id as the current value Ith as shown in line 422 . (v) Calculate the datum extraction threshold voltage Vt (extraction Vt) based on the intersection of the current value Ith (line 422) and curve 416 . As shown in FIG.

[0061] Thus, point 426 (extracted Vt) is based on the measurements obtained from a set of transistors, thereby adjusting the ideal Vt to obtain the extracted Vt according to the actual performance of many transistors. In Figure 4A , the aforementioned, the technique for determining ideal Vt can also be obtained “offline” without the need for actual testing of the transistor. The technology described in Figure 4B previously can be obtained “online” by performing actual field tests (or simulations) on the transistor.

[0062] A schematic diagram of the Iref curve corresponding to the Euclidean distance (L2) and different n values ​​is shown in Figure 4C .

[0063] Before explaining the relationship Figure 428, the purpose and method of calculating the adjusted current Iref are explained. The judgment of the adjusted current Iref is used to minimize the error in the calculated Euclidean distance. The adjustment current Iref can be defined as the datum current for calculating the Euclidean distance such that the Euclidean distance = Id / Iref. In other words, the exact value of the Euclidean distance between the stored data and the input data is obtained by dividing the measured drawer current Id by the adjusted current Iref.

[0064] For flash memory, the drain current Id does not follow the property that "for all Vg voltage values, the drain current Id is proportional to (Vg – Vt)²", which will lead to errors in the calculation of the Euclidean distance. To minimize this error, an adjustment current Iref can be calculated, where the value of the adjustment current Iref can be based on a defined value n, where the maximum value of n is equal to the number of logic values ​​that can be stored (or input), and the value of n can vary with the currently stored (or input) logic values.

[0065] Adjusting the current can be expressed as Where Idn = Id|(Vg-Vt) = ∆V×n. In other words, the drain current Idn, calculated corresponding to the value of n, is used to calculate the adjustment current Iref for that value of n, where ∆V is a predetermined value representing the incremental voltage change, used to set and judge different drain current Id values. It should be noted that... Where Vt can be the calculated ideal Vt or the extracted Vt. The formula for adjusting the current is used. Here are some examples: (i) If Iref is defined at "n=1", then (ii) If Iref is defined at "n=2", then (iii) If Iref is defined at "n=3", then (iv) If Iref is defined at "n=4", then (v) If Iref is defined at "n=5", then (vi) If Iref is defined at "n=6", then (vii) If Iref is defined at "n=7", then (viii) If Iref is defined at "n=8", then .

[0066] As shown in diagram 428, different Iref curves correspond to different n values. For example, curve 430 represents the Iref diagram for n=1, curve 432 for n=4, curve 434 for n=6, curve 436 for n=8, and curve 438 for the ideal state diagram. As shown, curves 434 and 436 are closest to the ideal curve 438. According to curve 436 (the Iref diagram for n=6), if the n value on the X-axis is 8 (i.e., the difference between the stored value and the input value is 8), the Euclidean distance result is approximately 60; according to curve 430 representing the Iref diagram for n=1, if the n value on the X-axis is also 8, the Euclidean distance result will be less than 100. As shown, using different Iref values ​​can change the calculated Euclidean distance. In the diagram, "Iref@n=6" is close to the ideal calculation, while "Iref@n=8" is closest to the ideal calculation.

[0067] As discussed above, the range of ∆V is between 0.05V and 0.3V. The characteristics of the transistor can be described as follows: ,in ,because Euclidean distance will be Using these formulas, some examples are provided below.

[0068] When ∆V is 0.05V and the extracted Vt (or ideal Vt) is 0.5V, And the Euclidean distance is .

[0069] When ∆V is 0.1V and the extracted Vt (or ideal Vt) is 0.5V, And the Euclidean distance is .

[0070] When ∆V is 0.3V and the extracted Vt (or ideal Vt) is 0.3V, And the Euclidean distance is .

[0071] Figure 5A shows a schematic diagram of a multi-level content addressable memory (MCAM) based on NOR flash memory, which can be used to calculate the Euclidean distance between stored data and input data.

[0072] Specifically, Figure 5A shows an MCAM circuit 500 for implementing IMS using the techniques disclosed herein. The MCAM circuit 500 includes a floating gate (FG) transistor 502 and a floating gate (FG') transistor 506. Transistor 502 includes a gate connected to a bit line (WL) 504, a terminal (e.g., a source terminal) connected to a match line (ML, such as bit line (BL) 510), and a terminal (e.g., a drain terminal) connected to a source line 512. Transistor 506 includes a gate connected to a bit line (WL') 508, a terminal (e.g., a source terminal) connected to a match line (ML, such as bit line (BL) 510), and a terminal (e.g., a drain terminal) connected to a source line (SL) 512. The logical input value represented by the search input can be encoded using predetermined voltages on word lines (WL) 504 of transistor 502 and word lines (WL') 508 of transistor 506. The search input on the paired word lines 504 and 508 can represent a single bit of logical value. The search input can be compared with a stored value (e.g., a data bit represented by the value stored by transistors 502 and 506). For example, the stored data bit can be stored as two threshold voltages on transistors 502 and 506. As detailed in Figure 5C below, the stored data value (e.g., a stored data bit) is represented by the threshold voltages of the two transistors 502 and 506, where the threshold voltages are programmed according to the desired value of the data bit, and the search input value (e.g., a data bit to be compared with the stored data bit) is represented by the voltage applied to the two bit lines 504 and 508. The outputs of transistors 502 and 506 will depend on how close the search input value (such as the search voltage) is to the stored data value (such as the threshold voltage). The behavior of transistors 502 and 506 in one embodiment is described below.

[0073] In one embodiment, when the search voltage applied to bit line (WL) 504 falls within the matching range of the value of transistor 502 (e.g., the threshold voltage representing the stored data bit), the voltage on bit line (BL) 510 will not discharge through transistor 502, so that no current is output from the drain of transistor 502 to the source line 512. Similarly, when the search voltage applied to bit line (WL') 508 falls within the matching range of the value of transistor 506 (e.g., the threshold voltage representing the stored data bit), the voltage on bit line (BL) 510 will not discharge through transistor 506, so that no current is output from the drain of transistor 506 to the source line 512. Zero current (or very low current) on the source line 512 will be used to indicate that the "search voltage" matches the "stored logic value represented by the threshold voltages of transistors 502 and 506".

[0074] Furthermore, when the search voltage applied to the word line (WL) 504 does not fall within the range matched by the value of the transistor 502 (e.g., the threshold voltage representing the stored data bit), the transistor 502 discharges on the bit line (BL) 510 according to the difference between the search voltage and the (programmed) threshold voltage of the transistor 502 (e.g., proportional to the square of the difference between the search voltage and the (programmed) threshold voltage), so that the drain of the transistor 502 outputs current to the source line 512, which is based on (e.g., proportionally) the search voltage. Similarly, when the search voltage applied to word line (WL) 508 does not fall within the range matched by the value of transistor 506 (e.g., the threshold voltage representing the stored data bit), transistor 506 discharges on bit line (BL) 510 according to the difference between the search voltage and the (programmed) threshold voltage of transistor 506 (e.g., proportional to the square of the difference between the search voltage and the (programmed) threshold voltage), so that the drain of transistor 506 outputs current to source line 512, which is based on (e.g., proportionally) the search voltage.

[0075] Figure 5B shows a schematic diagram of eight threshold levels used for data storage and eight voltages representing different search or input values.

[0076] Specifically, Figure 5B shows the distribution of memory cells as shown in Figure 5A or other memory cells disclosed herein. In Figure 5B, the X-axis corresponds to voltage, and the Y-axis corresponds to the number of memory cells.

[0077] As shown in Figure 5B, memory cells can have a distribution corresponding to threshold voltages Vt, such as Vt0, Vt1, Vt2, Vt3, Vt4, Vt5, Vt6, and Vt7 (Vt0~Vt7). In response to being programmed to store data, each memory cell can have a threshold voltage level (Vt0~Vt7) corresponding to the stored value. Furthermore, as shown in Figure 5B, voltage levels V0, V1, V2, V3, V4, V5, V6, and V7 (V0~V7) are arranged sequentially along the X-axis and located at the peak of the threshold voltage level distribution Vt0~Vt7. Voltage levels V0~V7 can be referred to as search or input voltage levels.

[0078] Figure 5C shows tables 514 and 516 representing different floating raster values ​​for stored data and different character line values ​​for input (search) data.

[0079] Specifically, Table 514 shows the different threshold voltage Vt values ​​used to store different logic values. For example, Table 514 shows the specific encoding of logic values ​​to (programmed) threshold voltages. For instance, to store the logic value 0, transistor 502 will be programmed to have a threshold voltage corresponding to Vt0, and transistor 506 will be programmed to have a threshold voltage corresponding to Vt7. To store the logic value 1, transistor 502 will be programmed to have a threshold voltage corresponding to Vt1, and transistor 506 will be programmed to have a threshold voltage corresponding to Vt6. To store the logic value 2, transistor 502 will be programmed to have a threshold voltage corresponding to Vt2, and transistor 506 will be programmed to have a threshold voltage corresponding to Vt5. To store the logic value 3, transistor 502 will be programmed to have a threshold voltage corresponding to Vt3, and transistor 506 will be programmed to have a threshold voltage corresponding to Vt4. To store the logic value 4, transistor 502 will be programmed to have a threshold voltage corresponding to Vt4, and transistor 506 will be programmed to have a threshold voltage corresponding to Vt3. In order to store the logic value 5, transistor 502 will be programmed to have a threshold voltage corresponding to Vt5, and transistor 506 will be programmed to have a threshold voltage corresponding to Vt2.

[0080] To store logic value 6, transistor 502 will be programmed to have a threshold voltage corresponding to Vt6, and transistor 506 will be programmed to have a threshold voltage corresponding to Vt1. To store logic value 7, transistor 502 will be programmed to have a threshold voltage corresponding to Vt7, and transistor 506 will be programmed to have a threshold voltage corresponding to Vt0. Since this can be achieved using MCAM technology, transistors 502 and 506 can also be programmed to have "don't care" values ​​(such as Vt7). The values ​​of Vt0-Vt7 can be determined using the techniques disclosed herein, such that Vt0-Vt7 are based on ideal Vt or extracted Vt, and the voltage difference between each Vt level is determined by ∆V.

[0081] This is just one example of using MCAM to store eight logic values. Transistors can be configured to store more or fewer logic values.

[0082] For figures 5A to 5C, Vti+1–Vti=Vi+1–Vi=∆V, where Vi is the peak value in the Vti distribution, and i is 0 to 6. Vtn=Vt0+n×∆V, where n is 0 to 7. Vt0 to Vtn can be equal to or close to the ideal Vt or extracted Vt.

[0083] Figure 6 shows a table 600 of different drain current values ​​provided based on the difference between the stored value and the input value.

[0084] Specifically, Table 600 illustrates that for a stored value of 0 and an input (search) value of 0, the drain current can be represented as I0, indicating that the stored value and the input value are essentially matched. In other words, the Euclidean distance between the stored value and the input value is 0. The drain current I0 can correspond to the drain current Id0 or Id (n=0). Furthermore, as shown in the figure, when the input value increases from 0 to 7, and the stored value remains 0, the drain current increases to currents I1, I2, I3, I4, I5, I6, and I7, respectively. Currents I1 to I7 can be represented by drain currents Id1 to Id7. Table 600 further shows that for a stored value of 1 and an input (search) value of 0, the drain current can be represented by I1. When the input (search) value increases to 1 and the stored value remains 1, the drain current decreases to current I0, indicating that the stored value matches the input value. As the input (search) value increases from 2 to 7, while the stored value remains at 1, the drain currents increase to currents I1, I2, I3, I4, I5, and I6, respectively. Table 600 further shows the corresponding behavior for stored values ​​2 to 7. As shown in Figure 5A, the currents I1 to I7 in the left diagonal portion of Table 600 flow through the floating gate (FG) transistor 502, while the floating gate (FG') transistor 506 is in the off state. Similarly, as shown in Figure 5A, the currents I1 to I7 in the right diagonal portion of Table 600 flow through the floating gate (FG') transistor 506, while the floating gate (FG) transistor 502 is in the off state.

[0085] In this embodiment, the Euclidean distance is , where n is 1 to 7, and I0 (or I0) is less than I1 (or I1).

[0086] Figure 7 shows... The relationship between Vg and Vg is shown in Figure 700. As the difference between the stored value and the input value increases, the current (distance) also increases.

[0087] Specifically, the line labeled Vt0 indicates that when the gate voltage Vg is greater than V0... The current value will increase. Therefore, when the gate voltage Vg is V0 (equal to the value of Vt0), The current value is 0 (e.g.: When the gate voltage Vg is V7 (different from the value of Vt0), The current value becomes This indicates a larger Euclidean distance. The same principle applies to lines from Vt1 to Vt7.

[0088] Figure 8 shows a memory based on two-dimensional NOR, where the output current increases as the difference between the stored value and the input value increases.

[0089] In Figure 8, the current output on the source line (SL) represents the Euclidean distance between the input search and the stored content. A lower output current indicates a smaller Euclidean distance between the input search and the stored content (e.g., high similarity), while a higher output current indicates a larger Euclidean distance between the input search and the stored content (e.g., low similarity).

[0090] Here, Example 802 represents a logic input value of 0 and a stored logic value of 0. As previously described, the logic value 0 is stored by setting the threshold voltage Vt of the powered-on transistor to Vt0 (e.g., based on a reference threshold voltage Vt, an ideal reference threshold voltage, or an extracted reference threshold voltage Vt), and setting the threshold voltage Vt of the powered-off transistor to Vt7. This is only one example of storing the logic value 0, and it can also be implemented using other techniques. The logic value 0 is used as the input for input search by providing a voltage V0 on the word line (WL) of the powered-on transistor and on the inverted word line. A voltage V7 is supplied. As shown in the diagram, because V0 is essentially equal to (or less than) Vt0, no current flows through the transistor. Similarly, because V7 is essentially equal to (or less than) Vt7, no current flows through the transistor. In other words, since V0 is not greater than Vt0 and V7 is not greater than Vt7, both transistors are off / closed, indicating a match. This current deficiency is denoted by I0, for example, the current on the source line (SL) is twice I0 (or 0).

[0091] Example 804 represents a logic input value of 1 and a stored logic value of 0. As mentioned earlier, the logic value 0 is stored by setting the threshold voltage Vt of the powered-on transistor to Vt0 and the threshold voltage Vt of the powered-off transistor to Vt7. This is just one example of storing the logic value 0, and it can also be implemented using other techniques. The logic value 1 is used as an input search input, which is achieved by providing a voltage V1 on the word line (WL) of the powered-on transistor and on the inverted word line. A voltage V6 is provided. As shown in the diagram, since V1 is greater than Vt0, a current I1 flows through the upper transistor; however, since V6 is less than Vt7, no current flows through the lower transistor. In other words, because V1 exceeds Vt0, while V6 does not exceed Vt7, the upper transistor is turned on, and the lower transistor is turned off. Therefore, this represents a mismatch between the input value and the stored value. Here, the current is represented as I1, and the current on the source line (SL) is approximately I1.

[0092] Example 806 represents a logic input value of 2 and a stored logic value of 0. As mentioned earlier, the logic value 0 is stored by setting the threshold voltage Vt of the powered-on transistor to Vt0 and the threshold voltage Vt of the powered-off transistor to Vt7. The logic value 2 is used as the input search input by providing a voltage V2 on the word line (WL) of the powered-on transistor and on the inverted word line. A voltage V5 is provided. As shown in the diagram, since V2 is greater than Vt0, a current I2 will flow through the upper transistor; however, since V5 is less than Vt7, no current will flow through the lower transistor. In other words, because V2 exceeds Vt0 and V5 does not exceed Vt7, the upper transistor is turned on and the lower transistor is turned off. The current I2 is greater than the current I1 in Example 804 because the voltage V2 is greater than the voltage V1. This means that in Example 806, the mismatch between the input value and the stored value is greater than the mismatch in Example 804. Here, the current is represented as I2, and the current on the source line (SL) is approximately I2, which is approximately four times the current I1.

[0093] Example 808 represents a logic input value of 3 and a stored logic value of 0. As mentioned earlier, the logic value 0 is stored by setting the threshold voltage Vt of the powered-on transistor to Vt0 and the threshold voltage Vt of the powered-off transistor to Vt7. The logic value 3 is used as an input search input by providing a voltage V3 to the word (WL) of the powered-on transistor and on the inverted word line. A voltage V4 is provided. As shown in the diagram, since V3 is greater than Vt0, a current I3 will flow through the upper transistor; however, since V4 is less than Vt7, no current will flow through the lower transistor. In other words, because V3 is greater than Vt0 and V4 is not greater than Vt7, the upper transistor is turned on, while the lower transistor is turned off. The current I3 is greater than the current I2 in Example 806 because the voltage V3 is greater than the voltage V2. This means that in Example 808, the mismatch between the input value and the stored value is greater than the mismatch in Example 806. Here, the current is represented as I3, and the current on the source line (SL) is approximately I3, which is approximately nine times the current I1.

[0094] Example 810 represents a logic input value of 4 and a stored logic value of 0. As mentioned earlier, the logic value 0 is stored by setting the threshold voltage Vt of the powered-on transistor to Vt0 and the threshold voltage Vt of the powered-off transistor to Vt7. The logic value 4 is used as the input search input by providing a voltage V4 on the word line (WL) of the powered-on transistor and on the inverted word line. A voltage V3 is provided. As shown in the diagram, since V4 is greater than Vt0, a current I4 will flow through the upper transistor; however, since V3 is less than Vt7, no current will flow through the lower transistor. In other words, because V4 is greater than Vt0 and V3 is not greater than Vt7, the upper transistor is turned on, while the lower transistor is turned off. The current I4 is greater than the current I3 in Example 808 because the voltage V4 is greater than the voltage V3. This means that in Example 810, the mismatch between the input value and the stored value is greater than the mismatch in Example 808. Here, the current is represented as I4, and the current on the source line (SL) is approximately I4, which is approximately 16 times the current I1.

[0095] Example 812 represents a logic input value of 5 and a stored logic value of 0. As mentioned earlier, the logic value 0 is stored by setting the threshold voltage Vt of the powered-on transistor to Vt0 and the threshold voltage Vt of the powered-off transistor to Vt7. The logic value 5 is used as the input search input by providing a voltage V5 on the word line (WL) of the powered-on transistor and on the inverted word line. A voltage V2 is provided. As shown in the diagram, since V5 is greater than Vt0, a current I5 flows through the upper transistor; however, since V2 is less than Vt7, no current flows through the lower transistor. In other words, because V5 is greater than Vt0, and V2 is not greater than Vt7, the upper transistor is turned on, while the lower transistor is turned off. The current I5 is greater than the current I4 in Example 810 because the voltage V5 is greater than the voltage V4. This means that in Example 812, the mismatch between the input value and the stored value is greater than the mismatch in Example 810. Here, the current is represented as I5, and the current on the source line (SL) is approximately I5, which is approximately 25 times the current I1.

[0096] Example 814 represents a logic input value of 6 and a stored logic value of 0. As mentioned earlier, the logic value 0 is stored by setting the threshold voltage Vt of the powered-on transistor to Vt0 and the threshold voltage Vt of the powered-off transistor to Vt7. The logic value 6 is used as the input search input by providing a voltage V6 on the word line (WL) of the powered-on transistor and on the inverted word line. A voltage V1 is provided. As shown in the diagram, since V6 is greater than Vt0, a current I6 flows through the upper transistor; however, since V1 is less than Vt7, no current flows through the lower transistor. In other words, because V6 is greater than Vt0 and V1 is not greater than Vt7, the upper transistor is turned on, while the lower transistor is turned off. The current I6 is greater than the current I5 in Example 812 because the voltage V6 is greater than the voltage V5. This means that in Example 814, the mismatch between the input value and the stored value is greater than the mismatch in Example 812. Here, the current is represented as I6, and the current on the source line (SL) is approximately I6, which is approximately 36 times the current I1.

[0097] Example 816 represents a logic input value of 7 and a stored logic value of 0. As mentioned earlier, the logic value 0 is stored by setting the threshold voltage Vt of the powered-on transistor to Vt0 and the threshold voltage Vt of the powered-off transistor to Vt7. The logic value 7 is used as the input search input by providing a voltage V7 on the word line (WL) of the powered-on transistor and on the inverted word line. A voltage V0 is provided. As shown in the diagram, since V7 is greater than Vt0, a current I7 flows through the upper transistor; however, since V0 is less than Vt7, no current flows through the lower transistor. In other words, because V7 is greater than Vt0, and V0 is not greater than Vt7, the upper transistor is turned on, while the lower transistor is turned off. The current I7 is greater than the current I6 in Example 814 because the voltage V7 is greater than the voltage V6. This means that in Example 816, the mismatch between the input value and the stored value is greater than the mismatch in Example 814. Here, the current is represented as I7, and the current on the source line (SL) is approximately I7, which is approximately 49 times the current I1.

[0098] Figure 9 shows a 2D NOR-based memory arithmetic array 900, which is used to compare input data with stored data and provide the current output representing the Euclidean distance between the input data and the stored data.

[0099] Array 900 includes transistors 902, 904, 906, and 908 in a first NOR row, transistors 910, 912, 914, and 916 in a second NOR row, and transistors 918, 920, 922, and 924 in a third NOR row. Bit line (BL1) 926 is connected to each end of transistors 902, 904, 906, and 908 in the first NOR row, bit line (BL2) 928 is connected to each end of transistors 910, 912, 914, and 916 in the second NOR row, and bit line (BL3) 930 is connected to each end of transistors 918, 920, 922, and 924 in the third NOR row.

[0100] The logical input value (x1) 932 is provided in the form of a 1-bit input query to a pair of character lines in the first pair of NOR columns, namely character line (WL) 934 and the inverted character line (x1). )936. The logical input value (x2)938 is provided as input for searching a pair of character lines in the second pair of NOR columns, namely character line (WL)940 and the inverted character line ( 942. Logic input values ​​(x1)932 and (x2)938 are provided to their respective pairs of word lines, as encoded as shown in Figure 5C. The value stored by a pair of transistors 902 and 904 is represented as (a1)944, and the value stored by a pair of transistors 906 and 908 is represented as (a2)946. The value stored by a pair of transistors 910 and 912 is represented as (b1)948, and the value stored by a pair of transistors 914 and 916 is represented as (b2)950. The value stored by a pair of transistors 918 and 920 is represented as (c1)952, and the value stored by a pair of transistors 922 and 924 is represented as (c2)954. The storage method of each stored value (a1)944, (a2)946, (b1)948, (b2)950, (c1)952 and (c2)954 in their respective transistor pairs is shown in the coding in Figure 5C.

[0101] The output current based on the stored logic value and input search will be provided by the source line (SL1) 956 of the first NOR row. The output current based on the stored logic value and input search will be provided by the source line (SL2) 958 of the second NOR row. The output current based on the stored logic value and input search will be provided by the source line (SL3) 960 of the third NOR row. The output on the source line (SL1) 956 can be expressed as (x1-a1)²+(x2-a2)²+⋯+(xm-am)² (reference element 962), which can represent the Euclidean distance between the inputs x1, x2, …Xm and the stored data a1, a2, …am. The output on source line (SL2) 958 can be expressed as (x1-b1)²+(x2-b2)²+⋯+(xm-bm)² (reference element 964), which represents the Euclidean distance between the inputs x1, x2, …Xm and the stored data b1, b2, …bm. The output on source line (SL3) 960 can be expressed as (x1-c1)²+(x2-c2)²+⋯+(xm-cm)² (reference element 966), which represents the Euclidean distance between the inputs x1, x2, …Xm and the stored data c1, c2, …cm.

[0102] As previously mentioned, logic values ​​are stored in bit lines along the row direction, while input searches are received across word lines. The Euclidean distance between the input search and the stored value can be determined by detecting the values ​​on different source lines. If a common source line (CSL) connects all source lines, the current detected by switching between different bit lines (e.g., sequentially switching to different bit lines) can be used to determine the Euclidean distance between the input search (e.g., x1) and the data stored across lines (e.g., stored data (a1) 944, followed by stored data (b1) 948, and then stored data (c1) 952). If array 900 has individual source lines (e.g., without a CSL), the currents of the source lines (SL) can be detected in parallel. For example, the results of comparing (x1)932 with (a1)944, comparing (x1)932 with (b1)948, and comparing (x1)932 with (c1)952 can be provided in parallel to (SL1)956, (SL2)958, and (SL3)960 by simultaneously switching (BL1)926, (BL2)928, and (BL3)930.

[0103] The elements in Figure 9 are merely examples of this disclosure, which can also be implemented as a two-dimensional NOR array with more rows, columns and elements.

[0104] Figure 10 illustrates a two-dimensional NOR flash memory architecture 1000, in which a search character is input to each character line, the search character is compared with the stored data characters stored in the line, and the Euclidean distance technique is applied to determine the distance between the search character and the stored data characters.

[0105] Specifically, the two-dimensional NOR flash memory architecture 1000 includes transistors 1002, 1004, 1006, and 1008 in a first row, which have endpoints connected to bit line (BL1) 1026. The two-dimensional NOR flash memory architecture 1000 also includes transistors 1010, 1012, 1014, and 1016 in a second row, which have endpoints connected to bit line (BL2) 1028. The two-dimensional NOR flash memory architecture 1000 also includes transistors 1018, 1020, 1022, and 1024 in a third row, which have endpoints connected to bit line (BL3) 1030. In this embodiment, data word 1032 can be stored by transistors 1002, 1004, 1006, and 1008 in the first row. In this embodiment, a pair of transistors 1002 and 1006 can be used to store the first logic value of data word 1032, while a pair of transistors 1004 and 1008 can be used to store the second logic value of data word 1032. In other words, a pair of transistors 1002 and 1006 can store a logic value of 1 bit, while a pair of transistors 1004 and 1008 can store another logic value of 1 bit.

[0106] A 1-bit input search can be provided to a pair of transistors 1002 and 1006, indicating a search for a portion of character 1034. Another 1-bit input search can be provided to another pair of transistors 1004 and 1008, indicating a search for another portion of character 1034. For example, the entire input search or the search for character 1034 can be performed on character line (WL1) 1036, character line (WL2) 1038, and the inverted character line (WL1). )1040 and inverted character line ( Received on 1042. Logic input values ​​are provided to their respective character line pairs (such as character line (WL1) 1036 and inverted character line (WL1) 1042). The search character 1034 is compared with the data character 1032, and the result provides current to the common source line (CSL) 1044. Assuming bit line (BL1) 1026 is on while bit line (BL2) 1028 and bit line (BL3) 1030 are off, this current can be determined by using the techniques of this disclosure to determine the Euclidean distance between the search character 1034 and the data character 1032. The character lines and inverted character lines can be located in adjacent columns, as shown in Figure 9, or in non-adjacent columns, as shown in Figure 10. In the embodiments provided in this disclosure, the character lines and inverted character lines can be adjusted to be adjacent or non-adjacent.

[0107] The elements in Figure 10 are merely examples of this disclosure, which can also be implemented as a two-dimensional NOR array with more rows, columns, and elements.

[0108] Figure 11 shows the 2T-NOR flash memory architecture 1100. According to this architecture, a search character is input on each MG line to compare the search character with the stored data character stored in a row. Furthermore, according to this architecture, Euclidean distance technology can be applied to determine the distance between the search character and the stored data character.

[0109] Specifically, the 2T-NOR flash memory architecture 1100 includes pairs of transistors in the first row, such as transistors 1102 and 1104, transistors 1106 and 1108, transistors 1110 and 1112, and transistors 1114 and 1116. The transistors in the first row are connected to bit lines (BL1) 1150.

[0110] The 2T-NOR flash memory architecture 1100 includes pairs of transistors in the second row, such as transistors 1118 and 1120, transistors 1122 and 1124, transistors 1126 and 1128, and transistors 1130 and 1132. The transistors in the second row are connected to bit line (BL2) 1152.

[0111] The 2T-NOR flash memory architecture 1100 also includes pairs of transistors in the third row, such as transistors 1134 and 1136, transistors 1138 and 1140, transistors 1142 and 1144, and transistors 1146 and 1148. The transistors in the third row are connected to bit line (BL3) 1154.

[0112] Select gate line (SG1) 1156 is connected to transistors 1104, 1120, and 1136 in the column; select gate line (SG2) 1158 is connected to transistors 1108, 1124, and 1140 in the column; inverse select gate line (SG2) 1158 is connected to transistors 1108, 1124, and 1140 in the column. )1160 is connected to transistors 1112, 1128, and 1144 in the column, anti-selection gate line ( )1162 is connected to transistors 1116, 1132, and 1148 in the column. Select gate line (SG1) 1156, select gate line (SG2) 1158, inverse select gate line (SG1) 1156, inverse ... )1160 and anti-selection gate line ( )1162 is used to enable or disable the search on the corresponding column by turning on or off the transistor connected to it.

[0113] The main gate line (MG1) 1166 is connected to transistors 1102, 1118, and 1134 in the column; the main gate line (MG2) 1168 is connected to transistors 1106, 1122, and 1138 in the column; the reverse main gate line ( )1170 is connected to transistors 1110, 1126, and 1142 in the column, reverse main gate line ( )1172 is connected to transistors 1114, 1130, and 1146 in the column. Main gate line (MG1) 1166, main gate line (MG2) 1168, reverse main gate line ( )1170 and reverse main gate pole line ( 1172 is used to provide the search character 1165 to one or more selected rows of transistors. For example, the data character 1164 may be stored in the first row (e.g., stored in transistors 1102, 1106, 1110, and 1114). The select gate and inverse select gate lines can be turned on to enable the search for each column. Similar to Figures 9 and 10, a 1-bit input search can be provided to a pair of transistors 1102 and 1110 to represent a portion of the search character 1165, while a 1-bit input search can be provided to another pair of transistors 1106 and 1114 to represent another portion of the search character 1165. A logic value of the search character 1165 can be provided to the main gate line 1166 (MG1) and the inverse main gate line (MG1). )1170, while another logic value for search character 1165 can be provided to the main gate pole (MG2) 1168 and the reverse main gate pole ( )1172. Logic input values ​​are provided to their respective main gate pole pairs (e.g., main gate pole (MG1) 1166 and reverse main gate pole (MG1) 1172. (1170), can be encoded as shown in Figure 5C. In other embodiments, it can also be implemented with other configurations to input logic values. The output current on the current source line (CSL) 1174 can be used to determine the Euclidean distance between the search character 1165 and the data character 1164, assuming that bit line (BL1) 1150 is on and bit line (BL2) 1152 and bit line (BL3) 1154 are off, the techniques described in this disclosure can be used.

[0114] The components in Figure 11 are merely examples of this disclosure, which can also be implemented as a 2T-NOR flash memory architecture with more rows, columns, and components.

[0115] Figure 12 shows the architecture of a split-gate NOR flash memory. According to this architecture, a search character is input on each MG line to compare the search character with the stored data character stored in a row. Furthermore, Euclidean distance technology can be applied to determine the distance between the search character and the stored data character based on this architecture.

[0116] Specifically, the split-gate NOR flash memory architecture 1200 includes split-gate transistors 1202, 1204, 1206, and 1208 in the first row, which are connected to bit line (BL1) 1226. The split-gate NOR flash memory architecture 1200 also includes split-gate transistors 1210, 1212, 1214, and 1216 in the second row, which are connected to bit line (BL2) 1228. The split-gate NOR flash memory architecture 1200 also includes split-gate transistors 1218, 1220, 1222, and 1224 in the third row, which are connected to bit line (BL3) 1230. Each split-gate transistor (e.g., 1202, 1204, 1206, 1208, 1210, 1212, 1214, 1216, 1218, 1220, 1222, and 1224) contains two gates (e.g., a primary gate, such as a floating gate, for data storage, and a selection gate).

[0117] Select gate line (SG1) 1232 is connected to the select gate of transistors 1202, 1210, and 1218 in the column. Select gate line (SG2) 1234 is connected to the select gate of transistors 1204, 1212, and 1220 in the column. Inverse select gate line ( Line 1236 is connected to the select gate of transistors 1206, 1214 and 1222 in the column, and the anti-select gate line ( )1238 is connected to the select gate of transistors 1208, 1216, and 1224 in the column. Select gate line 1232 (SG1), select gate line (SG2), 1234, and anti-select gate line ( Lines 1236 and inverse selection gate lines ( The 1238 series is used to enable or disable the search on the corresponding column by turning on or off the selective gate of the transistor connected to it.

[0118] The main gate line (MG1) 1244 is connected to the main gate of transistors 1202, 1210, and 1218 in the column; the main gate line (MG2) 1246 is connected to the main gate of transistors 1204, 1212, and 1220 in the column; the reverse main gate line ( )1248 is connected to the main gate of transistors 1206, 1214 and 1222 in the column, and the reverse main gate line ( )1250 is connected to the main gate of transistors 1208, 1216, and 1224 in the column. Main gate line 1244 (MG1), main gate line (MG2), 1246, and reverse main gate line ( )1248 and reverse main gate pole line ( 1250 is used to provide the search character 1242 to one or more selected rows of transistors. For example, the data character 1240 may be stored in the first row (e.g., stored in transistors 1202, 1204, 1206, and 1208). The select gate and inverse select gate lines can be turned on to enable searching in each of the four columns. Similar to Figures 9-11, a 1-bit input search may be provided to a pair of transistors 1202 and 1206 to represent a portion of the search character 1242, while a 1-bit input search may be provided to another pair of transistors 1204 and 1208 to represent another portion of the search character 1242. A logic value of the search character 1242 may be provided to the main gate line (MG1) 1244 and the inverse main gate line (MG1). )1248, and another logic value for search character 1242 can provide access to the main gate pole (MG2) 1246 and the reverse main gate pole ( )1250. Logic input values ​​are provided to their respective pairs of master gate poles (e.g., master gate pole (MG1) 1244 and reverse master gate pole (MG1) 1250. (1248), can be encoded as shown in Figure 5C. Alternatively, it can be implemented in other configurations to input logic values. The output current on the current source line (CSL) 1252 can be used to determine / determine the Euclidean distance between the search character 1242 and the data character 1240, assuming bit line (BL1) 1226 is on and bit line (BL2) 1228 and bit line (BL3) 1230 are off, the techniques described in this disclosure can be used.

[0119] The components in Figure 12 are merely examples of this disclosure, which can also be implemented as a discrete-gate NOR flash memory architecture with more rows, columns, and components.

[0120] Figure 13 shows a two-dimensional NOR flash memory architecture 1300. According to this architecture, two search characters are input on each character line to compare the two search characters with two stored data characters stored in a row. Furthermore, Euclidean distance technology can be applied to determine the distance between the search characters and the stored data characters based on this architecture.

[0121] Specifically, the two-dimensional NOR flash memory architecture 1300 includes transistors 1302, 1304, 1306, and 1308 in a first row, each having an endpoint connected to bit line (BL1) 1326. The two-dimensional NOR flash memory architecture 1300 also includes transistors 1310, 1312, 1314, and 1316 in a second row, each having an endpoint connected to bit line (BL2) 1328. The two-dimensional NOR flash memory architecture 1300 also includes transistors 1318, 1320, 1322, and 1324 in a third row, each having an endpoint connected to bit line (BL3) 1330. In this embodiment, data word (DWA) 1332 may be stored by transistors 1302 and 1304 in the first row, while data word (DWB) 1334 may be stored by transistors 1306 and 1308.

[0122] Enter the search term 1336, which can be obtained from the character line (WL1) 1338 and the inverted character line ( )1340 receives, while the input search or search character '1342' can be obtained by character line (WL2) 1344 and inverted character line ( )1346 receives. Similar to Figures 9-12, search character 1336 can represent a 1-bit input search (logic value), which can be provided to a pair of transistors 1302 and 1304; search character '1342 can represent a 1-bit input search (logic value), which can be provided to a pair of transistors 1306 and 1308. Logic input values ​​(representing 1-bit input searches) are provided to their respective character line pairs (e.g., character line (WL1) 1338 and inverted character line (WL1) 1338). (1340), can be performed according to the coding shown in Figure 5C.

[0123] The result of comparing search character 1336 with data character (DWA) 1332 will provide a current on common source line (CSL) 1348, which can be used to determine the Euclidean distance between search character 1336 and data character (DWA) 1332 using the techniques described herein. Similarly, the result of comparing search character 1342 with data character (DWB) 1334 will also provide a current on common source line (CSL) 1348, which can be used to determine the Euclidean distance between search character 1342 and data character (DWB) 1334 using the techniques described herein. In this embodiment, a search character (e.g., search character 1336) can be compared with a data character (e.g., data character (DWA) 1332) at a time. Search character 1336 can be entered at a different time point than search character 1342 for searching, thus different search characters can be used at different times. For example, searching for character 1336 can be done using character line (WL1) 1338 and the reverse character line (WL1). )1340 receives, while character line (WL2) 1344 and inverted character line ( )1346 is then turned off, thus the search is performed solely based on search character 1336. In another embodiment, search character '1342 may be composed of character line (WL2) 1344 and inverse character line ( )1346 receives, while character line (WL1) 1338 and inverted character line ( )1340 is turned off, so the search is performed only based on the search character '1342'.

[0124] The components in Figure 13 are merely examples of this disclosure, which can also be implemented as a two-dimensional NOR flash memory architecture with more rows, columns, and components.

[0125] Figure 14 shows the 2T-NOR flash memory architecture 1400. According to this architecture, two search characters are input on each character line to compare the two search characters with two stored data characters stored in a row. According to this architecture, Euclidean distance technology can be applied to determine the distance between the search characters and the stored data characters.

[0126] Specifically, the 2T-NOR flash memory architecture 1400 includes pairs of transistors in the first row, including transistors 1402 and 1404, transistor pairs 1406 and 1408, transistor pairs 1410 and 1412, and transistor pairs 1414 and 1416. The transistors in the first row are connected to bit lines (BL1) 1450.

[0127] The 2T-NOR flash memory architecture 1400 also includes pairs of transistors in the second row, including transistors 1418 and 1420, transistor pairs 1422 and 1424, transistor pairs 1426 and 1428, and transistor pairs 1430 and 1432. The transistors in the second row are connected to bit line (BL2) 1452.

[0128] The 2T-NOR flash memory architecture 1400 also includes pairs of transistors in the third row, including transistors 1434 and 1436, transistor pairs 1438 and 1440, transistor pairs 1442 and 1444, and transistor pairs 1446 and 1448. The transistors in the third row are connected to bit line (BL3) 1454.

[0129] Select gate line (SG1) 1456 is connected to a row of transistors 1404, 1420 and 1436, and anti-select gate line (SG1) 1456 is connected to a row of transistors 1404, 1420 and 1436. )1458 is connected to a row of transistors 1408, 1424 and 1440, selecting the gate line (SG2). 1460 is connected to a row of transistors 1412, 1428 and 1444, deselecting the gate line (SG2). )1462 is connected to a row of transistors 1416, 1432, and 1448. Select gate line (SG1) 1456, anti-select gate line ( )1458, Selective gate line (SG2) 1460 and inverse gate line ( )1462 is used to enable or disable the search on the corresponding column by turning on or off the transistor connected to it.

[0130] The main gate line (MG1) 1470 is connected to a row of transistors 1402, 1418, and 1434, and the reverse main gate line (MG1) 1470 is connected to a row of transistors 1402, 1418, and 1434. )1472 is connected to a row of transistors 1406, 1422 and 1438, the main gate line (MG2) 1476 is connected to a row of transistors 1410, 1426 and 1442, and the reverse main gate line ( )1478 is connected to a row of transistors 1414, 1430, and 1446. Main gate line (MG1) 1470 and reverse main gate line ( )1472 is a transistor used to provide search characters 1468 to one or more selected columns and rows, while the main gate line (MG2) 1476 and the reverse main gate line ( Search character '1478 is used to provide search character '1474 to one or more selected columns and rows of transistors. Similar to Figures 9-13, search character '1468 can represent a 1-bit input search (logic value), which can be provided to a pair of transistors 1402 and 1406, while search character '1474 can represent a 1-bit input lookup search (logic value), which can be provided to a pair of transistors 1410 and 1414. Logic input values ​​(representing 1-bit input searches) are provided to their respective master gate pairs (e.g., character line (WL1) 1470 and inverse master gate line (WL1)). (1472), can be performed according to the coding shown in Figure 5C.

[0131] For example, data character (DWA) 1464 can be stored in the first and second columns of the first row (e.g., stored in transistors 1402 and 1406), while data character (DWB) 1466 can be stored in the third and fourth columns of the first row (e.g., stored in transistors 1410 and 1414). The select gate and deselect gate lines are enabled to allow searching of each of the four columns. Search character 1468 provides access to the main gate (MG1) line 1470 and the deselect gate line (…). )1472, while the search character '1474 can provide access to the main gate pole (MG2) 1476 and the reverse main gate pole ( 1478. The output current on the common source line (CSL) 1480 can be determined using the techniques described in this disclosure, determining the Euclidean distance between search character 1468 and data character (DWA) 1464, and between search character '1474 and data character (DWB) 1466. Search character 1468 and search character '1474 can be entered at different times for searching, thus allowing different search characters to be used for searching at different times.

[0132] The components in Figure 14 are merely examples of this disclosure, which can also be implemented as a 2T-NOR flash memory architecture 1400 with more rows, columns and components.

[0133] Figure 15 shows the discrete gate NOR flash memory architecture 1500. According to this architecture, two search characters are input on each character line to compare the two search characters with two stored data characters stored in a row. According to this architecture, Euclidean distance technology can be applied to determine the distance between the search characters and the stored data characters.

[0134] Specifically, the split-gate NOR flash memory architecture 1500 includes split-gate transistors 1502, 1504, 1506, and 1508 in the first row, which are connected to bit line (BL1) 1526. The split-gate NOR flash memory architecture 1500 also includes split-gate transistors 1510, 1512, 1514, and 1516 in the second row, which are connected to bit line (BL2) 1528. The split-gate NOR flash memory architecture 1500 also includes split-gate transistors 1518, 1520, 1522, and 1524 in the third row, which are connected to bit line (BL3) 1530. Each split-gate transistor (e.g., 1502, 1504, 1506, 1508, 1510, 1512, 1514, 1516, 1518, 1520, 1522, and 1524) contains two gates (e.g., a primary gate, such as a floating gate, for data storage, and a select gate).

[0135] The select gate line (SG1) 1532 is connected to the select gate of a row of transistors 1502, 1510, and 1518, and the anti-select gate line (SG1) 1532 is connected to the select gate of a row of transistors 1502, 1510, and 1518. )1534 is connected to the select gate of a row of transistors 1504, 1512 and 1520, select gate line (SG2) 1536 is connected to the select gate of a row of transistors 1506, 1514 and 1522, anti-select gate line ( )1538 is connected to the select gate of a row of transistors 1508, 1516, and 1524. Select gate line (SG1) 1532, anti-select gate line ( )1534, Selective gate line (SG2) 1536 and inverse gate line ( )1538 is used to enable or disable the search on the corresponding column by turning on or off the selective gate of the transistor connected to it.

[0136] The main gate line (MG1) 1546 is connected to the main gate of a row of transistors 1502, 1150, and 1518. The reverse main gate line ( 1548 is connected to the main gate of a row of transistors 1504, 1512, and 1520. Main gate line (MG2) 1552 is connected to the main gate of a row of transistors 1506, 1514, and 1522. Reverse main gate line (MG2) 1554 is connected to the main gate of a row of transistors 1508, 1516, and 1524. Main gate line (MG1) 1546 and reverse main gate line ( )1548 is used to provide search characters 1544 to one or more selected columns of transistors, while the main gate (MG2) line 1552 and the anti-main gate line ( 1554 is used to provide the search character '1550' to one or more selected columns of transistors. For example, data character (DWA) 1540 can be stored in the first and second columns of the first row (e.g., stored in transistors 1502 and 1204), while data character (DWB) 1542 can be stored in the third and fourth columns of the first row (e.g., stored in transistors 1506 and 1508). The select gate and select gate inversion line can be turned on to enable searching in each of the four columns. Similar to Figures 9-14, a 1-bit input search can be provided to a pair of transistors 1502 and 1504, representing search character 1546. A 1-bit input search can be provided to a pair of transistors 1506 and 1508, representing search character '1550'. The logic value of search character 1544 can be provided to the main gate (MG1) line 1546 and the inversion main gate line (MG1). )1548, while the logic value of the search character '1550' can be provided to the main gate (MG2) line 1552 and the reverse main gate line ( )1554. Logic input values ​​are provided to their respective main gate pole pairs (e.g., main gate pole (MG1) 1546 and reverse main gate pole (MG1) 1554. )1548), as shown in Figure 5C. The output current on the common source line (CSL) 1556 can be determined using the techniques described in this disclosure to determine the Euclidean distance between search character 1544 and data character (DWA) 1540, search character '1550 and data character (DWB) 1542. Search character 1544 and search character '1550 can be entered at different times to allow different search characters to be used for searching at different times. For example, when searching search character 1544, the main gate (MG2) line 1552 and the anti-main gate line ( )1554 will be turned off. In another embodiment, when searching for search character '1550, the main gate line (MG1) 1546 and the reverse main gate line ( )1548 will be shut down.

[0137] The components in Figure 15 are merely examples of this disclosure, which can also be implemented as a discrete-gate NOR flash memory architecture with more rows, columns, and components.

[0138] Figure 16 shows a split-gate NOR flash memory architecture 1600. According to this architecture, two search characters are input on different character lines to compare the two search characters with two stored data characters stored in the same row. According to this architecture, each column in the NOR flash memory architecture is disabled for searching, and Euclidean distance technology can be applied to determine the distance between the search characters and the stored data characters.

[0139] Specifically, the split-gate NOR flash memory architecture 1600 includes a first row of split-gate transistors 1602, 1604, 1606, 1608, 1610, 1612, 1614, and 1616, which are connected to bit line (BL1) 1652. The split-gate NOR flash memory architecture 1600 also includes a second row of split-gate transistors 1618, 1620, 1622, 1624, 1628, 1630, 1632, and 1634, which are connected to bit line (BL2) 1654. The split-gate NOR flash memory architecture 1600 also includes a third row of split-gate transistors 1636, 1638, 1640, 1642, 1644, 1646, 1648, and 1650, which are connected to bit line (BL3) 1656. Each split-gate transistor (e.g., 1602, 1604, 1606, 1608, 1610, 1612, 1614, 1616, 1618, 1620, 1622, 1624, 1628, 1630, 1632, 1634, 1636, 1638, 1640, 1642, 1644, 1646, 1648, and 1650) contains two gates (e.g., a primary gate, such as a floating gate, for data storage, and a selection gate).

[0140] Select gate line (SG1) 1658 connects to the select gates of transistors 1602, 1618, and 1636 in a row. Select gate line (SG2) 1660 connects to the select gates of transistors 1604, 1620, and 1638 in a row. Select gate line (SG3) 1662 connects to the select gates of transistors 1606, 1622, and 1640 in a row. Select gate line (SG4) 1664 connects to the select gates of transistors 1608, 1624, and 1642 in a row. Inverse select gate line (…) The 1666 is connected to the select gate of a row of transistors 1610, 1628, and 1644. The anti-select gate line ( )1668 is connected to the select gate of a row of transistors 1612, 1630, and 1646. The anti-select gate line ( The 1670 is connected to the select gate of a row of transistors 1614, 1632, and 1648. The anti-select gate line ( )1672 is connected to the select gate of a row of transistors 1616, 1634 and 1650.

[0141] The first part of the data characters, containing data character (DWA) 1674, is stored in the main gates of transistors 1602 and 1604 in the first and second columns of the first row. The second part of the data characters, containing data character (DWA) 1676, is stored in the main gates of transistors 1610 and 1612 in the fifth and sixth columns of the first row. The first part of the data characters, containing data character (DWB) 1678, is stored in the main gates of transistors 1606 and 1608 in the third and fourth columns of the first row. The second part of the data characters, containing data character (DWB) 1680, is stored in the main gates of transistors 1614 and 1616 in the seventh and eighth columns of the first row.

[0142] In this embodiment, select gate line (SG1) 1658 and select gate line (SG2) 1660 are turned on to allow the first portion of the search character, namely the search character 1682 provided to the main gate line (MG1) 1684 and the main gate line (MG2) 1686, to be compared with the data character (DWA) 1674. Furthermore, the inverse select gate line (SG1) 1658 is also turned on. )1666 and anti-selection gate line ( )1668 is turned on to allow the search for the second part of the character, which contains the part provided to the reverse main gate pole line ( )1688 and reverse main gate pole line ( The search character 1683 of 1690 is used to compare the second part with the data character (DWA) 1676.

[0143] Furthermore, in this embodiment, the select gate line (SG3) 1662 and select gate line (SG4) 1664 are turned off, therefore the data provided through the main gate line (MG3) 1692 and main gate line (MG4) 1694 will not be compared with the data character (DWB) 1678. Similarly, the inverse select gate line ( Line 1670 and the anti-selection gate line ( Line 1672 is closed, therefore through the reverse main gate line ( )1696 and reverse main gate pole line ( The information provided by 1698 will not be compared with the data characters (DWB) 1680.

[0144] Similar to Figures 9-15, a 1-bit input search can be provided to a pair of transistors 1602 and 1610 to represent a portion of search characters 1682 and 1683. A 1-bit input search can be provided to a pair of transistors 1604 and 1612 to represent the remaining portions of search characters 1682 and 1683. In other embodiments, this concept can be implemented in other memories in Figures 9-15, where a 1-bit input search can be provided to a transistor 1602 and 1604 to represent search character 1682. A 1-bit input search can be provided to a pair of transistors 1610 and 1612 to represent search character 1683. Logic input values ​​are provided to their respective master gate pairs (e.g., master gate (MG1) and anti-master gate (MG2)). This can be done according to the coding shown in Figure 5C.

[0145] The output current generated by comparing search character 1682 with data character (DWA) 1674 and by comparing search character 1683 with data character (DWA) 1676 is provided to the common source line (CSL) 1699. This current is used to determine the Euclidean distance between search characters 1682 and 1683, and between data characters (DWA) 1674 and 1676, specifically the sum of the Euclidean distances between search characters 1682 and 1674, and between search characters 1683 and 1676.

[0146] Using this architecture, multiple data characters can be stored in a single bit line (BL) (e.g., stored in a single row). The select gate line, inverse select gate line, master gate line, and inverse master gate line of unused columns can be turned off (e.g., biasing the unused select gate line and inverse select gate line to 0V, and biasing the unused master gate line and inverse master gate line to less than or equal to 0V).

[0147] The components in Figure 16 are merely examples of this disclosure, which can also be implemented as a discrete-gate NOR flash memory architecture with more rows, columns, and components.

[0148] Figure 17 shows a three-dimensional NOR flash memory architecture 1700. According to this architecture, a search character is input on each character line of a row of transistors in a block to compare the search character with the stored data characters stored in the columns of transistors in that block. According to this architecture, Euclidean distance technology can be applied to determine the distance between the search character and the stored data characters.

[0149] Specifically, the three-dimensional NOR flash memory architecture 1700 includes blocks in multiple rows. Transistors 1702, 1704, and 1706 are used to store data words 1730, and further include bit lines (BL1) 1708, bit lines (BL2) 1710, bit lines (BL3) 1712, source lines (SL1) 1714, source lines (SL2) 1716, source lines (SL3) 1718, word lines (WL1m) 1720, word lines (WL1m-1) 1722, word lines (WL11) 1724, word lines (WLkm) 1726, and word lines (WLkm-1) 1728. Search character 1732 can be provided as (input m) 1734, (input m-1) 1736, and (input 1) 1738 to character line (WL1m) 1720, character line (WL1m-1) 1722, and character line (WL11) 1724, respectively. The same or similar concepts described above in relation to Figures 10-16 also apply to Figure 17, namely, using stored data to represent logical values ​​and using input search to perform searches to represent logical values.

[0150] According to this implementation, the input search (e.g., search character 1732) is provided to multiple character lines on a single block, where one data character 1730 is stored in the bit line (BL1) 1708 of the single block, and the block select transistor sharing the same bit line in unused data blocks will be turned off, or the character line of an unused block will be turned off.

[0151] The components in Figure 17 are merely examples of this disclosure, which can also be implemented as a three-dimensional NOR flash memory architecture with more rows, columns, and components.

[0152] Figure 18 shows a three-dimensional NOR flash memory architecture. According to this architecture, a search character is input on a character line of each different block to compare the search character with the stored data character stored on a character line of each different block. According to this architecture, Euclidean distance technology can be applied to determine the distance between the search character and the stored data character.

[0153] Specifically, the three-dimensional NOR flash memory architecture 1800 includes multiple blocks, with transistors 1802 and 1804 spanning these blocks and used to store data words 1828. The flash memory architecture 1800 also includes bit lines (BL1) 1806, (BL2) 1808, (BL3) 1810, source lines (SL1) 1812, (SL2) 1814, (SL3) 1816, word lines (WL1m) 1818, (WL1m-1) 1820, (WL11) 1822, (WLkm) 1824, and (WLkm-1) 1826. Search character 1830 can be provided to character line (WLKm) 1824 via character line (WL1m) 1818 as "input k" 1832, "input k-1" 1834, and "input 1" 1836. The same or similar concepts described in the content related to Figures 10-16 above also apply to Figure 18, namely, using stored data to represent logical values ​​and using input search to search to represent logical values.

[0154] According to this implementation, the input search (e.g., search character 1830) is provided to a character line in each different block, where the bit line (BL3) 1810 of each different block stores a data character 1828. Character lines in unused layers can be turned off, and character lines in unused blocks can also be turned off.

[0155] The components in Figure 18 are merely examples of this disclosure, which can also be implemented as a three-dimensional NOR flash memory architecture with more rows, columns, and components.

[0156] Figure 19 shows a three-dimensional NOR flash memory architecture. According to this architecture, a search character is input on multiple character lines in each different block to compare the search character with the stored data characters stored on multiple character lines in each different block. According to this architecture, Euclidean distance technology can be applied to determine the distance between the search character and the stored data characters.

[0157] Specifically, the 3D NOR flash memory architecture 1900 includes multiple blocks and multiple layers, with transistors 1902, 1904, 1906, and 1908 spanning multiple blocks and layers to store data words 1934. The flash memory architecture 1900 also includes bit lines (BL1) 1912, (BL2) 1914, (BL3) 1916, source lines (SL1) 1918, (SL2) 1920, (SL3) 1922, word lines (WL1m) 1928, (WL1m-1) 1930, (WL11) 1932, (WLkm) 1924, and (WLkm-1) 1926. The search character 1936 is provided as input from multiple layers of multiple blocks to character line 1938. The same or similar concepts described in the foregoing content related to Figures 10-16 also apply to Figure 19, namely, using stored data to represent logical values ​​and using input search to search for logical values.

[0158] According to this implementation, input search (e.g., search character 1936) can provide multiple character lines to multiple blocks, where one character line in each different block can be used to store a data character 1934. Character lines in unused layers can be turned off, and character lines in used blocks can also be turned off.

[0159] The components in Figure 19 are merely examples of this disclosure, which can also be implemented as a three-dimensional NOR flash memory architecture with more rows, columns, and components.

[0160] The technology described herein can be applied to various types of memory, including at least MOSFET transistors, FinFET transistors, and TFET transistors. Furthermore, this technology can be implemented in at least floating gate flash memory, SONOS flash memory, floating dot flash memory, NOR flash memory, NAND flash memory, split-gate NOR flash memory, 2T NOR flash memory, and dual-transistor zero-capacitance (2T0C) devices.

[0161] Figure 20 shows a simplified schematic diagram of a storage system, including memory that uses an IMS to search for character sequences in order to implement the various Euclidean distance techniques described in this disclosure.

[0162] Figure 20 is a simplified schematic diagram of a chip. The memory system 2100 includes a memory array 2160, such as a two-dimensional or three-dimensional NOR flash memory. The memory system 2100 is configured to perform various memory operations, including page programming, programming, reading, clearing, or other operations applied to the NOR flash memory, as well as IMS operations. The various parts of the memory system 2100 can be implemented as a single integrated circuit chip, or separately in multiple chip modules, or implemented on multiple chips for specific needs. Other parts of the memory system 2100 (e.g., configuration circuitry 2102) can be implemented independently.

[0163] In this embodiment, the memory system 2100 includes a controller 2110. The controller 2110 includes control circuitry for memory operations in memory mode, such as state machines or other logic circuitry. The IMS operation in IMS mode includes a sequencer supporting consecutive matching operations. The controller 2110 may include or access control registers storing device operating parameters, including a threshold register 2111 for storing parameters that set other values, such as ΔV, as previously described. The controller 2110 can be used to implement the aforementioned Euclidean distance technique.

[0164] Memory array 2160 may include floating gate memory cells or dielectric charge trapping memory cells. Each of these cells is used to store multiple bits by establishing multiple programming levels corresponding to the amount of charge stored, i.e., establishing a threshold voltage Vt for the memory cell. In various embodiments, memory system 2100 may include single-layer memory cells (SLC), multi-layer memory cells, or other memory structures described herein, capable of storing more than one bit in each cell (e.g., MLC, TLC, or XLC).

[0165] In other embodiments, the memory cell may include programmable resistance memory cells, ferroelectric memory cells, phase change memory cells, and other types of non-volatile and volatile memory cell technologies.

[0166] The memory system 2100 includes a set of bit lines 2165, which are connected to corresponding sets of memory cells in the memory array 2160.

[0167] A set of character lines 2145 are connected to the gates of memory cells in memory array 2160. Character line decoder 2140 and search character buffer 2141 are connected to the set of character lines 2145 and are used to drive the operating voltage required for read and write operations in response to address decoding, and to perform IMS operation in response to an input search character in search character buffer 2141.

[0168] Page buffer 2170 is connected to bit line 2165 and coupled to cache register 2190. Page buffer 2170 may include a set of latches or other types of storage elements for read / write operations (e.g., programming, clearing) and IMS operations. During memory storage operations, input and output data can be provided through cache register 2190 and across line 2135. Page buffer 2170 may be disposed on integrated circuitry, with its latches adjacent to and operatively connected to logic circuitry used for in-memory operations. Page buffer 2170 includes in-memory match accumulator logic 2175, which uses one or more latches also applied to in-memory operations to implement the function of an in-memory match accumulator. In some embodiments, the logic circuitry of in-memory match accumulator 2175 is disposed within the page buffer and is also used for other memory operations, such as selecting a state during programming operations or clearing data after verifying programming.

[0169] The address on bus 2130 is transferred from controller 2110 to page buffer 2170 and word line decoder 2140.

[0170] In IMS mode, cache 2190 can be used to temporarily store matching results, such as stored characters matched by similarity, and metadata of stored characters related to IMS operations. Furthermore, logic circuitry can be connected to the cache and located in the data path between cache 2190 and page buffer 2170 to perform logic operations using the IMS operation results stored in the cache.

[0171] In the embodiment shown in Figure 20, the controller 2110 uses a bias arrangement state machine 2120 to control the supply voltage generated or provided by the voltage supply of a specific block for application to read and write (programming, clearing) operations in IMS operation and storage modes.

[0172] The controller 2110 may be implemented using special-purpose logic circuitry known in the art. In other embodiments, the control logic includes a general-purpose processor, which may be implemented on the same integrated circuit to execute computer programs to control device operation. In other embodiments, the control logic may be implemented using a combination of special-purpose logic circuitry and a general-purpose processor.

[0173] Configuration circuitry 2102 may include a general-purpose processor, a special-purpose processor, a processor configured as a memory controller, or other processor using memory device 2100. All or part of configuration circuitry 2102 may be implemented on the same integrated circuit as the memory. In one example of a system, configuration circuitry 2102 may include a digital processing system that includes a memory controller to interface with memory system 2100, and may also be a system that includes DRAM and GPU circuitry to perform further computational functions.

[0174] Configuration circuit 2102 can be connected to other control terminals not shown in the figure, such as chip selection terminals, and can provide instructions or commands to system 2100.

[0175] Configuration circuit 2102 may include one or more file systems. The file systems perform actions such as storing, retrieving, and updating data stored in memory according to requests from applications. Generally, configuration circuit 2102 may include programs that perform memory management functions, as well as other functions capable of generating status information about data stored in memory. Furthermore, configuration circuit 2102 may also include applications, file systems, flash translation layer programs, and other components capable of generating data status information.

[0176] The control logic in controller 2110 is used to perform: (i) programming the memory device to store stored data based on one or more threshold voltages; (ii) providing one or more search voltages to the memory device based on input data; and (iii) determining the similarity level between the stored data and the input data based on the output current from the memory device, wherein the output current is used to represent the Euclidean distance between the stored logic value representing the stored data and the input logic value representing the input data. Furthermore, memory controller 2110 can be configured to store one of n logic values ​​as the stored logic value represented by the data stored in each cell of the memory device, where n is a positive integer and can be 1 to 15 or more.

[0177] Furthermore, the control logic in configuration circuit 2102 can also determine / determine a reference threshold voltage (Vt), based on which the memory controller can perform the following operations: (i) programming the memory device using one or more programming voltages to set one or more threshold voltages; and (ii) providing the one or more search voltages, wherein the reference threshold voltage is determined to make the Euclidean distance between the output current, the stored logic value, and the input logic value. Furthermore, the control logic for determining the reference threshold voltage (Vt) may include the following operations: determining the peak value of Vg, which is aligned with the peak point of the calculated partial derivative curve; determining... The point on the curve relating the gate voltage (Vg) to the peak value of the determined Vg is calculated; The tangent line on the curve relating the gate voltage (Vg) to that point, where the slope of the tangent line is defined by the peak point of the calculated partial derivative curve; the ideal reference threshold voltage Vt value is determined, which corresponds to the point on the calculated tangent line at that point. =0 is a point. The reference threshold voltage (Vt) can be determined based on the extracted reference threshold voltage Vt, which is calculated by applying the ideal reference threshold voltage Vt to a group of memory cells in the memory device. The method of determining the extracted reference threshold voltage Vt includes the following operations: determining the actual median drain current Id of a group of memory cells in the memory device at the determined ideal voltage Vt, and defining the median drain current Id as the current Ith; determining the extracted reference threshold voltage Vt from the confirmed relationship curve between the drain current Id and the gate voltage (Vg), and using the extracted reference threshold voltage Vt as the voltage corresponding to the current Id in the relationship curve. Accordingly, the extracted reference threshold voltage Vt will be an adjusted version of the ideal voltage Vt, which is adjusted according to the actual performance differences between a group of memory cells. The configuration circuit 2102 also configures logic to set the ΔV voltage value. Based on the ΔV voltage value, the reference threshold voltage (Vt) can be adjusted to store different logic values ​​among n logic values. The configuration circuit 2102 also includes logic for minimizing the error of the Euclidean distance by defining an adjustment current Iref, wherein the Euclidean distance is calculated from the stored logic value and the input value, and the adjustment current Iref is used to divide the output current, for example through an analog current divider.

[0178] Other embodiments of the methods described in this disclosure may include a non-transitory computer-readable storage medium containing instructions that can be executed by a processor to perform the aforementioned methods. Other implementations of this disclosure may also include a system comprising memory and one or more processors capable of executing instructions stored in the memory to perform the aforementioned methods.

[0179] Any of the aforementioned data structures and encodings, implemented in various ways, can be stored in a computer-readable storage medium. A computer-readable storage medium can be any device or medium capable of storing program code and / or data for use by a computer system, including but not limited to: volatile memory, non-volatile memory, application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), magnetic and optical storage devices such as magnetic disk drives, magnetic tapes, CDs, DVDs, and other media now known or to be developed in the future capable of storing computer-readable media.

[0180] While this disclosure is based on the foregoing embodiments and examples, it should be understood that these embodiments are illustrative only and not restrictive. Those skilled in the art can naturally make modifications and combinations that conform to the spirit of this disclosure and the scope of the claims.

[0181] 100: Two-dimensional search memory 110: Data 111: Encoded Data 120: Search 140: Encoding 150: Memory Array 160: Data Encoder 170: Search Encoder 171: String selection line 172: Character Line 180: Bit line 182: Source line 184: Common source line 200: 3D Search Memory 210: Data 211: Encoded Data 220: Search 240: Encoding 250: Memory Array 260: Data Encoder 270: Search Encoder 271: String selection line 280: Bit line 282: Source Line 284: Common source line 299: Two-dimensional memory array 300: Relationship Diagram 302: Curve 304: Relationship Diagram 306: Curve 308: Curve 310: Relationship Diagram 312: Curve 314: Relationship Diagram 316: Curve 400: Relationship Diagram 402: Curve 404: Curve 406: Vertical dashed line 408: Voltage 409: points 410: Tangent 412: Intersection 416: Curve 418: points 420: Vertical dashed line 422: Line 424: Vertical line 426: points 428: Relationship Diagram 430: Curve 432: Curve 434: Curve 436: Curve 438: Curve 500: MCAM circuit 502: Transistor 504: Bitline 506: Transistor 508: Bitline 510: Bit line 512: Source Line 514: Table 516: Table 600: Form 700: Relationship Diagram 802: Example 804: Example 806: Example 808: Example 810: Example 812: Example 814: Example 816: Example 900: Array 902: Transistor 904: Transistor 906: Transistor 908: Transistor 910: Transistor 912: Transistor 914: Transistor 916: Transistor 918: Transistor 920: Transistor 922: Transistor 924: Transistor 926: Bitline 928: Bitline 930: Bitline 932: Logical Input Value 934: Character Line 936: Inverted character line 938: Logical Input Value 940: Character Line 942: Inverted character line 944: Stored Value 946: Stored Value 948: Stored Value 950: Stored value 952: Stored Value 954: Stored Value 1000: Flash Memory Architecture 1002: Transistor 1004: Transistor 1006: Transistor 1008: Transistor 1010: Transistor 1012: Transistor 1014: Transistor 1016: Transistor 1018: Transistor 1020: Transistor 1022: Transistor 1024: Transistor 1034: Search Characters 1036: Character Line 1038: Character Line 1040: Inverted character line 1042: Inverted character line 1100: Flash Memory Architecture 1102: Transistor 1104: Transistor 1106: Transistor 1108: Transistor 1110: Transistor 1112: Transistor 1114: Transistor 1116: Transistor 1118: Transistor 1120: Transistor 1122: Transistor 1124: Transistor 1126: Transistor 1128: Transistor 1130: Transistor 1132: Transistor 1134: Transistor 1136: Transistor 1138: Transistor 1140: Transistor 1142: Transistor 1144: Transistor 1146: Transistor 1148: Transistor 1150: Bit line 1152: Bitline 1154: Bitline 1156: Select gate line 1158: Select gate line 1160: Inverse Selection Gate Line 1162: Inverse Selection Gate Line 1166: Main gate pole line 1168: Main gate pole line 1170: Reverse main gate pole line 1172: Reverse main gate pole line 1174: Current source line 1200: Flash Memory Architecture 1202: Transistor 1204: Transistor 1206: Transistor 1208: Transistor 1210: Transistor 1212: Transistor 1214: Transistor 1216: Transistor 1218: Transistor 1220: Transistor 1222: Transistor 1224: Transistor 1226: Bitline 1228: Bitline 1230: Bitline 1232: Select gate line 1234: Select gate line 1236: Inverse Selection Gate Line 1238: Inverse Selection Gate Line 1242: Search Characters 1244: Main gate pole line 1246: Main gate pole line 1248: Reverse main gate pole line 1250: Reverse main gate pole line 1252: Current source line 1300: Flash Memory Architecture 1302: Transistor 1304: Transistor 1306: Transistor 1308: Transistor 1310: Transistor 1312: Transistor 1314: Transistor 1316: Transistor 1318: Transistor 1320: Transistor 1322: Transistor 1324: Transistor 1326: Bitline 1328: Bitline 1330: Bitline 1332: Data Characters 1334: Data Characters 1336: Search Characters 1338: Character Line 1340: Inverted character line 1342: Search character' 1344: Character Line 1346: Inverted character line 1348: Common source line 1400: Flash Memory Architecture 1402: Transistor 1404: Transistor 1406: Transistor 1408: Transistor 1410: Transistor 1412: Transistor 1414: Transistor 1416: Transistor 1418: Transistor 1420: Transistor 1422: Transistor 1424: Transistor 1426: Transistor 1428: Transistor 1430: Transistor 1432: Transistor 1434: Transistor 1436: Transistor 1438: Transistor 1440: Transistor 1442: Transistor 1444: Transistor 1450: Bitline 1452: Bitline 1454: Bitline 1456: Select gate line 1458: Select gate line 1460: Inverse Selection Gate Line 1462: Inverse Selection Gate Line 1464: Data Characters 1468: Search Characters 1470: Main gate pole line 1472: Reverse main gate pole line 1474: Search character' 1476: Main gate pole line 1478: Reverse main gate pole line 1500: Flash Memory Architecture 1502: Transistor 1504: Transistor 1506: Transistor 1508: Transistor 1510: Transistor 1512: Transistor 1514: Transistor 1516: Transistor 1518: Transistor 1520: Transistor 1522: Transistor 1524: Transistor 1526: Bitline 1528: Bitline 1530: Bitline 1532: Select gate line 1534: Inverse Selection Gate Line 1536: Select gate line 1538: Inverse Selection Gate Line 1540: Data Characters 1542: Data Characters 1546: Main gate pole line 1548: Reverse main gate pole line 1550: Search character' 1552: Main gate pole line 1554: Reverse main gate pole line 1600: Flash Memory Architecture 1602: Transistor 1604: Transistor 1606: Transistor 1608: Transistor 1610: Transistor 1612: Transistor 1614: Transistor 1616: Transistor 1618: Transistor 1620: Transistor 1622: Transistor 1624: Transistor 1626: Transistor 1628: Transistor 1630: Transistor 1632: Transistor 1634: Transistor 1636: Transistor 1638: Transistor 1640: Transistor 1642: Transistor 1644: Transistor 1646: Transistor 1648: Transistor 1650: Transistor 1652: Bitline 1654: Bitline 1656: Bitline 1658: Selecting the gate line 1660: Select gate line 1662: Select gate line 1664: Selecting the gate line 1666: Inverse Selection Gate Line 1668: Inverse Selection Gate Line 1670: Inverse Selection Gate Line 1672: Inverse Selection Gate Line 1674: Data Characters 1676: Data Characters 1678: Data Characters 1680: Data Characters 1684: Main gate pole line 1686: Main gate pole line 1688: Reverse main gate pole line 1690: Reverse main gate pole line 1699: Common source line 1700: Flash Memory Architecture 1702: Transistor 1704: Transistor 1706: Transistor 1708: Bitline 1710: Bitline 1712: Source Line 1714: Source Line 1716: Source Line 1718: Bitline 1720: Bitline 1722: Bitline 1724: Bitline 1726: Bitline 1728: Bitline 1730: Data Characters 1732: Search Characters 1800: Flash Memory Architecture 1806: Bitline 1808: Bitline 1810: Bitline 1812: Bitline 1814: Bitline 1816: Bitline 1818: Bitline 1820: Bitline 1822: Bitline 1824: Bitline 1826: Bitline 1828: Data Characters 1830: Search Characters 1832: Input k 1834: Input k-1 1836: Input 1 1900: Flash Memory Architecture 1902: Transistor 1904: Transistor 1906: Transistor 1908: Transistor 1912: Bitline 1912: Bitline 1914: Bitline 1916: Bitline 1918: Source Line 1920: Source Line 1922: Source Line 1924: Source Line 1926: Source Line 1928: Source Line 1932: Source Line 1934: Data Characters 1936: Search Characters 2100: System 2102: Configuration Circuit 2110: Controller 2111: Threshold register 2120: Biased Arrangement State Machine 2130: Busbar 2135: Route 2140: Character Line Decoder 2141: Search Character Buffer 2145: Character Line 2160: Memory Array 2165: Bitline 2170: Page Buffer 2175: Memory Matching Accumulator 2190: Cache register

[0182] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A memory system comprising: a memory device for storing data for searching within the memory; a memory controller having logic to perform: (i) programming the memory device to store stored data according to one or more programming voltages; (ii) providing one or more search voltages to the memory device according to input data; and (iii) determining a similarity between the stored data and the input data based on an output current from the memory device, wherein the output current represents an Euclidean distance between a stored logic value representing the stored data and an input logic value representing the input data; and a configuration circuit having logic to determine a reference threshold voltage, wherein the configuration circuit makes the determination based on the following actions of the memory controller: (i) programming the memory device using the one or more programming voltages to set one or more threshold voltages; and (ii) providing the one or more search voltages; wherein the reference threshold voltage is determined such that the output current represents the Euclidean distance between the stored logic value and the input logic value; The memory controller is configured to store one of n logic values ​​as the stored logic value, wherein the stored logic value is represented by the stored data of each cell of the memory device, and n is an integer greater than zero; the configuration circuit also has logic to perform: setting a voltage value ΔV according to the reference threshold voltage to store different logic values ​​among the n logic values; and minimizing an error of the Euclidean distance, wherein the error is calculated by defining an adjustment current Iref between the stored logic value and the input logic value, and the output current is divided according to the adjustment current.

2. The memory system as claimed in claim 1, wherein the reference threshold voltage is determined based on an ideal reference threshold voltage, which is calculated by interpolation of a characteristic curve of a known or confirmed characteristic, and the characteristic curve is represented by a relationship curve of a gate voltage; wherein Id is a drain current provided by the memory device in response to the gate voltage.

3. The memory system as claimed in claim 2, wherein the logic of the configuration circuit for determining the reference threshold voltage comprises: calculating a partial derivative curve for the known or confirmed characteristics of the memory device; and identifying the value of the gate voltage as the ideal reference threshold voltage, wherein the value of the gate voltage is determined based on a peak point and a tangent of the partial derivative curve, the tangent being tangent to a confirmation point on the relationship curve corresponding to the peak point; wherein the reference threshold voltage is set based on the calculated ideal reference threshold voltage.

4. The memory system as claimed in claim 3, wherein the logic of the configuration circuit for determining the reference threshold voltage comprises: determining a peak value of the gate voltage, wherein the peak value is aligned with a voltage at the peak point of the partial derivative curve; determining a point on the relation curve aligned with the peak value; calculating a tangent line tangent to the confirmation point on the relation curve, wherein the slope of the tangent line is defined by the peak point of the partial derivative curve; and determining a value of the ideal reference threshold voltage such that the value of the gate voltage corresponds to a point on the tangent line, wherein the point satisfies 0.

5. The memory system as claimed in claim 2, wherein the reference threshold voltage is determined based on an extract reference threshold voltage, the extract reference threshold voltage being calculated by applying the ideal reference threshold voltage to a group of memory cells in the memory device.

6. The memory system as claimed in claim 5, wherein the extraction reference threshold voltage is determined by: determining an actual median drain current of the ideal reference threshold voltage of the memory cell group of the memory device, and defining the actual median drain current as a current Ith; and determining the extraction reference threshold voltage from the relationship curve, and using the extraction reference threshold voltage as the voltage corresponding to the current Ith on the relationship curve, such that the extraction reference threshold voltage is an improved version of the ideal reference threshold voltage adjusted according to the actual changes of the memory cell group.

7. The memory system as described in claim 1, where n is a value between 1 and 8.

8. The memory system as claimed in claim 1, wherein the adjustment current Iref is calculated based on the voltage value ΔV, n and the reference threshold voltage.

9. The memory system as claimed in claim 1, wherein the output current is divided according to the adjustment current before determining the Euclidean distance.

10. The memory system as described in claim 1, wherein the memory device is a multi-level content-addressed memory.

11. A memory system comprising: a memory device for storing data for searching within the memory; a memory controller having logic to perform: (i) programming the memory device to store stored data according to one or more programming voltages; (ii) providing one or more search voltages to the memory device according to input data; and (iii) determining a similarity between the stored data and the input data based on an output current from the memory device, wherein the output current represents an Euclidean distance between a stored logic value representing the stored data and an input logic value representing the input data; and a configuration circuit having logic to determine a reference threshold voltage, wherein the configuration circuit makes the determination based on the following actions of the memory controller: (i) programming the memory device using the one or more programming voltages to set one or more threshold voltages; and (ii) providing the one or more search voltages; wherein the reference threshold voltage is determined such that the output current represents the Euclidean distance between the stored logic value and the input logic value; The memory device is a two-dimensional NOR flash memory; a pair of columns in a specific row of the two-dimensional NOR flash memory is used to store data; a plurality of character lines of the two-dimensional NOR flash memory are used to input data corresponding to the stored data, and the character lines are connected to the pair of columns in the specific row; and a row of the two-dimensional NOR flash memory is used to store one or more data characters.

12. The memory system as claimed in claim 11, wherein the two-dimensional NOR flash memory is configured as a dual-transistor NOR flash memory, and one transistor of each dual-transistor pair is used to enable or disable the search for a particular transistor array.

13. The memory system as claimed in claim 11, wherein the two-dimensional NOR flash memory is configured as a discrete-gate NOR flash memory, and a gate of each transistor is used to enable or disable the search for a particular array of transistors.

14. A memory system comprising: a memory device for storing data for searching within the memory; a memory controller having logic to perform: (i) programming the memory device to store stored data according to one or more programming voltages; (ii) providing one or more search voltages to the memory device according to input data; and (iii) determining a similarity between the stored data and the input data based on an output current from the memory device, wherein the output current represents an Euclidean distance between a stored logic value representing the stored data and an input logic value representing the input data; and a configuration circuit having logic to determine a reference threshold voltage, wherein the configuration circuit makes the determination based on the following actions of the memory controller: (i) programming the memory device using the one or more programming voltages to set one or more threshold voltages; and (ii) providing the one or more search voltages; wherein the reference threshold voltage is determined such that the output current represents the Euclidean distance between the stored logic value and the input logic value; The memory device is a three-dimensional NOR flash memory.

15. A memory device comprising: a plurality of memory cells for storing data for searching within the memory; and a memory controller configured to perform: programming the memory device to store stored data according to one or more programming voltages, wherein the one or more programming voltages are set based on a reference threshold voltage; providing one or more search voltages to the memory device according to input data, wherein the one or more search voltages are set based on the reference threshold voltage; and determining a similarity between the stored data and the input data based on an output current from the memory device, wherein the output current is used to represent an Euclidean distance between a stored logic value representing the stored data and an input logic value representing the input data; wherein the reference threshold voltage is determined such that the output current represents the Euclidean distance between the stored logic value and the input logic value. The reference threshold voltage is determined based on an ideal reference threshold voltage, which is calculated by interpolation of a characteristic line with known or confirmed characteristics, and the characteristic line is represented by a relationship curve between a gate voltage; where Id is a drain current provided by the memory device in response to the gate voltage.

16. The memory device as claimed in claim 15, wherein the logic for determining the reference threshold voltage comprises: calculating a partial derivative curve for the known or confirmed characteristic of the memory device; and identifying the value of the gate voltage as the ideal reference threshold voltage, wherein the value of the gate voltage is determined based on a peak point and a tangent of the partial derivative curve, the tangent being tangent to a confirmation point on the curve corresponding to the peak point; wherein the reference threshold voltage is set based on the calculated ideal reference threshold voltage.

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