Semiconductor structure and method for forming the same and memory cell

Abstract

This invention provides a semiconductor device structure and a method for forming the same. In some embodiments, a placement process is performed to implant dopants into the source / drain regions to improve device performance. For example, additional dopants can be used to enhance the source / drain regions of the transistors in a static random access memory (SRAM) cell, thereby improving the performance of the SRAM cell.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor technology, and more particularly to semiconductor structures and methods of forming them, as well as memory cells. Prior Technology

[0002] Traditionally, integrated circuits (ICs) are built in a stacked manner. An IC has transistors at the bottom layer, while interconnect structures (such as vias and wires) are on top of the transistors to provide connections. Power rails (such as metal lines for voltage sources and ground planes) are also located above the transistors and can be part of the interconnect structures. As IC dimensions continue to shrink, so do power rails. This miniaturization inevitably leads to an increase in voltage drop across the power rails and an increase in power consumption of the IC. Summary of the Invention

[0003] In some embodiments, a method for forming a semiconductor structure is provided, the method comprising forming a transistor on the front side of a substrate, wherein the transistor includes: a first source / drain region; a second source / drain region; a channel region adjacent to the first source / drain region and the second source / drain region; and a gate structure formed on the channel region, wherein the first source / drain region and the second source / drain region include a first type of dopant having a first concentration; forming a masking layer over the transistor, wherein the masking layer includes an opening, the masking layer covers the first source / drain region, and the second source / drain region is aligned with the opening; performing a placement process to introduce the first type of dopant; and forming a source / drain contact in the opening to connect the second source / drain region.

[0004] In some embodiments, a semiconductor structure is provided, the semiconductor structure including a first source / drain region; a second source / drain region; a first channel region connected to the first source / drain region and the second source / drain region; and a first gate structure disposed on the first channel region, wherein the first source / drain region includes a first type dopant of a first concentration, the second source / drain region includes a second type dopant of a second concentration, wherein the second concentration is greater than the first concentration, and the second concentration is in the range of about 1E21cm-3 to about 4E21cm-3.

[0005] In other embodiments, a memory cell is provided, the memory cell including a first transistor including: a first source / drain region; a second source / drain region; and a first channel region connected to the first source / drain region and the second source / drain region; and a second transistor including: a first source / drain region; a third source / drain region; and a second channel region connected to the first source / drain region and the third source / drain region, wherein the first source / drain region and the third source / drain region include a first concentration of n-type dopant, and the second source / drain region includes a second concentration of n-type dopant, wherein the second concentration is greater than the first concentration. Simple Explanation of the Diagram

[0006] The embodiments of the present invention can be better understood from the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Figure 1A is a circuit diagram of a six-transistor (6T) static random-access memory (SRAM) cell according to an embodiment of the present invention. Figures 1B and 1C are top views of a static random access memory cell structure according to an embodiment of the present invention. Figures 1D, 1E, and 1F are cross-sectional schematic diagrams of a static random access memory unit according to an embodiment of the present invention. Figure 1G is a cross-sectional schematic diagram of a static random access memory unit according to another embodiment of the present invention. Figure 2 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention. Figures 3A, 3B, 3C, 3D, 3E, 4, 5A, 5B, 5C, 5D, 6A, 6B, 6C, 6D, 7A, 7B, 7C, 7D, 8A, and 8B schematically show the various stages of manufacturing a semiconductor device structure according to embodiments of the present invention. Figures 9A, 9B, 10A, 10B, 11A, and 11B schematically show the various stages of manufacturing a semiconductor device structure according to embodiments of the present invention. Figures 12A and 12B schematically show the structure of a semiconductor device according to an embodiment of the present invention. Implementation

[0007] It is important to understand that the following disclosure provides many different embodiments or examples of implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment disclosed, but may depend on the processing conditions and / or required nature of the components. Furthermore, in the following description, embodiments in which the first component is formed above or on the second component include those where the first and second components are in direct contact, and embodiments in which additional components may be formed between the first and second components so that the first and second components are not in direct contact. In addition, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0008] Furthermore, to facilitate the description of the relationship between one element or component and another (or multiple elements or components) in the diagram, spatially related terms such as "below," "under," "lower part," "above," "upper part," and similar terms may be used. In addition to the orientation shown in the diagram, spatially related terms also cover different orientations of the device during use or operation. The device may also be positioned elsewhere (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly.

[0009] The various embodiments described below generally relate to introducing dopants of Group V elements (e.g., phosphorus and arsenic) into the source / drain regions of an n-type metal-oxide semiconductor (NMOS) in static random access memory (SRAM) to achieve an adjustable SRAM beta ratio, thereby improving SRAM Vmax and Vccmin, enhancing SRAM I-cell performance, and reducing current crowding. The Group V element implantation is applied to the source / drain region of the ground potential (Vss) connected to the pull-down (PD) transistor in the SRAM cell. In some embodiments, the ground potential (Vss) is connected from the back side of the substrate, and the Group V element is implanted from the back side of the substrate. In some embodiments, the Group V element is implanted from the front side of the substrate. In some embodiments, the Group V element can be implanted from both the front and back sides of the substrate.

[0010] While the embodiments of this invention discuss nanostructured channel field-effect transistors, such as gate all-around (GAA) field-effect transistors, including horizontal gate all-around (HGAA) and vertical gate all-around (VGAA) field-effect transistors, some aspects of these embodiments can be used in other processes and / or other devices, such as planar field-effect transistors, fin field-effect transistors, and other suitable devices. Those skilled in the art will readily understand that other modifications are also contemplated within the scope of the embodiments of this invention. In the case of a gate all-around (GAA) transistor structure, the GAA structure can be patterned by any suitable method. For example, these structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual or multiple patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than those achievable using a single direct photolithography process. For instance, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the full-wrap gate structure.

[0011] Figure 1A is a circuit diagram of a six-transistor (6T) static random access memory (SRAM) cell 10 according to some embodiments. The SRAM cell 10 includes a first inverter 20, formed by a pull-up transistor PUx and a pull-down transistor PDx. The SRAM cell 10 further includes a second inverter 40, formed by a pull-up transistor PU and a pull-down transistor PD. Furthermore, the first inverter 20 and the second inverter 40 are coupled between a voltage bus Vdd and a ground potential Vss. In some embodiments, the pull-up transistors PUx and PU may be p-type metal oxide semiconductor (PMOS) transistors, and the pull-down transistors PDx and PD may be n-type metal oxide semiconductor (NMOS) transistors, and the scope of this application is not limited in this respect.

[0012] In Figure 1A, the first inverter 20 and the second inverter 40 are cross-coupled. That is, the input of the first inverter 20 is connected to the output of the second inverter 40. Similarly, the input of the second inverter 40 is connected to the output of the first inverter 20. The output of the first inverter 20 is referred to as storage node 30. Similarly, the output of the second inverter 40 is referred to as storage node 50. In normal operating mode, storage node 30 and storage node 50 are in opposite logic states. By employing two cross-coupled inverters, the static random access memory unit 10 can use a latching structure to store data, so that as long as it is powered through the voltage bus Vdd, the stored data will not be lost without applying a refresh cycle.

[0013] In a static random access memory (SRAM) device using six transistor static random access memory (SRAM) cells, the cells are arranged in rows and columns. The columns of the SRAM array are formed through bit line pairs, namely bit line BLx and bit line BL. The cells of the SRAM device are disposed between corresponding bit line pairs. As shown in Figure 1A, SRAM cell 10 is disposed between bit line BLx and bit line BL.

[0014] In Figure 1A, the static random access memory (SRAM) cell 10 further includes a transfer gate transistor (PGx) connected between bit line BLx and storage node 30 of the first inverter 20. The SRAM cell 10 further includes a transfer gate transistor (PG) connected between bit line BL and storage node 50 of the second inverter 40. The gates of the transfer gate transistors PGx and PG are connected to word line WL, which connects to SRAM cells in rows of the SRAM array.

[0015] During operation, if the transmission gate transistors PGx and PG are inactive, the static random access memory (SRAM) cell 10 will maintain the complementary values ​​at storage nodes 30 and 50 indefinitely as long as power is supplied through the voltage bus Vdd. This is because each inverter in the cross-coupled inverter pair drives the input of the other inverter, thereby maintaining the voltage of the storage node. This situation will remain stable until the SRAM is powered off or a write cycle occurs, thereby changing the data stored at the storage node.

[0016] In the circuit diagram of Figure 1A, the pull-up transistors PUx and PU are p-type transistors. The pull-down transistors PDx and PD, and the transmission gate transistors PGx and PG are n-type transistors. According to various embodiments, the pull-up transistors PUx and PU, the pull-down transistors PDx and PD, and the transmission gate transistors PGx and PG can be implemented using nanostructured channel field-effect transistors.

[0017] The structure of the static random access memory (SRAM) cell 10 in Figure 1A is described in the context of a 6-transistor SRAM. However, those skilled in the art will understand that the components of the various embodiments described herein can be used to form other types of devices, such as memory devices with 8-transistor SRAM or memory devices other than SRAM. Furthermore, embodiments of the present invention can be used as stand-alone memory devices, memory devices integrated with another integrated circuit, or the like. Therefore, the embodiments discussed herein illustrate ways of making and using the contents of the embodiments of the present invention and do not limit the scope of the embodiments of the present invention.

[0018] Figure 1B is a schematic top view of a static random access memory (SRAM) cell 10 according to an embodiment of the present invention. Figure 1C is a schematic top view of a SRAM cell 10 according to an embodiment of the present invention, showing a conductive layer connecting the transistors. The transistors of the SRAM cell 10 are formed on a substrate above a pair of p-type wells 126p and an n-type well 126n between the pair of p-type wells 126p. Fin structures 128a, 128b, 128c, and 128d are on the substrate. Gate structures 130a and 130b are formed above the fin structures 128a, 128b, 128c, and 128d. Each fin structure 128a, 128b, 128c, and 128d contains two or more nanosheet semiconductor channels. During manufacturing, the portions of fin structures 128a, 128b, 128c, and 128d not covered by gate structures 130a and 130b are etched back, and epitaxial source / drain structures are then formed on both sides of gate structures 130a and 130b to form a transistor.

[0019] Fin structures 128a and 128d are formed above two p-type wells 126p, respectively. Fin structures 128a and 128d may have a width W1. Fin structures 128b and 128c are formed above an n-type well 126n. Fin structures 128b and 128c may have a width W2. In some embodiments, the width W1 is greater than the width W2. The pull-down transistor PD and the transmission gate transistor PG are n-type transistors formed along the fin structure 128a above one p-type well 126p, while the pull-down transistor PDx and the transmission gate transistor PGx are n-type transistors formed along the fin structure 128d above the other p-type well 126p. The pull-up transistors PU and PUx are p-type transistors formed along the fin structures 128b and 128c above the n-type well 126n. The gates of the pull-down transistor PD and the pull-up transistor PU are connected. The gates of the pull-down transistor PDx and the pull-up transistor PUx are connected.

[0020] In the configurations shown in Figures 1B and 1C, the pull-down transistors PD / PDx and the transfer gate transistors PG / PGx are formed along the same fin structures 128a / 128d, and therefore have approximately the same source / drain widths (the dimensions of the source / drain regions along the directions of gate structures 130a and 130b). Therefore, the pull-down transistors PD / PDx and the transfer gate transistors PG / PGx in conventional static random access memory (SRAM) structures have approximately the same saturation currents PD Isat and PG Isat. Therefore, the beta of the ratio PD Isat / PG Isat is defined as equal to 1 and cannot be adjusted. It has been observed that the beta value affects the performance of SRAM.

[0021] According to embodiments of the present invention, additional n-type dopants (i.e., Group V elements) are implanted into the enhanced source / drain region 132ND of the pull-down transistor PD / PDx to increase the saturation current PD Isat of the pull-down transistor PD / PDx. By adjusting the concentration of the implanted enhanced source / drain region 132ND, the beta (i.e., the ratio of PD Isat / PG Isat) can be adjusted to improve the performance of static random access memory (SRAM). It has been observed that as the beta value increases, for example, when the beta > 1.0, the statistic noise margin (SNM) of the SRAM increases, thereby reducing the SRAM cell's tolerance to interference. Furthermore, increasing the beta value can also reduce the inverter switch point. In some embodiments, the beta value can be adjusted to a range between 1.0 and 4.4. In some embodiments, the beta value can be adjusted to a range between about 1.0 and about 2.5 to reduce interference or improve tolerance to interference. Additional implantation of the enhanced source / drain region 132ND can also reduce or eliminate any voids or gaps in the enhanced source / drain region 132ND. Voids or gaps in the source / drain region can lead to higher resistance and weaker static random access memory (SRAM) DC-DC performance. Therefore, the additional implantation of the enhanced source / drain region 132ND according to embodiments of the present invention reduces the resistance in the enhanced source / drain region 132ND and improves the DC-DC performance of the SRAM cell.

[0022] Figures 1D, 1E, and 1F are schematic cross-sectional views of a static random access memory (SRAM) cell 10 along lines DD, EE, and FF of Figure 1B, according to some embodiments of the present invention. The SRAM cell 10 includes a fully wound gate transistor. Figure 1D is a schematic cross-sectional view along fin structure 128a, showing the source / drain regions and gate structure of the pull-down transistor PD and the transfer gate transistor PG. Figure 1E schematically shows the source / drain regions of the pull-down transistor PD and the pull-up transistor PU arranged side-by-side. Figure 1F is a schematic cross-sectional view along fin structure 128b, showing the source / drain region and gate structure of the pull-up transistor PU.

[0023] In Figures 1D, 1E, and 1F, the static random access memory cell 10 includes a fully wound gate transistor. Gate structures 130a and 130b include two or more semiconductor channel layers 106, a gate dielectric layer 172 surrounding the semiconductor channel layers 106, and a gate electrode layer 174 forming around the gate dielectric layer 172. Source / drain regions 132N and 132P are disposed on both sides of the gate structures 130a and 130b to form transistors. In some embodiments, the source / drain region 132P and the enhanced source / drain region 132ND are disposed above the well portion 116 of the fin structure, as shown in Figure 1E. In some embodiments, a first epitaxial region 150 and an isolation layer 152 are disposed between the well portion 116 and the source / drain region 132P.

[0024] As shown in Figure 1D, the transfer gate transistor PG is contained in source / drain regions 132N on both sides of the gate structure 130b. The source / drain regions 132N contain one or more epitaxial layers with n-type dopant. In some embodiments, each source / drain region 132N contains three layers: a barrier epitaxial layer 153N formed from the exposed surface of the semiconductor channel layer 106, a transition epitaxial layer 154N formed above the barrier epitaxial layer 153N, and a bulk epitaxial layer 156N formed above the transition epitaxial layer 154N.

[0025] In some embodiments, the barrier epitaxial layer 153N comprises a semiconductor material capable of preventing dopants in subsequently formed epitaxial layers from diffusing into the semiconductor channel layer 106. In some embodiments, the barrier epitaxial layer 153N comprises SiAs. The transition epitaxial layer 154N may be made of one or more layers of Si, SiP, SiC, SiAs, SiSb, and SiCP containing n-type dopants (e.g., phosphorus (P) or arsenic (As)). In some embodiments, the transition epitaxial layer 154N comprises a SiP layer having n-type dopants ranging from about 1E19 cm⁻³ to about 2E21 cm⁻³. The bulk epitaxial layer 156N may be made of one or more layers of Si, SiP, SiC, and SiCP containing n-type dopants (e.g., phosphorus (P) or arsenic (As)). In some embodiments, the transition epitaxial layer 154N and the bulk epitaxial layer 156N may comprise the same semiconductor material but have different dopant concentrations. The dopant concentration of the bulk epitaxial layer 156N may be substantially greater than the dopant concentration of the transition epitaxial layer 154N. In some embodiments, the dopant concentration of the bulk epitaxial layer 156N can be in the range of about 5E19 cm⁻³ to about 4E21 cm⁻³.

[0026] As shown in Figure 1D, the pull-down transistor PD includes a source / drain region 132N and enhanced source / drain regions 132ND disposed on both sides of the gate structure 130a. The aforementioned source / drain region 132N is shared with the transmission gate transistor PG.

[0027] In some embodiments, the enhanced source / drain region 132ND may be fabricated simultaneously with the source / drain region 132N, and subsequently reinforced with additional dopants or implants. In some embodiments, the enhanced source / drain region 132ND comprises three layers: a barrier epitaxial layer 153N formed from the exposed surface of the semiconductor channel layer 106, an enhanced transition epitaxial layer 154ND formed above the barrier epitaxial layer 153N, and an enhanced bulk epitaxial layer 156ND formed above the enhanced transition epitaxial layer 154ND.

[0028] In some embodiments, the dopant concentration in the enhanced transition epitaxial layer 154ND may be greater than the dopant concentration in the transition epitaxial layer 154N, and the dopant concentration in the enhanced transition epitaxial layer 154ND is in the range of about 1E21cm-3 to about 5E21cm-3, for example, in the range of about 1E21cm-3 to about 4E21cm-3.

[0029] In some embodiments, the dopant concentration in the enhanced bulk epitaxial layer 156ND may be greater than the dopant concentration in the bulk epitaxial layer 156N, and the dopant concentration in the enhanced bulk epitaxial layer 156ND is in the range of about 1E21cm-3 to about 5E21cm-3, for example, in the range of about 1E21cm-3 to about 4E21cm-3.

[0030] The enhanced transition epitaxial layer 154ND may be made of one or more layers of Si, SiP, SiC, SiAs, SiSb, and SiCP containing n-type dopants (e.g., phosphorus (P) or arsenic (As)). In some embodiments, the enhanced transition epitaxial layer 154ND comprises a SiP layer having an n-type dopant ranging from about 1E21 cm⁻³ to about 5E21 cm⁻³.

[0031] The enhanced bulk epitaxial layer 156ND may be made of one or more layers of Si, SiP, SiC, and SiCP containing n-type dopants (e.g., phosphorus (P) or arsenic (As)). In some embodiments, the enhanced transition epitaxial layer 154ND and the enhanced bulk epitaxial layer 156ND may contain the same semiconductor material but with different dopant concentrations. The dopant concentration of the enhanced bulk epitaxial layer 156ND may be substantially greater than that of the enhanced transition epitaxial layer 154ND. In some embodiments, the dopant concentration of the enhanced bulk epitaxial layer 156ND may be in the range of about 1E21 cm⁻³ to about 9E21 cm⁻³.

[0032] As shown in Figure 1F, the pull-up transistor PU includes source / drain regions 132P disposed on both sides of the gate structure 130a. The source / drain regions 132P include one or more epitaxial layers having p-type dopant. In some embodiments, each source / drain region 132P includes two layers: a first source / drain layer 154P formed from the semiconductor channel layer 106 and a bulk epitaxial layer 156P. The first source / drain layer 154P may be made of one or more layers of Si, SiGe, or Ge having p-type dopant (e.g., boron (B)). In some embodiments, the dopant concentration of the first source / drain layer 154P may be in the range of about 1 x 10¹⁹ cm⁻³ to about 2 x 10²¹ cm⁻³. The bulk epitaxial layer 156P is formed from the first source / drain layer 154P. The bulk epitaxial layer 156P can be made of Si, SiGe, or Ge with p-type dopant (e.g., boron (B)) for use with p-type field-effect transistors. In some embodiments, the first source / drain layer 154P and the bulk epitaxial layer 156P may contain the same semiconductor material but have different dopant concentrations. The dopant concentration of the bulk epitaxial layer 156P may be substantially greater than the dopant concentration of the first source / drain layer 154P. In some embodiments, the dopant concentration of the bulk epitaxial layer 156P may be in the range of about 5 x 10¹⁹ cm⁻³ to about 4 x 10²¹ cm⁻³.

[0033] In some embodiments, the pull-down transistor PD is connected from the back side of the substrate 101 to the ground potential Vss. As shown in Figures 1D, 1E, and 1F, the enhancement source / drain region 132ND is connected from the back-side source / drain contact 160 to the ground potential Vss. When connected from the back side, at least a portion of the first epitaxial region 150 and the isolation layer 152 are removed from the enhancement source / drain region 132ND.

[0034] Alternatively, the enhanced source / drain region 132ND can be connected to the ground potential Vss through the front source / drain contact 194. Figure 1G is a schematic cross-sectional view of the static random access memory (SRAM) cell 10a according to an embodiment of the present invention. The SRAM cell 10a is similar to the SRAM cell 10, except that the enhanced source / drain region 132ND can be connected to the ground potential Vss through the front source / drain contact 194 and the front via 198.

[0035] By enhancing the source / drain regions of the pull-down transistor PD, various performance improvements are achieved in the static random access memory (SRAM) cells 10 and 10a. It has been observed that enhancing the source / drain region 132ND of the pull-down transistor PD with a phosphorus (P) concentration between 1E21cm⁻³ and 4E21cm⁻³ improves the beta value (PD / PG Isat) in the range of 1.1 to 1.2; increases Vmax (voltage overdrive of the SRAM cell) by approximately 50mV to approximately 100mV; reduces Vccmin (the minimum voltage at which the SRAM cell can perform read / write operations) by 10mV to 20mV; increases Icell performance by approximately 5% to approximately 10%; and improves CPF (a measure of SRAM performance through read / write operations) by approximately 5% to approximately 10%.

[0036] The dopant concentration can be selected based on circuit design and performance targets. For example, when the concentration of phosphorus (P) dopant is between 1E21cm⁻³ and 4E21cm⁻³ to enhance the source / drain region 132ND of a pull-down transistor PD, Vmax increases by approximately 50mV to approximately 70mV; Vccmin decreases by approximately 10mV to 13mV. When the concentration of phosphorus (P) dopant is between 2E21cm⁻³ and 3E21cm⁻³ to enhance the source / drain region 132ND of a pull-down transistor PD, Vmax increases by approximately 70mV to approximately 85mV; Vccmin decreases by approximately 13mV to 16mV. When the concentration of phosphorus (P) dopant is in the range between 3E21cm-3 and 4E21cm-3, the enhanced source / drain region 132ND of the pull-down transistor PD is enhanced, Vmax increases in the range between approximately 85mV and approximately 100mV; Vccmin decreases in the range between 16mV and 20mV.

[0037] Figure 2 is a flowchart of a method 200 for forming a semiconductor device according to an embodiment of the present invention. In some embodiments, method 200 may be used to manufacture a static random access memory cell 10. Figures 3A, 3B, 3C, 3D, 3E, 4, 5A, 5B, 5C, 5D, 6A, 6B, 6C, 6D, 7A, 7B, 7C, 7D, 8A, and 8B schematically show the stages of manufacturing a semiconductor device structure 100 using method 200 according to an embodiment of the present invention. It should be understood that additional operations may be provided before, during, and after the processes shown in the figures, and for additional embodiments of the method, some operations described below may be replaced or eliminated. The order of operations / processes is not limited and the order of operations / processes may be interchanged. The manufactured semiconductor device structure 100 may include one or more components of the static random access memory cell 10.

[0038] In operation 202 of method 200, a device layer 102 including a transistor is formed on the front side of the substrate 101, as shown in Figures 3A to 3E. Figure 3A is a perspective view of a portion of the semiconductor device structure 100 according to some embodiments. Figures 3B, 3C, and 3D are schematic cross-sectional views of the semiconductor device structure 100 along lines BB, CC, and DD of Figure 3A. Figure 3E is a schematic cross-sectional view of the semiconductor device structure 100 along line EE of Figure 3D. As shown in Figures 3A to 3E, the semiconductor device structure 100 includes a transistor having multiple channels formed by a stack of semiconductor layers formed above the front side of the substrate 101.

[0039] Substrate 101 may be a semiconductor substrate. Substrate 101 may comprise a crystalline semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, substrate 101 is an insulating layer-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer. In some embodiments, substrate 101 is a silicon substrate.

[0040] The substrate 101 may include various regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for n-type field-effect transistors (NFETs) and phosphorus for p-type field-effect transistors (PFETs).

[0041] In some embodiments, the stack of semiconductor layers comprises alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel field-effect transistors. In some embodiments, the stack of semiconductor layers may comprise alternating semiconductor channel layers 106 and sacrificial layers (not shown). The semiconductor channel layers 106 and the sacrificial layers are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the semiconductor channel layer 106 may be made of Si, and the sacrificial layer may be made of SiGe. In some examples, the semiconductor channel layer 106 may be made of SiGe, and the sacrificial layer may be made of Si. Alternatively, in some embodiments, either the semiconductor channel layer 106 or the sacrificial layer may be or comprise other materials, such as Ge, SiC, GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or combinations thereof. In some embodiments, the sacrificial layer may be a dielectric layer.

[0042] Semiconductor stacks can be formed through suitable deposition processes, such as epitaxy. For example, epitaxial growth of semiconductor stacks can be performed through molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0043] Semiconductor channel layer 106, or a portion thereof, may form a nanostructured channel of semiconductor device structure 100 in subsequent fabrication stages. The term nanostructure is used herein to refer to any material portion having a nanometer or even micrometer size and an elongated shape (regardless of the cross-sectional shape of this portion). Thus, this term refers to elongated material portions with circular or substantially circular cross-sections, as well as bundled or rod-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sections. Gate electrodes may surround the nanostructured channel of semiconductor device structure 100. Semiconductor device structure 100 may include nanostructured transistors. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, fully wound gate (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gate electrodes surrounding the channel. The use of semiconductor channel layer 106 to define channels or multiple channels of semiconductor device structure 100 is further discussed below.

[0044] Each semiconductor channel layer 106 may have a thickness ranging from about 5 nm to about 30 nm. Each sacrificial layer may have a thickness equal to, less than, or greater than the thickness of the semiconductor channel layer 106. In some embodiments, each sacrificial layer has a thickness ranging from about 2 nm to about 50 nm. Figures 3A to 3D show three semiconductor channel layers 106 for illustrative purposes only and are not intended to limit the specific descriptions in the claimed item. It should be understood that any number of semiconductor channel layers 106 may be formed in the stack of semiconductor layers, and the number of semiconductor channel layers 106 may depend on a predetermined number of channels in the semiconductor device structure 100.

[0045] Fin structures 128 are formed from a stack of semiconductor layers. Fin structures 128 may be semiconductor fins. Each fin structure 128 has an upper portion comprising a semiconductor channel layer 106 and a sacrificial layer, and a well portion 116 formed from a substrate 101. Fin structures 128 may be formed by patterning a hard mask layer formed on the stack of semiconductor layers using a multi-patterning operation including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element comprising the photoresist layer. In some embodiments, the step of patterning the photoresist layer to form the mask element may be performed using an electron beam (e-beam) lithography process. The etching process forms trenches in the unprotected area, through a stack of hard masking layers, through semiconductor layers, and into the substrate 101, leaving a plurality of extending fin structures 128. The trenches extend in the X direction. Dry etching (e.g., reactive ion etching), wet etching, and / or a combination thereof can be used to etch the trenches.

[0046] After the fin structure 128 is formed, an insulating material is formed on the substrate 101. The insulating material fills the trenches between adjacent fin structures 128 until the fin structure 128 is embedded in the insulating material. Next, a planarization operation (e.g., chemical mechanical polishing (CMP) and / or etch-back) is performed to expose the top of the fin structure 128. The insulating material can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-dielectric-constant dielectric material, or any suitable dielectric material. The insulating material can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD). The insulating material is recessed to form an isolation region 118. The recesses in the insulating material expose a portion of the fin structure 128, such as a stack of semiconductor layers. The recesses in the insulating material expose trenches between adjacent fin structures 128. The isolation region 118 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material can be flush with or below the surface of the sacrificial layer contacting the well portion 116 formed by the substrate 101. In some embodiments, the isolation region 118 is a shallow trench isolation (STI) region.

[0047] In some embodiments, one or more sacrificial gate structures are formed over the semiconductor device structure 100. The sacrificial gate structure is formed over a portion of the fin structure 128. Each sacrificial gate structure may include a sacrificial gate dielectric layer, a sacrificial gate electrode layer, and a masking layer. The sacrificial gate dielectric layer, the sacrificial gate electrode layer, and the masking layer may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer, the sacrificial gate electrode layer, and the masking layer, and then patterning these layers into a sacrificial gate structure.

[0048] One or more gate spacers are formed. In some embodiments, the gate spacers include a first gate spacer 138 and a second gate spacer 139. The first gate spacer 138 is deposited on an exposed surface of the semiconductor device structure 100. For example, the first gate spacer 138 is deposited on the fin structure 128, the isolation region 118, and the sacrificial gate structure. The first gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. The first gate spacer 138 may be formed by any suitable process. In some embodiments, the first gate spacer 138 is a compliant layer formed by a compliant process (e.g., atomic layer deposition (ALD) process). The second gate spacer 139 is deposited on the first gate spacer 138. The second gate spacer 139 may comprise any suitable dielectric material, such as SiOx, SiON, SiN, SiOCN, or SiCO. The second gate spacer 139 may have a thickness ranging from about 0.5 nm to about 5 nm. The second gate spacer 139 may be formed by any suitable process. In some embodiments, the second gate spacer 139 is deposited by chemical vapor deposition, plasma-assisted chemical vapor deposition, or electron cyclotron resonance CVD (ECR-CVD).

[0049] The portion of fin structure 128 not covered by the sacrificial gate structure, the first gate spacer wall 138, and the second gate spacer wall 139 is recessed to a height higher than, flush with, or lower than the top surface of isolation region 118. This recess in the fin structure 128 can be achieved through an etching process. The etching process can be dry etching (e.g., reactive ion etching, neutron beam etching, or similar methods) or wet etching (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH)) or any suitable etchant. Well portion 116 is exposed on both sides of the sacrificial gate structure.

[0050] In some embodiments, the edge portions of each sacrificial layer of the semiconductor layer stack are horizontally removed to form internal spacer walls 144 between the semiconductor channel layers 106. Removal of the edge portions of the sacrificial layers forms recesses. In some embodiments, the edge portions of the sacrificial layers are removed by a selective wet etching process. In cases where the sacrificial layers are made of SiGe and the semiconductor channel layers 106 are made of Si, the sacrificial layers can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0051] After removing the edge portions of each sacrificial layer, a dielectric layer is deposited in the recess to form an internal spacer 144. The internal spacer 144 can be made of a low-dielectric-constant dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The internal spacer 144 can be formed by first forming the compliant dielectric layer using a compliant deposition process (e.g., atomic layer deposition), followed by anisotropic etching to remove portions of the compliant dielectric layer other than the internal spacer 144. The semiconductor channel layer 106 protects the internal spacer 144 during the anisotropic etching process.

[0052] In some embodiments, a first epitaxial region 150 is formed on an exposed well portion 116. In some embodiments, the first epitaxial region 150 comprises undoped silicon or undoped silicon-germanium. The first epitaxial region 150 may be formed on a semiconductor surface, for example, by epitaxy on the exposed well portion 116 and the semiconductor channel layer 106. A subsequent etching process is performed to remove the portion of the first epitaxial region 150 formed on the semiconductor channel layer 106. The first epitaxial region 150 formed on the exposed well portion 116 may form a concave top surface due to the etching process. In some embodiments, the first epitaxial region 150 has a thickness in the Z direction ranging from about 5 nm to about 50 nm.

[0053] An isolation layer 152 is then formed on the first epitaxial region 150. The isolation layer 152 can be formed by first forming a dielectric layer on an exposed surface of the semiconductor device structure 100, followed by performing one or more etching processes to remove portions of the dielectric layer other than the isolation layer 152. The isolation layer 152 may comprise any suitable dielectric material. In some embodiments, the isolation layer 152 comprises SiN. The isolation layer 152 can be formed using any suitable process. In some embodiments, the isolation layer 152 may be formed by chemical vapor deposition.

[0054] Source / drain regions 132P and 132N are then formed for p-type and n-type devices, respectively. In some embodiments, source / drain regions 132P and 132N may comprise one or more epitaxial materials. In this document, source and drain regions are used interchangeably, and their structures are substantially the same. Furthermore, depending on the context, source / drain regions may be individually or collectively referred to as source or drain. In some embodiments, p-type and n-type source / drain regions may be formed individually using one or more masking layers.

[0055] The source / drain regions 132P and 132N contain different materials and are formed individually. For example, a source / drain region 132P for a p-type device can be formed, while a masking layer covers the area for the source / drain region 132N; and a masking layer covers the area for the source / drain region 132P, thus forming the source / drain region 132P, and vice versa.

[0056] The source / drain region 132N may include two or more epitaxial material layers formed sequentially. In some embodiments, as shown in Figure 3B, the source / drain region 132N includes a barrier epitaxial layer 153N formed from the exposed surface of the semiconductor channel layer 106, a transition epitaxial layer 154N formed above the barrier epitaxial layer 153N, and a bulk epitaxial layer 156N formed above the transition epitaxial layer 154N.

[0057] A barrier epitaxial layer 153N is formed from the exposed surface of the semiconductor channel layer 106. The barrier epitaxial layer 153N may be formed from a semiconductor material capable of preventing the diffusion of dopants from subsequently formed epitaxial layers into the semiconductor channel layer 106. In some embodiments, the barrier epitaxial layer 153N is a compound comprising a semiconductor material and a Group V element. For example, the barrier epitaxial layer 153N is a compound comprising silicon and a Group V element, such as SiAs. In some embodiments, the barrier epitaxial layer 153N is SiAs having a Si:As ratio in the range of about 1.0 to about 3.0.

[0058] In some embodiments, the barrier epitaxial layer 153N may be included in a discrete portion surrounding the end portion of the semiconductor channel layer 106. In other embodiments, the barrier epitaxial layer 153N may be a continuous layer. The barrier epitaxial layer 153N may be formed by an epitaxial growth method using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. In some embodiments, the barrier epitaxial layer 153N is selectively formed on a semiconductor material (e.g., semiconductor channel layer 106) but not on a dielectric material (e.g., isolation layer 152 and internal spacer 144). In some embodiments, the transition epitaxial layer 154N includes facets that correspond to crystal planes of the material used for the semiconductor channel layer 106.

[0059] The transition epitaxial layer 154N may be made of one or more layers of Si, SiP, SiC, SiAs, SiSb, and SiCP containing n-type dopants (e.g., phosphorus (P) or arsenic (As)). In some embodiments, the transition epitaxial layer 154N comprises a SiP layer having n-type dopants in the range of about 1 x 10¹⁹ cm⁻³ to about 2 x 10²¹ cm⁻³. The transition epitaxial layer 154N may be formed by epitaxial growth methods using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. In some embodiments, the transition epitaxial layer 154N is a continuous layer formed above the barrier epitaxial layer 153N and the internal spacer wall 144. The transition epitaxial layer 154N does not contact the semiconductor channel layer 106. The barrier epitaxial layer 153N is disposed between the transition epitaxial layer 154N and the semiconductor channel layer 106. In some embodiments, the transition epitaxial layer 154N is selectively formed on a semiconductor material (e.g., the barrier epitaxial layer 153N) and not on a dielectric material (e.g., the isolation layer 152 and the internal spacer 144).

[0060] A bulk epitaxial layer 156N is formed from a transition epitaxial layer 154N. The bulk epitaxial layer 156N can be formed by epitaxial growth methods using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. The bulk epitaxial layer 156N can be made of one or more layers of Si, SiP, SiC, and SiCP containing an n-type dopant (e.g., phosphorus (P) or arsenic (As)). In some embodiments, the transition epitaxial layer 154N and the bulk epitaxial layer 156N can contain the same semiconductor material but have different dopant concentrations. The dopant concentration of the bulk epitaxial layer 156N can be substantially greater than the dopant concentration of the transition epitaxial layer 154N. In some embodiments, the dopant concentration of the bulk epitaxial layer 156N can be in the range of about 5 x 10¹⁹ cm⁻³ to about 4 x 10²¹ cm⁻³. The bulk epitaxial layer 156N can be epitaxially grown from the transition epitaxial layer 154N. The quality of the bulk epitaxial layer 156N can be improved due to the facets of the transition epitaxial layer 154N.

[0061] The barrier epitaxial layer 153N, the transition epitaxial layer 154N, and the bulk epitaxial layer 156N can be collectively referred to as the source / drain region 132N. In some embodiments, the transition epitaxial layer 154N and the bulk epitaxial layer 156N are crystalline semiconductor materials.

[0062] As shown in Figure 3E, the source / drain region 132P may include a first source / drain layer 154P and a bulk epitaxial layer 156P. The first source / drain layer 154P may be made of one or more layers of Si, SiGe, or Ge having a p-type dopant (e.g., boron (B)). In some embodiments, the dopant concentration of the first source / drain layer 154P may be in the range of about 1 x 10¹⁹ cm⁻³ to about 2 x 10²¹ cm⁻³. The first source / drain layer 154P may be formed by an epitaxial growth method using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. In some embodiments, the first source / drain layer 154P is selectively formed on a semiconductor material (e.g., semiconductor channel layer 106) and not on a dielectric material (e.g., isolation layer 152 and internal spacer 144).

[0063] A bulk epitaxial layer 156P is formed from a first source / drain layer 154P. The bulk epitaxial layer 156P can be formed by epitaxial growth methods using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. The bulk epitaxial layer 156P can be made of Si, SiGe, or Ge having p-type dopants (e.g., boron (B)) for p-type field-effect transistors. In some embodiments, the first source / drain layer 154P and the bulk epitaxial layer 156P may contain the same semiconductor material but have different dopant concentrations. The dopant concentration of the bulk epitaxial layer 156P can be substantially greater than the dopant concentration of the first source / drain layer 154P. In some embodiments, the dopant concentration of the bulk epitaxial layer 156P can be in the range of about 5 x 10¹⁹ cm⁻³ to about 4 x 10²¹ cm⁻³. The bulk epitaxial layer 156P can be epitaxially grown from the first source / drain layer 154P. The first source / drain layer 154P and the bulk epitaxial layer 156P can be collectively referred to as the source / drain region 132P.

[0064] A contact etch stop layer (CESL) 162 is compliantly formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the second gate spacer 139, the isolation region 118, and the bulk epitaxial layer 156 of the source / drain regions 132N / 132P. The CESL 162 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbide nitride, silicon oxynitride, carbon nitride, silicon oxide, carbon silicon oxide, or similar combinations thereof, and may be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. In some embodiments, the CESL 162 is a single layer. In some embodiments, the CESL 162 comprises two or more layers. An interlayer dielectric (ILD) layer 164 is then formed on the CESL 162. The material used for the interlayer dielectric layer 164 may comprise compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for the interlayer dielectric layer 164. The interlayer dielectric layer 164 may be deposited using a plasma-assisted chemical vapor deposition process or other suitable deposition techniques. In some embodiments, after the formation of the interlayer dielectric layer 164, a thermal process may be performed on the semiconductor device structure 100 to anneal the interlayer dielectric layer 164.

[0065] Next, a gate replacement process can be performed to remove the sacrificial gate structure and form gate structures 130a and 130b. Gate structures 130a and 130b may include a gate dielectric layer 172 and a gate electrode layer 174. The gate dielectric layer 172 is formed to surround the exposed portion of the semiconductor channel layer 106, and the gate electrode layer 174 is formed on the gate dielectric layer 172. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 172 and the exposed portion of the semiconductor channel layer 106, and one or more work function layers (not shown) are formed between the gate dielectric layer 172 and the gate electrode layer 174. In some embodiments, the gate dielectric layer 172 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, other high dielectric constant dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high dielectric constant dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high dielectric constant dielectric materials, and / or combinations thereof. The gate dielectric layer 172 can be formed by chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. The work function layer can comprise polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metallic alloys, or other suitable materials. The gate electrode layer 174 may comprise one or more layers of conductive material, such as platinum (Pt), palladium (Pd), tantalum (Ta), ytterbium (Yb), aluminum (Al), silver (Ag), titanium (Ti), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), copper (Cu), or similar materials and / or combinations thereof. The gate electrode layer 174 may be formed by chemical vapor deposition, atomic layer deposition, electroplating, or other suitable deposition techniques. The gate electrode layer 174 may also be deposited above the upper surface of the interlayer dielectric layer 164. Subsequently, the gate dielectric layer 172 and the gate electrode layer 174 formed above the interlayer dielectric layer 164 are removed by, for example, chemical mechanical polishing, until the top surface of the interlayer dielectric layer 164 is exposed. It should be understood that the semiconductor device structure 100 may undergo further processes, such as cut metal gate (CMG) processing and / or continuous poly on diffusion edge (CPODE) processing. The cut metal gate process divides the gate electrode layer 174 into multiple individually controllable segments. The continuous poly on diffusion edge process forms an isolation structure 108 between devices.

[0066] An etch stop layer 166 and a second interlayer dielectric layer 168 are formed above the interlayer dielectric layer 164 and the gate electrode layer 174. The etch stop layer 166 may contain the same material as the contact etch stop layer 162 and may be formed using the same process as the contact etch stop layer 162. The second interlayer dielectric layer 168 may contain the same material as the interlayer dielectric layer 164 and may be formed using the same process as the interlayer dielectric layer 164. An opening is formed in the second interlayer dielectric layer 168, the etch stop layer 166, the interlayer dielectric layer 164, and the contact etch stop layer 162 to expose the bulk epitaxial layer 156. In some embodiments, portions of the interlayer dielectric layer 164 and the contact etch stop layer 162 located above the bulk epitaxial layer 156 may be removed. The opening may be formed using an etching process, such as a dry etching process, a wet etching process, or a combination thereof. A patterned mask can be formed above the second interlayer dielectric layer 168, and the pattern of the patterned mask is transferred to the second interlayer dielectric layer 168, the etch stop layer 166, the interlayer dielectric layer 164 and the contact etch stop layer 162.

[0067] A silicate layer 192 is formed on the exposed portion of the source / drain regions 132N / 132P. The silicate layer 192 can be formed using any suitable process. In some embodiments, a metal layer is first formed on the semiconductor device structure 100. The metal layer may comprise Ti, Ni, Ru, Co, W, or other suitable metals. In some embodiments, the metal layer is a multilayer structure. The multilayer structure may comprise a metal layer and a metal nitride or metal oxide layer. The metal layer can be deposited using any suitable process, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. After the metal layer is deposited, an annealing process is performed to react the bulk epitaxial layer 156 with the metal layer, thereby forming the silicate layer 192. The silicate layer 192 may comprise any suitable material, such as NiSi, TiSi, CoSi, RuSi, or WSi.

[0068] A front source / drain contact 194 is deposited in the opening. The front source / drain contact 194 may be conductive and may contain one or more materials having Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. The front source / drain contact 194 may be formed by any suitable method, such as electrochemical plating (ECP) or physical vapor deposition.

[0069] In operation 204 of method 200, a front interconnect structure 104 is formed above device layer 102. The front interconnect structure 104 may include multiple dielectric layers and conductors and vias embedded in the dielectric layers. The conductors and vias provide electrical connections to the front source / drain contact 194 and gate electrode layer 174 to supply signals and / or power to the transistors in device layer 102. As shown in Figures 3A to 3D, front vias 196 and 198 are formed in the front interconnect structure 104 to connect the gate electrode layer 174 and the front source / drain contact 194.

[0070] In operation 206 of method 200, the semiconductor device structure 100 is flipped and the substrate 101 is thinned for back-side processing, as shown in Figures 4 and 5A to 5D. Figures 4 and 5A are schematic perspective views of the semiconductor device structure 100. Figures 5B, 5C, and 5D are schematic cross-sectional views of the semiconductor device structure 100 along lines BB, CC, and DD of Figure 5A. After forming the front-side interconnect structure 104, the semiconductor device structure 100 is flipped and a back-side thinning process is performed. In some embodiments, a carrier wafer (not shown) may be bonded to the front side of the semiconductor device structure 100, and the semiconductor device structure 100 is flipped such that the back side 101b of the substrate 101 faces upward for back-side processing, as shown in Figure 4. The back side 101b of the substrate 101 may be thinned using planarization or polishing operations (e.g., chemical mechanical polishing). After the substrate 101 is thinned, the back surface of the semiconductor device structure 100 includes the substrate 101, the isolation region 118 and the isolation structure 108, as shown in Figure 5A.

[0071] In operation 208 of method 200, an etch stop layer 134 and a hard mask layer 136 are deposited above the back surface of the semiconductor device structure 100, as shown in Figures 6A to 6D. Figure 6A is a schematic perspective view of the semiconductor device structure 100. Figures 6B, 6C, and 6D are schematic cross-sectional views of the semiconductor device structure 100 along lines BB, CC, and DD of Figure 6A.

[0072] The etch stop layer 134 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbide nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or similar combinations thereof, and may be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. In some embodiments, the etch stop layer 134 comprises a silicon nitride layer having a thickness in the range of about 5 nm to about 13 nm.

[0073] The hard mask layer 136 may comprise compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. In some embodiments, the hard mask layer 136 may be a silicon oxide layer having a thickness in the range of about 20 nm to about 30 nm. The hard mask layer 136 may be deposited using a plasma-assisted chemical vapor deposition process or other suitable deposition techniques.

[0074] In operation 210 of method 200, a back-side source / drain contact opening 146 is formed, as shown in Figures 7A to 7D. Figure 7A is a schematic perspective view of the semiconductor device structure 100. Figures 7B, 7C, and 7D are schematic cross-sectional views of the semiconductor device structure 100 along lines BB, CC, and DD of Figure 7A.

[0075] In some embodiments, the back-side source / drain contact opening 146 is aligned with the source / drain region 132N for connection from the back side, for example, to a low-voltage power supply (ground potential Vss). In a static random access memory (SRAM) architecture, the back-side source / drain contact opening 146 may be aligned with the drain region of the pull-down transistor PD / PDx.

[0076] In some embodiments, the back-side source / drain contact opening 146 is aligned with the source / drain region 132N without exposing the source / drain region 132N, as shown in Figures 7B and 7C. The back-side source / drain contact opening 146 forms an isolation layer 152 over the source / drain region 132N, passing through the hard mask layer 136, the etch stop layer 134, the substrate 101, and the first epitaxial region 150.

[0077] The back-side source / drain contact opening 146 can be formed by an etching process, such as a dry etching process, a wet etching process, or a combination thereof. The pattern of the opening can be formed in a hard mask layer 136 above the substrate 101, and the pattern of the patterned hard mask layer 136 is transferred to the substrate 101 and the first epitaxial region 150.

[0078] In operation 212 of method 200, a implantation process is performed to implant the source / drain region 132N below the back-side source / drain contact opening 146, as shown in Figures 7A to 7D. In some embodiments, dopant 148 reaches the source / drain region 132N below the bottom of the back-side source / drain contact opening 146. A hard mask layer 136 protects the source / drain region outside the back-side source / drain contact opening 146. Dopant 148 enters the source / drain region 132N below the back-side source / drain contact opening 146. In one aspect, dopant 148 increases the dopant concentration in the source / drain region 132N to increase the saturation current. In another aspect, dopant 148 can improve the crystal structure of the source / drain region 132N by filling or reducing voids or vacancies in the source / drain region 132N.

[0079] In some embodiments, the implantation process implants one or more dopants corresponding to existing dopants in the source / drain regions. For example, an n-type dopant (e.g., phosphorus or arsenic) is implanted into an n-type source / drain region 132N. In some embodiments, the implantation process implants one or more Group V elements into the n-type source / drain region 132N.

[0080] In the embodiments shown in Figures 7A to 7D, dopant 148 enters the bulk epitaxial layer 156N and the transition epitaxial layer 154N (transition epitaxial layer 154) in the source / drain region 132N. In some embodiments, dopant 148 does not enter the barrier epitaxial layer 153N due to the elemental composition and crystal structure of the barrier epitaxial layer 153N. Furthermore, the barrier epitaxial layer 153N further prevents dopant from diffusing from the transition epitaxial layer 154N and the bulk epitaxial layer 156N into the semiconductor channel layer 106.

[0081] The implantation process can be performed at a certain energy level and duration to achieve the target dopant concentration and depth range. In some embodiments, the implantation energy of the implantation process is in the range of about 3 k eV to about 4 k eV.

[0082] In some embodiments, the doping depth d1 of the doped region is in the range of approximately 30 nm to approximately 40 nm, as shown in Figure 7B. In some embodiments, the doping depth d1 covers at least two semiconductor channel layers 106. In some embodiments, the doping depth d1 covers all semiconductor channel layers 106, for example, from the bottom semiconductor channel layer 106 to the top semiconductor channel layer 106. The doping depth d1 and the number of semiconductor channel layers 106 covered can be fine-tuned according to the circuit design.

[0083] The implantation process dops the source / drain regions to create an enhanced source / drain region 132ND. In some embodiments, the dopant is phosphorus. In some embodiments, the dopant concentration added to the enhanced source / drain region 132ND during operation 212 is in the range of about 1E21 cm⁻³ to about 5E21 cm⁻³, for example, in the range of about 1E21 cm⁻³ to about 4E21 cm⁻³. That is, the enhanced source / drain region 132ND has a higher concentration of n-type dopant compared to the undoped source / drain region 132N during operation 212. As described above, the source / drain region 132N may contain an n-type dopant concentration in the range of about 5E19 cm⁻³ to about 4E21 cm⁻³. Therefore, the enhanced source / drain region 132ND may have an n-type dopant concentration in the range of about 1E21 cm⁻³ to about 8E21 cm⁻³.

[0084] In some embodiments, the difference between the source / drain region 132ND and the source / drain region 132N can be enhanced to adjust the beta value (PD / PG Isat).

[0085] In some embodiments, the dopant has a uniform distribution along the doping depth d1. In other embodiments, the dopant has a concentration gradient along the doping depth d1. For example, the dopant has a higher concentration at a horizontal height near the isolation layer 152 or the bottom semiconductor channel layer 106, and a lower concentration at a horizontal height near the front source / drain junction 194 or the topmost semiconductor channel layer 106.

[0086] In some embodiments, the dopant is uniformly distributed in the bulk epitaxial layer 156N and the transition epitaxial layer 154N. In other embodiments, the dopant has a concentration gradient from the bulk epitaxial layer 156N to the transition epitaxial layer 154N.

[0087] In operation 214 of method 200, a back-side source / drain contact 160 is formed in the back-side source / drain contact opening 146, as shown in Figures 8A and 8B. In some embodiments, after the placement process, the isolation layer 152 is removed from the bottom of the back-side source / drain contact opening 146 to expose the enhanced source / drain region 132ND.

[0088] In some embodiments, a silicon layer 158 is first formed on the exposed surface of the enhanced source / drain region 132ND. In some embodiments, a pad 161 is formed in the back-side source / drain contact opening 146, for example, on the substrate 101, the isolation layer 152, the first epitaxial region 150 (if still remaining on the sidewall of the back-side source / drain contact opening 146), and the isolation region 118. The pad 161 may contain any suitable material. In some embodiments, the pad 161 is a nitride layer, such as a silicon nitride layer. In some embodiments, the pad 161 contains the same material as the etch stop layer 134. The pad 161 may first form a dielectric layer on the exposed surface of the semiconductor device structure 100, followed by an anisotropic etching process to remove a portion of the dielectric layer formed on the horizontal surface of the semiconductor device structure 100. For example, a portion of the dielectric layer formed on the enhanced source / drain region 132ND is removed by an anisotropic etching process.

[0089] Next, a back-side source / drain contact 160 is formed to electrically connect to the enhanced source / drain region 132ND. The back-side source / drain contact 160 may be conductive and may contain one or more of the following materials: Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. The back-side source / drain contact 160 may be formed by any suitable method, such as electrochemical plating (ECP) or physical vapor deposition. After forming the back-side source / drain contact 160, a planarization operation (e.g., chemical mechanical polishing) may be performed to remove excess conductive material and the hard mask layer 136.

[0090] After planarization, a back-side interconnect structure can be formed to connect the back-side source / drain contacts 160. In some embodiments, the semiconductor device structure 100 includes static random access memory cells, and the back-side source / drain contacts 160 are Vss nodes, which can be connected to the voltage bus Vdd through the back-side interconnect structure.

[0091] Figures 9A to 9B, 10A to 10B, and 11A to 11B schematically illustrate the various stages of manufacturing a semiconductor device structure 100a according to some embodiments. In some embodiments, when the semiconductor device structure 100a includes a static random access unit 10, Figures 9A, 10A, and 11A are schematic cross-sectional views along line EE of Figure 1B, while Figures 9B, 10B, and 11B are schematic cross-sectional views along line DD of Figure 1B. The semiconductor device structure 100a can be manufactured in a manner similar to that of the semiconductor device structure 100 described above, except that some source / drain regions are reinforced before forming the front source / drain contacts 194.

[0092] Figures 9A and 9B are schematic cross-sectional views of the semiconductor device structure 100a before the formation of the front source / drain contact 194. The front source / drain contact opening 190 is formed in the second interlayer dielectric layer 168, the etch stop layer 166, the interlayer dielectric layer 164, and the contact etch stop layer 162 to expose the bulk epitaxial layer 156 in the source / drain regions 132N / 132P. In some embodiments, portions of the interlayer dielectric layer 164 and the contact etch stop layer 162 located above the bulk epitaxial layer 156 can be removed.

[0093] In some embodiments, a patterned masking layer 191 may be formed over the semiconductor device structure 100a to expose a portion of the source / drain regions 132N / 132P for front-side enhancement placement processes, as shown in Figures 10A and 10B. In some embodiments, the patterned masking layer 191 may be a patterned photoresist layer. In some embodiments, the patterned masking layer 191 exposes a portion of the n-type source / drain regions 132N. For example, the patterned masking layer 191 exposes the drain region of the pull-down transistor PD / PDx (i.e., the n-type source / drain region 132N of the pull-down transistor PD / PDx connected to the Vss node).

[0094] Next, a implantation process is performed to incorporate additional dopant into the exposed source / drain region 132N to form an enhanced source / drain region 132ND. The implantation process may be similar to the implantation process described in operation 212. In some embodiments, dopant 148 reaches the source / drain region 132N below the bottom of the exposed front source / drain contact opening 190. A patterned masking layer 191 protects the underlying source / drain regions 132N, 132P. Dopant 148 enters the source / drain region 132N exposed through the front source / drain contact opening 190. On one hand, dopant 148 increases the dopant concentration in the source / drain region 132N, resulting in an increased saturation current. On the other hand, by filling or reducing voids or vacancies in the source / drain region 132N, dopant 148 can improve the crystal structure of the source / drain region 132N.

[0095] In some embodiments, the implantation process implants one or more dopants corresponding to existing dopants in the source / drain regions. For example, an n-type dopant (e.g., phosphorus or arsenic) is implanted into an n-type source / drain region 132N. In some embodiments, the implantation process implants one or more Group V elements into the n-type source / drain region 132N.

[0096] In some embodiments, dopant 148 enters the bulk epitaxial layer 156N and the transition epitaxial layer 154N in the source / drain region 132N. In some embodiments, dopant 148 does not enter the barrier epitaxial layer 153N due to the elemental composition and crystal structure of the barrier epitaxial layer 153N. Furthermore, the barrier epitaxial layer 153N further prevents dopant from diffusing from the transition epitaxial layer 154N and the bulk epitaxial layer 156N into the semiconductor channel layer 106.

[0097] The implantation process can be performed at certain energy levels and durations to achieve the target dopant concentration and target dopant depth range. In some embodiments, the implantation energy of the implantation process is in the range of about 3 k eV to about 4 k eV. In some embodiments, the doping depth d2 of the doped region is in the range of about 30 nm to about 40 nm. In some embodiments, the doping depth d2 covers at least two semiconductor channel layers 106. In some embodiments, the doping depth d2 covers all semiconductor channel layers 106, for example from the top semiconductor channel layer 106 to the bottom semiconductor channel layer 106. The doping depth d2 and the number of semiconductor channel layers 106 covered can be fine-tuned according to the circuit design. The implantation process dops the source / drain region to enhance the source / drain region 132ND. In some embodiments, the dopant is phosphorus. In some embodiments, the dopant concentration added to the enhanced source / drain region 132ND is in the range of about 1E21 cm⁻³ to about 5E21 cm⁻³, for example, in the range of about 1E21 cm⁻³ to about 4E21 cm⁻³.

[0098] In some embodiments, the front reinforcement fabric shown in Figures 10A and 10B may be used to replace the back reinforcement fabric in Figures 7A to 7D and operation 212. In other embodiments, the front reinforcement fabric shown in Figures 10A and 10B may be combined with the back reinforcement fabric shown in Figures 7A to 7D.

[0099] As shown in Figures 11A and 11B, after the front-side enhancement placement, the patterned masking layer 191 is removed to expose all source / drain regions. A silicon layer 192 is formed on the exposed surfaces of the source / drain regions. The silicon layer 192 can be formed using any suitable process. Front-side source / drain contacts 194 are deposited in the front-side source / drain contact openings 190. Subsequently, a front-side interconnect structure 104 is formed over the semiconductor device structure 100a.

[0100] In some embodiments, the semiconductor device structure 100a may be further back-side processed, such as operations 206, 208, 210, 212 and 214 of method 200, to form a semiconductor device structure having a back-side Vss connection, similar to the semiconductor device structure shown in Figures 8A to 8B.

[0101] Alternatively, the semiconductor device structure 100a can be completed without back-side processing. For example, after the front-side enhancement placement shown in Figures 10A and 10B, the enhanced source / drain region 132ND is connected to the Vss node through a front-side interconnect structure. Figures 12A and 12B schematically show the semiconductor device structure 100b according to an embodiment of the present invention. Figure 12A is a schematic cross-sectional view along line EE of Figure 1B, and Figure 12B is a schematic cross-sectional view of the pull-down transistor PD along line DD of Figure 1B.

[0102] Semiconductor device structure 100b is similar to semiconductor device structure 100, except that the enhanced source / drain region 132ND is connected to the Vss node through the front via 198b instead of the back source / drain contact 160.

[0103] Although the above describes a fully wound gate device, the embodiments of the present invention can also be used in other structures, such as fin field-effect transistor devices (e.g., random access memory cells with fin field-effect transistors).

[0104] This invention provides a semiconductor device structure and a method for forming the same. In some embodiments, a placement process is performed to implant dopants into the source / drain regions to improve device performance, such as adjusting the static random access memory (SRAM) beta ratio, improving SRAM Vmax and Vccmin, enhancing SRAM Icell performance, and reducing current crowding.

[0105] Some embodiments of the present invention provide a method comprising: forming a transistor on the front side of a substrate, wherein the transistor includes: a first source / drain region; a second source / drain region; a channel region adjacent to the first source / drain region and the second source / drain region; and a gate structure formed on the channel region, wherein the first source / drain region and the second source / drain region contain a first type of dopant having a first concentration; forming a masking layer over the transistor, wherein the masking layer includes an opening, the masking layer covers the first source / drain region, and the second source / drain region is aligned with the opening; performing a placement process to introduce the first type of dopant; and forming a source / drain contact in the opening to connect the second source / drain region.

[0106] In some other embodiments, the first type is of type n.

[0107] In some other embodiments, the second source / drain region has a second concentration of dopant after the implantation process, the second concentration being greater than the first concentration, and the second concentration being in the range of about 1E21cm-3 to about 4E21cm-3.

[0108] In some other embodiments, the step of forming the transistor includes: simultaneously forming a first source / drain region and a second source / drain region, comprising: forming a first barrier epitaxial layer and a second barrier epitaxial layer on both ends of the channel region; forming a first transition epitaxial layer on the first barrier epitaxial layer, and forming a second transition epitaxial layer on the second barrier epitaxial layer; and forming a first bulk epitaxial layer on the first transition epitaxial layer, and forming a second bulk epitaxial layer on the second transition epitaxial layer.

[0109] In some other embodiments, the first barrier layer and the second barrier layer comprise SiAs.

[0110] In some other embodiments, the step of performing the implantation process includes implanting a second transition epitaxial layer and a second bulk epitaxial layer.

[0111] In some other embodiments, the masking layer is formed above the back side of the substrate, and the source / drain contacts are back side contacts.

[0112] In some other embodiments, the masking layer is formed above the front side of the substrate.

[0113] Some embodiments of the present invention provide a semiconductor structure comprising: a first source / drain region; a second source / drain region; a first channel region connected to the first source / drain region and the second source / drain region; and a first gate structure disposed on the first channel region, wherein the first source / drain region contains a first type dopant of a first concentration, and the second source / drain region contains a second type dopant of a second concentration, wherein the second concentration is greater than the first concentration and the second concentration is in the range of about 1E21cm-3 to about 4E21cm-3.

[0114] In some other embodiments, the first source / drain region includes: a first barrier epitaxial layer disposed at a first end of the first channel region; a first transition epitaxial layer disposed on the first barrier epitaxial layer; and a first bulk epitaxial layer disposed on the first transition epitaxial layer; the second source / drain region includes: a second barrier epitaxial layer disposed at a second end of the first channel region; a second transition epitaxial layer disposed on the second barrier epitaxial layer; and a second bulk epitaxial layer disposed on the second transition epitaxial layer.

[0115] In some other embodiments, the first type is n-type, and the first barrier epitaxial layer and the second barrier epitaxial layer comprise SiAs.

[0116] In some other embodiments, the second transition epitaxial layer and the second bulk epitaxial layer have a higher dopant concentration than the first transition epitaxial layer and the first bulk epitaxial layer.

[0117] In some other embodiments, the semiconductor structure further includes: a second channel region, wherein a first source / drain region is connected to a first end of the second channel region; and a third source / drain region, connected to a second end of the second channel region, wherein the third source / drain region contains a first type dopant of a first concentration.

[0118] In some other embodiments, the first channel region comprises two or more vertically stacked plurality of semiconductor channel layers.

[0119] In some other embodiments, the semiconductor structure further includes: a first front-side source / drain contact disposed on a first source / drain region; a second front-side source / drain contact disposed on a second source / drain region; and a back-side source / drain contact disposed on the second source / drain region.

[0120] Some embodiments of the present invention provide a memory cell, the memory cell including a first transistor including: a first source / drain region; a second source / drain region; and a first channel region connected to the first source / drain region and the second source / drain region; and a second transistor including: a first source / drain region; a third source / drain region; and a second channel region connected to the first source / drain region and the third source / drain region, wherein the first source / drain region and the third source / drain region contain a first concentration of n-type dopant, and the second source / drain region contains a second concentration of n-type dopant, wherein the second concentration is greater than the first concentration.

[0121] In some other embodiments, the second concentration is in the range of about 1E21cm-3 to about 4E21cm-3.

[0122] In some other embodiments, the first channel region comprises two or more vertically stacked plurality of semiconductor channel layers.

[0123] In some other embodiments, the first source / drain region, the second source / drain region, and the third source / drain region each include: a barrier epitaxial layer disposed on the end portion of a plurality of semiconductor channel layers; a transition epitaxial layer disposed on the barrier epitaxial layer; and a first bulk epitaxial layer disposed on the transition epitaxial layer.

[0124] In some other embodiments, the second source / drain region is connected to a low-voltage power supply.

[0125] The foregoing outlines the features of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments of the present invention.

[0126] 10,10a: Static Random Access Memory (SRAM) units 20: First inverter 30, 50: Storage nodes 40: Second inverter 100, 100a, 100b: Semiconductor device structure 101: Base 101b: Dorsal 102: Device Layer 104: Front-side interconnect structure 106: Semiconductor Channel Layer 108: Isolation Structure 116: Well Area Section 118: Quarantine Zone 126n: n-type well 126p: P-type well 128, 128a, 128b, 128c, 128d: Fin structures 130a, 130b: Gate structure 132N, 132P: Source / Drain Region 132ND: Enhanced source / drain region 134: Etching Stop Layer 136: Hard mask layer 138: First gate gap wall 139: Second gate gap wall 144: Internal spacer wall 146: Backside source / drain contact opening 148: Dopant 150: First epitaxial crystal zone 152: Isolation layer 153N: Barrier epitaxial layer 154,154N: Transition epitaxial layer 154P: First source / drain layer 154ND: Enhanced transition epitaxial layer 156, 156N, 156P: Bulk epitaxial layers 156ND: Enhanced bulk epitaxial layer 158, 192: Silicon layer 160: Backside source / drain junction 161: Padding 162: Contact Etching Stop Layer 164: Interlayer dielectric layer 166: Etching Stop Layer 168: Second interlayer dielectric layer 172: Gate Dielectric Layer 174: Gate electrode layer 190: Front source / drain contact opening 191: Patterned mask layer 194: Front side source / drain contact 196, 198, 198b: Front through holes 200: Method 202,204,206,208,210,212,214: Operations BL, BLx: Bit lines PU, PUx: Pull-up transistors PD, PDx: Pull-down transistors PG, PGx: Transmission gate transistor Vdd: Voltage bus Vss: Grounding potential WL: Character Line W1, W2: Width d1, d2: Doping depth

Claims

1. A method of forming a semiconductor structure, comprising: forming a transistor on the front side of a substrate, wherein the transistor includes: a first source / drain region; a second source / drain region; a channel region adjacent to and connected to the first source / drain region and the second source / drain region; and a gate structure formed on the channel region, wherein the first source / drain region and the second source / drain region contain a first type of dopant having a first concentration; forming a mask layer over the transistor, wherein the mask layer includes an opening, the mask layer covers the first source / drain region, and the second source / drain region is aligned with the opening; A planting process is performed to introduce the first type of dopant, wherein after the planting process, the second source / drain region has a second concentration of dopant, the second concentration being greater than the first concentration; and a source / drain contact is formed in the opening to connect the second source / drain region.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein the first type is n-type.

3. The method for forming a semiconductor structure as claimed in claim 1, wherein the second concentration is in the range of about 1E21cm-3 to about 4E21cm-3.

4. A method for forming a semiconductor structure according to any one of claims 1 to 3, wherein the step of forming the transistor includes: simultaneously forming the first source / drain region and the second source / drain region, including: forming a first barrier epitaxial layer and a second barrier epitaxial layer on both ends of the channel region; forming a first transition epitaxial layer on the first barrier epitaxial layer and forming a second transition epitaxial layer on the second barrier epitaxial layer; forming a first bulk epitaxial layer on the first transition epitaxial layer and forming a second bulk epitaxial layer on the second transition epitaxial layer.

5. The method for forming a semiconductor structure as claimed in claim 4, wherein the step of performing the implantation process includes implanting the second transition epitaxial layer and the second bulk epitaxial layer.

6. A method for forming a semiconductor structure as claimed in any one of claims 1 to 3, wherein the masking layer is formed above the back side of the substrate, and the source / drain contact is a back side contact.

7. A method for forming a semiconductor structure as claimed in any one of claims 1 to 3, wherein the masking layer is formed above the front side of the substrate.

8. A semiconductor structure comprising: a first source / drain region; a second source / drain region; a first channel region connected to and adjacent to the first source / drain region and the second source / drain region; and a first gate structure disposed on the first channel region, wherein the first source / drain region comprises a first type dopant of a first concentration, and the second source / drain region comprises a second type dopant of a second concentration, wherein the second concentration is greater than the first concentration and the second concentration is in the range of about 1E21cm-3 to about 4E21cm-3.

9. The semiconductor structure of claim 8, wherein the first source / drain region comprises: a first barrier epitaxial layer disposed at a first end of the first channel region; a first transition epitaxial layer disposed on the first barrier epitaxial layer; and a first bulk epitaxial layer disposed on the first transition epitaxial layer; the second source / drain region comprises: a second barrier epitaxial layer disposed at a second end of the first channel region; a second transition epitaxial layer disposed on the second barrier epitaxial layer; and a second bulk epitaxial layer disposed on the second transition epitaxial layer.

10. The semiconductor structure of claim 8 or 9 further includes: a second channel region, wherein the first source / drain region is connected to a first end of the second channel region; and a third source / drain region, connected to a second end of the second channel region, wherein the third source / drain region contains the first concentration of the first type of dopant.

11. The semiconductor structure of claim 8 or 9 further includes: a first front-side source / drain contact disposed on the first source / drain region; a second front-side source / drain contact disposed on the second source / drain region; and a back-side source / drain contact disposed on the second source / drain region.

12. A memory cell, comprising: a first transistor, including: a first source / drain region; a second source / drain region; and a first channel region connected to and connected to the first source / drain region and the second source / drain region; and a second transistor, including: the first source / drain region; a third source / drain region; and a second channel region connected to the first source / drain region and the third source / drain region, wherein the first source / drain region and the third source / drain region contain a first concentration of n-type dopant, and the second source / drain region contains a second concentration of n-type dopant, wherein the second concentration is greater than the first concentration.

13. The memory cell of claim 12, wherein the first channel region comprises two or more vertically stacked plurality of semiconductor channel layers.

14. The memory cell of claim 13, wherein the first source / drain region, the second source / drain region, and the third source / drain region each include: a barrier epitaxial layer disposed on the end portion of the plurality of semiconductor channel layers; a transition epitaxial layer disposed on the barrier epitaxial layer; and a first bulk epitaxial layer disposed on the transition epitaxial layer.

15. The memory cell of any one of claims 12 to 14, wherein the second source / drain region is connected to a low-voltage power supply.

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