Semiconductor module

Abstract

A semiconductor module includes: a first substrate having a first surface; stacked memory chips disposed on the first surface and including "a plurality of stacked memory chips" and "a first inductor disposed across the plurality of memory chips"; and a first semiconductor chip disposed on the first surface and separated from the stacked memory chips, and including a second inductor; wherein the stacked memory chips include "a second surface parallel to the first surface and being the outermost surface on the side of the first substrate" and "a third surface perpendicular to the second surface and being the outermost surface on the side of the first semiconductor chip", the first inductor is configured to be parallel to the third surface and separated from the third surface, the first semiconductor chip includes "a fourth surface parallel to the first surface and being the outermost surface on the side of the first substrate" and "a fifth surface parallel to the third surface and being the outermost surface on the side of the stacked memory chips", the second inductor is configured to be parallel to the fifth surface and separated from the fifth surface, and the first inductor and the second inductor communicate in a non-contact manner.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor module. Prior Technology

[0002] In recent years, electronic computers in data centers and other applications have included semiconductor modules that mount multiple memory chips onto a single package substrate, such as stacked memory chips, multiple integrated circuit (IC) chips containing arithmetic processing circuitry, and multiple IC chips containing image processing circuitry. Through these semiconductor modules, electronic computers can achieve a large memory capacity while simultaneously processing large amounts of data through data communication between the individual IC chips and memory chips.

[0003] For example, Patent Documents 1-4 and Non-Patent Document 1 disclose examples of stacked wafers or methods for mounting stacked wafers, in which multiple wafers are stacked. Furthermore, Patent Documents 2, 3, and 5 disclose techniques for non-contact communication between two wafers. Moreover, Patent Documents 1-4 and Non-Patent Documents 1-3 disclose techniques for forming wiring on the sidewalls of stacked wafers as examples of stacked wafer mounting methods.

[0004] Patent Documents Patent Document 1: Japanese Patent Publication No. H3-501428; Patent Document 2: International Patent Publication No. 2021 / 095083; Patent Document 3: International Patent Publication No. 2021 / 199447; Patent Document 4: Japanese Patent Publication No. 2012-156478; Patent Document 5: Japanese Patent Publication No. 2017-069456

[0005] Non-patent literature Non-Patent Literature 1: A. Agnesina et al., “A Novel 3D DRAM Memory Cube Architecture for Space Applications,” 2018 55th ACM / ESDA / IEEE Design Automation Conference (DAC), 2018, pp. 1-6, doi: 10.1109 / DAC.2018.8465911. Non-Patent Literature 2: RW Johnson, “3-D Packaging: A Technology Review,” pp. 1-70, 23 Jun 2005. https: / / nepp.nasa.gov / docuploads / EA7E7EA1-BD30-4DA4-BD615FEA1A7F5AE9 / 3D%20Packaging%20Report%20071805.pdf Non-Patent Literature 3: RM Lea et al., “3-D Stacked Chip Packaging Solution for Miniaturized Massively Parallel Processing,” IEEE Trans. Adv Packag., 22 (3), Aug 1999. Summary of the Invention

[0006] On the other hand, for example, this semiconductor module uses multiple through electrodes and multiple bumps to mount multiple memory chips (stacked memory chips), multiple IC chips containing arithmetic processing circuits, and multiple IC chips containing image processing circuits onto a single packaging substrate. Furthermore, for example, this semiconductor module uses interposers or silicon bridges capable of high-density interconnect (HDI). As a result, the manufacturing cost of the semiconductor module increases, and the power consumption of the semiconductor module increases due to the increase in resistance and parasitic capacitance.

[0007] Furthermore, the techniques for forming wiring on the sidewalls of stacked wafers disclosed in Patent Documents 1-4 and Non-Patent Documents 1-3 include novel processes for forming wiring on the sidewalls of stacked wafers. Accordingly, in Patent Documents 1-4 and Non-Patent Documents 1-3, the manufacturing cost increases due to the novel processes of the semiconductor module. Furthermore, the techniques described in Patent Documents 2 and 3 include novel processes for forming wiring for contactless communication (e.g., wireless communication, inductive communication) on the sidewalls of stacked wafers or the bottom surface of stacked memory wafers. Accordingly, in the techniques described in Patent Documents 2 and 3, the manufacturing cost increases due to the novel processes for wireless communication. Furthermore, in the technology described in Patent Document 5, since the angle between the surfaces of the two chips in which inductors are respectively located is 0 degrees or 180 degrees, inductive communication is generally performed by combining the edges of the inductors that face each other on the two chips. Compared with the structure that can perform inductive communication through multiple edges of the inductors, the communication quality of the technology described in Patent Document 5 is further reduced.

[0008] In view of these problems, one objective of one embodiment of the present invention is to provide a semiconductor module capable of suppressing manufacturing costs. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor module capable of suppressing power consumption. And, one objective of one embodiment of the present invention is to provide a semiconductor module capable of suppressing quality degradation in inductive communication.

[0009] A semiconductor module according to one embodiment of the present invention includes: a first substrate, including a first surface parallel to a first direction and a second direction intersecting the first direction; stacked memory chips disposed on the first surface along a third direction intersecting the first and second directions and including "a plurality of memory chips stacked along the third direction" and "a first inductor disposed across the plurality of memory chips"; and a first semiconductor chip disposed on the first surface and separated from the stacked memory chips along the first direction, and including a second inductor; wherein the stacked memory chip includes "a first surface parallel to the first surface and a second surface intersecting the first direction and a third surface intersecting the first and second directions"; The surface is described as "the outermost second surface of the first substrate side" and "the surface parallel to the second and third directions is the outermost third surface of the first semiconductor wafer side". The first inductor is configured to be parallel to the third surface and separate from the third surface. The first semiconductor wafer includes "the outermost fourth surface of the first substrate side which is parallel to and faces the first surface" and "the outermost fifth surface of the stacked memory wafer side which is parallel to and faces the third surface". The second inductor is configured to be parallel to the fifth surface and separate from the fifth surface. The first inductor and the second inductor communicate in a non-contact manner.

[0010] Another semiconductor module related to one embodiment of the present invention includes: a first substrate, including a first surface parallel to a first direction and a second direction intersecting the first direction; stacked memory chips disposed on the first surface and including "a second surface parallel to a third direction intersecting the first and second directions and simultaneously along the second direction, which is the outermost surface of the second direction", "a third surface parallel to the first surface and simultaneously along the third direction, which is the outermost surface of the first surface", "a plurality of memory chips stacked parallel to the third surface", and "a [missing information] disposed across the plurality of memory chips". The first inductor and the first semiconductor chip are disposed between the first surface and the third surface and include the fourth surface, which is the outermost surface of the first surface, which is parallel to and faces the first surface; the fifth surface, which is opposite to the fourth surface and faces the third surface, which is the outermost surface of the third surface; and the second inductor, which is parallel to the fifth surface.

[0011] The first semiconductor chip of the aforementioned semiconductor module may be a stacked IC chip comprising multiple stacked IC chips. Each of the multiple IC chips includes a sealing ring disposed on the outer periphery of the aforementioned IC chip. The wiring layer of each of the multiple IC chips includes the aforementioned sealing ring and a portion of the aforementioned second inductor. When viewed from the end face, the aforementioned sealing ring is parallel to the semiconductor substrate of the aforementioned IC chip and extends along the aforementioned second direction and is disposed on the semiconductor substrate of the aforementioned IC chip. A portion of the aforementioned first inductor is disposed on the side closer to the aforementioned third surface than the aforementioned sealing ring and overlaps the aforementioned sealing ring. A portion of the aforementioned second inductor is disposed on the side closer to the aforementioned fifth surface than the aforementioned sealing ring and overlaps the aforementioned sealing ring.

[0012] The first semiconductor chip in the aforementioned semiconductor module may be a stacked IC chip comprising multiple stacked IC chips, wherein the number of stacked memory chips is less than the number of stacked IC chips.

[0013] The first semiconductor chip of the aforementioned semiconductor module may be a stacked IC chip that includes multiple stacked IC chips. The aforementioned stacked memory chip includes multiple aforementioned first inductors. The aforementioned stacked IC chip includes multiple aforementioned second inductors. The multiple aforementioned first inductors are arranged in a matrix parallel to the aforementioned third surface, and the multiple aforementioned second inductors are arranged in a matrix parallel to the aforementioned fifth surface.

[0014] The aforementioned semiconductor module may further include: a first internal wiring exposed on the aforementioned third surface; a first side wiring disposed on the aforementioned third surface and electrically connected to the aforementioned first internal wiring; a second internal wiring exposed on the aforementioned fifth surface; a second side wiring disposed on the aforementioned fifth surface and electrically connected to the aforementioned second internal wiring; and a side connection terminal disposed between the aforementioned third surface and the aforementioned fifth surface to electrically connect the aforementioned first side wiring and the aforementioned second side wiring.

[0015] In the aforementioned semiconductor module, a bump layer containing multiple bumps may be further included between the aforementioned second and fourth surfaces and the aforementioned first surface. From a top-view perspective, the diameter of the aforementioned bumps is more than 10 μm and less than 150 μm.

[0016] From a top-down view of the aforementioned semiconductor module, the number of bumps on the second surface may be different from the number of bumps on the fourth surface.

[0017] From a top-down view of the aforementioned semiconductor module, the length between the bumps along the first direction among the plurality of bumps on the second surface can be less than the length between the bumps along the first direction among the plurality of bumps on the fourth surface.

[0018] From a top-down view of the aforementioned semiconductor module, the diameter of each of the plurality of bumps disposed on the aforementioned second surface can be the same as the diameter of each of the plurality of bumps disposed on the aforementioned fourth surface.

[0019] When viewed from the end face of the aforementioned semiconductor module, the length from the aforementioned first face to the end of the aforementioned first inductor can be the same as the length from the aforementioned first face to the aforementioned second inductor.

[0020] From a top-down view of the aforementioned semiconductor module, the diameter of each of the plurality of bumps disposed on the aforementioned second surface may be different from the diameter of each of the plurality of bumps disposed on the aforementioned fourth surface; when viewed from the end face, the length from the aforementioned first surface to the end of the aforementioned first inductor may be the same as the length from the aforementioned first surface to the aforementioned second inductor.

[0021] It can be configured as follows: each of the aforementioned plurality of memory chips has a chip ID, and when the aforementioned first semiconductor chip initiates communication in the aforementioned contactless manner, it sends the aforementioned chip ID to the aforementioned stacked memory chips.

[0022] It can be configured as follows: each of the aforementioned plurality of IC chips has a chip ID, and when the aforementioned first semiconductor chip initiates communication in the aforementioned contactless manner, the IC chip corresponding to the aforementioned chip ID among the aforementioned plurality of IC chips and the aforementioned stacked memory chip perform communication in the aforementioned contactless manner.

[0023] The stacked memory chip can be configured as follows: the aforementioned stacked memory chip includes a first transceiver circuit electrically connected to the aforementioned first inductor; the aforementioned first semiconductor chip includes a plurality of the aforementioned second inductors and a second transceiver circuit electrically connected to each of the plurality of the aforementioned second inductors; the aforementioned stacked memory chip selects one of the plurality of the aforementioned second inductors; the aforementioned first inductor and the aforementioned one second inductor communicate in a non-contact manner.

[0024] It can be configured as follows: the aforementioned stacked memory chip includes a plurality of the aforementioned first inductors and a first transceiver circuit electrically connected to each of the plurality of the aforementioned first inductors; the aforementioned first semiconductor chip includes a second transceiver circuit electrically connected to the aforementioned second inductor; the aforementioned first semiconductor chip selects one of the plurality of the aforementioned first inductors; the aforementioned second inductor communicates with the aforementioned first inductor in a non-contact manner.

[0025] The stacked memory chip can be configured as follows: the aforementioned stacked memory chip includes a plurality of the aforementioned first inductors, the aforementioned first semiconductor chip includes a plurality of the aforementioned second inductors, the aforementioned first semiconductor chip communicates through all combinations of the plurality of the aforementioned first inductors and the plurality of the aforementioned second inductors, obtains data on the strength of the communication through the aforementioned combinations, and selects one of the plurality of the aforementioned first inductors and one of the plurality of the aforementioned second inductors based on the obtained data; the aforementioned semiconductor module communicates with the aforementioned first inductor and the aforementioned second inductor in a non-contact manner.

[0026] It can be configured such that the aforementioned first semiconductor chip performs the following at multiple communication speeds: communicating through all combinations of each of the aforementioned first inductors and each of the aforementioned second inductors, and obtaining data on the strength of the communication through all the aforementioned combinations.

[0027] The first semiconductor chip of the aforementioned semiconductor module may be a stacked IC chip comprising multiple stacked IC chips. The second inductor is disposed across the multiple IC chips. Each of the multiple memory chips and each of the multiple IC chips includes a semiconductor substrate and a wiring layer stacked on the semiconductor substrate. Among the multiple memory chips, the semiconductor substrate of at least one memory chip is exposed on the third surface. Among the multiple IC chips, the semiconductor substrate of at least one IC chip is exposed on the fifth surface.

[0028] The first semiconductor chip of the aforementioned other semiconductor module may be a stacked IC chip comprising multiple stacked IC chips. The second inductor is disposed on the IC chip closest to the third surface. Each of the multiple memory chips and each of the multiple IC chips includes a semiconductor substrate and a wiring layer stacked on the semiconductor substrate. Among the multiple memory chips, the semiconductor substrate of at least one memory chip is exposed on the third surface. Simple Explanation of the Diagram

[0029] Figure 1 is a perspective view illustrating the structure of a semiconductor module related to the first embodiment of the present invention.

[0030] Figure 2 is a top view illustrating the structure of a semiconductor module related to the first embodiment of the present invention.

[0031] Figure 3 is a cross-sectional view of the end section structure of the semiconductor module along line A1-A2 shown in Figure 1.

[0032] Figure 4 is a block diagram illustrating the structure of a semiconductor module related to the first embodiment of the present invention.

[0033] Figure 5 is a perspective view illustrating a plurality of inductors included in a stacked memory chip and a plurality of inductors included in a first semiconductor chip in relation to the first embodiment of the present invention.

[0034] Figure 6 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, the first semiconductor chip, and the bump layer shown in Figure 3.

[0035] Figure 7 is an enlarged cross-sectional view of a portion of the end section structure of an IC chip related to the first embodiment of the present invention.

[0036] Figure 8 is a block diagram illustrating the structure of a stacked memory chip related to the first embodiment of the present invention.

[0037] Figure 9 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, the first semiconductor chip, and the bump layer of the semiconductor module related to the second embodiment of the present invention.

[0038] Figure 10 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, the first semiconductor chip, and the bump layer of the semiconductor module related to the third embodiment of the present invention.

[0039] Figure 11 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, the first semiconductor chip, and the bump layer of the semiconductor module related to the fourth embodiment of the present invention.

[0040] Figure 12 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, bonding layer, third semiconductor chip, bump layer and packaging substrate of the semiconductor module related to the fifth embodiment of the present invention.

[0041] Figure 13 is a perspective view illustrating a plurality of inductors included in a stacked memory chip and a plurality of inductors included in a third semiconductor chip in relation to the fifth embodiment of the present invention.

[0042] Figure 14 is a block diagram illustrating the structure of a semiconductor module related to the fifth embodiment of the present invention.

[0043] Figure 15 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, bonding layer, third semiconductor chip, bump layer and packaging substrate of the semiconductor module related to the sixth embodiment of the present invention.

[0044] Figure 16 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, the first semiconductor chip, and the bump layer of the semiconductor module related to the seventh embodiment of the present invention.

[0045] Figure 17 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, the first semiconductor chip, and the bump layer of the semiconductor module related to the eighth embodiment of the present invention.

[0046] Figure 18 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, the first semiconductor chip, and the bump layer of the semiconductor module related to the ninth embodiment of the present invention.

[0047] Figure 19 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, the first semiconductor chip, and the bump layer of the semiconductor module related to the 10th embodiment of the present invention.

[0048] Figure 20 is a top view illustrating the structure of the bump layer of a semiconductor module related to the tenth embodiment of the present invention.

[0049] Figure 21 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip, the first semiconductor chip, and the bump layer of the semiconductor module related to the 11th embodiment of the present invention.

[0050] Figure 22 is a top view illustrating the structure of the sealing ring and wiring related to the 12th embodiment of the present invention, and is a cross-sectional view showing the end cross-sectional structure of the sealing ring and wiring along the E1-E2 line of the top view.

[0051] Figure 23 is a top view illustrating the structure of the sealing ring and inductor related to the 13th embodiment of the present invention.

[0052] Figure 24 is a cross-sectional view of the sealing loop and the end section of the inductor along line E3-E4 of Figure 23.

[0053] Figure 25 is a cross-sectional view of the end section structure of the inductor along line E5-E6 of Figure 23.

[0054] Figure 26 is a cross-sectional view of the end section structure of the inductor along line E7-E8 of Figure 23.

[0055] Figure 27 is a top view illustrating the structure of the sealing ring and inductor related to the 14th embodiment of the present invention.

[0056] Figure 28 is a cross-sectional view of the sealing ring and the end section of the inductor along line E9-E10 of Figure 27.

[0057] Figure 29 is a cross-sectional view of the end section structure of the sealing ring and inductor shown in Figure 27.

[0058] Figure 30 is a top view illustrating the structure of the sealing ring and inductor related to the 15th embodiment of the present invention.

[0059] Figure 31 is a cross-sectional view of the end section structure of the inductor along line E11-E12 in Figure 30.

[0060] Figure 32 is a cross-sectional view of the sealing ring and the end section of the inductor along line E13-E14 of Figure 30.

[0061] Figure 33 is a cross-sectional view of the end section structure of the inductor along line E15-E16 of Figure 30.

[0062] Figure 34 is a top view illustrating the structure of the sealing ring and wiring related to the 16th embodiment of the present invention, and is a cross-sectional view showing the end cross-sectional structure of the sealing ring and wiring along lines F1-F2 in the top view.

[0063] Figure 35 is a top view illustrating a method for manufacturing an inductor according to the 17th embodiment of the present invention, and a cross-sectional view illustrating the end cross-sectional structure of the inductor along line F3-F4 in the top view.

[0064] Figure 36 is a top view illustrating a method for manufacturing an inductor according to the 17th embodiment of the present invention, and a cross-sectional view illustrating the end cross-sectional structure of the inductor along line F5-F6 in the top view.

[0065] Figure 37 is a perspective view illustrating a plurality of inductors included in a stacked memory chip of a semiconductor module related to the 18th embodiment of the present invention and a plurality of inductors included in a first semiconductor chip.

[0066] Figure 38 is a diagram illustrating the individual authentication number (ID) of each chip related to the 18th embodiment of the present invention.

[0067] Figure 39 is a flowchart illustrating an example of an inductive communication method for a semiconductor module related to the 18th embodiment of the present invention.

[0068] Figure 40 is a flowchart illustrating an example of an inductive communication method for a semiconductor module related to the 18th embodiment of the present invention.

[0069] Figure 41 is a block diagram illustrating the structure of the first semiconductor wafer related to the 18th embodiment of the present invention.

[0070] Figure 42 is a block diagram illustrating an example of the structure of a semiconductor module related to the 19th embodiment of the present invention.

[0071] Figure 43 is a block diagram illustrating an example of the structure of a semiconductor module related to the 20th embodiment of the present invention. Implementation

[0072] The embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different forms and is not limited to the description of the embodiments exemplified below. The drawings illustrate aspects such as width, thickness, and shape of various parts to make the explanation clearer, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and the drawings, elements that are the same as those previously described in related existing figures are sometimes labeled with the same symbols (or labeled with symbols such as a, b, etc. after numbers), and detailed descriptions are appropriately omitted. Moreover, the labels "first" and "second" for each element are merely identifiers to distinguish the elements and have no additional meaning unless specifically stated otherwise.

[0073] In one embodiment of the present invention, the case where a component or region is located "above (or below)" another component or region, unless otherwise specified, includes not only the case where it is located directly above (or directly below) another component or region, but also the case where it is located above (or below) another component or region and therein is another constitutive element.

[0074] In one embodiment of the present invention, the first direction D1 intersects the second direction D2, and the third direction D3 intersects the first direction D1 and the second direction D2 (D1D2 plane).

[0075] In one embodiment of the present invention, when using designations such as "same" and "consistent," "same" and "consistent" may encompass errors within the design scope. Furthermore, in one embodiment of the present invention, when errors within the design scope are included, expressions such as "slightly the same" and "slightly consistent" are sometimes used.

[0076] <First Embodiment>

[0077] The semiconductor module 10 related to the first embodiment will now be described with reference to Figures 1 to 8.

[0078] <1-1. Overview of Semiconductor Module 10>

[0079] First, the outline of the semiconductor module 10 will be described with reference to Figures 1 to 5. Figure 1 is a perspective view showing the structure of the semiconductor module 10. Figure 2 is a top view showing the structure of the semiconductor module 10. Figure 3 is a cross-sectional view showing the end cross-sectional structure of the semiconductor module 10 along A1-A2 shown in Figure 2. Figure 4 is a block diagram showing the functional block structure of the semiconductor module. Figure 5 is a perspective view showing the plurality of inductors 172 included in the stacked memory chip 100 and the plurality of inductors 272 included in the first semiconductor chip 200, and is a perspective view showing the structure of inductors 172 and 272.

[0080] As shown in Figure 1, Figure 2, or Figure 3, the semiconductor module 10 includes a stacked chip group 30, a cover 40, a sealing structure 50, and a packaging substrate 60. Furthermore, the semiconductor module 10 may also include a thermally conductive sheet 80 and a metal film 90.

[0081] The stacked chip assembly 30 includes a first surface 32 electrically connected to the package substrate 60 relative to the third direction D3, a second surface 34 opposite to and parallel to the first surface 32, and multiple chips. Details will be described later, but for example, as shown in FIG2 or FIG3, the stacked chip assembly 30 includes multiple stacked memory chips 100, a first semiconductor chip 200, multiple stacked DRAM (Dynamic Random Access Memory) 300, multiple support substrates 400, multiple second semiconductor chips 600, and a bump layer 800. Furthermore, for example, the bump layer 800 includes multiple bumps 82. The multiple bumps 82 correspond to output terminals of the stacked chip assembly 30. For example, as shown in FIG2, the stacked chip assembly 30 includes 12 stacked memory chips 100, 1 first semiconductor chip 200, 12 stacked DRAM 300, 4 support substrates 400, and 3 second semiconductor chips 600. The structure of the stacked chip group 30 is not limited to the structure shown in FIG2. The structure of the stacked chip group 30 can be appropriately changed according to the application or specifications of the semiconductor module 10. Each of the stacked memory chip 100, the first semiconductor chip 200 and the second semiconductor chip 600 is electrically connected to a plurality of bumps 82 and electrically connected to the packaging substrate 60.

[0082] Without distinguishing between the various first semiconductor wafers 200, a first semiconductor wafer is referred to as a first semiconductor wafer 200. Similarly, without distinguishing between the various stacked DRAMs 300, the various support substrates 400, and the various second semiconductor wafers 600, no uppercase English letters are added after the symbols. Likewise, without distinguishing between the various stacked DRAMs 300, the various support substrates 400, and the various second semiconductor wafers 600, uppercase English letters are added after the symbols.

[0083] The cover 40 covers the stacked chip assembly 30 and is in contact with the first surface 62 of the packaging substrate 60. For example, the cover 40 may contain a metallic material or a sealing material. For example, the metallic material may include gold, nickel, tin, etc., and the sealing material may include resin materials such as epoxy resin, curing agents, fillers, and additives. The cover 40 functions to protect the stacked chip assembly 30 from physical impacts and oxidation caused by contamination or moisture. Furthermore, the cover 40 may also function as a heat sink.

[0084] The sealing structure 50 surrounds the stacked chip assembly 30, is in contact with the stacked chip assembly 30, and is also in contact with the first surface 62 of the packaging substrate 60. For example, the sealing structure 50 includes a sealing material. For example, the sealing material includes resin materials such as epoxy resin, curing agents, fillers, and additives. The sealing structure 50 functions to fix the stacked chip assembly 30 to the packaging substrate 60 while protecting the stacked chip assembly 30 from physical impacts.

[0085] The packaging substrate 60 includes a multilayer wiring structure with interconnects and insulating layers stacked alternately, and is a printed circuit board capable of high-density interconnect (HDI). For example, the packaging substrate 60 can be: an organic laminate substrate, a silicon interposer layer with wiring formed on a silicon substrate (e.g., a Si wafer), an active interposer layer with active components added to the silicon interposer layer, a substrate with embedded silicon bridges embedding a silicon wafer with wiring attached to an organic substrate, a glass core substrate with wiring formed using glass as the core material, or an RDL (Redistribution Layer) interposer layer with wiring formed in an insulating film, etc. The packaging substrate 60 can be any substrate with rewiring capabilities, and is not limited to the substrates shown here. For example, the packaging substrate 60 related to this embodiment includes a first surface 62, a second surface 64, and multiple wiring layers 66, 68, 70, 72, and 74. Wiring layers 66, 68, 70, 72, and 74 are arranged parallel to the first direction D1 and the second direction D2, and are stacked sequentially along the third direction D3. Multiple wiring layers 66 and 74 include multiple electrodes 67 and multiple electrodes 75. Multiple wiring layers 68, 70, and 72 include multiple wirings 69, multiple wirings 71, and multiple wirings 73. Multiple electrodes 67 are exposed on the first surface 62, and multiple electrodes 75 are exposed on the second surface 64. Electrodes 67 are electrically connected to wirings 69, wirings 69 are electrically connected to wirings 71, wirings 71 are electrically connected to wirings 73, and wirings 73 are electrically connected to electrodes 75. In FIG3, the illustration of the insulating layer stacked with the wirings is omitted. Furthermore, the number of stacks in the multilayer wiring structure of the package substrate 60 is not limited to the number of stacks shown in FIG3 (4 layers). The number of stacks in the multilayer wiring structure of the package substrate 60 can be appropriately changed according to the application or specifications of the semiconductor module 10.

[0086] Furthermore, the packaging substrate 60 has the function of connecting the stacked memory chip 100, the first semiconductor chip 200, the stacked DRAM 300, and the second semiconductor chip 600 to external devices. The packaging substrate 60 also has the function of connecting a plurality of bumps 82 to electrodes 75 corresponding to each bump 82. The length (pitch) between two adjacent bumps 82 is shorter than the length (pitch) between two adjacent electrodes 75. The packaging substrate 60 has the function of extending the distance between the bumps 82 to the distance between the electrodes 75. That is, the packaging substrate 60 has the function of rewiring in a manner that makes the distance between the bumps 82 match the distance between the electrodes 75. As a result, the semiconductor module 10 becomes easier to electrically connect to the motherboard (figure omitted).

[0087] For example, the metal film 90 can be disposed along the third direction D3 in a manner that is adjacent to the second surface 34 of the stacked wafer group 30, and the heat-conducting sheet 80 can be disposed between the metal film 90 and the cover 40. For example, the metal film 90 and the heat-conducting sheet 80 together with the cover 40 have the function of releasing the heat generated by the semiconductor module 10 to the outside of the semiconductor module 10.

[0088] Next, the functional block structure of the semiconductor module 10 will be described with reference to Figures 2 to 4. Structures identical or similar to those in Figures 1 to 3 will be described as needed, and sometimes descriptions of structures identical or similar to those in Figures 1 to 3 will be omitted.

[0089] As shown in Figure 2, Figure 3 or Figure 4, the semiconductor module 10 includes stacked memory chips 100A, 100B and 100C, a first semiconductor chip 200, a second semiconductor chip 600A and stacked DRAM.

[0090] Stacked memory chips 100A, 100B, and 100C contain the same structure. The functional block structure of stacked memory chip 100A will be described in the following description, and the functional block structures of stacked memory chips 100B and 100C will be described as needed.

[0091] The stacked memory chip 100A includes multiple through-chip interface-IO (TCI-IO) 112 and multiple memory modules 111. The multiple TCI-IOs 112 are electrically connected to the memory modules 111. For example, the stacked memory chip 100 includes the functions of storing received data and transmitting stored data.

[0092] The TCI-IO 112 includes an inductor 172 (first inductor), a transceiver circuit 114, and a parallel-to-series conversion circuit 113. The inductor 172 is electrically connected to the transceiver circuit 114 via terminals A and B. The transceiver circuit 114 is electrically connected to the parallel-to-series conversion circuit 113. The parallel-to-series conversion circuit 113 is electrically connected to the memory module 111.

[0093] Inductor 172 has the function of performing inductive communication in a non-contact manner with inductor 272 (second inductor) of the first semiconductor wafer 200, and also has the function of performing inductive communication in a non-contact manner with inductor 672 of the second semiconductor wafer 600.

[0094] For example, the transceiver circuit 114 has the function of amplifying the signal (data) received through the inductor 172 and removing noise from the received signal (data). Furthermore, for example, the transceiver circuit 114 has the function of using a parallel-to-series converter circuit 113 to load the converted desired signal (data) onto the radio wave. The signal received through the inductor 172 includes multiple parallel signals from the first semiconductor chip 200 or the second semiconductor chip 600. The aforementioned desired signal includes multiple parallel signals from the memory module 111.

[0095] For example, in step 1, the parallel-to-serial conversion circuit 113 performs a parallel-to-serial conversion on multiple parallel signals from the first semiconductor chip 200 or the second semiconductor chip 600, converting them into serial signals (sequential signals). Serial signals use a single signal path (wiring) for high-speed transmission. In step 2, before reaching the memory module 111, the parallel-to-parallel conversion on the aforementioned serial signals restores them to multiple parallel signals, and then sends these multiple parallel signals to the memory module 111. For example, when sending signals (data) from the memory module 111 to the first semiconductor chip 200 or the second semiconductor chip 600, the parallel-to-serial conversion circuit 113 continues from step 2 and executes step 1. The parallel-to-serial conversion circuit 113 is referred to, for example, as a SerDes circuit (Serialize and Deseriarise Circuit).

[0096] For example, memory module 111 includes the functions of generating and transmitting multiple parallel signals, controlling the receiving of multiple parallel signals and storing them in memory cell array 115 (see Figure 8).

[0097] The first semiconductor chip 200 includes multiple TCI-IOs 212 and multiple CPUs (Central Processing Units) 220 (e.g., CPU 220A, CPU 220B, CPU 220C). The multiple TCI-IOs 212 are electrically connected to the multiple CPUs 220.

[0098] The TCI-IO 212 includes an inductor 272, a transceiver circuit 214, and a parallel-to-series converter circuit 213. The inductor 272 is electrically connected to the transceiver circuit 214 via terminals C and D. The transceiver circuit 214 is electrically connected to the parallel-to-series converter circuit 213. For example, the parallel-to-series converter circuit 213 is electrically connected to the CPU 220A.

[0099] The structure and function of inductor 272, transceiver circuit 214 and parallel-series conversion circuit 213 are the same as those of inductor 172, transceiver circuit 114 and parallel-series conversion circuit 113.

[0100] CPU 220 includes multiple arithmetic circuits capable of performing arithmetic processing. For example, CPU 220A has the following functions: reading the control program stored in the stacked DRAM 300A via the stacked memory chip 100A and executing the processing according to the control program, while sending commands (instructions) to each IC chip 110 in a manner that executes the processing according to the control program.

[0101] The second semiconductor chip 600 includes multiple TCI-IOs 612 and multiple GPUs (Graphics Processing Units) 620 (e.g., GPU 620A, GPU 620B). The multiple TCI-IOs 612 are electrically connected to the multiple GPUs 620.

[0102] The TCI-IO 612 includes an inductor 672, a transceiver circuit 614, and a parallel-to-serial converter circuit 613. The inductor 672 is electrically connected to the transceiver circuit 614 via terminals E and F. The transceiver circuit 614 is electrically connected to the parallel-to-serial converter circuit 613. For example, the parallel-to-serial converter circuit 613 is electrically connected to a GPU 620A.

[0103] The structure and function of inductor 672, transceiver circuit 614 and parallel-series conversion circuit 613 are the same as those of inductor 272, transceiver circuit 214 and parallel-series conversion circuit 213.

[0104] GPU 620 includes multiple computing circuits capable of image processing or image processing. That is, the second semiconductor chip 600 has the same structure as the first semiconductor chip 200 and is a chip specializing in image processing or image processing. For example, GPU 620A has the following functions: reading the control program stored in the stacked DRAM 300B via the stacked memory chip 100B and executing the processing according to the control program, while simultaneously sending commands (instructions) to each IC chip 110 in a manner that executes the processing according to the control program.

[0105] Next, the outline of inductive communication will be explained with reference to Figure 5. Constructions identical or similar to those in Figures 1-4 will be described as needed, and sometimes descriptions of such constructions will be omitted.

[0106] The stacked memory chip 100 includes a plurality of inductors 172, which are configured to be parallel to and separate from a third surface 146 (parallel to both the second and third directions D3). The plurality of inductors 172 are arranged along the second direction D2. Each of the plurality of inductors 172 includes a terminal A, a terminal B, a first portion 172a, a second portion 172b, a third portion 172c, a fourth portion 172e, and a fifth portion 172d.

[0107] Part 5 172d extends along the second direction D2, one end of which is electrically connected to terminal A, and the other end of which is electrically connected to one end of part 4 172e. Part 4 172e extends along the third direction D3, and the other end of which is electrically connected to one end of part 1 172a. Part 1 172a extends along the second direction D2, and the other end of which is electrically connected to one end of part 2 172b. Part 2 172b extends along the third direction D3, and the other end of which is electrically connected to one end of part 3 172c. Part 3 172c extends along the second direction D2, and the other end of which is electrically connected to terminal B.

[0108] The first semiconductor wafer 200 includes a plurality of inductors 272 (second inductors), which are parallel to the location where the plurality of inductors 172 are disposed and are arranged parallel to and separate from the third surface 206 of the first semiconductor wafer 200. The plurality of inductors 272 are arranged along a second direction D2. Each of the plurality of inductors 272 includes a terminal C, a terminal D, a first portion 272a, a second portion 272b, a third portion 272c, a fourth portion 272e, and a fifth portion 272d.

[0109] Part 5 272d extends along the second direction D2, one end of which is electrically connected to terminal C, and the other end of which is electrically connected to one end of part 4 272e. Part 4 272e extends along the third direction D3, and the other end of which is electrically connected to one end of part 1 272a. Part 1 272a extends along the second direction D2, and the other end of which is electrically connected to one end of part 2 272b. Part 2 272b extends along the third direction D3, and the other end of which is electrically connected to one end of part 3 272c. Part 3 272c extends along the second direction D2, and the other end of which is electrically connected to terminal D.

[0110] Viewed from the first direction D1 on a plane parallel to the second and third directions D2 and D3, inductors 172 and 272 are arranged parallel to each other and facing each other. Furthermore, inductors 172 and 272 overlap. Among the plurality of inductors 172 and 272, one inductor 172 and one inductor 272 facing each other are coupled by a magnetic field, enabling one-to-one non-contact communication between them. For example, communication between inductors accompanied by magnetic field coupling is called: inductive communication, signal communication, data communication, etc. Moreover, the shapes of inductors 172 and 272 are not limited to rectangular shapes; any shape that allows for inductive communication is acceptable.

[0111] For example, inductors 172 and 272 are arranged parallel to each other and facing each other, enabling one-to-one communication through magnetic field coupling. In the example shown in Figure 5, the magnetic field is generated by the first portion 172a of inductor 172 and the first portion 272a of inductor 272, and by the fourth portion 172e of inductor 172 and the fourth portion 272e of inductor 272. The magnetic fields generated by the second, third, and fifth portions of each inductor are omitted. The magnetic field shown in Figure 5 is an example where the normal vectors of the parallel surfaces of inductors 172 and 272 (e.g., the third surface 146 and the third surface 206) are aligned; the actual generated magnetic field is not limited to the magnetic field shown in Figure 5.

[0112] Inductor 272 has the same structure and function as inductor 172. In addition, the view of a plane parallel to the second direction D2 and the third direction D3 from the first direction D1 is sometimes referred to as a top view.

[0113] Furthermore, inductors 172 for stacked memory chips 100A and 100C can be formed parallel to each other on their opposite surfaces. Stacked memory chip 100C is an adjacent stacked memory chip to stacked memory chip 100A. As a result, inductors 172 of stacked memory chip 100A and 100C can perform inductive communication. For example, if there is sufficient data transmission time, stacked memory chips 100A and 100C can perform inductive communication to transmit all data from stacked memory chip 100A to stacked memory chip 100C.

[0114] Each of the multiple stacked DRAMs 300 stores, for example, a control program for controlling the multiple stacked memory chips 100, the first semiconductor chip 200, and the multiple second semiconductor chips 600 within the semiconductor module 10. The stacked DRAMs 300 may be, for example, high-performance DRAMs capable of communication over a wide bandwidth, such as those called HBM (High Bandwidth Memory).

[0115] Furthermore, the stacked DRAM 300 and the stacked memory chip 100 may also include inductors (illustrations omitted) that span multiple DRAM chips. For example, similarly, the stacked DRAM 300 and the stacked memory chip 100 may also communicate inductively with the inductor 272 of the adjacent first semiconductor chip 200 or the inductor 672 of the second semiconductor chip 600.

[0116] As explained above, the stacked memory chip 100 is electrically connected to the first semiconductor chip 200 and the second semiconductor chip 600 using a bump layer 800 and a package substrate 60, without the need for expensive components such as interposers or silicon bridges. Furthermore, the stacked memory chip 100 and the first semiconductor chip 200 and the second semiconductor chip 600 can transmit and receive signals using contactless inductive communication, rather than by laying long signal paths through wiring, through electrodes, and bumps.

[0117] As a result, since the manufacturing process of the semiconductor module 10 does not include the process of connecting the stacked memory chip 100, the first semiconductor chip 200, and the second semiconductor chip 600 to an interposer or silicon bridge, manufacturing costs can be suppressed, and the decline in manufacturing yield can be prevented. Furthermore, the semiconductor module 10 includes a structure that can suppress resistance and parasitic capacitance, and the inductive communication of the semiconductor module 10 can suppress the power consumption of the semiconductor module 10.

[0118] Furthermore, the normal vectors of the inductor 172 of the stacked memory chip 100 and the inductor 272 of the first semiconductor chip 200 and the second semiconductor chip 600 are aligned. As a result, the semiconductor module 10 is a module that can achieve "increased efficiency in signal transmission using inductive communication".

[0119] Furthermore, inductor 172 is not exposed on the end faces (first face 142, second face 144, third face 146, etc.) of the stacked memory chip 100. Similarly, inductors 272 and 672 (see Figure 4) are also not exposed on the end faces of the first semiconductor chip 200 and the second semiconductor chip 600, as is inductor 172. As a result, the semiconductor module 10 can suppress corrosion or deterioration of the components within the stacked memory chip 100 caused by inductor exposure, and can also suppress moisture absorption and impurity intrusion into the stacked memory chip 100 caused by inductor exposure. In other words, the long-term reliability of the semiconductor module 10 can be maintained without compromising its reliability.

[0120] Furthermore, as described above, for example, the semiconductor module 10 is electrically connected to the motherboard (not shown) via bumps (not illustrated) electrically connected to the electrode 75. Accordingly, the semiconductor module 10 has a structure that makes it relatively easy to remove from the motherboard. Therefore, for example, in the event of a malfunction in the stacked memory chip 100, the semiconductor module 10 can be removed from the motherboard and replaced. Furthermore, since the stacked memory chip 100 on the semiconductor module 10 is electrically connected to the packaging substrate 60 via bumps 82, the stacked memory chip 100 has a structure that allows it to be removed from the packaging substrate 60. Therefore, it is also possible to remove the malfunctioning stacked memory chip 100 from the packaging substrate 60 and electrically connect a new stacked memory chip 100 to the packaging substrate 60.

[0121] <1-2. End section structure of stacked wafer group 30>

[0122] The end cross-sectional structure of the stacked chip group 30 is described with reference to Figures 1 to 7. Figure 6 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 shown in Figure 3. Figure 7 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the IC chip 110. Structures identical or similar to those in Figures 1 to 5 are described as needed, and sometimes descriptions of structures identical or similar to those in Figures 1 to 5 are omitted.

[0123] <1-2-1. Overview of Stacked Memory Chip 100>

[0124] The end cross-sectional structure of the stacked chip group 30 is described with reference to Figures 1 to 6. As shown in Figure 6, the stacked memory chip 100A includes a configuration in which multiple IC chips 110 are stacked on a package substrate 60 along a third direction D3. The stacked memory chip 100A includes: a first surface 142, which is the side on which the package substrate 60 is disposed and is parallel to both the first direction D1 and the second direction D2; a second surface 144, which is opposite to the first surface 142 and parallel to the first surface 142 relative to the third direction D3; a third surface 146, which is the side on which the first semiconductor chip 200 is disposed and is perpendicular to both the first surface 142 and the second surface 144; and a fourth surface 148, which is opposite to the third surface 146 relative to the first direction D1.

[0125] Furthermore, the first surface 142 is the outermost surface below the stacked memory chip 100 along the third direction D3 system, and the second surface 144 is the outermost surface above the stacked memory chip 100 along the third direction D3 system. Additionally, the third surface 146 is the outermost surface of the stacked memory chip 100 on the side where the first semiconductor chip 200 is disposed along the first direction D1 system, and the fourth surface 148 is the outermost surface of the stacked memory chip 100 on the opposite side of the third surface 146 along the first direction D1 system.

[0126] Furthermore, the stacked memory chip 100A is electrically connected to the stacked DRAM 300A and the packaging substrate 60. For example, the first surface 142 of the stacked memory chip 100A is electrically connected to a plurality of bumps 82 and simultaneously electrically connected to the packaging substrate 60 (a plurality of electrodes 75), and the second surface 144 of the stacked memory chip 100A is electrically connected to the stacked DRAM 300A through a through electrode 131 (see Figure 7).

[0127] Each of the multiple IC chips 110 includes a transistor layer 130 and a wiring layer 150. The transistor layer 130 includes a semiconductor substrate 173, but for ease of explanation, the transistor layer 130 and the semiconductor substrate 173 are shown separately in the figure. Further details will be described later, but for example, the wiring layer 150 includes a multilayer wiring structure with through electrodes or wirings interleaved with insulating layers. The number of multilayer wirings in the wiring layer 150 can be appropriately varied according to the specifications and applications of the semiconductor module 10.

[0128] Without distinguishing between the various IC chips 110, the IC chip is presented as IC chip 110. With distinction between the various IC chips 110, the memory chip is presented as IC chip 110n, IC chip 110n+1, IC chip 110n+2, etc.

[0129] For example, the stacked memory chip 100A includes four IC chips 110 (IC chip 110n+3, IC chip 110n+2, IC chip 110n+1, and IC chip 110n). The stacked memory chip 100A includes IC chips 110n+3, IC chip 110n+2, IC chip 110n+1, and IC chip 110n, which are stacked sequentially along the third direction D3 in order close to the first surface 62 of the packaging substrate 60.

[0130] For example, IC chip 110n is a TCI-IO chip 500A. For example, TCI-IO chip 500A includes: a portion of terminals A and B of inductor 172, transceiver circuit 114, and parallel-to-serial conversion circuit 113.

[0131] Furthermore, the stacked memory chip 100A includes an inductor 172 disposed across multiple IC chips 110. The inductor 172 is disposed parallel to the third direction D3 (third surface 146) along the second direction D2 and separated from the third surface 146. For example, the distance L1 between the end 101 of the inductor 172 shown in FIG. 6 and the first surface 62 of the package substrate 60 is the inductor 172 along the third direction D3, and the length L2 is the inductor 172. For example, the length L2 is the length of each of the first portion 172a, the second portion 172b, and the fourth portion 172e, and can be the length of opposite sides of the first portion 172a including terminals A and B, the third portion 172c, and the fifth portion 172d. For example, the length L2 can be the diameter of the inductor 172. For example, the inductor 172 shown in Figure 6 is disposed across IC chip 110n+3, IC chip 110n+2, IC chip 110n+1 and IC chip 110n. Details will be described later, but the inductor 172 is formed using multiple wirings, through electrodes, etc.

[0132] IC chip 110n includes a semiconductor substrate 173n, a transistor layer 130n, and a wiring layer 150n. IC chip 110n+1 includes a semiconductor substrate 173n+1, a transistor layer 130n+1, and a wiring layer 150n+1. As shown in Figure 6, IC chips 110n+3 and 110n+2, like IC chips 110n and 110n+1, also include corresponding semiconductor substrates 173n, transistor layers 130n, and wiring layers 150n.

[0133] For example, the stacking (bonding) of IC chips 110 can use techniques such as fusion bonding and silicon direct bonding (SDB). Since fusion bonding and SDB are techniques used in this field, detailed descriptions are omitted here. For example, bonding IC chips 110 with their wiring layers 150 facing each other is called face-to-face (F2F) bonding. For example, bonding IC chips 110 with their semiconductor substrates 173 contained in their transistor layers 130 facing each other is called back-to-back (B2B) bonding. For example, bonding IC chips 110 with their wiring layers 150 and semiconductor substrates 173 contained in their transistor layers 130 facing each other is called face-to-back (F2B) bonding.

[0134] Furthermore, for example, a mounting structure in which the semiconductor substrate 173 side of the IC chip 110 is electrically connected to the packaging substrate 60 and the stacking direction is upward along the third direction D3 is called an upward mounting structure. On the other hand, for example, a mounting structure in which the wiring layer 150 side of the IC chip 110 is electrically connected to the packaging substrate 60 and the stacking direction is downward along the third direction D3 is called a downward mounting structure.

[0135] That is, the stacked memory chip 100A shown in Figure 6 includes four IC chips 110n~110n+3 bonded by F2B, which are mounted face down on the packaging substrate 60.

[0136] The stacking number, bonding, and mounting structure of the IC chips 110 in the stacked memory chip 100A shown in Figure 6 is an example. The stacking number, bonding, and mounting structure of the IC chips 110 in the stacked memory chip 100A are not limited to the bonding and mounting structure shown in Figure 6. For example, the stacked memory chip 100A may also include two IC chips 110n and 110n+1 bonded via F2B, mounted face up on the packaging substrate 60.

[0137] <1-2-2. Overview of the first semiconductor wafer 200>

[0138] As shown in Figure 6, the first semiconductor wafer 200 and the stacked memory wafer 100A both include a structure in which multiple IC wafers 110 are stacked on the packaging substrate 60 along the third direction D3. The first semiconductor wafer 200 includes: a first surface 202, which is the side on which the packaging substrate 60 is disposed and is parallel to both the first direction D1 and the second direction D2; a second surface 144, which is opposite to the first surface 202 and parallel to the first surface 202 relative to the third direction D3; a third surface 206, which is the side on which the stacked memory wafer 100A is disposed and is perpendicular to both the first surface 202 and the second surface 204; and a fourth surface 208, which is opposite to the third surface 206 relative to the first direction D1.

[0139] Furthermore, the first surface 202, along the third direction D3, is the outermost surface below the first semiconductor wafer 200, and the second surface 204, along the third direction D3, is the outermost surface above the first semiconductor wafer 200. Additionally, the third surface 206, along the first direction D1, is the outermost surface of the first semiconductor wafer 200 on the side where the stacked memory wafer 100A is disposed, and the fourth surface 208, along the first direction D1, is the outermost surface of the first semiconductor wafer 200 on the opposite side to the third surface 206.

[0140] Furthermore, the first semiconductor wafer 200 is bonded to the support substrate 400B and electrically connected to the packaging substrate 60. For example, the first surface 202 of the first semiconductor wafer 200 is electrically connected to a plurality of bumps 82 and electrically connected to the packaging substrate 60 (a plurality of electrodes 75), and the second surface 204 of the first semiconductor wafer 200 is bonded to the support substrate 400B by fusion or direct silicon bonding.

[0141] For example, as shown in Figure 2, the first semiconductor chip 200 includes multiple CPUs 220. For instance, the first semiconductor chip 200 includes three CPUs: 220A, 220B, and 220C. CPUs 220A, 220B, and 220C have the same structure and function. In the following description of the first semiconductor chip 200, CPU 220A will be used as an example, and CPUs 220B and 220C will be described as needed.

[0142] The support substrate 400 functions to support the first semiconductor wafer 200 and the second semiconductor wafer 600. Furthermore, the support substrate 400 and the bump layer 800 can also adjust the length of the first semiconductor wafer 200 from the first surface 62 of the packaging substrate 60 to the bonding surface between the support substrate 400 and the first semiconductor wafer 200, parallel to the third direction D3. For example, the support substrate 400A supports three CPUs 220A, 220B, and 220C, and its length (height) within the first semiconductor wafer 200, measured from the first surface 62, is adjusted.

[0143] For example, the first semiconductor chip 200 includes four IC chips 110 (IC chip 110n+7, IC chip 110n+6, IC chip 110n+5, and IC chip 110n+4). The stacked memory chip 100A includes IC chips 110n+7, IC chip 110n+6, IC chip 110n+5, and IC chip 110n+4 stacked sequentially along the third direction D3 in order close to the first surface 62 of the packaging substrate 60.

[0144] For example, the IC chip 110n+7 series IO chip 700A, the IC chips 110n+6 and 110n+5 series CPU 220A, and the IC chip 110n+4 series TCI-IO chip 500C. Furthermore, the wiring layer 150n+7 side of the IC chip 110n+7 corresponds to the first surface 202, and the semiconductor substrate 173n+4 side of the IC chip 110n+4 corresponds to the second surface 204.

[0145] For example, the TCI-IO chip 500C includes: a portion of terminals C and D of inductor 272, transceiver circuitry 214, and parallel-to-serial conversion circuitry 213. For example, the IO chip 700A functions as an interface between the semiconductor module 10 and external devices for inputting and outputting control signals, power supply voltage (VDD), and ground voltage (VSS) between the stacked memory chip 100, CPU 220A, and TCI-IO chip 500C and external devices. For example, voltage VDD is a power supply voltage such as 1 V or 3 V, and voltage VSS is 0 V.

[0146] Furthermore, the first semiconductor wafer 200 includes an inductor 272 disposed across a plurality of IC wafers 110. The inductor 272 is disposed parallel to the third direction D3 (third surface 206) along the second direction D2 and separate from the third surface 206. For example, the distance L1 between the end 101 of the inductor 272 shown in FIG. 6 and the first surface 62 of the package substrate 60 is the inductor 272 along the third direction D3, and the length L2 is the inductor 272. For example, the length L2 is the length of each of the first portion 272a, the second portion 272b, and the fourth portion 272e, and can be the length of opposite sides of the first portion 272a including terminals C and D, the third portion 272c, and the fifth portion 272d. For example, the length L2 can be the diameter of the inductor 272. For example, the inductor 272 shown in Figure 6 is disposed across IC chips 110n+7, 110n+6, 110n+5, and 110n+4. Inductor 272, like inductor 172, is formed using multiple wirings, through electrodes, etc.

[0147] IC chip 110n+4 includes a semiconductor substrate 173n+4, a transistor layer 130n+4, and a wiring layer 150n+4. As shown in Figure 6, IC chips 110n+5, 110n+6, and 110n+7 also include corresponding semiconductor substrates 173, transistor layers 130, and wiring layers 150, just like IC chip 110n+4.

[0148] The first semiconductor wafer 200 shown in Figure 6 includes four IC wafers 110n+4 to 110n+7 that are F2B bonded and mounted face down on the packaging substrate 60.

[0149] Similar to the stacked memory chip 100A, the stacking number, bonding, and mounting structure of the IC chip 110 of the first semiconductor chip 200 shown in Figure 6 is an example. The stacking number, bonding, and mounting structure of the IC chip 110 of the first semiconductor chip 200 are not limited to the bonding and mounting structure shown in Figure 6. For example, the first semiconductor chip 200 may include a structure in which 5 or more IC chips 110 are bonded via F2B, or a structure in which 3 or fewer IC chips are bonded via F2B, and may also be mounted face-up on the packaging substrate 60.

[0150] As explained above, the stacked memory chip 100 includes an inductor 172 spanning IC chips 110n, 110n+1, 110n+2, and 110n+3, and the first semiconductor chip 200 includes an inductor 272 spanning IC chips 110n+4, 110n+5, 110n+6, and 110n+7. As a result, the diameters of the inductors in the stacked memory chip 100 and the first semiconductor chip 200 are not dependent on the thickness of a single IC chip, and therefore can be increased compared to the case where inductors are formed on a single IC chip. Accordingly, the semiconductor module 10 is a module that aims to "increase the efficiency of signal transmission in inductive communication".

[0151] Furthermore, by increasing the size of inductors 172 and 272, the semiconductor module 10 can further expand the operational margin for inductive communication with positional offset between inductors compared to the case where inductors are formed on an IC chip.

[0152] Furthermore, inductor 172 is not exposed on the third surface 146, and inductor 272 is not exposed on the third surface 206. As a result, for example, since inductors 172 and 272 can suppress damage caused by electrostatic discharge (ESD), the semiconductor module 10 can suppress the decline in the long-term reliability of inductors 172 and 272.

[0153] Furthermore, the second semiconductor chip 600 has a different function than the first semiconductor chip 200, but has the same structure. The semiconductor module 10 includes a structure that enables inductive communication between the stacked memory chip 100 and the second semiconductor chip 600, and the stacked memory chip 100 and the second semiconductor chip 600 have the same function as the stacked memory chip 100 and the first semiconductor chip 200.

[0154] <1-2-3. Overview of IC Chip 110>

[0155] As shown in Figure 7, the IC chip 110 includes: a first surface 102 parallel to the first direction D1 and the second direction D2, a second surface 104 opposite to the first surface 102 relative to the third direction D3, a transistor layer 130, and a wiring layer 150. The first surface 102 is the side opposite to the side where the transistor layer 130 and the wiring layer 150 are disposed, and the second surface 104 is the side opposite to the side where the wiring layer 150 and the transistor layer 130 are disposed.

[0156] For example, transistor layer 130 includes: semiconductor substrate 173, device separation region 174, active region 175, transistor 176, insulating layer 177, a portion of wiring 178, and through electrode 131. For example, semiconductor substrate 173 is a Si substrate or Si wafer, and is referred to as semiconductor substrate.

[0157] For example, the through electrode 131 is formed in a manner that penetrates the transistor layer 130 and is electrically connected to the wiring 178.

[0158] As described in "1-2-1. Overview of Stacked Memory Chip 100", wiring layer 150 includes a multi-layer wiring structure with interconnected wiring and insulating layers. Wiring layer 150 includes, for example, a portion of wiring 178, insulating layer 179, wiring 180, insulating layer 181, insulating layer 182, and wiring 183. Wiring 183 may also be a through electrode.

[0159] For example, wiring 178 is provided through insulating layer 177 and electrically connected to the source or drain of transistor 176. For example, wiring 180 is provided through insulating layer 179 and electrically connected to wiring 178. For example, wiring 183 is provided through insulating layer 182 and electrically connected to wiring 180. The wiring connections shown in FIG7 are examples, and the wiring connections are not limited to the configuration shown in FIG7. The wiring connections can be appropriately changed according to the application or specifications of semiconductor module 10. In addition, the IC chip 110 included in stacked memory chip 100 is sometimes referred to as a memory chip, and the IC chip 110 included outside of stacked memory chip 100 is sometimes simply referred to as an IC chip.

[0160] <1-3. Structure of Stacked Memory Chip 100>

[0161] The functional block structure of the stacked memory chip 100 will now be described with reference to FIG8. FIG8 is a block diagram illustrating the functional block structure of the stacked memory chip 100. Structures that are the same as or similar to those in FIG1 to FIG7 will be described as needed, and sometimes the description of structures that are the same as or similar to those in FIG1 to FIG7 will be omitted.

[0162] As shown in Figure 8, the stacked memory chip 100 includes multiple memory modules 111. Each of the multiple memory modules 111 includes a memory cell array 115.

[0163] Each of the multiple memory modules 111 includes the functions of storing data contained in a received signal in a memory cell array 115 and reading data from the memory cell array 115 and sending a signal containing that data. The multiple memory modules 111 are electrically connected to multiple power supply lines 164, multiple ground lines 165 and multiple signal transmission lines 166.

[0164] For example, multiple power supply lines 164 and multiple ground lines 165 are electrically connected to multiple bumps 82 and simultaneously electrically connected to the package substrate 60, supplying power supply voltages VDD and VSS from external circuitry. Furthermore, for example, multiple signal transmission lines 166 are electrically connected to TCI-IO 112. These multiple signal transmission lines 166 are connected via inductors to the first semiconductor chip 200, the second semiconductor chip 600, and external circuitry (not shown), supplying control signals such as address signals and enable signals, as well as data signals, to control the IC chip 110 from the first semiconductor chip 200, the second semiconductor chip 600, and the external circuitry.

[0165] The memory cell array 115 includes multiple memory cells (illustration omitted). Each of the multiple memory cell arrays 115 is, for example, SRAM (Static Random Access Memory), and each of the multiple memory cells is an SRAM cell. Furthermore, the SRAM, SRAM cells, and memory module 111 for SRAM can employ technologies used in the field of SRAM. Accordingly, detailed descriptions are omitted here. Additionally, the multiple memory cell arrays 115 and the multiple memory cells can be memory cell arrays and memory cells other than SRAM, such as MRAM (Magnetoresistive Random Access Memory) and MRAM cells.

[0166] <Second Embodiment>

[0167] The semiconductor module 10A related to the second embodiment will now be described with reference to FIG9. FIG9 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 of the semiconductor module 10A. Structures that are the same as or similar to those in FIG1 to FIG8 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in FIG1 to FIG8 will be omitted.

[0168] The structure of semiconductor module 10A shown in (1) to (3) below is different from that of semiconductor module 10. (1) The IC chip 110n+3 of the stacked memory chip 100A is a TCI-IO chip 500A. (2) The inductor 172 is electrically connected to the transistor layer 130n+3 and the wiring layer 150n+3 of the stacked memory chip 100A. (3) The ends of the semiconductor substrates 173n+1 and 173n+2 of the stacked memory chip 100A and the third surface 146 are filled with an insulating film 190.

[0169] The structure of semiconductor module 10A, except for the structures shown in (1) to (3), is the same as that of semiconductor module 10. Based on this, the differences from semiconductor module 10 will be explained here. Furthermore, similar to semiconductor module 10, the number of IC chips 110 stacks, bonding and mounting structure can be appropriately changed according to the specifications and uses of semiconductor module 10A.

[0170] For example, the insulating film 190 may be made of SiO2, SiN, SiON, SiCN, or composite films thereof. Furthermore, the insulating film 190 may also cover the insulating layers exposed on the third surface 146 (e.g., insulating layers 179, 181, and 182 as shown in FIG7).

[0171] In particular, if the insulating layer exposed on the third surface 146 contains a low dielectric constant film, there is a risk that the insulating layer exposed on the third surface 146 may be contaminated by metal, which may cause corrosion or deterioration of the components in the IC chip 110 due to moisture absorption and the intrusion of impurities.

[0172] For example, the semiconductor module 10A can have an insulating film 190 covering the third surface 146. As a result, the semiconductor module 10A can suppress contamination of the semiconductor substrates 173n+1 and 173n+2 due to metal, as well as corrosion and deterioration of the components within the IC chip 110 due to moisture absorption and impurities. Accordingly, the semiconductor module 10A can maintain reliability without compromising long-term reliability.

[0173] Furthermore, semiconductor module 10A has the same function as semiconductor module 10.

[0174] <Third Embodiment>

[0175] The semiconductor module 10B related to the third embodiment will now be described with reference to FIG10. FIG10 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 of the semiconductor module 10B. Structures that are the same as or similar to those in FIG1 to FIG9 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in FIG1 to FIG9 will be omitted.

[0176] The structure of semiconductor module 10B shown in (1) and (2) below is different from that of semiconductor module 10A. (1) An insulating film 190 is filled between the semiconductor substrate 173n+2 and the third surface 146 of the stacked memory chip 100B. (2) An insulating film 190 is filled between the end of the semiconductor substrate 173n+5, the end of the semiconductor substrate 173n+6 and the end of the semiconductor substrate 173n+7 of the first semiconductor chip 200 and the third surface 206.

[0177] The structure of semiconductor module 10B, except for the structures shown in (1) and (2), is the same as that of semiconductor module 10A. Therefore, the differences from semiconductor module 10A will be explained here. Furthermore, similar to semiconductor module 10A, the number of IC chips 110 stacks, bonding, and mounting structure can be appropriately changed according to the specifications and applications of semiconductor module 10B. Moreover, as long as the structure of semiconductor module 10B is not contradictory, it can also be appropriately applied to semiconductor modules other than semiconductor modules 10 and 10A.

[0178] Semiconductor module 10B has the same function as semiconductor modules 10 and 10A.

[0179] <Fourth Implementation>

[0180] The semiconductor module 10C related to the fourth embodiment will now be described with reference to FIG11. FIG11 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 of the semiconductor module 10C. Structures that are the same as or similar to those in FIG1 to FIG10 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in FIG1 to FIG10 will be omitted.

[0181] The structure of semiconductor module 10C shown below (1) to (7) is different from that of semiconductor module 10. (1) The stacked memory chip 100A includes three IC chips 110 (IC chip 110n, IC chip 110n+1 and IC chip 110n+2). (2) The IC chips 110n, IC chip 110n+1 and IC chip 110n+2 of the stacked memory chip 100A are stacked sequentially along the third direction D3 in order of proximity to the first surface 62 of the package substrate 60. (3) The IC chip 110n+2 of the stacked memory chip 100A is a TCI-IO chip 500A. (4) An inductor 172 is disposed across the IC chips 110n, IC chip 110n+1 and IC chip 110n+2 of the stacked memory chip 100A. (5) The inductor 172 is electrically connected to the transistor layer 130n+2 and the wiring layer 150n+2 of the stacked memory chip 100A. (6) The thickness of each of the IC chips 110n, 110n+1 and 110n+2 of the stacked memory chip 100A is thickness T1. (7) The thickness of each of the IC chips 110n+4, 110n+5, 110n+6 and 110n+7 of the first semiconductor chip 200 is thickness T2.

[0182] The structure of semiconductor module 10C, except for the structures shown in (1) to (7), is the same as that of semiconductor module 10B. Furthermore, similar to semiconductor module 10B, the number of IC chips 110 stacks, bonding, and mounting structure can be appropriately changed according to the specifications and applications of semiconductor module 10C. Moreover, as long as the structure of semiconductor module 10C is not contradictory, it can also be appropriately applied to semiconductor modules other than semiconductor modules 10, 10A, and 10B. Semiconductor module 10C has the same functional effects as semiconductor module 10.

[0183] <Fifth Embodiment>

[0184] The semiconductor module 10D related to the fifth embodiment will now be described with reference to Figures 12 to 14. Figure 12 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chips 100A and 100D, bonding layer 850, third semiconductor chip 900, bump layer 800 (bumps 82), and packaging substrate 60 of the semiconductor module 10D. Figure 13 is a perspective view showing the plurality of inductors 172 included in the stacked memory chip 100A, the plurality of inductors 172 included in the stacked memory chip 100D, and the plurality of inductors 372 included in the third semiconductor chip 900. Figure 14 is a block diagram showing the functional block structure of the semiconductor module 10D. Structures that are the same as or similar to those in Figures 1 to 11 will be described as needed, and sometimes the description of structures that are the same as or similar to those in Figures 1 to 11 will be omitted.

[0185] The structure of semiconductor module 10D shown in (1) to (4) below is different from that of semiconductor module 10. (1) Includes a third semiconductor chip 900. (2) Stacked memory chips 100A and 100D are disposed on a first surface 902 and include "a first surface 142 and a second surface 144 parallel to the third direction D3 and the second direction D2 and being the outermost surface along the second direction D2", "a third surface 146 parallel to the first surface 902 of the third semiconductor chip 900 and being the outermost surface along the third direction D3 of the first surface 902", "a plurality of IC chips 110 stacked parallel to the third surface 146" and "an inductor 172 disposed across the plurality of IC chips 110". (3) The first surface 142 of the stacked memory chip 100A and the second surface 144 of the stacked memory chip 100D are F2B bonded. (4) The third surface 146 of the stacked memory chip 100A and the third surface 146 (100D) of the stacked memory chip 100D are connected to the first surface 902 of the third semiconductor chip 900 through the bonding layer 850.

[0186] The structure of semiconductor module 10D, except for the structures shown in (1) to (4), is the same as that of semiconductor module 10. Therefore, the differences from semiconductor module 10 will be explained here. Furthermore, similar to semiconductor module 10, the number of IC chips 110 stacks, bonding, and mounting structure can be appropriately changed according to the specifications and applications of semiconductor module 10D. Moreover, as long as the structure of semiconductor module 10D is not contradictory, it can also be appropriately applied to semiconductor modules other than semiconductor module 10. Furthermore, the structure and function of stacked memory chip 100D are the same as those of stacked memory chip 100A, and the structure and function of packaging substrate 60 in semiconductor module 10D are the same as those of packaging substrate 60 in semiconductor module 10. Therefore, detailed descriptions of stacked memory chip 100D and packaging substrate 60 are omitted here.

[0187] <5-1. Overview of Semiconductor Module 10D>

[0188] First, the outline of the semiconductor module 10D will be described with reference to FIG12. The third semiconductor chip 900 includes a second surface 904 that is parallel to and faces the first surface 62 of the packaging substrate 60 and is the outermost surface of the first surface 62 side, a first surface 902 that is opposite to the second surface 904 and faces the third surface 146 of the stacked memory chips 100 (100A and 100D) and is the outermost surface of the third surface 146 side, and an IC chip 110n+8. Furthermore, the third semiconductor chip 900 is connected to the third surface 146 (stacked memory chips 100A and 100D) via a bonding layer 850, and is electrically connected to the first surface 902 via a plurality of bumps 82, and is disposed between the first surface 902 and the third surface 146. The IC chip 110n+8 includes a transistor layer 130n+8 that includes a semiconductor substrate 173n+8 and a wiring layer 150n+8. For ease of explanation, the semiconductor substrate 173n+8 shown in FIG. 12 is separate from the transistor layer 130n+8. Furthermore, the third semiconductor wafer 900 includes a plurality of inductors 372 configured to be parallel to and separate from the first surface 902. For example, the plurality of inductors 372 are disposed across the wiring layer 150n+8 and the transistor layer 130n+8. The plurality of inductors 372 can perform inductive communication with each of the corresponding inductors 172 and inductor 172q. Additionally, for example, when the third semiconductor wafer 900 includes a plurality of IC wafers 110, the inductors 372 are disposed on the IC wafer 110 closest to the third surface 146.

[0189] The third semiconductor chip 900 has a structure and function that includes multiple arithmetic circuits (not shown) capable of "performing arithmetic processing of control signals and signals containing data". Furthermore, the third semiconductor chip 900 has the same structure and function as the IO chip 700A and the TCI-IO. Accordingly, the third semiconductor chip 900 is connected to the stacked memory chips 100A and 100D via inductor communication. Furthermore, the third semiconductor chip 900 is electrically connected to the packaging substrate 60 (electrode 75) via multiple bumps 82. Furthermore, the third semiconductor chip 900 is electrically connected to an external circuit (not shown) disposed on the packaging substrate 60 or an external circuit (not shown) disposed outside the semiconductor module 10D, and can receive control signals such as address signals and enable signals, as well as signals containing data, from the external circuit to control the stacked memory chips 100A and 100D, and supply (transmit) them to the stacked memory chips 100A and 100D.

[0190] As described above, the first surface 902 of the third semiconductor wafer 900 is connected to the bonding layer 850. The second surface 904 of the third semiconductor wafer 900 is connected to a plurality of bumps 82. Although not shown in the figure, for example, the third semiconductor wafer 900 is electrically connected to the bumps 82 using the through electrode 131 shown in FIG7.

[0191] Although the illustrations are omitted, for example, the stacked DRAM 300A (see Figure 14) is electrically connected to a through electrode (not shown) exposed on the second surface 144 of the stacked memory chip 100A, and the stacked DRAM 300D (see Figure 14) is electrically connected to a through electrode (not shown) exposed on the first surface 142 of the stacked memory chip 100D. Furthermore, the stacked DRAMs 300A and 300D are also connected to the third semiconductor chip 900 via a bonding layer 850, just like the stacked memory chips 100A and 100D.

[0192] <5-2. Overview of Inductive Communication in Semiconductor Module 10D>

[0193] Next, the outline of the inductor communication of the semiconductor module 10D will be explained with reference to Figure 13.

[0194] The structures of inductors 172 and 172q are the same as those of inductor 172 in the first embodiment. Therefore, a detailed description of the inductors is omitted here.

[0195] Furthermore, the inductor 372 has the same construction as the inductor 172. For example, multiple inductors 372 are configured to be parallel to a first surface 902 and a second surface 904 (parallel to the first direction D1 and the second direction D2) and separated from the first surface 902 on the first surface 902 side. The multiple inductors 372 are arranged in a matrix parallel to the first surface 902 and the second surface 904. Each of the multiple inductors 372 includes a terminal E, a terminal F, a first part 372a, a second part 372b, a third part 372c, a fourth part 372e, and a fifth part 372d.

[0196] Part 5 372d extends along the second direction D2, one end of which is electrically connected to terminal E, and the other end of which is electrically connected to one end of part 4 372e. Part 4 372e extends along the first direction D1, and the other end of which is electrically connected to one end of part 1 372a. Part 1 372a extends along the second direction D2, and the other end of which is electrically connected to one end of part 2 372b. Part 2 372b extends along the first direction D1, and the other end of which is electrically connected to one end of part 3 372c. Part 3 372c extends along the second direction D2, and the other end of which is electrically connected to terminal F.

[0197] Inductors 172 and 372 are disposed on a surface parallel to the first direction D1 and the second direction D2 (the third surface 146 and the first surface 902) and perpendicular to the third direction D3.

[0198] When viewed from the third direction D3 on a plane parallel to the first direction D1 and the second direction D2 (e.g., the first plane 902), each of the multiple inductors 172 and its corresponding inductor 372 are parallel to each other and overlap simultaneously, enabling one-to-one communication. For example, in Figure 13, inductors 172 and 372 are parallel to each other and overlap simultaneously for inductive communication, and inductors 172q and 372f are parallel to each other and overlap simultaneously for inductive communication. Furthermore, similar to the shapes of inductors 172 and 172q, the shape of inductor 372 is not limited to a rectangular shape, as long as it allows for inductive communication. This view, viewed from the third direction D3 on a plane parallel to the first direction D1 and the second direction D2 (e.g., the first plane 902), is sometimes referred to as a top view.

[0199] For example, as shown in the lower part of Figure 13, inductors 172 and 372 are arranged parallel to each other and facing each other, enabling one-to-one non-contact inductive communication through magnetic field coupling. In the example shown in the lower part of Figure 13, the magnetic field is generated by the first part 172a of inductor 172 and the first part 372a of inductor 372, and by the second part 172b of inductor 172 and the second part 372b of inductor 372. The magnetic fields generated by the third, fourth, and fifth parts of each inductor are omitted.

[0200] The magnetic field shown in Figure 13 is an example of the magnetic field generated relative to the normal vectors of the parallel surfaces of inductors 172 and 372 (e.g., the third surface 146 and the first surface 902). The actual magnetic field generated is not limited to the magnetic field shown in Figure 13.

[0201] <5-3. Structure of Semiconductor Module 10D>

[0202] Next, the functional block structure of the semiconductor module 10D will be described with reference to Figures 12 to 14.

[0203] As shown in Figure 12, Figure 13 or Figure 14, the semiconductor module 10D includes stacked memory chips 100A and 100D, stacked DRAM 300A and 300D, and a third semiconductor chip 900.

[0204] The stacked memory chip 100A and stacked DRAM 300A of semiconductor module 10D have the same structure and function as the stacked memory chip 100A and stacked DRAM 300A of semiconductor module 10. Furthermore, the stacked memory chip 100D and stacked DRAM 300D have the same structure and function as the stacked memory chip 100A and stacked DRAM 300A. Therefore, the description of the structure and function of the stacked memory chips 100A and 100D and the stacked DRAM 300A and 300D of semiconductor module 10D is omitted.

[0205] The third semiconductor chip 900 includes a plurality of TCI-IO 312s and a logic module 910. The plurality of TCI-IO 312s are electrically connected to the logic module 910. As described above, the third semiconductor chip 900 has the same structure and function as the IO chip 700A and the TCI-IO, capable of performing arithmetic processing of control signals and signals containing data. For example, the logic module 910 may also have the same structure and function as at least a portion of the IO chip 700A and the TCI-IO. For example, the third semiconductor chip 900 may also include a plurality of IC chips 110. For example, multiple TCI-IO 312s are formed on the first IC chip 110, and the logic module 910 is formed on another IC chip 110. The first IC chip 110 and the other IC chip 110 can be joined by F2B bonding.

[0206] The TCI-IO 312 includes an inductor 372 (the third inductor), a transceiver circuit 314, and a parallel-to-series converter circuit 313. The inductor 372 is electrically connected to the transceiver circuit 314 via terminals E and F. The transceiver circuit 314 is electrically connected to the parallel-to-series converter circuit 313. The parallel-to-series converter circuit 313 is electrically connected to the logic module 910.

[0207] The structure and function of inductor 372, transceiver circuit 314 and parallel-to-series conversion circuit 313 are the same as those of inductor 172, transceiver circuit 114 and parallel-to-series conversion circuit 113 in semiconductor module 10.

[0208] The semiconductor module 10D, which has the structure and function described above, has the same effect as the semiconductor module 10.

[0209] <Sixth Implementation>

[0210] The semiconductor module 10E related to the sixth embodiment will now be described with reference to FIG15. FIG15 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chips 100A and 100D, bonding layer 850, third semiconductor chip 900, bump layer 800 (bump 82) and packaging substrate 60 of the semiconductor module 10E. Structures that are the same as or similar to those in FIG1 to FIG14 will be described as needed, and sometimes the description of structures that are the same as or similar to those in FIG1 to FIG14 will be omitted.

[0211] The structure of semiconductor module 10E shown below (1) is different from that of semiconductor module 10D. (1) The ends of the semiconductor substrates 173n+1, 173n+2 and 173n+3 of the stacked memory chips 100A and 100D are filled with an insulating film 190 between the end of the semiconductor substrate 173n+1, the end of the semiconductor substrate 173n+2 and the end of the semiconductor substrate 173n+3 and the third surface 146.

[0212] The structure of semiconductor module 10E, except for the structure shown in (1), is the same as that of semiconductor module 10D. Therefore, the differences from semiconductor module 10D will be explained here. Furthermore, similar to semiconductor module 10, the number of IC chips 110 stacks, bonding, and mounting structure can be appropriately changed according to the specifications and applications of semiconductor module 10E. Moreover, the structure of semiconductor module 10E can be appropriately applied to semiconductor modules other than semiconductor module 10, provided it does not contradict each other.

[0213] Semiconductor module 10E has the same function as semiconductor modules 10B and 10D.

[0214] <Seventh Embodiment>

[0215] The semiconductor module 10F related to the seventh embodiment will now be described with reference to FIG16. FIG16 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 (bump 82) of the semiconductor module 10F. Structures that are the same as or similar to those in FIG1 to FIG15 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in FIG1 to FIG15 will be omitted.

[0216] The structure of semiconductor module 10F shown in (1) to (3) below is different from that of semiconductor module 10. (1) The thickness of IC chip 110n and IC chip 110n+3 of the stacked memory chip 100A is thickness T1, the thickness of IC chip 110n+1 is thickness T3, and the thickness of IC chip 110n+2 is thickness T4. (2) The thickness of each of IC chip 110n+4, IC chip 110n+5, IC chip 110n+6 and IC chip n+7 of the first semiconductor chip 200 is thickness T2. (3) For example, thickness T1 is the same as thickness T2, thickness T1 is thinner than thickness T3 and thicker than thickness T4.

[0217] The structure of semiconductor module 10F, except for the structures shown in (1) to (3), is the same as that of semiconductor module 10. Therefore, the differences from semiconductor module 10 will be explained here. Furthermore, similar to semiconductor module 10, the number of IC chips 110 stacks, bonding, and mounting structure can be appropriately changed according to the specifications and applications of semiconductor module 10F. Moreover, as long as the structure of semiconductor module 10F is not contradictory, it can also be appropriately applied to semiconductor modules other than semiconductor module 10.

[0218] As described above, the semiconductor module 10F includes multiple IC chips 110 of varying thicknesses. The semiconductor module 10F can be used to accommodate inductors across the multiple IC chips 110.

[0219] Semiconductor module 10F has the same function as semiconductor module 10.

[0220] <Eighth Implementation>

[0221] The semiconductor module 10G related to the eighth embodiment will now be described with reference to FIG17. FIG17 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 (bump 82) of the semiconductor module 10G. Structures that are the same as or similar to those in FIG1 to FIG16 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in FIG1 to FIG16 will be omitted.

[0222] The structure of semiconductor module 10G shown below (1) is different from that of semiconductor module 10. (1) A structure 860 having a material containing a magnetic permeability higher than that of the material contained in the stacked memory chip 100A and the material contained in the first semiconductor chip 200 is located between the third surface 146 of the stacked memory chip 100A and the third surface 206 of the first semiconductor chip 200.

[0223] The structure of semiconductor module 10G, except for the structure shown in (1), is the same as that of semiconductor module 10. Therefore, the differences from semiconductor module 10 will be explained here. Furthermore, similar to semiconductor module 10, the number of IC chips 110 stacks, bonding, and mounting structure can be appropriately changed according to the specifications and applications of semiconductor module 10G. Moreover, as long as the structure of semiconductor module 10G is not contradictory, it can also be appropriately applied to semiconductor modules other than semiconductor module 10.

[0224] For example, structure 860 may contain Ni as a material, or it may contain a material with a magnetic permeability equal to or greater than that of Ni. For example, structure 860 is coated onto the first surface 62 of packaging substrate 60 between the third surface 146 of stacked memory chip 100A and the third surface 206 of first semiconductor chip 200 using an inkjet printer or the like. For example, the width W1 between the third surface 146 of stacked memory chip 100A and the third surface 206 of first semiconductor chip 200 is 30 μm.

[0225] The semiconductor module 10F has a structure 860 containing a material with high magnetic permeability, which increases the Q value in inductive communication compared to the case without structure 860. As a result, the semiconductor module 10F can improve the efficiency of inductive communication.

[0226] Furthermore, semiconductor module 10G has the same effect as semiconductor module 10.

[0227] <Ninth Embodiment>

[0228] The semiconductor module 10H related to the ninth embodiment will now be described with reference to FIG18. FIG18 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 (bump 82) of the semiconductor module 10H. Structures that are the same as or similar to those in FIG1 to FIG17 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in FIG1 to FIG17 will be omitted.

[0229] The structure of semiconductor module 10H shown in (1) to (3) below is different from that of semiconductor module 10. (1) Multiple inductors 172 are arranged along the third direction D3. Although not shown in the figure, multiple inductors 172 are also arranged along the second direction D2. (2) Multiple inductors 272 are arranged along the third direction D3. Although not shown in the figure, multiple inductors 272 are also arranged along the second direction D2. (3) The ends (e.g., ends 101 and 103) of the inductors facing each other are equidistant from the first surface 62 of the package substrate 60.

[0230] The structure of semiconductor module 10H, except for the structures shown in (1) to (3), is the same as that of semiconductor module 10. Therefore, the differences from semiconductor module 10 will be explained here. Furthermore, similar to semiconductor module 10, the number of IC chips 110 stacks, bonding, and mounting structure can be appropriately changed according to the specifications and applications of semiconductor module 10G. Moreover, the structure of semiconductor module 10H can also be appropriately applied to semiconductor modules other than semiconductor module 10, provided that they do not contradict each other.

[0231] Multiple inductors 172 are arranged in a matrix along the first direction D1 and the third direction D3. The multiple inductors 172 are configured to be parallel to the third surface 146 and separated from the third surface 146.

[0232] Similarly, the multiple inductors 172 are arranged in a matrix along the first direction D1 and the third direction D3, and are set to be parallel to the third surface 206 and separated from the third surface 206.

[0233] For example, inductor 172o spans IC chips 110n and 110n+1, and inductor 172p spans IC chips 110n+2 and 110n+3. Terminals A and B of inductors 172o and 172p are located on IC chip 110n. Furthermore, inductor 272o spans IC chips 110n+4 and 110n+5, and inductor 272p spans IC chips 110n+6 and 110n+7. Terminals C and D of inductors 272o and 272p are located on IC chip 110n+4. IC chip 110n is a TCI-IO chip 500A, and IC chip 110n+4 is a TCI-IO chip 500C.

[0234] Furthermore, inductors 172p and 272p are arranged facing each other. The length L1 from the first surface 62 to the end 101 of inductor 172p is the same as the length L1 from the first surface 62 to the end 101 of inductor 272p. Also, the length L3 of inductor 172p along the third direction D3 is the same as the length L3 of inductor 272p along the third direction D3.

[0235] Similar to inductors 172p and 272p, inductors 172o and 272o are arranged facing each other. The length L4 from the first surface 62 to the end 103 of inductor 272o is the same as the length L4 from the first surface 62 to the end 103 of inductor 272o. Furthermore, the length L3 of inductor 172o along the third direction D3 is the same as the length L3 of inductor 272o along the third direction D3.

[0236] Inductors 172o and 272o can communicate in a non-contact manner by means of magnetic field coupling, and inductors 172p and 272p can communicate in a non-contact manner by means of magnetic field coupling.

[0237] As explained above, the semiconductor module 10H includes a configuration in which the terminals of a plurality of inductors arranged along the third direction D3 are connected to the same TCI-IO chip. That is, because the terminals of the plurality of inductors in the semiconductor module 10H are concentrated on the same TCI-IO chip, the semiconductor module 10H can suppress the dispersion of wiring contained in the plurality of inductors within the IC chip. Furthermore, for example, the wiring (e.g., the respective third and fifth portions) connecting to the terminals of adjacent inductors 172o and 172p is sufficiently separated. Accordingly, interference between the inductors can be suppressed.

[0238] Furthermore, the semiconductor module 10H has the same function as the semiconductor module 10.

[0239] <10th Embodiment>

[0240] The semiconductor module 10J related to the tenth embodiment will now be described with reference to Figures 19 and 20. Figure 19 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 (bump 82) of the semiconductor module 10J. Figure 20 is a top view illustrating the structure of the bump layer 800 of the semiconductor module 10J. Structures that are the same as or similar to those in Figures 1 to 18 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in Figures 1 to 18 will be omitted.

[0241] <10-1. Overview of Semiconductor Module 10J>

[0242] First, the outline of semiconductor module 10J will be described with reference to Figure 19.

[0243] One of the challenges of the semiconductor module 10J is to align the position of the inductor 172 on the first surface 62 of the self-packaging substrate 60 with the position of the inductor 272 on the first surface 62 of the self-packaging substrate 60 in order to improve the efficiency of signal transmission using inductive communication.

[0244] Semiconductor module 10J includes the structures shown in (1) to (6) below as one of the means to solve this problem. The structures shown in (1) to (6) below are different from those of semiconductor module 10. (1) The bump layer 800 includes not only multiple bumps 82, but also multiple bumps 82A. (2) For example, the diameter of bump 82 is length D1, and the diameter of bump 82A is length D2, where length D1 is longer than length D2. (3) For example, the length between the centers of two adjacent bumps 82 is the same as the length between the centers of two adjacent bumps 82A, which is length X1. (4) The stacked memory chip 100A is electrically connected to the packaging substrate 60 (multiple electrodes 75) through multiple bumps 82. (5) The first semiconductor chip 200 is electrically connected to the packaging substrate 60 (multiple electrodes 75) through multiple bumps 82A. (6) For example, the length L6 from the first surface 62 of the packaging substrate 60 to the first surface 202 of the first semiconductor chip 200 is longer than the length L5 from the first surface 62 of the packaging substrate 60 to the first surface 142 of the stacked memory chip 100A.

[0245] The structure of semiconductor module 10J, except for the structures shown in (1) to (6), is the same as that of semiconductor module 10. Therefore, the differences from semiconductor module 10 will be explained here. Furthermore, similar to semiconductor module 10, the number of IC chips 110 stacks, bonding, and mounting structure can be appropriately changed according to the specifications and applications of semiconductor module 10J. Moreover, as long as the structure of semiconductor module 10J is not contradictory, it can also be appropriately applied to semiconductor modules other than semiconductor module 10.

[0246] For example, lengths X1 and X2 are parallel to the first direction D1, and lengths L5, L6, L1, and L2 are parallel to the third direction D3. Furthermore, for example, lengths Y1 (see Figure 20) and Y2 (see Figure 20) are parallel to the second direction D2.

[0247] As explained above, in order to improve the efficiency of signal transmission in inductive communication, the semiconductor module 10J makes the length D2 of bump 82A longer than the length D1 of bump 82, and the length L5 longer than the length L6. As a result, the length L1 from the first surface 62 of the packaging substrate 60 to the end 101 of the inductor 172 becomes the same as the length L1 from the first surface 62 of the packaging substrate 60 to the end 101 of the inductor 272.

[0248] Accordingly, the semiconductor module 10J can align the position of the inductor 172 on the first surface 62 of the self-packaging substrate 60 with the position of the inductor 272 on the first surface 62 of the self-packaging substrate 60. As a result, since the normal vector of the inductor 172 of the stacked memory chip 100 is consistent with the normal vectors of the inductors 272 and 672 of the first semiconductor chip 200 and the second semiconductor chip 600, the semiconductor module 10J can aim to improve the efficiency of signal transmission in inductive communication.

[0249] Furthermore, semiconductor module 10J has the same function as semiconductor module 10.

[0250] <10-2. Structure of bump layer 800 in semiconductor module 10J>

[0251] Next, the structure of the bump layer 800 of the semiconductor module 10J will be described with reference to FIG20.

[0252] For example, a stacked memory chip 100A is electrically connected to a packaging substrate 60 (multiple electrodes 75) via 16 bumps 82. On the other hand, a first semiconductor chip 200 is electrically connected to the packaging substrate 60 (multiple electrodes 75) via 25 bumps 82A. Accordingly, the number of multiple bumps 82 may be different from the number of multiple bumps 82A.

[0253] For example, lengths D1 and D2 can be different, and lengths X1 and X2 can be different. Alternatively, lengths D1 and D2 can be the same, and lengths X1 and X2 can be different. Lengths Y1 and Y2 can be the same as lengths X1 and X2.

[0254] For example, the length D1 of the diameter of bump 82 and the length D2 of the diameter of bump 82A can be more than 10 μm and less than 150 μm.

[0255] As explained above, one of the objectives of the semiconductor module 10J is to align the position of the inductor 172 on the first surface 62 of the self-packaging substrate 60 with the position of the inductor 272 on the first surface 62 of the self-packaging substrate 60. This allows for adjustment of the diameters of the bumps 82 connecting the stacked memory chip 100 to the packaging substrate 60, the diameters of the bumps 82A connecting the first semiconductor chip 200 to the packaging substrate 60, as well as the lengths between the centers of adjacent bumps 82 and adjacent bumps 82A. Accordingly, the bump layer 800 of the semiconductor module 10J has a high degree of freedom.

[0256] <11th Embodiment>

[0257] The semiconductor module 10K related to the 11th embodiment will now be described with reference to FIG21. FIG21 is an enlarged cross-sectional view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 (bump 82) of the semiconductor module 10K. Structures that are the same as or similar to those in FIG1 to FIG20 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in FIG1 to FIG20 will be omitted. In addition, the illustration of the inductor is omitted in FIG21.

[0258] The structure of semiconductor module 10K shown below (1) to (4) is different from that of semiconductor module 10. (1) The stacked memory chip 100A includes a side power supply wiring 162, a side ground wiring 163, and an insulating film 52. (2) The first semiconductor chip 200 includes a side power supply wiring 262, a side ground wiring 263, and an insulating film 54. (3) The semiconductor module 10K includes a plurality of bumps 84. (4) Each of the plurality of bumps 84 electrically connects the side power supply wiring 162 to the side power supply wiring 262 corresponding to its respective bump 84, and electrically connects the side ground wiring 163 to the side ground wiring 263 corresponding to its respective bump 84.

[0259] The structure of semiconductor module 10K, except for the structures shown in (1) to (4), is the same as that of semiconductor module 10. Therefore, the differences from semiconductor module 10 will be explained here. Furthermore, similar to semiconductor module 10, the number of IC chips 110 stacks, bonding, and mounting structure can be appropriately changed according to the specifications and applications of semiconductor module 10K. Moreover, as long as the structure of semiconductor module 10K is not contradictory, it can also be appropriately applied to semiconductor modules other than semiconductor module 10.

[0260] For example, power supply wiring 164 (see Figure 8) is exposed on wiring layer 150n (see Figure 6) of IC chip 110n and wiring layer 150n+2 (see Figure 6) of IC chip 110n+2. Side power supply wiring 162 covers power supply wiring 164 and is electrically connected to it. Furthermore, side power supply wiring 162 is connected to the third surface 146. Similarly, for example, ground wiring 165 (see Figure 8) is exposed on wiring layer 150n+1 (see Figure 6) of IC chip 110n+1. Side ground wiring 163 covers ground wiring 165 and is electrically connected to it. Furthermore, side ground wiring 163 is connected to the third surface 146.

[0261] Furthermore, the insulating film 52 is disposed on the side power wiring 162, the side ground wiring 163, and the third surface 146 that is not connected to the side power wiring 162 and the side ground wiring 163. At this time, the side power wiring 162 and the side ground wiring 163 are exposed from the insulating film 52.

[0262] For example, the side power wiring 262 has the same structure as the side power wiring 162, covering the power wiring (not shown) exposed from the wiring layer 150n+4 (see Figure 6) of IC chip 110n+6 and the wiring layer 150n+6 (see Figure 6) of IC chip 110n+6, and is electrically connected. The side ground wiring 263 has the same structure as the side ground wiring 163, covering the ground wiring (not shown) exposed from the wiring layer 150n+5 (see Figure 6) of IC chip 110n+5, and is electrically connected.

[0263] Furthermore, the insulating film 54 is disposed on the side power supply wiring 262, the side grounding wiring 263, and the third surface 206 that is not connected to the side power supply wiring 262 and the side grounding wiring 263. At this time, the side power supply wiring 262 and the side grounding wiring 263 are exposed from the insulating film 54.

[0264] Among the plurality of bumps 84, the bumps 84 corresponding to the side power wiring 162 and the side power wiring 262 electrically connect the side power wiring 162 and the side power wiring 262. Furthermore, among the plurality of bumps 84, the bumps 84 corresponding to the side ground wiring 163 and the side ground wiring 263 electrically connect the side ground wiring 163 and the side ground wiring 263.

[0265] Insulating films 52 and 54 are formed using the same material as insulating film 190.

[0266] As explained above, semiconductor module 10K can use side wiring to electrically connect adjacent chips to each other. As a result, for example, semiconductor module 10K can share the power supply voltages VDD and VSS supplied to the power wiring between adjacent chips.

[0267] Furthermore, semiconductor module 10K has the same effect as semiconductor module 10.

[0268] <12th Embodiment>

[0269] The structure of the sealing ring 160 and signal transmission wiring 166 related to the 12th embodiment of the present invention will now be described with reference to FIG22. FIG22 is a top view showing the structure of the sealing ring 160 and ground wiring 165, and is a cross-sectional view showing the end cross-sectional structure of the sealing ring 160 and signal transmission wiring 166 along the E1-E2 line in the top view. Structures that are the same as or similar to those in FIG1 to FIG21 will be described as needed, and sometimes the description of structures that are the same as or similar to those in FIG1 to FIG21 will be omitted. In addition, the structure of the sealing ring 160 and signal transmission wiring 166 related to the 12th embodiment can be appropriately applied to semiconductor modules related to various embodiments, as long as they do not contradict each other.

[0270] IC chip 110 includes a sealing ring 160. The sealing ring 160 is disposed on the outer periphery 192 and formed on the wiring layer 150. Signal transmission wiring 166 is formed overlapping the sealing ring 160 and is formed on the side closer to the third surface 146 than the sealing ring 160. For example, the outer periphery 192 is the peripheral portion of IC chip 110, which is the portion close to each surface (e.g., the first surface 142, the second surface 144, the third surface 146, and the fourth surface 148) of the stacked memory chip 100, the first semiconductor chip 200, and the second semiconductor chip 600. As explained in "1-1. Overview of Semiconductor Module 10", the wiring layer 150 includes a multilayer wiring structure. Furthermore, for example, when the signal transmission wiring 166 included in semiconductor modules 10D and 10E is formed overlapping the sealing ring 160, the signal transmission wiring 166 is formed on the side closer to the first surface 902 than the sealing ring 160.

[0271] For example, the wiring layer 150, extending from the semiconductor substrate 173a towards the insulating layer 182, comprises a 7-layer (layer 1 to layer 7) multilayer wiring structure. The 7-layer multilayer wiring structure includes: insulating layer 151a, via 151b, insulating layer 152a, wiring 152b, insulating layer 153a, via 153b, insulating layer 154a, wiring 154b, insulating layer 155a, via 155b, insulating layer 156a, wiring 156b, insulating layer 182, and wiring 183. The insulating layer 151a of the first layer is formed on the transistor layer 130, and the via 151b of the first layer penetrates the insulating layer 151a and is formed on the transistor layer 130. The insulating layer 152a of the second layer is formed on the insulating layer 151a and the via 151b, and the wiring 152b of the second layer penetrates the insulating layer 152a and is formed on the via 151b. Comparing with the first and second layers of a multilayer wiring structure, the insulating layer 153a and via 153b of the third layer, the insulating layer 154a and wiring 154b of the fourth layer, the insulating layer 155a and via 155b of the fifth layer, the insulating layer 156a and wiring 156b of the sixth layer, and the insulating layer 182 and wiring 183 of the seventh layer are formed sequentially from the semiconductor substrate 173 side toward the insulating layer 182. For example, signal transmission wiring 166, power wiring 164 (see Figure 8), and ground wiring 165 (see Figure 8) are formed using wiring 183. A portion of inductors 172, 272, 372, or 672 can also be formed using wiring 183.

[0272] For example, insulating layers 182, 156a, 155a, and 154a are formed using insulating materials that are different from materials with low dielectric constants (low-k materials). Insulating materials forming insulating layers 182, 156a, 155a, and 154a include, for example, SiO2, SiCN, SiN, and SiON.

[0273] For example, the sealing ring 160 has the function of inhibiting the intrusion of moisture, impurities, etc., from each side of the stacked memory chip 100, the first semiconductor chip 200, and the second semiconductor chip 600. As a result, the semiconductor module related to each embodiment of the present invention can inhibit the corrosion and deterioration of wiring accompanied by moisture absorption and the intrusion of impurities through the sealing ring 160.

[0274] <13th Embodiment>

[0275] The sealing ring 160n and inductor 172 related to the 13th embodiment will now be described with reference to Figures 23-26. Figure 23 is a top view showing the structure of the sealing ring 160n and inductor 172. Figure 24 is a cross-sectional view showing the end cross-sectional structure of the sealing ring 160n and inductor 172 along lines E3-E4 of Figure 23. Figure 25 is a cross-sectional view showing the end cross-sectional structure of the inductor 172 along lines E5-E6 of Figure 23. Figure 26 is a cross-sectional view showing the end cross-sectional structure of the inductor 172 along lines E7-E8 of Figure 23. Structures that are the same as or similar to those in Figures 1-22 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in Figures 1-22 will be omitted. Furthermore, the structures of the sealing ring 160n and inductor 172 related to the 13th embodiment can be appropriately applied to semiconductor modules related to various embodiments, as long as they do not contradict each other.

[0276] The inductor 172 shown in Figures 23-26, when viewed from the end face, is an inductor with multiple turns formed across multiple IC chips 110, and is formed on the third surface 146 side, closer to the sealing ring 160n. Furthermore, the inductor 172 shown in Figures 23-26 is the inductor 172 included in the semiconductor module associated with each embodiment.

[0277] As an example, the inductor 172 shown in Figures 23-26 has two turns, but the number of turns of inductor 172 is not limited to two turns; it can have one turn or more than three turns. The number of turns of the inductor can be appropriately selected according to the specifications and applications of the semiconductor module related to each implementation.

[0278] Furthermore, as an example, the inductor 172 formed across multiple IC chips as shown in Figures 23 to 26 is connected to the semiconductor substrate 173 and includes a through electrode 131 that penetrates the semiconductor substrate 173. However, an insulating film different from the semiconductor substrate 173 may also be provided between the through electrode 131 and the semiconductor substrate 173.

[0279] Furthermore, as an example, the inductor formed across multiple IC chips shown in Figures 23 to 26 is inductor 172, but the inductor formed across multiple IC chips shown in Figures 23 to 26 can be inductor 272, inductor 372, or inductor 672.

[0280] As shown in Figures 24-26, the first surface 102n of IC chip 110n is bonded to the second surface 104n+1 of IC chip 110n+1. As an example, inductor 172 is disposed across two IC chips (IC chips 110n and 110n+1). Inductor 172 may also be disposed across three or more IC chips 110.

[0281] Figure 25 illustrates a cross-sectional view (structure) of the inductor 172 viewed from the third surface 146 towards the fourth surface 148. When viewed from the third surface 146 towards the fourth surface 148, the inductor 172 shown in Figure 25 is an example of a two-turn inductor that spans two IC chips (IC chips 110n and 110n+1). Furthermore, the inductor 172 is configured to be parallel to and separate from the third surface 146 and the fourth surface 148.

[0282] The inductor 172 shown in Figures 23-26 includes: terminal A, terminal B, wiring 183j, via 184j, wiring 156j, via 155j, wiring 154j, via 153j, wiring 152j, via 151j, through electrode 131j, wiring 196j, wiring 183nj, via 184nj, wiring 156nj, via 155nj, wiring 154nj, via 153nj, wiring 152nj, via 153nk, wiring 154nk, via 155nk, wiring 156nk, via 184nk, wiring 183nk, wiring 196nk, through electrode 131k, via 151k, wiring 152k, via 153k, and wiring. 154k, via 155k, wiring 156k, via 184k, wiring 183k, via 184m, wiring 156m, via 155m, wiring 154m, via 153m, wiring 152m, via 151m, through electrode 131m, wiring 196nm, wiring 183nm, via 184nm, wiring 156nm, via 155nm, wiring 154nm, via 155no, wiring 156no, via 184no, wiring 183no, wiring 196no, through electrode 131o, via 151o, wiring 152o, via 153o, wiring 154o, via 155o, wiring 156o, via 184o and wiring 183o.

[0283] IC chip 110n includes: wiring 196j, wiring 183nj, via 184nj, wiring 156nj, via 155nj, wiring 154nj, via 153nj, wiring 152nj, via 153nk, wiring 154nk, via 155nk, wiring 156nk, via 184nk, wiring 183nk, wiring 196nk, wiring 196nm, wiring 183nm, via 184nm, wiring 156nm, via 155nm, wiring 154nm, via 155no, wiring 156no, via 184no, wiring 183no, wiring 196no, and sealing ring 160n. The function and structure of sealing ring 160n are the same as those of sealing ring 160. The function and structure of sealing ring 160n will be described as required.

[0284] Widget 152nj is formed on the same layer as wiring 152b of IC chip 110n. Vias 153nj and 153nk are formed on the same layer as via 153b of IC chip 110n. Widgets 154nj, 154nk, and 154nm are formed on the same layer as wiring 154b of IC chip 110n. Vias 155nj, 155nk, 155nm, and 155no are formed on the same layer as via 155b of IC chip 110n. Widgets 156nj, 156nk, 156nm, and 156no are formed on the same layer as wiring 156b of IC chip 110n. Widgets 183nj, 183nk, 183nm, and 183no are formed on the same layer.

[0285] Vias 184nj, via 184nk, via 184nm and via 184no are formed on the third direction D3 between the insulating layer 156a, wiring 156nj, wiring 156nk, wiring 156nm and wiring 156no on which the IC wafer 110n is formed, and the layer on which wiring 183nj, wiring 183nk, wiring 183nm and wiring 183no are formed.

[0286] Wiring 196j, wiring 196nk, wiring 196nm and wiring 196no are formed on wiring 183nj, wiring 183nk, wiring 183nm and wiring 183no.

[0287] IC chip 110n+1 includes: terminal A, terminal B, wiring 183j, via 184j, wiring 156j, via 155j, wiring 154j, via 153j, wiring 152j, via 151j, through electrode 131j, through electrode 131k, via 151k, wiring 152k, via 153k, wiring 154k, via 155k, wiring 156k, and via 18. 4k, wiring 183k, via 184m, wiring 156m, via 155m, wiring 154m, via 153m, wiring 152m, via 151m, through electrode 131m, through electrode 131o, via 151o, wiring 152o, via 153o, wiring 154o, via 155o, wiring 156o, via 184o, wiring 183o, and sealing ring 160n+1. The function and structure of sealing ring 160n+1 are the same as those of sealing ring 160. The function and structure of sealing ring 160n+1 will be described as required.

[0288] Vias 151j, 151k, 151m, and 151o are formed on the same layer as via 151b of IC chip 110n+1. Wiring 152j, 152k, 152m, and 152o are formed on the same layer as wiring 152b of IC chip 110n+1. Vias 153j, 153k, 153m, and 153o are formed on the same layer as via 153b of IC chip 110n+1. Wiring 154j, 154k, 154m, and 154o are formed on the same layer as wiring 154b of IC chip 110n+1. Vias 155j, 155k, 155m, and 155o are formed on the same layer as via 155b of IC chip 110n+1. Widgets 156j, 156k, 156m, and 156o are formed on the same layer as wiring 156b of IC chip 110n+1. Widgets 183j, 183k, and 183o are formed on the same layer. Vias 184j, 184k, 184m, and 184o are formed on the same layer.

[0289] Through electrodes 131j, 131k, 131m, and 131o are formed in a manner that penetrates the transistor layer 130n+1 and are connected to vias 151j, 151k, 151m, and 151o. Furthermore, if IC wafer 110n+1 is bonded to IC wafer 110n, then through electrodes 131j, 131k, 131m, and 131o are connected to wirings 196j, 196nk, 196nm, and 196no of IC wafer 110n.

[0290] The connection of inductor 172 is explained here.

[0291] Wiring 183j extends along the first direction D1, with one end electrically connected to terminal B and the other end electrically connected to via 184j. Wiring 183j is configured to overlap and cross both sealing rings 160n and 160n+1. Via 184j, wiring 156j, via 155j, wiring 154j, via 153j, wiring 152j, via 151j, through electrode 131j, wiring 196j, wiring 183nj, via 184nj, wiring 156nj, via 155nj, wiring 154nj, and via 153nj extend along the third direction D3 and are electrically connected. Wiring 154nj is electrically connected to one end of wiring 152nj. Wiring 152nj extends along the second direction D2, and the other end of wiring 152nj is electrically connected to via 153nk.

[0292] Guide hole 153nk, wiring 154nk, guide hole 155nk, wiring 156nk, guide hole 184nk, wiring 183nk, wiring 196nk, through electrode 131k, guide hole 151k, wiring 152k, guide hole 153k, wiring 154k, guide hole 155k, wiring 156k, and guide hole 184k extend along the third direction D3 and are electrically connected. Guide hole 184k is electrically connected to one end of wiring 183k. Wiring 183k extends along the second direction D2, and the other end of wiring 183k is electrically connected to guide hole 184k. Via 184nm, wiring 156nm, via 155nm, wiring 154nm, via 153nm, wiring 152nm, via 151nm, through electrode 131nm, wiring 196nm, wiring 183nm, via 184nm, wiring 156nm, and via 155nm extend along the third direction D3 and are electrically connected. Via 155nm is electrically connected to one end of wiring 154nm. Wiring 154nm extends along the second direction D2, and the other end of wiring 154nm is electrically connected to via 155no.

[0293] Guide hole 155no, wiring 156no, guide hole 184no, wiring 183no, wiring 196no, through electrode 131o, guide hole 151o, wiring 152o, guide hole 153o, wiring 154o, and guide hole 155o extend along the third direction D3 and are electrically connected. Guide hole 155o is electrically connected to one end of wiring 156o. Wiring 156o extends along the second direction D2, then bends towards the first direction D1 and extends along the first direction D1.

[0294] The other end of the wiring 156o extending along the first direction D1 is electrically connected to the via 184o. The via 184o extends along the third direction D3 and is electrically connected to one end of the wiring 183o. The wiring 183o extends along the first direction D1, and the other end of the wiring 183o is electrically connected to terminal A. The wiring 183o is configured to overlap with and cross the sealing ring 160.

[0295] Wiring 183g extends along a first direction D1, overlapping and crossing the sealing ring 160. After crossing the sealing ring 160, wiring 183g bends in a second direction D2 and extends along that direction. Then, after extending along the second direction D2, wiring 183g bends in the first direction D1 and extends along that direction. The other end of wiring 183g extending along the second direction D2 is electrically connected to terminal A.

[0296] As shown in Figure 23, wiring 183j and wiring 183o, which overlap with the sealing ring 160, are formed on the same plane and are formed parallel to the first direction D1.

[0297] As shown in Figure 25, the through-electrode 131j, through-hole 196j, through-hole 183nj, through-hole 184nj, through-hole 156nj, through-hole 155nj, through-hole 154nj, through-hole 153nj, through-hole 152nj, through-hole 151j, through-hole 183nj, through-hole 154nj, through-hole 155nj, through-hole 154nj, through-hole 153nj, through-hole 152nj, through-hole 153nk, through-hole 154nk, through-hole 155nk, through-hole 156nk, through-hole 184nk, through-hole 183nk, through-hole 196nk, through-electrode 131k, through-hole 151k, through-hole 152k, through-hole 153k, through-hole 154k, and through-hole 155k are connected via wiring 183j, through-hole 184j, through-hole 156nj, through-hole 155k, through-hole 156nj, through-hole 154k, and through-hole 155k. Wiring 156k, via 184k, wiring 183k, via 184m, wiring 156m, via 155m, wiring 154m, via 153m, wiring 152m, via 151m, through electrode 131m, wiring 196nm, wiring 183nm, via 184nm, wiring 156nm, via 155nm, wiring 154nm, via 155no, wiring 156no, via 184no, wiring 183no, wiring 196no, through electrode 131o, via 151o, wiring 152o, via 153o, wiring 154o, via 155o, and wiring 156o are used to form the actual coil portion of the two-turn inductor 172.

[0298] That is, the inductor 172 is configured as follows: wiring 183k, which is disposed on the same layer as wiring 183j and wiring 183o, which are "overlapping on the sealing rings 160n and 160n+1 and disposed on the same layer as each other" but do not overlap on the sealing ring 160; and multiple wirings, which are disposed on the same layer as the wiring constituting the sealing rings 160n and 160n+1 and span two IC chips (110n and 110n+1).

[0299] Furthermore, as shown in Figures 23 and 25, the actual coil portion of the two-turn inductor 172 is not exposed on the third surface 146.

[0300] The actual coil portion of the inductor 172, which is disposed across two IC chips on the third side 146, is formed using wiring that constitutes a sealing ring 160. In this way, the wiring 183j and wiring 183o connected to the actual coil portion of the inductor 172 can overlap and cross the sealing rings 160n and 160n+1.

[0301] As a result, the two-turn inductor 172 constructed in the manner described above is insulated from the sealing rings 160n and 160n+1 through the insulating layers 151a~182 disposed on each of the two IC chips 110n and 110n+1, and will not be short-circuited with the sealing rings 160n and 160n+1.

[0302] Figures 23-26 illustrate a single inductor 172, but IC chips 110n and 110n+1 contain multiple inductors 172. For example, the multiple inductors 172 are arranged along a second direction D2.

[0303] <14th Embodiment>

[0304] The sealing ring 160 and inductor 172f related to the 14th embodiment will now be described with reference to Figures 27-29. Figure 27 is a top view showing the structure of the sealing ring 160 and inductor 172f. Figure 28 is a cross-sectional view showing the end cross-sectional structure of the sealing ring 160 and inductor 172f along lines E9-E10 of Figure 27. Figure 29 is a cross-sectional view showing the end cross-sectional structure of the sealing ring 160 and inductor 172f shown in Figure 27 viewed from the depth direction from the third surface 146 toward the fourth surface 148. The function and structure of the sealing ring 160 related to the 14th embodiment are the same as those of the sealing ring 160 related to the 12th embodiment. The function and structure of the sealing ring 160 related to the 14th embodiment will be described as needed. Structures that are the same as or similar to those in Figures 1-26 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in Figures 1-26 will be omitted. Furthermore, the structures of the sealing ring 160 and the inductor 172f related to the 14th embodiment can be appropriately applied to the semiconductor modules related to each embodiment, as long as they do not contradict each other.

[0305] In the 14th embodiment, the inductor 172f is formed on an IC chip 110. Its other structure is the same as that of inductor 172. The same structure as inductor 172 will be described as needed. Furthermore, as an example, the inductor formed on an IC chip shown in Figures 27-29 is inductor 172f, but the inductors 272, 372, and 672 of the semiconductor modules related to each embodiment include the same structure as inductor 172f, including a structure capable of one-to-one non-contact inductive communication with inductor 172f.

[0306] As shown in Figure 27, inductor 172f, like inductor 172, includes terminals A and B, a first portion 172a, a second portion 172b, a third portion 172c, a fourth portion 172e, and a fifth portion 172d. Inductor 172f, viewed from the second surface 104 of IC chip 110 along the third direction D3, is an example of a single-turn inductor. The fifth portion 172d extends along the second direction D2, with one end electrically connected to terminal B and the other end electrically connected to one end of the fourth portion 172e. The fourth portion 172e extends along the first direction D1, with the other end electrically connected to one end of the first portion 172a. The first portion 172a extends along the second direction D2, with the other end electrically connected to one end of the second portion 172b. Part 2 172b extends along the first direction D1, and the other end of part 2 172b is electrically connected to one end of part 3 172c. Part 3 172c extends along the second direction D2, and the other end of part 3 172c is electrically connected to terminal A.

[0307] As shown in Figures 27-29, inductor 172f is parallel to the first surface 102 and the second surface 104. Furthermore, the first portion 172a of inductor 172f corresponds to the end of inductor 172f on the third surface 146 side. The first portion 172a is not exposed on the third surface 146. Inductor 172f is formed by overlapping and extending across the sealing ring 160. That is, the length of the sealing ring 160 extending along the first direction D1 is shorter than the length of the inductor 172f extending along the first direction D1. For example, inductor 172f is formed using wiring 183b. Furthermore, for example, when inductor 172f included in semiconductor modules 10D and 10E is formed by overlapping the sealing ring 160, inductor 172f is formed closer to the first surface 902 side than the sealing ring 160.

[0308] Furthermore, as shown in FIG29, the inductor 172f and the sealing ring 160, viewed along the depth direction from the third surface 146 toward the fourth surface 148, are stacked from the semiconductor substrate 173 side toward the wiring layer 150 side below the third direction D3. The vias 151b, 153b, and 155b forming the sealing ring 160 and the wirings 152b, 154b, and 156b forming the sealing ring 160 extend along the second direction D2. The lengths of the vias 151b, 153b, and 155b and the wirings 152b, 154b, and 156b along the second direction D2 are longer than the length of the first portion 172a of the inductor 172f along the second direction D2.

[0309] Figures 27-29 illustrate a single inductor 172f, but the IC chip 110 includes multiple inductors 172f. For example, the multiple inductors 172f are arranged along the second direction D2.

[0310] Inductor 172f is covered by insulating layer 182 and is not exposed on the side of IC chip 110. Furthermore, inductor 172f spans sealing ring 160 and is formed to be shorter than sealing ring 160 when viewed from the third side 146. As a result, inductor 172f, through insulating layer 182 and sealing ring 160, can suppress corrosion and deterioration of wiring caused by moisture absorption, impurities, etc.

[0311] Furthermore, by suppressing corrosion and deterioration of the wiring caused by moisture absorption and the intrusion of impurities, the insulation between adjacent inductors 172f can be ensured, and short circuits between adjacent inductors 172f can be suppressed. As a result, for example, the distance between adjacent inductors 172f and the distance between inductor 172f and inductor 272 can be shortened. Accordingly, the semiconductor module including inductor 172f in various embodiments can increase the number of inductors 172f in IC chip 110, while improving the communication quality between inductor 172f and inductor 272.

[0312] Furthermore, since the inductor 172f is not exposed on any surface of the IC chip 110, the semiconductor module associated with each embodiment includes a structure capable of suppressing damage to the inductor 172f caused by ESD. As a result, for example, an ESD protection circuit for the inductor 172f is no longer required. Accordingly, the power consumption generated by the ESD protection circuit of the semiconductor module associated with each embodiment can be suppressed, and the power consumption of the semiconductor module associated with each embodiment can be reduced. Moreover, the signal delay generated by the ESD protection circuit can be suppressed, making high-speed operation of the semiconductor module associated with each embodiment possible.

[0313] Accordingly, semiconductor modules associated with various embodiments of the inductor with the structures shown in Figures 27 to 29 can maintain reliability without compromising long-term reliability.

[0314] <15th Embodiment>

[0315] The sealing ring 160 and inductor 172g related to the 15th embodiment will now be described with reference to Figures 30-33. Figure 30 is a top view showing an example of the structure of the sealing ring 160 and inductor 172g. Figure 31 is a cross-sectional view showing the end cross-sectional structure of the inductor 172g along lines E11-E12 of Figure 30. Figure 32 is a cross-sectional view showing the end cross-sectional structure of the sealing ring 160 and inductor 172g along lines E13-E14 of Figure 30. Figure 33 is a cross-sectional view showing the end cross-sectional structure of the inductor 172g along lines E15-E16 of Figure 30. The function and structure of the sealing ring 160 related to the 15th embodiment are the same as those of the sealing ring 160 related to the 12th embodiment. The function and structure of the sealing ring 160 related to the 15th embodiment will be described as needed. The same or similar structures as those in Figures 1 to 29 will be described as needed, and sometimes the description of the same or similar structures as those in Figures 1 to 29 will be omitted. In addition, the structures of the sealing ring 160 and the inductor 172g related to the 15th embodiment can be appropriately applied to the semiconductor modules related to each embodiment, as long as they do not contradict each other.

[0316] The inductor 172g associated with the 15th embodiment is formed on an IC chip 110 in the same way as the inductor 172f associated with the 14th embodiment. Its other structure is the same as that of inductor 172. The same structure as inductor 172 will be described as needed. Furthermore, as an example, the inductor formed on an IC chip shown in Figures 30-33 is inductor 172g, but the inductors 272, 372, and 672 of the semiconductor modules associated with each embodiment have the same structure as inductor 172g, including a structure capable of one-to-one non-contact inductive communication with inductor 172g. In addition, the IC chip 110 includes a plurality of inductors 172g arranged along the second direction D2.

[0317] The inductor 172g shown in Figures 30-33 includes: terminal A, terminal B, wiring 152c, via 153c, wiring 154c, via 155c, wiring 156c, via 184a, wiring 183c, via 184b, wiring 156d, via 155d, wiring 154d, via 155e, wiring 156e, via 184c, wiring 183d, via 184d, wiring 156f, via 155f, wiring 154e, via 155g, wiring 156g, via 184e, wiring 183e, via 184f, wiring 156h, via 184g, wiring 183f, via 184h, wiring 156i, via 184i, and wiring 183g.

[0318] When the inductor 172g is viewed through the IC chip 110 from the second surface 104 side along the third direction D3, it is an example of a three-turn inductor. Furthermore, the inductor 172g is parallel to the first surface 102 and the second surface 104 and perpendicular to the third surface 146 and the fourth surface 148.

[0319] Wiring 152c is formed on the same layer as wiring 152b, and via 153c is formed on the same layer as via 153b. Wiring 154c, wiring 154d, and wiring 154e are formed on the same layer as wiring 154b. Vias 155c, via 155d, via 155e, via 155f, and via 155g are formed on the same layer as via 155b. Wiring 156c, wiring 156d, wiring 156e, wiring 156f, wiring 156g, wiring 156h, and wiring 156i are formed on the same layer as wiring 156b. Wiring 183c, wiring 183d, wiring 183e, wiring 183f, and wiring 183g are formed on the same layer as wiring 183b.

[0320] Guide holes 184a, 184b, 184c, 184d, 184e, 184f, 184g, 184h, and 184i are formed in the third direction D3 between the layer on which the insulating layer 156a and wirings 156b to 156i are formed and the layer on which wirings 183c, 183d, 183e, 183f, and 183g are formed.

[0321] Wiring 152c extends along the second direction D2, with one end electrically connected to terminal F and the other end electrically connected to via 153c. Via 153c, wiring 154c, via 155c, wiring 156c, and via 184a extend along the third direction D3 and are electrically connected. Via 184a is electrically connected to one end of wiring 183c. Wiring 183c extends along the first direction D1, with the other end electrically connected to via 184b. Wiring 183c is configured to overlap with and cross the sealing ring 160.

[0322] Via 184b, wiring 156d, and via 155d extend along the third direction D3 and are electrically connected. Via 155d is electrically connected to one end of wiring 154d. Wiring 154d extends along the second direction D2, and the other end of wiring 154d is electrically connected to via 155e. Via 155e, wiring 156e, and via 184c extend along the third direction D3 and are electrically connected. Via 184c is electrically connected to one end of wiring 183d. Wiring 183d extends along the first direction D1, and the other end of wiring 183d is electrically connected to via 184d. Wiring 183d is configured to overlap with and cross the sealing ring 160.

[0323] Via 184d, wiring 156f, and via 155f extend along the third direction D3 and are electrically connected. Via 155f is electrically connected to one end of wiring 154e. Wiring 154e extends along the second direction D2, and the other end of wiring 154e is electrically connected to via 155g. Via 155g, wiring 156g, and via 184e extend along the third direction D3 and are electrically connected. Via 184e is electrically connected to one end of wiring 183e. Wiring 183e extends along the first direction D1, and the other end of wiring 183e is electrically connected to via 184f. Wiring 183e is configured to overlap with and cross the sealing ring 160.

[0324] Via 184f extends along the third direction D3 and is electrically connected to one end of wiring 156h. Wiring 156h extends along the second direction D2, and the other end of wiring 156h is electrically connected to via 184g. Via 184g extends along the third direction D3 and is electrically connected to one end of wiring 183f. Wiring 183f extends along the first direction D1, and the other end of wiring 183f is electrically connected to via 184h. Wiring 183f is configured to overlap with and cross the sealing ring 160.

[0325] The via 184h extends along the third direction D3 and is electrically connected to one end of the wiring 156i. The wiring 156i extends along the second direction D2, and the other end of the wiring 156i is electrically connected to the via 184i. The via 184i extends along the third direction D3 and is electrically connected to one end of the wiring 183g.

[0326] Wiring 183g extends along a first direction D1, overlapping and crossing the sealing ring 160. After crossing the sealing ring 160, wiring 183g bends in a second direction D2 and extends along that direction. Then, after extending along the second direction D2, wiring 183g bends in the first direction D1 and extends along that direction. The other end of wiring 183g extending along the second direction D2 is electrically connected to terminal A.

[0327] As shown in Figure 30, wiring 183c, wiring 183d, wiring 183e, wiring 183f and wiring 183g that overlap with the sealing ring 160 are formed on the same plane, and a portion of wiring 183c, wiring 183e, wiring 183d, wiring 183e, wiring 183f and wiring 183g are formed parallel to the first direction D1.

[0328] As shown in Figure 30 or Figure 31, wiring 152c, wiring 154e, wiring 156i, and a portion of wiring 183g are stacked and overlap each other along the third direction D3, and formed parallel to each other along the second direction D2. Wiring 152c is formed on the same layer as wiring 152b forming the sealing ring 160, wiring 154e is formed on the same layer as wiring 154b forming the sealing ring 160, and wiring 156i is formed on the same layer as wiring 156b forming the sealing ring 160.

[0329] As shown in Figure 30 or Figure 33, a portion of wiring 154d, wiring 156h, and wiring 183g are stacked and overlap each other along the third direction D3, and are formed parallel to each other along the second direction D2. Wiring 154d is formed on the same layer as wiring 154b constituting the sealing ring 160, and wiring 156h is formed on the same layer as wiring 156b constituting the sealing ring 160.

[0330] As shown in Figure 30, wiring 183c and wiring 183e face each other, as do wiring 183d and wiring 183f. As shown in Figure 30, Figure 31 or Figure 33, wiring 154d faces each other, as do wiring 154e, and wiring 156h faces each other.

[0331] That is, the inductor 172g is constructed by the following: wiring 183c and wiring 183e and wiring 183d and wiring 183f overlap the sealing ring 160, are formed on the same layer and face each other; wiring 154d and wiring 154e are formed on the same layer as wiring 154b constituting the sealing ring 160 and face each other; and wiring 156h and wiring 156i are formed on the same layer as wiring 156b constituting the sealing ring 160.

[0332] Furthermore, as shown in Figures 30 and 33, wiring 183g, wiring 156h, and wiring 154d overlap each other and correspond to the ends of the third surface 146 side of inductor 172g. Wiring 183g, wiring 156h, and wiring 154d are not exposed on the third surface 146. Furthermore, wiring 183g, wiring 156i, wiring 154e, and wiring 152c overlap each other and correspond to the ends opposite to the third surface 146 side of inductor 172g.

[0333] By forming the end of the third surface 146 side of the inductor 172g and the end opposite to the third surface 146 side of the inductor 172g as shown in Figures 30 and 33, the wiring 183c~183g of the inductor 172g can overlap the sealing ring 160 and cross the sealing ring 160 in the cross section shown in Figure 32.

[0334] As a result, the three-turn inductor 172g associated with the 15th embodiment is insulated from the sealing ring 160 through the insulating layers 151a-182, and will not short-circuit with the sealing ring 160.

[0335] Accordingly, the semiconductor module associated with each embodiment including inductor 172g has the same effect as the semiconductor module associated with each embodiment including inductor 172f.

[0336] <16th Embodiment>

[0337] The sealing ring 160 and power wiring 165b related to the 16th embodiment will now be described with reference to FIG34. FIG34 is a top view illustrating an example of the structure of the sealing ring 160 and power wiring 165b, and is a cross-sectional view showing the end cross-sectional structure of the sealing ring 160 and power wiring 165b along lines F1-F2 in the top view. The function and structure of the sealing ring 160 related to the 16th embodiment are the same as those of the sealing ring 160 related to the 12th embodiment. The function and structure of the sealing ring 160 related to the 16th embodiment will be described as needed. Structures that are the same as or similar to those in FIG1 to 33 will be described as needed, and sometimes the description of structures that are the same as or similar to those in FIG1 to 33 will be omitted. Furthermore, the structures of the sealing ring 160 and power wiring 165b related to the 16th embodiment can be appropriately applied to semiconductor modules related to various embodiments as long as they do not contradict each other.

[0338] As shown in Figure 34, power wiring 165b is formed using wiring 183. Furthermore, a portion of power wiring 165b is disposed outside the outer periphery 192. Additionally, as explained in "1-1. Overview of Semiconductor Module 10", wiring layer 150 includes a multilayer wiring structure.

[0339] The end 165c of the power supply wiring 165b is exposed in the insulating layer 182 (third surface 146). The side power supply wiring 162 covers the end 165c and is electrically connected. Furthermore, the side power supply wiring 162 is connected to the third surface 146.

[0340] An insulating film 52 is disposed on the third surface 146, which is not connected to the side power wiring 162, and simultaneously covers the side power wiring 162. The insulating film 52 is formed using the same material as the insulating film 190.

[0341] For example, the manufacturing method of the power wiring 165b related to the 16th embodiment includes etching a semiconductor substrate 173 and filling the space between the etched semiconductor substrate 173 and each side (e.g., the third side 146, the second side 144, the first side 142, and the fourth side 148) of the stacked memory chip 100 with an insulating film 190. As a result, since the semiconductor substrate 173 is covered by the insulating film 190, contamination of the stacked memory chip 100 caused by metals and corrosion and deterioration of the components within the stacked memory chip 100 caused by moisture absorption and the intrusion of impurities can be suppressed.

[0342] Furthermore, for example, since the semiconductor substrate 173 is covered by the insulating film 190, there is no metal-related contamination of the stacked memory chips 100. As a result, short circuits between adjacent wirings and between IC chips 110 within the stacked memory chips 100 can be suppressed. Accordingly, the semiconductor modules of each embodiment, including the sealing ring 160 and power wiring 165b related to the 16th embodiment, can ensure insulation between adjacent wirings and between memory chips.

[0343] Furthermore, for example, the semiconductor module in each embodiment, including the sealing ring 160 and power wiring 165b related to the 16th embodiment, can suppress the corrosion and deterioration of the wiring caused by moisture absorption and the intrusion of impurities through the sealing ring 160.

[0344] Accordingly, semiconductor modules in each embodiment, including the sealing ring 160 and power wiring 165b related to the 16th embodiment, can maintain reliability without compromising long-term reliability.

[0345] <17th Embodiment>

[0346] Hereinafter, an example of a manufacturing method for the three-turn inductor 172j included in the semiconductor module 10K related to the 17th embodiment will be described with reference to Figures 35 and 36. Figure 35 is a top view illustrating the manufacturing method of the inductor 172j, and a cross-sectional view illustrating the end cross-sectional structure of the inductor 172j along lines F3-F4 in the top view. Figure 36 is a top view illustrating an example of a manufacturing method of the inductor 172j shown in Figure 35, and a cross-sectional view illustrating the end cross-sectional structure of the inductor along lines F5-F6. Structures identical or similar to those in Figures 1-34 will be described as needed, and sometimes descriptions of structures identical or similar to those in Figures 1-34 will be omitted. Furthermore, the structures of the sealing ring 160 and the power wiring 165b related to the 17th embodiment can be appropriately applied to the semiconductor modules related to each embodiment, provided they do not contradict each other.

[0347] The inductor 172j associated with the 17th embodiment is similar to the inductor 172 associated with the 13th embodiment. When viewed from the end face, it is an inductor with multiple turns formed across multiple IC chips 110. Its other structure is the same as that of inductor 172. The same structure as inductor 172 will be described as needed. Furthermore, as an example, the inductor associated with the 17th embodiment is inductor 172j, but the inductors 272, 372, and 672 of the semiconductor modules associated with each embodiment include the same structure as inductor 172j, including a structure capable of one-to-one non-contact inductive communication with inductor 172j. In addition, the IC chip 110 includes multiple inductors 172j arranged along the second direction D2.

[0348] As shown in Figures 35 and 36, the stacked memory chip 100A includes an inductor 172j with multiple turns formed across multiple IC chips 110 (IC chip 110n, IC chip 110n+1, IC chip 110n+2 and IC chip 110n+3).

[0349] Specifically, the stacked memory chip 100A includes a three-turn inductor 172j formed on and parallel to the third surface 146 using side wiring 361d.

[0350] Although the illustrations are omitted, similar to the embodiments, multiple inductors 172j are provided along the second direction D2. Furthermore, as an example, the manufacturing method of the inductor 172j related to the 17th embodiment includes forming two wirings 383 corresponding to the two terminals of the inductor 172j on the IC chip 110n. As another example, the manufacturing method of the inductor 172j related to the 17th embodiment may include: forming two wirings 383 corresponding to the two terminals of the inductor 172j on any one of IC chip 110n+1, IC chip 110n+2 or IC chip 110n+3; or it may include: among the two wirings 383 corresponding to the two terminals of the inductor 172j, the wiring 383 corresponding to one terminal is formed on any one of IC chip 110n+1, IC chip 110n+2 or IC chip 110n+3, while the wiring 383 corresponding to the remaining terminals is formed on an IC chip different from the IC chip on which the wiring 383 corresponding to one terminal is formed.

[0351] The manufacturing method of the inductor 172j related to the 17th embodiment includes: forming wiring connected to the two terminals of the three-turn inductor 172j using two wirings 383 of the IC chip 110n; forming side wirings 361d corresponding to the two terminals of the inductor 172j after the two wirings 383 are formed; and forming an insulating film 52 on a third surface 206 that covers the side wirings 361d but is not connected to them after the side wirings 361d are formed.

[0352] As shown in Figure 35, the wiring connected to the two terminals of the three-turn inductor 172j is formed through two wirings 383 of the IC chip 110n. Accordingly, the cross-section of each of the two wirings 383 is exposed on the third surface 146.

[0353] After the two wirings 383 of inductor 172j are formed, as shown in Figure 36, the side wirings 361d corresponding to the coils of the three-turn inductor 172j are formed on the third surface 146. That is, the side wirings 361d span multiple IC chips 110n, 110n+1, 110n+2 and 110n+3 and are formed on the third surface 146.

[0354] For example, the side wiring 361d is formed on the third surface 146 in such a way that it overlaps with each of the two wirings 383 exposed on the third surface 146 of the corresponding IC chip 110n, and the side wiring 361d is electrically connected to each of the cross sections of the two wirings 383.

[0355] Furthermore, for example, the side wiring 361d includes a first to a third loop of wiring from the inside to the outside. The first loop of wiring is formed by spanning three IC chips from IC chip 110n to IC chip 110n+2, and the second and third loops of wiring are formed by spanning four IC chips from IC chip 110n to IC chip 110n+3.

[0356] Similar to inductor 172, the width of the side wiring 361d around the cross-section of the wiring 383 of the three-turn inductor 172j is widened in a way that covers the cross-section of wiring 383.

[0357] As explained above, inductor 172j is formed using wiring 383 and side wiring 361d, which is different from wiring 383. Side wiring 361d is formed on the third surface 146 and is covered by insulating film 52. Accordingly, inductor 172j of the 17th embodiment has the same operating effect as inductor 172 of the 13th embodiment.

[0358] The sealing ring (e.g., sealing ring 160) can be formed along the third direction D3 using wiring in a layer lower than the layer with two wirings 383. For example, the wiring in a layer lower than the layer with two wirings 383 can be wiring within the wiring layer 150 of IC chip 110n, or wiring within IC chip 110n+1 to 110n+3.

[0359] <18th Embodiment>

[0360] An example of the inductive communication method of the semiconductor module 10L related to the 18th embodiment will be described with reference to Figures 37 to 41. Figure 37 is a perspective view showing the plurality of inductors 172 included in the stacked memory chip 100 of the semiconductor module 10L and the plurality of inductors 272 included in the first semiconductor chip 200. Figure 38 is a diagram showing the individual identification number (ID) of each chip included in the semiconductor module 10L. Figures 39 and 40 are flowcharts showing an example of the inductive communication method of the semiconductor module 10L. Figure 41 is a block diagram showing the structure of the first semiconductor chip 200. Structures that are the same as or similar to those in Figures 1 to 36 will be described as needed, and sometimes the description of structures that are the same as or similar to those in Figures 1 to 36 will be omitted. Furthermore, the inductive communication method of the semiconductor module 10L related to the 18th embodiment can be appropriately applied to semiconductor modules related to various embodiments as long as they do not contradict each other.

[0361] <18-1. Overview of Semiconductor Module 10L>

[0362] First, the outline of the semiconductor module 10L will be described with reference to Figures 37 and 38. For example, the structure of the semiconductor module 10L shown below (1) to (3) is different from that of the semiconductor module 10. (1) The stacked memory chip 100 includes a plurality of inductors 172 (e.g., inductors 172h, 172i, 172j, 172k, 172m and 172n) arranged in a matrix along the second direction D2 and the third direction D3, parallel to and separate from the third surface 146. (2) The first semiconductor chip 200 includes a plurality of inductors 272 (e.g., inductors 272h, 272i, 272j, 272k, 272m and 272n) arranged in a matrix along the second direction D2 and the third direction D3, parallel to and separate from the third surface 206. (3) Each of inductors 172h, 172i, 172j, 172k, 172m, and 172n can perform one-to-one non-contact inductive communication with each of the opposing inductors 272h, 272i, 272j, 272k, 272m, and 272n. For example, inductor 172m faces inductor 272m, and inductor 172m can perform non-contact inductive communication with inductor 272m.

[0363] The structure of semiconductor module 10L, except for the structures shown in (1) to (3), is the same as that of semiconductor module 10. Based on this, the differences from semiconductor module 10 will be explained here. Furthermore, similar to semiconductor module 10, the number of IC chips 110 stacked, the bonding and mounting structure can be appropriately changed according to the specifications and applications of semiconductor module 10L. Moreover, as long as the structure of semiconductor module 10L is not contradictory, it can also be appropriately applied to semiconductor modules other than semiconductor module 10. For example, when semiconductor module 10L is applied to semiconductor modules 10D and 10E, the first semiconductor chip 200 is replaced with the third semiconductor chip 900, the inductor 272 is replaced with the inductor 372, and the inductive communication method of semiconductor module 10L becomes the inductive communication method according to the specifications and applications of semiconductor modules 10D and 10E.

[0364] For example, as shown in Figure 38, semiconductor module 10L has the same structure as semiconductor module 10. Specifically, semiconductor module 10L includes stacked memory chips 100A and 100B, a first semiconductor chip 200, and a second semiconductor chip 600A. The first semiconductor chip 200 includes CPU 220A, CPU 220B, and CPU 220C. The second semiconductor chip 600A includes GPU 620A and GPU 620B. Each of the stacked memory chips 100A and 100B, the first semiconductor chip 200, and the second semiconductor chip 600A includes four IC chips 110 (IC chip 110n, IC chip 110n+1, IC chip 110n+2, and IC chip 110n+3).

[0365] Furthermore, as an example, each chip is associated with a chip ID as shown in Figure 38. For instance, the chip ID of the stacked memory chip 100A is 0100, and the chip ID of the IC chip 110n is 01. The chip ID of the IC chip 110n of the stacked memory chip 100A is a combination of the chip ID of the stacked memory chip 100A and the chip ID of the IC chip 110n, resulting in 0100-01. Accordingly, each chip within the semiconductor module 10L is an individually identifiable chip.

[0366] <18-2. An Example of an Inductive Communication Method for a Semiconductor Module 10L>

[0367] Next, an example of an inductive communication method for the semiconductor module 10L will be described with reference to Figures 39 and 40. This example of an inductive communication method for the semiconductor module 10L demonstrates inductive communication between the first semiconductor chip 200 and the stacked memory chip 100A. Inductive communication between other chips capable of inductive communication is the same as that described in this example of an inductive communication method for the semiconductor module 10L, and detailed descriptions are omitted.

[0368] For example, as shown in Figure 39, when inductive communication of semiconductor module 10L begins, the first semiconductor chip 200 executes a first command to select the plurality of inductors 172 and the plurality of inductors 272 contained in each IC chip (step 11 (S11) in Figure 39). The first command may be a command to select all the inductors contained in each IC chip, or it may be a command to select a portion of the inductors contained in each IC chip.

[0369] Next, the first semiconductor chip 200 executes a second command (step 13 (S13) in FIG39) after the first command to perform inductive communication with the selected plurality of inductors 172 and plurality of inductors 272.

[0370] For example, the CPU 220A of the first semiconductor chip 200 sends the first command and the second command to the CPU 220B and CPU 220C of the first semiconductor chip 200 and the stacked memory chip 100A in order to execute the first command and the second command. Specifically, the CPU 220A sends the second command, which communicates between the inductors 272 of the IC chips 110n to 110n+3 of the CPU 220B and CPU 220C and the inductors 172 of the IC chips 110n to 110n+3 of the stacked memory chip 100A, to the CPU 220B and CPU 220C and the stacked memory chip 100A.

[0371] For example, if the inductors selected in S11 are all the inductors included in each IC chip, inductive communication is performed between each of the inductors 172 and all combinations of each of the inductors 272. Referring to FIG37, inductor 172h communicates with each of inductors 272h, 272i, 272j, 272k, 272m, and 272n. Similarly, inductors 172i, 172j, 172k, 172m, and 172n communicate with each of inductors 272h, 272i, 272j, 272k, 272m, and 272n.

[0372] Next, the first semiconductor chip 200 (CPU 220A) executes a third command (step 15 (S15) in FIG39) to obtain the result of inductive communication performed in S13 with the selected plurality of inductors 172 and plurality of inductors 272. For example, the result of inductive communication may be data based on the communication strength (communication strength data), specifically, it may be data on the induced current of inductor 172 or inductor 272, or it may be data on the voltage based on the induced current of inductor 172 or inductor 272.

[0373] Semiconductor module 10L uses S15 to position the inductors relative to each other, allowing selection of a well-aligned combination of inductors. For example, good alignment can mean that the induced current is at its maximum, or that the voltage based on the induced current is at its maximum. For example, the sequence of well-aligned inductor combinations selected via S11~S15 can also be called a training sequence.

[0374] For example, CPU 220A sends a third command to CPU 220B, CPU 220C, and stacked memory chip 100A in the manner of executing the third command. Specifically, CPU 220A sends a third command, "to send data on the induced current of each inductor when communicating between the inductors 272 of IC chips 110n to 110n+3 of CPU 220B and CPU 220C and the inductors 172 of IC chips 110n to 110n+3 of stacked memory chip 100A," to CPU 220B, CPU 220C, and stacked memory chip 100A. For example, CPU 220A obtains the induced current data of each inductor.

[0375] Next, the first semiconductor chip 200 (CPU 220A) executes the fourth command using the data obtained in S15 based on the communication strength. The fourth command sends "0100 of the ID of the stacked memory chip 100A which contains one of the multiple inductors 172" and "0302 of the ID of the CPU 220B of the first semiconductor chip 200 which contains one inductor 272 corresponding to the one inductor 172" to the stacked memory chip 100A and the first semiconductor chip 200 (step 17 (S17) in FIG39).

[0376] For example, in S17, the CPU 220A selects the combination of inductors whose induced current data is maximized based on the communication strength data obtained in S15. For example, consider the combination of inductors whose induced current data is maximized as the combination of inductor 172h of IC chip 110n in the stacked memory chip 100A and inductor 272h of IC chip 110n of CPU 220B in the first semiconductor chip 200. In this scenario, CPU 220A sends together "0100-01 of the ID of IC chip 110n within the stacked memory chip 100A, which contains one of the multiple inductors 172h, namely inductor 172h" and "0302-01 of the ID of IC chip 110n of CPU 220B, which contains the first semiconductor chip 200 corresponding to one of the inductors 172h, namely inductor 272h" to CPU 220B, CPU 220C, and the stacked memory chip 100A.

[0377] Secondly, for example, the first semiconductor chip 200 (CPU 220A) will send a fifth command to the stacked memory chip 100A and the first semiconductor chip 200 to perform inductive communication in the combination selected in S17 (inductor 272h of IC chip 110n (ID 0302-01) of the first semiconductor chip 200 and inductor 172h of IC chip 110n (ID 0100-01) of the stacked memory chip 100A) (step 19 (S19) in FIG39).

[0378] The stacked memory chip 100A and the first semiconductor chip 200 perform inductive communication through the inductor 272h of the IC chip 110n of the first semiconductor chip 200 and the inductor 172h of the IC chip 110n of the stacked memory chip 100A.

[0379] Following the above operations, the semiconductor module 10L performs inductive communication by stacking memory chip 100A and first semiconductor chip 200.

[0380] <18-3. An Example of an Inductive Communication Method for a Semiconductor Module 10L>

[0381] Next, another example of the inductive communication method of the semiconductor module 10L will be described with reference to FIG40. One example of the inductive communication method of the semiconductor module 10L shows inductive communication between the first semiconductor chip 200 and the stacked memory chip 100A. Inductive communication between other chips capable of inductive communication is the same as that of the example of the inductive communication method of the semiconductor module 10L described herein, and detailed descriptions are omitted.

[0382] For example, as shown in Figure 40, when the inductive communication of the semiconductor module 10L begins, the first semiconductor chip 200 executes a first command to select the plurality of inductors 172 and the plurality of inductors 272 contained in each IC chip (step 21 (S21) in Figure 40). S21 is the same as S11, and its description is omitted here.

[0383] Next, the first semiconductor chip 200 executes a sixth command after the first command to select a plurality of inductors 172 and a plurality of inductors 272 to communicate at a plurality of communication speeds (step 23 (S23) in FIG40).

[0384] For example, the CPU 220A of the first semiconductor chip 200 sends the first command and the sixth command to the CPU 220B and CPU 220C of the first semiconductor chip 200 and the stacked memory chip 100A in a manner that executes the first command and the sixth command. Specifically, the CPU 220A sends the sixth command, which communicates at multiple communication speeds between the inductors 272 of the IC chips 110n to 110n+3 of the CPU 220B and CPU 220C and the inductors 172 of the IC chips 110n to 110n+3 of the stacked memory chip 100A, to the CPU 220B and CPU 220C and the stacked memory chip 100A.

[0385] For example, the multiple communication speeds can be the communication speed specified by the semiconductor module 10L, and two or more communication speeds that are different from that communication speed. For example, the multiple communication speeds can be the communication speed specified by the semiconductor module 10L, and a communication speed ±10% of that communication speed.

[0386] Next, the first semiconductor chip 200 (CPU 220A) executes the seventh command (step 25 (S25) in Figure 40) to obtain the "result of inductive communication between the selected multiple inductors 172 and multiple inductors 272 executed at multiple communication speeds in S23". For example, the result of inductive communication can be data based on the communication strength (communication strength data), just like in S15. Specifically, it can be data on the induced current of inductor 172 or inductor 272, or it can be data on the voltage based on the induced current of inductor 172 or inductor 272.

[0387] The semiconductor module 10L uses S25 to position the inductors relative to each other, allowing it to select a well-aligned combination of inductors. Simultaneously, it analyzes data on the strength of communications executed at multiple communication speeds to determine the minimum communication speed. For example, "well-aligned" can mean either the induced current is at its maximum, or the voltage based on the induced current is at its maximum. For example, the sequence of well-aligned inductor combinations selected via S21-S25 can also be called a training sequence.

[0388] For example, CPU 220A sends a 7th command to CPU 220B, CPU 220C, and stacked memory chip 100A in the manner of executing the 7th command. Specifically, CPU 220A sends a 7th command, which is used to "send data on the induced current of each inductor when communicating with each inductor 172 of IC chips 110n to 110n+3 of CPU 220B and CPU 220C at different communication speeds," to CPU 220B, CPU 220C, and stacked memory chip 100A. For example, CPU 220A obtains the induced current data of each inductor corresponding to multiple communication speeds. Furthermore, CPU 220A analyzes the obtained data and calculates the minimum communication speed.

[0389] Next, the first semiconductor chip 200 (CPU 220A) executes the fourth command, which sends the ID of the IC chip of the stacked memory chip capable of inductive communication and the ID of the IC chip of the first semiconductor chip to the stacked memory chip and the first semiconductor chip based on the communication strength data obtained in S25 (step 27 (S27) in FIG40).

[0390] For example, in S27, CPU 220A selects a combination of inductors capable of inductive communication at a higher communication speed than the minimum communication speed calculated in S25. For instance, consider a combination of inductors capable of inductive communication at a higher communication speed than the minimum communication speed, such as inductor 172j of IC chip 110n within stacked memory chip 100A and inductor 272j of IC chip 110n of CPU 220B within the first semiconductor chip 200. In this scenario, CPU 220A sends "ID 0100-01 of IC chip 110n within the stacked memory chip 100A containing inductor 172j" and "ID 0302-01 of IC chip 110n of CPU 220B containing the first semiconductor chip 200 corresponding to inductor 272j" to CPU 220B, CPU 220C, and stacked memory chip 100A.

[0391] Secondly, for example, the first semiconductor chip 200 (CPU 220A) will execute an eighth command to perform inductive communication at a higher communication speed than the minimum communication speed for the combination selected in S27 (inductor 272j of IC chip 110n (ID 0302-01) of the first semiconductor chip 200 and inductor 172j of IC chip 110n (ID 0100-01) of the stacked memory chip 100A) to the stacked memory chip 100A and the first semiconductor chip 200 (step 29 (S29) in FIG40).

[0392] The stacked memory chip 100A and the first semiconductor chip 200 perform inductive communication with the inductor 272j of the IC chip 110n of the first semiconductor chip 200 and the inductor 172j of the IC chip 110n of the stacked memory chip 100A at a communication speed higher than the minimum communication speed.

[0393] In accordance with the above operation, the semiconductor module 10L performs inductive communication at a higher communication speed than the minimum communication speed by stacking memory chip 100A and first semiconductor chip 200.

[0394] <18-4. First variation of the inductive communication method for semiconductor module 10L>

[0395] Next, a first variation of the inductor communication method of the semiconductor module 10L will be described. The semiconductor module 10L may combine the first variation of the inductor communication method of the semiconductor module 10L with the inductor communication method described in "18-2. An Example of the Inductor Communication Method of the Semiconductor Module 10L" or "18-3. An Example of the Inductor Communication Method of the Semiconductor Module 10L" to perform the operation.

[0396] A first variation of the inductor communication method of the semiconductor module 10L may include: after the first semiconductor chip 200 sends a signal containing data to the stacked memory chip 100, performing processing to confirm that the stacked memory chip 100 has correctly received the signal containing data. For example, the processing to confirm that the signal containing data has been correctly received is called verification processing in the field of memory device technology.

[0397] For example, if the semiconductor module 10L simultaneously sends a signal containing data from two adjacent inductors 172 to two corresponding inductors 272 (e.g., stacked memory chips 100), a collision may occur.

[0398] To avoid this collision, the semiconductor module 10L (e.g., the first semiconductor chip 200) can also perform a process to check whether a communication error has occurred at regular intervals. The process of checking whether a communication error has occurred can be a verification process. Furthermore, if the semiconductor module 10L (e.g., the first semiconductor chip 200) detects a communication error, it can also perform a process to resend the signal containing the data to the stacked memory chip 100.

[0399] As a result, the semiconductor module 10L is able to suppress collisions, communication errors, etc.

[0400] <18-5. Structure of the first semiconductor wafer 200>

[0401] First, the structure of the first semiconductor chip 200 will be described with reference to FIG41. FIG41 is a block diagram illustrating the structure of CPU 220A of the first semiconductor chip 200. In addition, CPU 220B and CPU 220C have the same structure as CPU 220A, and their description is omitted here.

[0402] CPU 220A includes a register 221 and a table 223. Register 221 is a memory circuit that sets the quality information (e.g., level 0, level 1, ..., level 7) of the stacked memory chip 100 according to the type (image data, text data, etc.) and frequency (communication speed) of the data transmitted and received via inductive communication. Table 223 is a memory circuit that links the quality information (register setting value) with the ID of the IC chip 110 within the stacked memory chip 100.

[0403] For example, CPU 220A transmits data according to the set level to IC chip 110 within stacked memory chip 100 corresponding to the set level.

[0404] For example, quality information can be assigned according to the order of level 0, level 1, ..., level 7. Information with high confidentiality can be assigned, information with large data volume (such as image data, video data, etc.) can be assigned, and information with high frequency (fast communication speed) can also be assigned.

[0405] Furthermore, as an example, Table 223 assigns IDs in the order of register settings: Level 0, Level 1, ..., Level 7, as 0100-01, 0100-02, ..., 0200-04. Each ID corresponds to the chip shown in Figure 38. For example, Level 2 is assigned to 0100-03 (IC chip 110n+2 of stacked memory chip 100A).

[0406] For example, highly confidential data, images, and other information-heavy data are sent to higher-level IC chips. Simpler information, such as text data, is sent to lower-level IC chips. Furthermore, high-frequency (fast communication speed) data is sent to higher-level IC chips.

[0407] Furthermore, for example, when the register 221 is a register for setting communication speed, the speed is set in the register in order of higher communication speed from the higher level (e.g., level 7). For example, the CPU 220A of the first semiconductor chip 200 can make the communication speed variable by reading the corresponding communication speed from the register 221, and can send data to the IC chip 110 with the corresponding communication speed.

[0408] <19th Embodiment>

[0409] The structure of the semiconductor module 10M related to the 19th embodiment will now be described with reference to FIG42. FIG42 is a block diagram illustrating the structure of the semiconductor module 10M. Structures that are the same as or similar to those in FIG1 to FIG41 will be described as needed, and sometimes the description of structures that are the same as or similar to those in FIG1 to FIG41 will be omitted. Furthermore, the structure of the semiconductor module 10M related to the 19th embodiment can be appropriately applied to semiconductor modules related to various embodiments as long as they do not contradict each other.

[0410] Semiconductor module 10M includes stacked memory chips 100 and a first semiconductor chip 200. Stacked memory chip 100 includes a TCI-IO 112 and a memory module 111 electrically connected to the TCI-IO 112. The first semiconductor chip 200 includes multiple TCI-IOs 212 and a CPU 220 electrically connected to the multiple TCI-IOs 212. The structure of each chip is as described in "1-1. Overview of Semiconductor Module 10", and is omitted here.

[0411] For example, a typical semiconductor module does not include the structure of semiconductor module 10M and the semiconductor modules associated with each implementation. In the circuits corresponding to memory chips and the first semiconductor chip in a typical semiconductor module, the wiring forming the transmitting coil of the inductor used for communication is thick, and the circuit corresponding to the transceiver circuit includes a large transistor.

[0412] On the other hand, the semiconductor module 10M and the semiconductor modules associated with each embodiment, for example, include a structure that enables inductive communication using small-sized inductors 172 and 272 and small-sized transistors. That is, the semiconductor module 10M has one TCI-IO 112 for the stacked memory chip 100 and multiple TCI-IO 212 for the first semiconductor chip 200, and has a relatively small circuit structure.

[0413] For example, semiconductor module 10M, having multiple TCI-IO 212s for one TCI-IO 112, can select the most suitable TCI-IO 212 among the multiple TCI-IO 212s for inductive communication with one TCI-IO 112. For example, semiconductor module 10M can also use the same communication method as semiconductor module 10L, selecting the most suitable TCI-IO 212 for inductive communication from combinations of one TCI-IO 112 (inductor 172) and multiple TCI-IO 212s (multiple inductors 272) through a training sequence. For example, semiconductor module 10M can also select the most suitable combination of communication speed, power (induced current or voltage), and communication quality (e.g., bit error rate within IC chip 110).

[0414] As a result, the communication method of the semiconductor module 10M is a communication method that makes it easy to select a combination of well-aligned inductors due to the alignment offset between the inductor 172 of the stacked memory chip 100 and the inductor 272 of the first semiconductor chip 200.

[0415] <20th Embodiment>

[0416] The structure of the semiconductor module 10N related to the 20th embodiment will now be described with reference to FIG43. FIG43 is a block diagram illustrating the structure of the semiconductor module 10N. Structures that are the same as or similar to those in FIG1 to FIG42 will be described as needed, and sometimes descriptions of structures that are the same as or similar to those in FIG1 to FIG42 will be omitted. Furthermore, the structure of the semiconductor module 10N related to the 20th embodiment can be appropriately applied to semiconductor modules related to various embodiments as long as they do not contradict each other.

[0417] Semiconductor module 10N and semiconductor module 10M both include stacked memory chips 100 and a first semiconductor chip 200. Stacked memory chip 100 includes multiple TCI-IOs 112 and a memory module 111 electrically connected to the multiple TCI-IOs 112. The first semiconductor chip 200 includes a TCI-IO 212 and a CPU 220 electrically connected to the TCI-IO 212. The structure of each chip is as described in "1-1. Overview of Semiconductor Module 10", and the description is omitted here.

[0418] On the other hand, the semiconductor module 10N and the semiconductor modules associated with each embodiment, for example, include a structure capable of inductive communication using small-sized inductors 172 and 272 and small-sized transistors. That is, in the semiconductor module 10M, the first semiconductor chip 200 has one TCI-IO 212, and the stacked memory chip 100 has multiple TCI-IO 112, resulting in a relatively small circuit structure.

[0419] For example, semiconductor module 10N, having multiple TCI-IO 112s for one TCI-IO 212, can select the most suitable TCI-IO 112 among the multiple TCI-IO 112s for inductive communication with one TCI-IO 212. For example, semiconductor module 10N can also use the same communication method as semiconductor module 10L, selecting the most suitable TCI-IO 112 for inductive communication from combinations of multiple TCI-IO 112s (multiple inductors 272) and one TCI-IO 212 (one inductor 272) through a training sequence. For example, semiconductor module 10N can also select the most suitable combination of communication speed, power (induced current or voltage), and communication quality (e.g., bit error rate within IC chip 110).

[0420] As a result, the communication method of semiconductor module 10N is similar to that of semiconductor module 10M. It is a communication method that makes it easier to select a combination of well-aligned inductors due to the alignment offset between the inductor 172 of the stacked memory chip 100 and the inductor 272 of the first semiconductor chip 200.

[0421] Various configurations of the semiconductor module exemplified by embodiments of the present invention can be appropriately combined as long as they do not contradict each other. Common technical matters in each embodiment are included even without explicit description. Furthermore, based on the semiconductor module disclosed in this specification and drawings, any addition, deletion, or design modification of appropriate constituent elements, or addition, omission, or change of processes by those skilled in the art to which this invention pertains, as long as they capture the essence of the present invention, are also included within the scope of this invention.

[0422] Even if other effects are achieved differently from those of the embodiments disclosed in this specification, those that are obvious from the description in this specification or that can be easily predicted by those skilled in the art to which this invention pertains should be understood as being achieved by this invention.

[0423] 10: Semiconductor Module 10A: Semiconductor Module 10B: Semiconductor Module 10C: Semiconductor Module 10D: Semiconductor Module 10E: Semiconductor Module 10F: Semiconductor Module 10G: Semiconductor Module 10H: Semiconductor Module 10J: Semiconductor Module 10K: Semiconductor Module 10L: Semiconductor Module 10M: Semiconductor Module 10N: Semiconductor Module 30: Stacked Chip Groups 32: Page 1 34: Page 2 40: Cover 50: Sealed structure 52: Insulating film 54: Insulating film 60: Packaging substrate 62: Page 1 64: Page 2 66: Wiring layer 67: Electrode 68: Wiring layer 69: Wiring 70: Wiring layer 71: Wiring 72: Wiring Layer 73: Wiring 74: Wiring Layer 75: Electrode 80: Thermally conductive sheet 82: Bump 82A: Bump 84: Bump 90:Metal film 100: Stacked memory chips 100A: Stacked memory chip 100B: Stacked memory chips 100C: Stacked memory chips 100D: Stacked memory chips 101:End 102: Page 1 102n: Page 1 103:End 104: Page 2 104n: Page 2 110: IC chips 110n: IC chip 111: Memory Module 112:TCI-IO 113: Parallel-to-Series Conversion Circuit 114: Transceiver Circuit 115: Memory Cell Array 130: Transistor layer 130n: Transistor layer 131: Through electrode 131j: Through electrode 131k: Through electrode 131m: Through electrode 131o: Through electrode 142: Page 1 144: Page 2 146: Page 3 148: Page 4 150: Wiring layer 150n: Wiring layer 151a: Insulation layer 151b: Guide hole 151j: Guide hole 151k: Pilot Hole 151m: Guide hole 151o: Guide hole 152a: Insulation layer 152b: Wiring 152c: Wiring 152j: Wiring 152k: cabling 152m: Wiring 152nj: Wiring 152o: Wiring 153a: Insulation layer 153b: Guide hole 153c: Guide hole 153j: Guide hole 153k: Guide hole 153m: Guide hole 153nj: Guide hole 153nk: Guide hole 153o: Guide hole 154a: Insulation layer 154b: Wiring 154c: Wiring 154d: Wiring 154e: Wiring 154j: Wiring 154k: cabling 154m: Wiring 154nj: Wiring 154nk: Wiring 154nm: Wiring 154o: Wiring 155a: Insulation layer 155b: Guide hole 155c: Guide hole 155d: Guide hole 155e: Guide hole 155f: Guide hole 155g: Guide hole 155j: Guide hole 155k: Guide hole 155m: Guide hole 155nj: Guide hole 155nk: Guide hole 155nm: via 155no: Guide hole 155°: Guide hole 156a: Insulation layer 156b: Wiring 156c: Wiring 156d: Wiring 156e: Wiring 156f: Wiring 156g: Wiring 156h: Wiring 156i: Wiring 156j: Wiring 156k: cabling 156m: Wiring 156nj: Wiring 156nk: Wiring 156nm: Wiring 156no: Wiring 156o: Wiring 160: Sealing 160n: Sealing 162: Side power supply wiring 163: Side grounding wiring 164: Power Wiring 165: Grounding wiring 165b: Power cabling 165c: End 166: Signal transmission cabling 172: Inductor 172a: Part 1 172b: Part 2 172c: Part 3 172d: Part 5 172e: Part 4 172f: Inductor 172g: Inductor 172h: Inductor 172i: Inductor 172j: Inductor 172k: Inductor 172m: Inductor 172n: Inductor 172o: Inductor 172p: Inductor 172q: Inductor 173: Semiconductor substrate 173a: Semiconductor substrate 173n: Semiconductor substrate 174: Component Separation Area 175: Active Region 176: Transistor 177: Insulation layer 178: Wiring 179: Insulation layer 180: Wiring 181: Insulation layer 182: Insulation layer 183: Wiring 183b: Wiring 183c: Wiring 183d: Wiring 183e: Wiring 183f: Wiring 183g: Wiring 183j: Wiring 183k: cabling 183nj: Wiring 183nk: Wiring 183nm: Wiring 183no: Wiring 183o: Wiring 184a: Guide hole 184b: Guide hole 184c: Guide hole 184d: Guide hole 184e: Guide hole 184f: Guide hole 184g: Guide hole 184h: Guide hole 184i: Guide Hole 184j: Guide hole 184k: Pilot Hole 184m: Guide hole 184nj: Guide hole 184nk: Guide hole 184nm: via 184no: Guide hole 184o: Guide hole 190: Insulating film 192:Peripheral part 196j: Wiring 196nk: Wiring 196nm: Wiring 196no: Wiring 200: The first semiconductor chip 202: Page 1 204: Page 2 206: Page 3 208: Page 4 212:TCI-IO 213: Parallel-Series Conversion Circuit 214: Transceiver Circuit 220: CPU 220A: CPU 220B: CPU 220C: CPU 221: Temporary Register 223: Table 262: Side power supply wiring 263: Side grounding wiring 272: Inductor 272a: Part 1 272b: Part 2 272c: Part 3 272d: Part 5 272e: Part 4 272h: Inductor 272i: Inductor 272j: Inductor 272k: Inductor 272m: Inductor 272n: Inductor 272o: Inductor 272p: Inductor 300: Stacked DRAM 300A: Stacked DRAM 300B: Stacked DRAM 300D: Stacked DRAM 312:TCI-IO 313: Parallel-Series Conversion Circuit 314: Transceiver Circuit 361d: Side wiring 372: Inductor 372a: Part 1 372b: Part 2 372c: Part 3 372d: Part 5 372e: Part 4 372f: Inductor 383: Wiring 400: Support substrate 400A: Support substrate 400B: Support substrate 500A: TCI-IO chip 500C:TCI-IO chip 600: Second Semiconductor Wafer 600A: Second Semiconductor Wafer 612:TCI-IO 613: Parallel-to-Series Conversion Circuit 614: Transceiver Circuit 620: GPU 620A: GPU 620B: GPU 672: Inductor 700A: I / O chip 800: Bump layer 850: Bonding layer 860: Structure 900: The third semiconductor chip 902: Page 1 904: Page 2 910: Logic Module A:Terminal B: Terminal C: Terminal D: Terminal E: terminal F: Terminal D1: Direction 1 D2: Second Direction D3: 3rd direction L1: Length L2: Length L3: Length L4: Length L5: Length L6: Length T1: Thickness T2: Thickness T3: Thickness T4: Thickness W1: Width X1: Length X2: Length Y1: Length Y2: Length

Claims

1. A semiconductor module comprising: a first substrate having a first surface parallel to a first direction and a second direction intersecting the first direction; stacked memory chips disposed on the first surface along a third direction intersecting the first and second directions and comprising "a plurality of memory chips stacked along the third direction" and "a first inductor disposed across the plurality of memory chips"; and a first semiconductor chip disposed on the first surface and separated from the stacked memory chips along the first direction, and comprising a second inductor; wherein the stacked memory chips comprise "a plurality of memory chips stacked along the third direction" and "a first inductor disposed across the plurality of memory chips"; and a first semiconductor chip disposed on the first surface and separated from the stacked memory chips along the first direction, and comprising a second inductor; wherein the stacked memory chips comprise "a plurality of memory chips stacked along the third direction" and "a first inductor disposed across the plurality of memory chips". The outermost second surface of the first substrate side and the outermost third surface of the first semiconductor wafer side are parallel to the second and third directions. The first inductor is configured to be parallel to the third surface and separate from the third surface. The first semiconductor wafer includes the outermost fourth surface of the first substrate side which is parallel to and faces the first surface, and the outermost fifth surface of the stacked memory wafer side which is parallel to and faces the third surface. The second inductor is configured to be parallel to the fifth surface and separate from the fifth surface. The first inductor and the second inductor communicate in a non-contact manner.

2. A semiconductor module comprising: a first substrate having a first surface parallel to a first direction and a second direction intersecting the first direction; stacked memory chips disposed on the first surface and comprising "a second surface parallel to a third direction intersecting the first and second directions and being the outermost surface along the second direction", "a third surface parallel to the first surface and being the outermost surface along the third direction", "a plurality of memory chips stacked parallel to the third surface", and "a first inductor disposed across the plurality of memory chips". "; and a first semiconductor chip, disposed between the aforementioned first surface and the aforementioned third surface and including "a fourth surface that is parallel to and faces the aforementioned first surface and is the outermost surface of the aforementioned first surface", "a fifth surface that is opposite to the aforementioned fourth surface and faces the aforementioned third surface and is the outermost surface of the aforementioned third surface", and "a second inductor that is parallel to the aforementioned fifth surface"; wherein the aforementioned first inductor is configured to be separated from the aforementioned third surface along the aforementioned third surface, the aforementioned second inductor is configured to be separated from the aforementioned fifth surface along the aforementioned fifth surface, and the aforementioned first inductor and the aforementioned second inductor communicate in a non-contact manner.

3. The semiconductor module as described in claim 1 or claim 2, wherein the first semiconductor chip is a stacked IC chip comprising a plurality of stacked IC chips, each of the plurality of IC chips comprising a sealing ring disposed on the outer periphery of the IC chip, and the wiring layer of each of the plurality of IC chips comprising the sealing ring and a portion of the second inductor, wherein, when viewed from the end face, the sealing ring is parallel to the semiconductor substrate of the IC chip and extends along the second direction and is disposed on the semiconductor substrate of the IC chip, a portion of the first inductor is disposed on the third surface side of the sealing ring and overlaps the sealing ring, and a portion of the second inductor is disposed on the fifth surface side of the sealing ring and overlaps the sealing ring.

4. The semiconductor module as described in claim 1 or claim 2, wherein the first semiconductor chip is a stacked IC chip comprising a plurality of stacked IC chips, and the number of stacked memory chips is less than the number of stacked IC chips.

5. The semiconductor module as described in claim 1 or claim 2, wherein the first semiconductor chip is a stacked IC chip comprising a plurality of stacked IC chips, the stacked memory chip comprising a plurality of the first inductors, the stacked IC chip comprising a plurality of the second inductors, the plurality of the first inductors being arranged in a matrix parallel to the third surface, and the plurality of the second inductors being arranged in a matrix parallel to the fifth surface.

6. The semiconductor module as claimed in claim 1, further comprising: a first internal wiring exposed on the aforementioned third surface; a first side wiring disposed on the aforementioned third surface and electrically connected to the aforementioned first internal wiring; a second internal wiring exposed on the aforementioned fifth surface; a second side wiring disposed on the aforementioned fifth surface and electrically connected to the aforementioned second internal wiring; and a side connection terminal disposed between the aforementioned third surface and the aforementioned fifth surface to electrically connect the aforementioned first side wiring and the aforementioned second side wiring.

7. The semiconductor module as described in claim 1, wherein the second and fourth surfaces and the first surface further include a bump layer containing a plurality of bumps, wherein the diameter of the bumps is more than 10 μm and less than 150 μm in a top view.

8. The semiconductor module as described in claim 7, wherein, in a top view, the number of the plurality of bumps disposed on the aforementioned second surface is different from the number of the plurality of bumps disposed on the aforementioned fourth surface.

9. The semiconductor module as described in claim 7, in a top view, the length between the aforementioned bumps along the aforementioned first direction among the aforementioned plurality of bumps on the aforementioned second surface is less than or equal to the length between the aforementioned bumps along the aforementioned first direction among the aforementioned plurality of bumps on the aforementioned fourth surface.

10. The semiconductor module as claimed in claim 7, wherein, in a top view, the diameter of each of the plurality of bumps disposed on the aforementioned second surface is the same as the diameter of each of the plurality of bumps disposed on the aforementioned fourth surface.

11. The semiconductor module as claimed in claim 10, wherein, when viewed from the end face, the length from the aforementioned first face to the end of the aforementioned first inductor is the same as the length from the aforementioned first face to the aforementioned second inductor.

12. The semiconductor module as claimed in claim 7, wherein, in a top view, the diameter of each of the plurality of bumps disposed on the aforementioned second surface is different from the diameter of each of the plurality of bumps disposed on the aforementioned fourth surface; and, when viewed from the end face, the length from the aforementioned first surface to the end of the aforementioned first inductor is the same as the length from the aforementioned first surface to the aforementioned second inductor.

13. The semiconductor module as described in claim 1 or claim 2 is configured such that each of the plurality of memory chips has a chip ID, and when the first semiconductor chip initiates communication in the aforementioned contactless manner, it sends the aforementioned chip ID to the aforementioned stacked memory chips.

14. The semiconductor module as described in claim 3 is configured such that each of the plurality of IC chips has a chip ID, and when the first semiconductor chip initiates communication in the aforementioned contactless manner, the aforementioned IC chip corresponding to the aforementioned chip ID among the plurality of IC chips performs communication with the aforementioned stacked memory chip in the aforementioned contactless manner.

15. The semiconductor module as described in claim 1 or claim 2 is configured such that: the aforementioned stacked memory chip includes a first transceiver circuit electrically connected to the aforementioned first inductor; the aforementioned first semiconductor chip includes a plurality of the aforementioned second inductors and a second transceiver circuit electrically connected to each of the plurality of the aforementioned second inductors; the aforementioned stacked memory chip selects one of the plurality of the aforementioned second inductors; and the aforementioned first inductor and the aforementioned one second inductor communicate in the aforementioned contactless manner.

16. The semiconductor module as described in claim 1 or claim 2 is configured such that: the aforementioned stacked memory chip includes a plurality of the aforementioned first inductors and a first transceiver circuit electrically connected to each of the plurality of the aforementioned first inductors; the aforementioned first semiconductor chip includes a second transceiver circuit electrically connected to the aforementioned second inductor; the aforementioned first semiconductor chip selects one of the plurality of the aforementioned first inductors; and the aforementioned second inductor communicates with the aforementioned one first inductor in the aforementioned contactless manner.

17. The semiconductor module as described in claim 1 or claim 2 is configured such that: the aforementioned stacked memory chip includes a plurality of the aforementioned first inductors, the aforementioned first semiconductor chip includes a plurality of the aforementioned second inductors, the aforementioned first semiconductor chip communicates through all combinations of each of the plurality of the aforementioned first inductors and each of the plurality of the aforementioned second inductors, obtains data on the strength of the communication through the aforementioned combinations, selects one of the plurality of the aforementioned first inductors and one of the plurality of the aforementioned second inductors based on the obtained data; the aforementioned semiconductor module communicates through the aforementioned first inductor and the aforementioned second inductor in the aforementioned non-contact manner.

18. The semiconductor module as described in claim 17 is configured such that the aforementioned first semiconductor chip performs, at multiple communication speeds, communication via all combinations of each of the aforementioned first inductors and each of the aforementioned second inductors, and obtains data regarding the strength of the communication via all combinations.

19. The semiconductor module as claimed in claim 1, wherein the first semiconductor chip is a stacked IC chip comprising a plurality of stacked IC chips, the second inductor is disposed across the plurality of IC chips, each of the plurality of memory chips and each of the plurality of IC chips comprises a semiconductor substrate and a wiring layer stacked on the semiconductor substrate, wherein at least one of the plurality of memory chips has its semiconductor substrate exposed on the third surface, and at least one of the plurality of IC chips has its semiconductor substrate exposed on the fifth surface.

20. The semiconductor module as claimed in claim 2, wherein the first semiconductor chip is a stacked IC chip comprising a plurality of stacked IC chips, the second inductor is disposed on the IC chip closest to the third surface, each of the plurality of memory chips and each of the plurality of IC chips comprises a semiconductor substrate and a wiring layer stacked on the semiconductor substrate, wherein, among the plurality of memory chips, the semiconductor substrate of at least one memory chip is exposed on the third surface.

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