Integrated circuit device and method of fabricating the same

Abstract

Some embodiments relate to an integrated circuit (IC) device including a substrate having first and second doped regions; a dielectric element located on the substrate and between the first and second doped regions, the dielectric element being configured to be closer to the second doped region than the first doped region; a first conductive element located on the dielectric element; a dielectric layer located on the first conductive element and the dielectric element and on the sidewalls of the first conductive element and the dielectric element, extending from the first doped region to the second doped region on the substrate; a second conductive element partially covering the first conductive element on the dielectric layer and between the first doped region and the first conductive element; and an oxide semiconductor element located on the second doped region and partially covering the first conductive element on the dielectric layer.

Claims

1. An integrated circuit (IC) device, comprising: The substrate includes a first doped region and a second doped region; A dielectric element is located on the substrate and between the first doped region and the second doped region, the dielectric element being configured to be closer to the second doped region than the first doped region; A first conductive element is located above the dielectric element; A dielectric layer is located on the first conductive element and the dielectric element and on the sidewalls of the first conductive element and the dielectric element, and extends from the first doped region to the second doped region on the substrate; A second conductive element partially covers the first conductive element above the dielectric layer and is located between the first doped region and the first conductive element. And an oxide semiconductor element, located on the second doped region and partially covering the first conductive element above the dielectric layer.

2. The IC device as claimed in claim 1, wherein the lengths of the dielectric element and the first conductive element are each less than half the distance between the first doped region and the second doped region.

3. The IC device as claimed in claim 1, wherein the thickness of the second conductive element above the first conductive element is substantially equal to the thickness of the oxide semiconductor element above the first conductive element.

4. The IC device as claimed in claim 1, wherein at least a portion of the first conductive element is not covered by the second conductive element and the oxide semiconductor element.

5. The IC device as claimed in claim 1, further comprising: A dielectric structure is disposed on the dielectric layer, the second conductive element, and the oxide semiconductor element; A first conductive contact element extends downward in the dielectric structure to the first doped region; A second conductive contact element extends downward in the dielectric structure to the oxide semiconductor element; And a third conductive contact element, which extends downward in the dielectric structure to the second conductive element.

6. A method of manufacturing an integrated circuit (IC) device, the method comprising: Dielectric elements are formed on the substrate; A first conductive element is formed over the dielectric element; A dielectric layer is formed over the first conductive element, located on the sidewalls of the first conductive element and the dielectric element, and extending over the substrate; A second conductive element is formed on the dielectric layer, partially covering the first conductive element and extending laterally in a direction away from the first conductive element; A first doped region and a second doped region are formed in the substrate through the dielectric layer, such that the first conductive element and the second conductive element are located between the first doped region and the second doped region and are adjacent to the first doped region and the second doped region, respectively. Remove a portion of the dielectric layer disposed on the second doped region of the substrate; And an oxide semiconductor element formed on the second doped region of the substrate and partially superimposed on the first conductive element.

7. A method of manufacturing an IC device as claimed in claim 6, wherein, in a plan view of the substrate, the first conductive element includes a portion disposed between the second conductive element and the oxide semiconductor element.

8. A method of manufacturing an IC device as claimed in claim 6, wherein the second conductive element comprises: The first upper surface partially covers the first conductive element; And a second upper surface, which is laterally offset from the first conductive element and closer to the substrate than the first upper surface.

9. A method of manufacturing an integrated circuit (IC) device, the method comprising: Deposit dielectric material on a substrate; A conductive material is deposited on the dielectric material; Remove portions of the dielectric material and the conductive material to form a dielectric element and a first conductive element covering the dielectric element; A dielectric layer is deposited on the substrate and the first conductive element; A conductive layer is deposited on top of the dielectric layer; Remove a portion of the conductive layer to form a second conductive element that partially covers the first conductive element and extends laterally in a direction away from the first conductive element; A first doped region and a second doped region are formed in the substrate through the dielectric layer, wherein the first doped region is configured to be adjacent to the distal end of the second conductive element away from the first conductive element, and wherein the second doped region is configured to be adjacent to the vertical wall of the dielectric layer at the distal end of the first conductive element away from the second conductive element; the portion of the dielectric layer above the second doped region is removed; an oxide semiconductor layer is deposited on the second conductive element, the second doped region, and the dielectric layer; And removing a portion of the oxide semiconductor layer to form an oxide semiconductor element disposed on the second doped region and partially located above the first conductive element.

10. The method of manufacturing an IC device as claimed in claim 9, wherein the vertical wall of the dielectric layer laterally surrounds the first conductive element.

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