Electronic device and operation method thereof

TWI942352BActive Publication Date: 2026-10-11SIGMASTAR TECH LTD
View PDF 5 Cites 0 Cited by

Patent Information

Application Number
TW114124253
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-06-26
Publication Date
2026-10-11
Estimated Expiration
2045-06-25

Smart Images

  • Figure TWG2TB001915529_001
    Figure TWG2TB001915529_001
  • Figure TWG2TB001915529_002
    Figure TWG2TB001915529_002
  • Figure TWG2TB001915529_003
    Figure TWG2TB001915529_003
Patent Text Reader

Abstract

This invention discloses an electronic device comprising memory, computing circuitry, and image processing circuitry. The computing circuitry executes program code and / or program instructions stored in the memory to execute the operating system of the electronic device. The image processing circuitry includes a first memory management circuitry and a functional circuitry. The first memory management circuitry accesses the memory. The functional circuitry accesses the memory via a virtual physical address, and the first memory management circuitry translates the virtual physical address into a physical address of the memory. The computing circuitry further executes a driver for the functional circuitry. The computing circuitry includes a second memory management circuitry. The driver accesses the memory via a kernel space address, and the second memory management circuitry translates the kernel space address into the virtual physical address.
Need to check novelty before this filing date? Find Prior Art

Claims

1. An electronic device comprising: a memory for storing a plurality of program codes and / or program instructions; a computing circuit coupled to the memory for executing the program codes and / or program instructions to execute an operating system of the electronic device; and an image processing circuit coupled to the memory, comprising: a first memory management circuit coupled to the memory for accessing the memory; and a functional circuit coupled to the first memory management circuit; wherein... The functional circuit accesses the memory through a virtual physical address, and the first memory management circuit translates the virtual physical address into a physical address of the memory; wherein, the computing circuit further executes the program code and / or program instructions to execute a driver program of the functional circuit; the computing circuit includes a second memory management circuit; the driver program accesses the memory through a kernel space address, and the second memory management circuit translates the kernel space address into the virtual physical address.

2. The electronic device as claimed in claim 1, wherein, The functional circuit generates initial data and stores the initial data in the virtual physical address, and the driver generates intermediate data based on the initial data and stores the intermediate data in the core space address.

3. The electronic device as claimed in claim 2, wherein, The core space address and the virtual physical address are mapped to the same physical address.

4. The electronic device as claimed in claim 2, wherein, The functional circuit is an image signal processor, and the initial data includes at least one of an exposure value, a white balance value, and a focus value.

5. The electronic device as claimed in claim 1, wherein, The computing circuit further executes an application of the electronic device, which accesses the memory through a user space address, and the second memory management circuit translates the user space address into the core space address.

6. The electronic device as claimed in claim 5, wherein, The functional circuit generates initial data and stores the initial data in the virtual physical address. The driver generates intermediate data based on the initial data and stores the intermediate data in the core space address. The application generates a calculation result based on the intermediate data and stores the calculation result in the user space address.

7. The electronic device as claimed in claim 6, wherein, The user space address, the core space address, and the virtual physical address are mapped to the same physical address.

8. The electronic device as claimed in claim 6, wherein, The functional circuit is an image signal processor, and the initial data includes at least one of an exposure value, a white balance value, and a focus value.

9. The electronic device as claimed in claim 5, wherein, The operating system is a Linux operating system. The application runs in one of the user spaces of the Linux operating system, while the driver runs in one of the kernel spaces of the Linux operating system.

10. A method of operating an electronic device, the electronic device comprising a memory, an image processing circuit, and a computing circuit coupled to each other, the computing circuit comprising a first memory management circuit, the image processing circuit comprising a second memory management circuit and a functional circuit coupled to each other, the first memory management circuit mapping a user space cache to a core space cache and mapping the core space cache to a hardware space cache, the second memory management circuit mapping the memory to the hardware space cache, the method comprising: controlling the functional circuit to generate initial data, and controlling the functional circuit to store the initial data in the hardware space cache; executing a driver of the functional circuit to read the initial data from the core space cache; executing the driver to generate intermediate data based on the initial data, and storing the intermediate data in the core space cache; executing an application to read the intermediate data from the user space cache; and executing the application to generate a calculation result based on the intermediate data, and storing the calculation result in the user space cache.

11. As in request item 10, wherein, The functional circuit accesses the hardware space cache through a virtual physical address, and the second memory management circuit translates the virtual physical address into one of the physical addresses of the memory.

12. As in request item 11, wherein, The computing circuit accesses the core space cache through a core space address, and the first memory management circuit translates the core space address into the virtual physical address.

13. As in request item 12, wherein, The computing circuit accesses the user space cache through a user space address, and the first memory management circuit translates the user space address into the core space address.

14. As in request item 13, wherein, The user space address, the core space address, and the virtual physical address are mapped to the same physical address.

15. As in request item 10, wherein, The functional circuit is an image signal processor, and the initial data includes at least one of an exposure value, a white balance value, and a focus value.

16. As in request item 10, wherein, The computing circuit executes a Linux operating system, and executes the application in one of the user spaces of the Linux operating system, and executes the driver in one of the kernel spaces of the Linux operating system.

17. An image processing circuit applied to an electronic device and coupled to a memory of the electronic device, the image processing circuit comprising: a memory management circuit coupled to the memory for accessing the memory; and a functional circuit coupled to the memory management circuit; wherein, The functional circuit accesses the memory through a virtual physical address, and the memory management circuit translates the virtual physical address into a physical address of the memory. The memory management circuit includes a virtual physical address protection circuit, which is used to determine whether the virtual physical address falls within an address range. When the virtual physical address does not fall within the address range, the virtual physical address protection circuit issues an interrupt.

18. The image processing circuit of claim 17, wherein, The functional circuit is an image signal processor that generates initial data, which includes at least one of an exposure value, a white balance value, and a focus value.

Citation Information

Patent Citations

  • Memory processing system and memory processing method

    CN118503155A

  • Memory management method based on virtual memory and devices using the same

    TW202503539A

  • Method and system for implementing multi-stage translation of virtual addresses

    US20150199280A1

  • Apparatus and method for memory management in a graphics processing environment

    US20210056051A1

  • Intermingling memory resources using multiple addressing modes

    US20250156336A1