Display device

Abstract

This disclosure relates to display panels and display devices, and more specifically, to display panels and display devices including thin-film transistors having high reliability and high current generation characteristics. The display panel includes: a substrate; a first active layer disposed on the substrate and including a first channel region; a second active layer overlapping a portion of the first active layer and including a second channel region not overlapping the first channel region of the first active layer; a first electrode and a second electrode disposed in corresponding portions of the first and second active layers and spaced apart from each other; a gate insulating layer disposed in corresponding portions of the upper surfaces of the first and second active layers; and a third electrode disposed on the gate insulating layer.

Description

[Technical Field]

[0001] This disclosure relates to electronic devices having a display, and more specifically, to a display panel and a display device. [Previous Technology]

[0002] Thin film transistors are widely used in the field of electronic devices as switching or driving devices.

[0003] In particular, since thin-film transistors can be manufactured on glass or plastic substrates, they are increasingly used as switching or driving devices for display devices (such as liquid crystal displays, organic light-emitting displays, quantum dot displays, etc.). Because the reliability of such transistors may decrease for various reasons, or the amount of current generated by the transistors may decrease, the electrical characteristics of the corresponding display devices may also deteriorate. [Summary of the Invention]

[0004] Conventional display devices suffer from low reliability or low current draw due to the structural properties of their active layers, resulting in degraded electrical characteristics. One or more embodiments of this disclosure can provide a display panel and display device capable of solving these problems.

[0005] One or more embodiments of this disclosure may provide a display panel and display device including one or more thin-film transistors having high electron mobility and improved reliability.

[0006] One or more embodiments of this disclosure can provide a display panel and display device including one or more thin-film transistors with high current and high reliability located in a non-display area by enabling one or more transistors to have the characteristic of generating high-level current.

[0007] According to various aspects of this disclosure, a display panel can be provided, comprising: a substrate; a first active layer disposed on the substrate and including a first channel region; a second active layer overlapping a portion of the first active layer and including a second channel region not overlapping the first channel region of the first active layer; a first electrode and a second electrode respectively disposed in corresponding portions of the first and second active layers and spaced apart from each other; a gate insulating layer disposed in corresponding portions of the upper surfaces of the first and second active layers; and a third electrode disposed on the gate insulating layer. The first channel region of the first active layer and the second channel region of the second active layer can be connected in parallel with each other.

[0008] According to various aspects of this disclosure, a display device may be provided, comprising: a display panel and a driving circuit for driving the display panel, wherein the display panel comprises: a substrate; a first active layer disposed on the substrate and including a first channel region; a second active layer overlapping a portion of the first active layer and including a second channel region not overlapping the first channel region of the first active layer; a first electrode and a second electrode respectively disposed in corresponding portions of the first active layer and spaced apart from each other; a gate insulating layer disposed in corresponding portions of the upper surfaces of the first active layer and the second active layer; and a third electrode disposed on the gate insulating layer.

[0009] According to one or more embodiments of the present disclosure, a display panel and display device can be provided having the following structure: a thin-film transistor includes an active layer comprising different materials, and the channel regions of the active layer are connected in parallel with each other. Thus, the display panel and display device can possess high capability and produce high performance by including a thin-film transistor with high current generation characteristics and high reliability.

[0010] According to one or more embodiments of the present disclosure, a display panel and a display device can be provided, having a structure in which one transistor is configured to have a plurality of first channel regions and a plurality of second channel regions that are alternately arranged. Thus, the display panel and display device can possess high capability and produce high performance through the inclusion of thin-film transistors with high current generation characteristics and high reliability disposed in non-display areas.

Implementation Method

[0012] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the drawings. In the following description, unless otherwise stated, the structures, embodiments, implementations, methods, and operations described herein are not limited to the specific examples or examples set forth herein, and may be varied as is known in the art. Unless otherwise stated, similar reference numerals denote similar elements throughout. The names of the various elements used in the following description are chosen for convenience of writing the specification only and may therefore differ from the names used in actual products. The advantages and features of the present disclosure and methods of implementation thereof will become clear through the exemplary embodiments described below with reference to the drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that the present disclosure is thorough and complete enough to assist those skilled in the art in fully understanding the scope of the present disclosure. Furthermore, the scope of protection of the present disclosure is defined by the claims and their equivalents. In the following description, detailed descriptions of relevant known functions or configurations may be omitted where such detailed descriptions may unnecessarily obscure aspects of the present disclosure. The shapes, dimensions, scales, angles, quantities, etc., shown in the drawings to describe various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the examples in the drawings. Unless a term such as "only" is used, one or more other elements may be added when the terms "comprising," "having," "including," "containing," "constituting," etc., are used. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context clearly indicates otherwise.

[0013] Although the terms "first," "second," A, B, (a), (b), etc., may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0014] When referring to the first element as "connected or coupled to" or "overlapping" with the second element, it should be interpreted that the first element can not only be "directly connected or coupled to" or "directly contact or overlap" with the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled" or "overlapped" with each other through a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled" or "contact or overlap" with each other.

[0015] When describing positional relationships, for example, when using terms such as "above," "on top," "below," "over," "below," "beside," "adjacent," etc., to describe the positional relationship between two components, one or more other components may be located between the two components, unless more restrictive terms such as "immediately," "directly," or "near" are used. For example, when one element or layer is positioned "above" another element or layer, a third element or layer may be inserted therebetween. Furthermore, the terms "left," "right," "top," "bottom," "downward," "upward," "upper," "lower," etc., refer to any reference frame.

[0016] Furthermore, when referring to any dimension, relative size, etc., it should be considered that the numerical value or corresponding information of an element or feature (e.g., level, range, etc.) includes tolerances or error ranges, which may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.) even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "may".

[0017] Various embodiments of the present disclosure will be described in detail below with reference to the drawings. Additionally, for ease of description, the scale of each element shown in the drawings may differ from the actual scale. Therefore, the elements shown are not limited to the specific scales they are shown in the drawings.

[0018] Figure 1 shows an example system configuration of a display device 100 according to various aspects of this disclosure.

[0019] Referring to FIG1, the display device 100 according to various aspects of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110.

[0020] The driving circuit may include a data driving circuit 120, a gate driving circuit 130, etc., and also includes a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130.

[0021] The display panel 110 may include a substrate SUB and signal lines such as multiple data lines DL and multiple gate lines GL disposed on the substrate SUB. The display panel 110 may include multiple sub-pixels SP connected to the multiple gate lines GL and the multiple data lines DL.

[0022] The display panel 110 may include a display area DA in which one or more images can be displayed and a non-display area NDA located outside the display area DA and not allowed to display images. For example, a plurality of sub-pixels SP for displaying images may be disposed in the display area DA of the display panel 110. Driving circuits (120, 130 and 140) may be electrically connected to or mounted on the non-display area NDA of the display panel 110, and one or more pads to which one or more integrated circuits or one or more printed circuits are connected may be disposed in the non-display area NDA.

[0023] The data drive circuit 120 may be a circuit for driving multiple data lines DL and capable of providing data signals to the multiple data lines DL. The gate drive circuit 130 may be a circuit for driving multiple gate lines GL and capable of providing gate signals to the multiple gate lines GL. The controller 140 may provide a data control signal DCS to the data drive circuit 120 to control the operating time of the data drive circuit 120. The controller 140 may provide a gate control signal GCS to the gate drive circuit 130 to control the operating time of the gate drive circuit 130.

[0024] The controller 140 can control the start of the scanning operation according to the corresponding time for processing each frame, convert the image data input from other devices or other image sources (e.g., host system) into the data signal form used in the data driving circuit 120, and then provide the converted image data Data to the data driving circuit 120, and control the data driving to be executed at a predetermined time according to the scanning process.

[0025] In order to control the gate drive circuit 130, the controller 140 can provide various types of gate control signals GCS, such as gate start pulse (GSP), gate shift clock (GSC), gate output enable (GOE) signal, etc.

[0026] In order to control the data drive circuit 120, the controller 140 can provide various types of data control signals DCS, such as source start pulse (SSP), source sampling clock (SSC), source output enable (SOE) signal, etc.

[0027] The controller 140 may be implemented as a separate element from the data drive circuit 120, or integrated with the data drive circuit 120 and thus implemented in a single integrated circuit.

[0028] The data driving circuit 120 can drive multiple data lines DL by providing a data voltage corresponding to the image data Data received from the controller 140 to the multiple data lines DL. The data driving circuit 120 can also be called a source driving circuit.

[0029] The data drive circuit 120 may include, for example, one or more source driver integrated circuits (SDICs).

[0030] In one or more embodiments, each source driver integrated circuit (SDIC) may be connected to the display panel 110 using tape-and-reel auto-bonding (TAB) technology, or to conductive pads, such as bonding pads of the display panel 110, using wafer-on-glass (COG) technology or wafer-on-panel (COP) technology, or to the display panel 110 using wafer-on-film (COF) technology.

[0031] The gate drive circuit 130 can provide a gate signal with a conduction level voltage or a gate signal with a cutoff level voltage according to the control of the controller 140. The gate drive circuit 130 can sequentially drive multiple gate lines GL by sequentially providing the gate signal with the conduction level voltage to multiple gate lines GL.

[0032] For example, the gate drive circuit 130 can be connected to the display panel 110 using tape-on-brush (TAB) technology, or connected to conductive pads, such as bonding pads of the display panel 110, using wafer-on-glass (COG) technology or wafer-on-panel (COP) technology, or connected to the display panel 110 using wafer-on-film (COF) technology. In one or more embodiments, the gate drive circuit 130 can be disposed in the non-display area NDA of the display panel 110 using gate-on-board (GIP) technology. The gate drive circuit 130 can be disposed on the substrate SUB or connected to the substrate SUB. In the example of implementing the gate drive circuit 130 using GIP technology, the gate drive circuit 130 can be disposed in the non-display area NDA of the substrate SUB. In the example of implementing the gate drive circuit 130 using wafer-on-glass (COG) technology, wafer-on-film (COF) technology, etc., the gate drive circuit 130 can be connected to the substrate SUB.

[0033] For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. In this example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be configured not to overlap with the sub-pixels SP, or may be configured to overlap with one or more or all of the sub-pixels SP.

[0034] When a specific gate line is selected and driven by the gate drive circuit 130, the data drive circuit 120 can convert the image data Data received from the controller 140 into an analog form data voltage and provide the data voltage generated from the conversion to multiple data lines DL.

[0035] The data driving circuit 120 may be located and / or electrically connected to, but not limited to, only one side or portion of the display panel 110 (e.g., the upper edge or the lower edge). In one or more embodiments, depending on the driving scheme, panel design, etc., the data driving circuit 120 may be located and / or electrically connected to, but not limited to, both sides or portions of the display panel 110 (e.g., the upper edge and the lower edge) or at least two of the four sides or portions of the display panel 110 (e.g., the upper edge, the lower edge, the left edge, and the right edge).

[0036] The gate drive circuit 130 may be located and / or electrically connected to, but not limited to, only one side or portion of the display panel 110 (e.g., the left edge or the right edge). In one or more embodiments, depending on the driving scheme, panel design, etc., the gate drive circuit 130 may be located and / or electrically connected to, but not limited to, both sides or portions of the display panel 110 (e.g., the left edge and the right edge) or at least two of the four sides or portions of the display panel 110 (e.g., the top edge, the bottom edge, the left edge, and the right edge).

[0037] Controller 140 may be a timing controller used in typical display technologies or a control device / apparatus capable of performing additional control functions besides the typical functions of a timing controller. In one or more embodiments, controller 140 may be one or more other control circuits different from the timing controller, or circuits or elements in a control device / apparatus. Controller 140 may be implemented using various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0038] The controller 140 can be installed on a printed circuit board, flexible printed circuit, etc., and can be electrically connected to the data drive circuit 120 and the gate drive circuit 130 through the printed circuit board, flexible printed circuit, etc.

[0039] In one or more aspects, the display device 100 may be a display including a backlight unit, such as a liquid crystal display device, or may be a self-emissive display, such as an organic light-emitting diode (OLED) display, a quantum dot (QD) display, a micro-light-emitting diode (M-LED) display, etc.

[0040] In embodiments where the display device 100 according to various aspects of the present disclosure is an OLED display or implemented using an OLED display, each sub-pixel SP may include an organic light-emitting diode (OLED) as a light-emitting element, wherein the organic light-emitting diode (OLED) is a self-emissive element. In embodiments where the display device 100 according to various aspects of the present disclosure is a QD display or implemented using a QD display, each sub-pixel SP may include a light-emitting element configured with quantum dots, wherein the quantum dots are self-emissive semiconductor crystals. In embodiments where the display device 100 according to various aspects of the present disclosure is a micro LED display or implemented using a micro LED display, each sub-pixel SP may include a micro LED as a light-emitting element, wherein the micro LED is a self-emissive element and includes inorganic materials.

[0041] FIG2 shows an example equivalent circuit of a sub-pixel SP included in a display device 100 according to aspects of the present disclosure. FIG3 shows another example equivalent circuit of a sub-pixel SP included in a display device 100 according to aspects of the present disclosure.

[0042] Referring to FIG2, in one or more embodiments, each of a plurality of sub-pixels SP disposed in the display panel 110 of the display device 100 according to aspects of the present disclosure may include, for example, a light-emitting element ED such as a light-emitting diode, a driving thin-film transistor DRT, a scanning thin-film transistor SCT, and a storage capacitor Cst.

[0043] Referring to FIG2, the light-emitting element ED may include a pixel electrode PE and a common electrode CE, and includes an emitting layer EL located between the pixel electrode PE and the common electrode CE.

[0044] The pixel electrode PE of the light-emitting element ED can be an electrode disposed in each sub-pixel SP, and the common electrode CE can be an electrode shared by all or at least some of the multiple sub-pixels SP. For example, the pixel electrode PE can be an anode electrode and the common electrode CE can be a cathode electrode. In another example, the pixel electrode PE can be a cathode electrode and the common electrode CE can be an anode electrode.

[0045] In one or more embodiments, the light-emitting element ED may be an organic light-emitting diode (OLED), a light-emitting diode (LED), a quantum dot light-emitting element, etc.

[0046] The driving thin-film transistor DRT can be a thin-film transistor used to drive a light-emitting element ED, and includes, for example, a first node N1, a second node N2 and a third node N3.

[0047] The first node N1 of the driving thin-film transistor DRT can be a source node (or source electrode) or a drain node (or drain electrode) of the driving thin-film transistor DRT, and can be electrically connected to the pixel electrode PE of the light-emitting element ED. The second node N2 of the driving thin-film transistor DRT can be a drain node (or drain electrode) or a source node (or source electrode) of the driving thin-film transistor DRT, and can be electrically connected to the driving voltage line DVL to provide the driving voltage EVDD. The third node N3 of the driving thin-film transistor DRT can be a gate node (or gate electrode) of the driving thin-film transistor DRT, and can be electrically connected to the source node (or source electrode) or a drain node (or drain electrode) of the scanning thin-film transistor SCT.

[0048] The scanning thin-film transistor SCT can be turned on or off via a scan signal SCAN (which is a type of gate signal), and can be connected between the third node N3 of the driving thin-film transistor DRT and the data line DL. In other words, the scanning thin-film transistor SCT can be turned on or off via a scan gate signal SCAN carried by the scan gate line SCL (which is a type of gate line GL), and can control the electrical connection between the data line DL and the third node N3 of the driving thin-film transistor DRT.

[0049] The scanning thin-film transistor SCT can be turned on by the scanning gate signal SCAN with a conduction level voltage, and transmits the data voltage Vdata provided through the data line DL to the third node N3 that drives the thin-film transistor DRT.

[0050] In an example where the scanning thin-film transistor SCT is an n-type transistor, the on-state voltage of the scan gate signal SCAN can be a high-level voltage. In another example where the scanning thin-film transistor SCT is a p-type transistor, the on-state voltage of the scan gate signal SCAN can be a low-level voltage.

[0051] The storage capacitor Cst can be connected between the first node N1 and the third node N3 of the driving thin-film transistor DRT. The storage capacitor Cst can store the amount of charge corresponding to the voltage difference between its two terminals and maintain the voltage difference between the two terminals for a predetermined frame time. Therefore, the sub-pixel SP can emit light within the predetermined frame time.

[0052] Referring to FIG3, in one or more embodiments, each of a plurality of sub-pixels SP disposed in the display panel 110 of the display device 100 according to aspects of the present disclosure may further include a sensing thin-film transistor SENT.

[0053] The sensing thin-film transistor SENT can be turned on or off by a sensing gate signal SENSE, which serves as a gate signal, and can be connected between the first node N1 of the driving thin-film transistor DRT and the reference voltage line RVL. In other words, the sensing thin-film transistor SENT can be turned on or off by a sensing gate signal SENSE carried by a sensing gate line SENL, which serves as another type of gate line GL, and can control the electrical connection between the reference voltage line and RVL and the first node N1 of the driving thin-film transistor DRT.

[0054] The sensing thin-film transistor SENT can be turned on by the sensing gate signal SENSE with a conduction level voltage, and transmits the reference voltage Vref provided through the reference voltage line RVL to the first node N1 of the driving thin-film transistor DRT.

[0055] In addition, the sensing thin-film transistor SENT can be turned on by the sensing gate signal SENSE with a conduction level voltage, and transmit the voltage in the first node N1 of the driving thin-film transistor DRT to the reference voltage line RVL.

[0056] In an example where the sensing thin-film transistor SENT is an n-type transistor, the on-state voltage of the sensing gate signal SENSE can be a high-level voltage. In another example where the sensing thin-film transistor SENT is a p-type transistor, the on-state voltage of the sensing gate signal SENSE can be a low-level voltage.

[0057] The function of the sensing thin-film transistor SENT in transmitting the voltage of the second node N2 of the driving thin-film transistor DRT to the reference voltage line RVL can be used in sensing drive or sensing mode for sensing at least one characteristic value of sub-pixel SP. In this embodiment, the voltage transmitted to the reference voltage line RVL can be a voltage used to calculate at least one characteristic value of pixel SP or a voltage added to or counted with at least one characteristic value of sub-pixel SP.

[0058] Each of the driving thin-film transistor DRT, scanning thin-film transistor SCT, and sensing thin-film transistor SENT included in the display panel 110 may be an n-type transistor or a p-type transistor. In this document, for ease of description, the driving thin-film transistor DRT, scanning thin-film transistor SCT, and sensing thin-film transistor SENT included in the display panel 110 are considered to be n-type transistors.

[0059] The storage capacitor Cst may be an external capacitor that is not an internal capacitor and is intentionally designed to be located outside the driving thin film transistor DRT, such as a parasitic capacitor (e.g., Cgs, Cgd), which may be formed between the gate node and the source node (or drain node) of the driving thin film transistor DRT.

[0060] In one embodiment, the scanning gate line SCL and the sensing gate line SENL can be different gate lines GL. In this embodiment, the scanning gate signal SCAN and the sensing gate signal SENSE can be separate gate signals, and the turn-on and turn-off times of the scanning thin-film transistor SCT and the sensing thin-film transistor SENT included in a sub-pixel SP may be independent of each other. That is, the turn-on and turn-off times of the scanning thin-film transistor SCT and the sensing thin-film transistor SENT included in a sub-pixel SP can be the same or different from each other.

[0061] In another embodiment, the scanning gate line SCL and the sensing gate line SENL can be the same gate line GL. That is, the gate nodes of the scanning thin-film transistor SCT and the sensing thin-film transistor SENT included in a sub-pixel SP can be connected to a single gate line GL. In this embodiment, the scanning gate signal SCAN and the sensing gate signal SENSE can be the same gate signal, and the turn-on and turn-off times of the scanning thin-film transistor SCT and the sensing thin-film transistor SENT included in a sub-pixel SP may be the same.

[0062] The subpixel structures shown in Figures 2 and 3 are merely examples and can be modified in various ways by further including one or more thin-film transistors or one or more capacitors.

[0063] Furthermore, although the discussion of the sub-pixel structure in Figures 2 and 3 is based on the example that the display device 100 is a self-emissive display device, in the example that the display device 100 is a liquid crystal display, each sub-pixel SP may include a thin-film transistor, a pixel electrode, etc.

[0064] FIG4 shows an example light shield included in a sub-pixel (e.g., a sub-pixel of FIG3) of a display device 100 according to various aspects of the present disclosure.

[0065] Referring to FIG4, the driving thin-film transistor (DRT) included in the sub-pixel SP of the display device 100 may have one or more unique electrical characteristics, such as threshold voltage, mobility, etc. When one or more unique electrical characteristics of the driving thin-film transistor (DRT) change, the current driving capability (current supply capability) of the driving thin-film transistor (DRT) may change, and thus the light emission characteristics of the sub-pixel SP including the driving thin-film transistor (DRT) may also be different.

[0066] One or more electrical characteristics (e.g., threshold voltage, mobility, etc.) of the driving thin-film transistor DRT may change with increasing driving time of the driving thin-film transistor DRT. When light irradiates the driving thin-film transistor DRT, especially the channel region of the driving thin-film transistor DRT, one or more electrical characteristics (e.g., threshold voltage, mobility, etc.) of the driving thin-film transistor DRT may differ.

[0067] To address these issues, as shown in Figure 4, to reduce variations in one or more electrical characteristics (e.g., threshold voltage, mobility, etc.) of the driving thin-film transistor (DRT), a light-shielding element LS can be disposed around the driving thin-film transistor (DRT). For example, the light-shielding element LS can be disposed below the channel region of the driving thin-film transistor (DRT).

[0068] In addition to being used for light shielding, the light shielding element LS can also be used as the main body of the driving thin film transistor DRT, and is located below the channel region of the driving thin film transistor DRT.

[0069] Consequently, a bulk effect may occur in the driving thin-film transistor (DRT). To reduce the influence of the bulk effect, the light-shielding member LS, which serves as the main body of the driving DRT, can be electrically connected to the first node N1 of the driving DRT. The first node N1 of the driving DRT can be, for example, the source node of the driving DRT.

[0070] In one or more embodiments, the light-shielding element LS may be disposed below the corresponding channel region of one or more other thin-film transistors (e.g., SCT and / or SENT), and below the channel region of the driving thin-film transistor DRT.

[0071] In one or more embodiments, thin-film transistors (DRT, SCT, and / or SENT) may be disposed in each sub-pixel SP included in the display area DA of the display panel 110. In one or more embodiments where the gate drive circuit 130 is disposed in the non-display area NDA of the display panel 110 using gate-in-board (GIP) technology, a plurality of transistors included in the gate drive circuit 130 implemented using GIP technology may be disposed in the non-display area NDA of the display panel 110.

[0072] FIG5 is a plan view of an example thin-film transistor included in a display panel 110 according to various aspects of the present disclosure. FIG6 is an exemplary cross-sectional view taken along line AB of FIG5. FIG7 and FIG8 are example cross-sectional views taken along line CD of FIG5. FIG9 and FIG10 are example cross-sectional views taken along line EF of FIG5. FIG11 is an example cross-sectional view taken along line GH of FIG5. FIG12 is an example cross-sectional view taken along line IJ of FIG5.

[0073] In one or more embodiments, the display panel 110 may include a display area DA in which one or more images may be displayed, and a non-display area NDA different from the display area DA. A plurality of thin-film transistors may be disposed in the display area DA and / or the non-display area NDA.

[0074] In one or more embodiments, all or at least some of the thin-film transistors disposed in the display panel 110 may be thin-film transistors (DRT, SCT and / or SENT) included in each of a plurality of sub-pixels SP disposed in the display area DA of the display panel 110.

[0075] In one or more embodiments, all or at least some of the thin-film transistors disposed in the display panel 110 may be thin-film transistors included in the gate drive circuit 130 implemented using GIP technology in the non-display area NDA of the display panel 110.

[0076] In the following, a discussion of thin-film transistor structures according to embodiments of the present disclosure is provided, based on the driving thin-film transistors DRTs included in each sub-pixel SP disposed in the display area DA as example thin-film transistors.

[0077] Referring to Figures 5 and 6, in one or more embodiments, the display panel 110 of the display device 100 may include a substrate 600, a buffer layer 601 on the substrate 600, a first active layer 510 on the buffer layer 601, and a first electrode 530, a second electrode 540, and a third electrode 550 disposed on the first active layer 510.

[0078] In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may include at least one thin-film transistor (Tr), and the at least one thin-film transistor (Tr) may include a first active layer 510, a second active layer 520, a first electrode 530, a second electrode 540 and a third electrode 550.

[0079] In one embodiment, the first electrode 530 may be the source of a thin-film transistor (Tr), and the second electrode 540 may be the drain of a thin-film transistor (Tr). In another embodiment, the first electrode 530 may be the drain of a thin-film transistor (Tr), and the second electrode 540 may be the source of a thin-film transistor (Tr). The third electrode 550 may be the gate electrode of a thin-film transistor (Tr).

[0080] Referring to Figure 6, the second active layer 520 may be disposed below the first active layer 510. For example, the second active layer 520 may be disposed between the buffer layer 601 and the first active layer 510.

[0081] The first active layer 510 may include a first channel region CH1, and the second active layer 520 may include a second channel region CH2.

[0082] Each of the first channel region CH1 and the second channel region CH2 may overlap with the third electrode 550. The first channel region CH1 and the second channel region CH2 may not overlap with each other.

[0083] The first active layer 510 and the second active layer 520 may include oxide semiconductor materials. The first active layer 510 and the second active layer 520 may include different oxide semiconductor materials. The oxide semiconductor material may be a semiconductor material obtained by controlling the conductivity and adjusting the bandgap through doping of the oxide material, and is generally a transparent semiconductor material with a wide bandgap.

[0084] For example, each of the first active layer 510 and the second active layer 520 may include at least one of the following compounds: indium zinc oxide (IZO), thin transparent tungsten-doped indium zinc oxide (WIZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium gallium tin zinc oxide (IGTZO), zinc oxynitride (ZnON), and indium gallium oxide (IGO). However, embodiments of this disclosure are not limited thereto. For example, any oxide semiconductor material capable of giving each of the first active layer 510 and the second active layer 520 a high mobility may be included in the first active layer 510 and the second active layer 520. In these examples, the respective mobilities of the first active layer 510 and the second active layer 520 may be different from each other.

[0085] In one embodiment, the first active layer 510 may include indium zinc oxide (IZO), and the second active layer 520 may include indium gallium zinc oxide (IGZO). However, embodiments of this disclosure are not limited thereto.

[0086] In an example where the first active layer 510 and the second active layer 520 respectively comprise indium zinc oxide (IZO) and indium gallium zinc oxide (IGZO), the indium content of indium zinc oxide (IZO) can be 50% to 70%, and the indium content of indium gallium zinc oxide (IGZO) can be 75% or more and less than 100%. In this way, an oxide semiconductor material with high mobility can be achieved by adjusting the corresponding indium content of this oxide semiconductor material.

[0087] When one or more active layers include the oxide semiconductor material as described above, the thin film transistor including one or more active layers can be called an oxide thin film transistor.

[0088] Referring to Figure 6, the gate insulating layer 602 may be disposed on the first active layer 510 and the second active layer 520. The gate insulating layer 602 may be disposed in corresponding portions of the upper surfaces of the first active layer 510 and the second active layer 520.

[0089] The gate insulation layer 602 may be disposed on a portion of the first active layer 510 and the second active layer 520 that overlap, on a portion of the second active layer 520 that does not overlap with the first active layer 510, and in a portion of the region located below the first active layer 510 that does not overlap with the first active layer 510.

[0090] The gate insulating layer 602 may overlap with the first channel region CH1 of the first active layer 510 and the second channel region CH2 of the second active layer 520.

[0091] The first electrode 530, the second electrode 540 and the third electrode 550 may be disposed on the first active layer 510 and the second active layer 520.

[0092] The first channel region CH1 of the first active layer 510 and the second channel region CH2 of the second active layer 520 may overlap with the gate electrode (e.g., the third electrode 550). The area of ​​the first active layer 510 disposed on the second active layer 520 around the second channel region CH2 and overlapping with the third electrode 550 may be at least a portion of the remaining area of ​​the first active layer 510 other than the first channel region CH1.

[0093] Although Figures 5 and 6 show a structure in which the third electrode 550, used as a gate electrode, is disposed on the first active layer 510 and the second active layer 520, the embodiments of this disclosure are not limited thereto. For example, the third electrode 550 may be disposed below the first active layer 510 and the second active layer 520.

[0094] Although Figures 5 and 6 show a structure in which the gate insulating layer 602 is disposed only below the third electrode 550, the embodiments of this disclosure are not limited thereto. For example, the gate insulating layer 602 may also be disposed in at least a portion of the remaining region other than the region where the first electrode 530 and the second electrode 540 contact the first active layer 510.

[0095] Referring to Figures 5 and 6, the first electrode 530, the second electrode 540 and the third electrode 550 can be spaced apart from each other.

[0096] In one or more embodiments, referring to FIG6, the first electrode 530 and the second electrode 540 may be configured to contact corresponding portions of the upper surface of the first active layer 510.

[0097] The third electrode 550 can be disposed on the gate insulating layer 602.

[0098] Each of the first electrode 530, the second electrode 540, and the third electrode 550 may be configured with a single layer or multiple layers. For example, each of the first electrode 530, the second electrode 540, and the third electrode 550 may be configured with a single layer including copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), molybdenum-titanium (MoTi), etc.

[0099] In an example where at least one of the first electrode 530, the second electrode 540 and the third electrode 550 is configured in multiple layers, at least one of the first electrode 530, the second electrode 540 and the third electrode 550 may include a corresponding lower electrode and a corresponding upper electrode that are electrically connected to each other.

[0100] The lower electrode may include a first metal, and the upper electrode may include a second metal different from the first metal. For example, the first metal may include molybdenum (Mo), titanium (Ti), molybdenum-titanium (MoTi), etc., and the second metal may include copper (Cu), aluminum (Al), etc. However, the embodiments of this disclosure are not limited thereto.

[0101] As shown in Figures 5 and 6, each of the first electrode 530 and the second electrode 540 may be disposed in a corresponding portion of the first active layer 510, for example, disposed in a corresponding portion of the upper surface of the first active layer 510, and electrically connected to the first active layer 510.

[0102] In one or more embodiments, each of the first electrode 530 and the second electrode 540 may overlap with both the first active layer 510 and the second active layer 520 in a portion of the region, and / or may overlap with only the first active layer 510 in another portion of the region.

[0103] For example, as shown in FIG5, the second active layer 520 disposed below the first active layer 510 can overlap with the first active layer 510 in the remaining area except for the second channel region CH2.

[0104] In one or more embodiments, the display device 100 according to various aspects of the present disclosure may include at least one thin-film transistor, the thin-film transistor including one or more first active layers 510, one or more second active layers 520, a first electrode 530, a second electrode 540 and a third electrode 550.

[0105] At least one thin-film transistor may have a structure in which the first active layer 510 and the second active layer 520 located in different regions share a first electrode 530, a second electrode 540 and a third electrode 550.

[0106] In an example where the first active layer 510 includes indium zinc oxide (IZO), when the first active layer 510 is electrically connected to indium zinc oxide (IZO), the electron mobility of the thin-film transistor can be increased. Therefore, it can provide the effect of reducing the power consumption of the display device 100.

[0107] In an example where the second active layer 520 includes indium gallium zinc oxide (IGZO), the conduction current of the thin-film transistor can be increased and the reliability of the thin-film transistor can be improved.

[0108] In other words, the thin-film transistors according to embodiments of the present disclosure can have high electron mobility and improved reliability.

[0109] Referring to Figures 7 and 8, the second active layer 520 may have a second channel region CH2 in a region where the second active layer 520 does not overlap with the first active layer 510.

[0110] Referring to Figures 7 and 8, the gate insulating layer 602 may be disposed on the second channel region CH2 of the second active layer 520 and a portion of the first active layer 510. The first active layer 510 overlapping the gate insulating layer 602 may be configured such that the first active layer 510 surrounds the second channel region CH2.

[0111] The first width W1 of the second channel region CH2 may be different from the second width W2 of the gate insulation layer 602.

[0112] For example, as shown in Figures 7 and 8, the first width W1 can be less than or equal to the second width W2.

[0113] The first width W1 of the second channel region CH2 of the second active layer 520 can be determined according to the position of the first active layer 510.

[0114] For example, as the area of ​​the first active layer 510 overlapping with the gate insulating layer 602 on the second active layer 520 increases, the first width W1 of the second channel region CH2 can be reduced. In another example, as the area of ​​the first active layer 510 overlapping with the gate insulating layer 602 on the second active layer 520 decreases, the first width W1 of the second channel region CH2 can be increased.

[0115] In this way, the first width Wl of the second channel region CH2 of the second active layer 520 can be adjusted by adjusting the overlap area between the first active layer 510 and the gate insulation layer 602, which makes the second active layer 520 more effectively have a short channel region without a separate process.

[0116] Referring to Figures 9 and 10, the gate insulation layer 602 can be disposed on the first channel region CH1 of the first active layer 510.

[0117] The first width W3 of the first channel region CH1 can be the same as the second width W2 of the gate insulating layer 602. Although Figures 9 and 10 show a structure where the second width W2 and the third width W3 are the same, the embodiments of this disclosure are not limited thereto. For example, the second width W2 can be smaller than the third width W3.

[0118] During the process of performing dry etching on the gate insulating layer material to form the gate insulating layer 602 disposed on the first active layer 510, the first active layer 510 may become partially conductive, and the area of ​​the first active layer 510 corresponding to the area where the gate insulating film 602 is finally disposed may not become conductive because the plasma has no effect on that area.

[0119] However, the area where the first active layer 510 becomes conductive can vary depending on the dry etching process conditions.

[0120] The first width W1, the second width W2 and the third width W3 mentioned above can refer to the corresponding minimum lengths in the direction perpendicular to the direction in which the gate insulation layer 602 is stacked on the first active layer 510.

[0121] Although Figures 7 and 9 show the structure in which the buffer layer 601 and the substrate 600 are disposed below the first active layer 510 or the second active layer 520, the structure according to the embodiments of this disclosure is not limited thereto.

[0122] For example, as shown in Figures 8 and 10, at least one light-shielding member 860 may be provided, such that at least one light-shielding member 860 corresponds to the area where the first channel area CH1 and the second channel area CH2 are provided.

[0123] The entire area of ​​the first channel region CH1 and the second channel region CH2 can overlap with the light-shielding member 860. In this way, one or more properties of one or more thin-film transistors can be prevented from being degraded by light irradiating the first channel region CH1 and the second channel region CH2.

[0124] Referring to Figure 11, the first active layer 510 can be disposed below the first electrode 530.

[0125] The second active layer 520 may be disposed below the first active layer 510. A portion of the second active layer 520 may overlap with a portion of the first active layer 510.

[0126] The buffer layer 601 and the substrate 600 may be disposed below the first active layer 510.

[0127] Referring to Figures 5 and 11, the first electrode 530 may be disposed in a portion of the region where the first active layer 510 and the second active layer 520 overlap with each other, and may also be disposed in a portion of the region where the first active layer 510 does not overlap with the second active layer 520.

[0128] Although FIG11 shows a structure in which the first active layer 510 and the second active layer 520 are disposed below the first electrode 530, the embodiments of the present disclosure are not limited thereto. For example, the elements disposed below the first electrode 530 and the structure formed thereunder can be applied or formed substantially equivalently below the second electrode 540.

[0129] Referring to Figure 12, the gate insulating layer 602 may be disposed below the third electrode 550. The first active layer 510 and the second active layer 520 may be spaced apart from each other below the gate insulating layer 602.

[0130] The first active layer 510 and the second active layer 520 shown in Figure 12 can be regions corresponding to the first channel region CH1 and the second channel region CH2, respectively, in the corresponding regions of the first active layer 510 and the second active layer 520.

[0131] Referring to FIG12, the buffer layer 601 and the substrate 600 may be disposed below the first active layer 510 and the second active layer 520.

[0132] The manufacturing process of the thin-film transistors shown in Figures 5 and 6 will be discussed below.

[0133] Figures 13 to 17 illustrate exemplary processes for manufacturing the thin-film transistors shown in Figures 5 and 6.

[0134] Referring to Figure 13, the buffer layer 601 can be disposed on the substrate 600.

[0135] Referring to Figure 14, the second active layer 520 may be disposed in a portion of the upper surface of the buffer layer 601.

[0136] The material of the second active layer can be formed on the buffer layer 601, and the second active layer 520 can be formed such that a portion of the upper surface of the buffer layer 601 is exposed through a patterning process using a photomask.

[0137] Referring to Figure 15, the first active layer pattern 1510 can be disposed on the buffer layer 601 on which the second active layer 520 is formed.

[0138] The first active layer pattern 1510 can be configured such that a portion of the upper surface of the second active layer 520 is exposed.

[0139] In other words, as shown in FIG15, a portion of the first active layer pattern 1510 can be disposed on a portion of the second active layer 520.

[0140] For example, as shown in FIG15, the first active layer pattern 1510 may be formed in the shape of "ㄷ", and at least a portion of the first active layer pattern 1510 may be spaced apart from the second active layer 520.

[0141] Meanwhile, in Figure 15, the area of ​​the second active layer 520 that does not overlap with the pattern 1510 of the first active layer can be a portion of the second channel region CH2 to be developed into the second active layer 520.

[0142] Referring to FIG15, the first active layer pattern 1510 may include: a first portion 1511, which extends along a first direction and partially overlaps with the second active layer 520; a second portion 1512, which extends along the first direction, partially overlaps with the second active layer 520 and is spaced apart from the first portion 1511; and a third portion 1513, which extends along a second direction intersecting the first direction, is disposed between the first portion 1511 and the second portion 1512 and does not overlap with the second active layer 520. Alternatively, the third portion 1513 may overlap with the second active layer 520.

[0143] The third part 1513 may be a portion of the first channel area CH1 that will be formed in the first active layer 510 in subsequent processes.

[0144] Although FIG15 shows that the portion of the second channel region CH2 to be developed as the second active layer 520 and the third portion 1513 as the portion of the first channel region CH1 to be developed as the first active layer 510 are spaced apart from each other, in one or more embodiments, the side surfaces of the portion to be developed as the second channel region CH2 and the side surfaces of the third portion 1513 may be in contact with each other.

[0145] For example, the third portion 1513 may extend in the second direction and contact a portion of the second channel region CH2 that will be developed into the second active layer 520. In this way, the size of the third portion 1513 can be varied according to the desired characteristics of the corresponding thin-film transistor (TR).

[0146] In another example, the second active layer 520 may extend in a second direction and contact a portion of the first channel region CH1 that will be developed into the first active layer 510.

[0147] Referring to FIG16, the gate insulating layer material 1602 can be disposed on the substrate 600 on which the second active layer 520 and the first active layer pattern 1510 are disposed.

[0148] Thereafter, electrode material can be disposed on gate insulating layer material 1602.

[0149] As shown in Figure 17, the electrode material can be patterned through a photomask process to form the first electrode 530, the second electrode 540 and the third electrode 550.

[0150] Thereafter, as shown in FIG17, the gate insulating layer material 1602 can be patterned by using the first to third electrodes (530, 540 and 550) as photomasks through a dry etching process, thereby forming a gate insulating layer material 602 that exposes a portion of the upper surface of the first active layer pattern.

[0151] In the dry etching process, the pattern of the first active layer located in the region where the first to third electrodes (530, 540, and 550) and the gate insulating layer 602 are not disposed can become conductive through plasma, thereby forming the first active layer 510. That is, the region of the first active layer 510, excluding the region overlapping with the first electrode 530, the second electrode 540, and the third electrode 550, can be a conductive enabling region. The first electrode 530 can be disposed on a portion of the first portion 1511. The second electrode 540 can be disposed on a portion of the second portion 1512. Each of the first electrode 530 and the second electrode 540 can be disposed on a region of the first active layer 510 disposed on the second active layer 520 and a portion of the region of the first active layer 510 that does not overlap with the second active layer 520. The third electrode 550 can overlap with the third portion 1513 of the first active layer 510. The first channel region CH1 of the first active layer 510 may overlap with the second active layer CH2, and the second channel region CH2 of the second active layer 520 may not overlap with the first active layer 510. Alternatively, the entirety of each of the first electrode 530 and the second electrode 540 may overlap with the first active layer 510 and the second active layer 520.

[0152] The portion of the first active layer 510 disposed in the area left by the first to third electrodes (530, 540 and 550) and the gate insulating layer 602 may not become conductive. In other words, the area of ​​the first active layer 510 disposed below the first to third electrodes (530, 540 and 550) and the gate insulating layer 602 may not become conductive.

[0153] Since the gate insulating layer 602 or the first active layer 510 is disposed on the second active layer 520, the second active layer 520 may not become conductive during the process of forming the gate insulating layer 602.

[0154] The region of the first active layer 510 that overlaps with the gate insulating layer 602 may include the first channel region CH1, and the region of the second active layer 520 that overlaps with the gate insulating layer 602 may include the second channel region CH2.

[0155] The thin-film transistor formed through the above process may include two channel regions for each thin-film transistor, and these two channel regions may be connected in parallel. In addition, the channel regions (first channel region and second channel region) may include different materials.

[0156] Through this structure, the thin-film transistor according to the embodiments of the present disclosure can have the characteristics of high electron mobility and improved reliability.

[0157] Figures 18 and 19 show example electrical characteristics of thin-film transistors according to Comparative Example 1, Comparative Example 2 and Example 1.

[0158] The thin-film transistor of Comparative Example 1 in Figures 18 and 19 can be a typical thin-film transistor comprising an active layer and a first to a third electrode disposed on the active layer, wherein the active layer comprises indium gallium zinc oxide (IGZO). The thin-film transistor of Comparative Example 2 can be a typical thin-film transistor comprising an active layer and a first to a third electrode disposed on the active layer, wherein the active layer comprises indium zinc oxide (IZO). The thin-film transistor of Example 1 can represent the thin-film transistor of Figure 5 as discussed above.

[0159] Figure 18 is a graph of gate voltage versus drain current for thin-film transistors according to Comparative Example 1, Comparative Example 2 and Example 1 (under positive bias temperature stress of 11 hours (PBTS 11hr)). Figure 19 is a graph of current and threshold voltage (Vth) change ΔVth for each thin-film transistor based on the area of ​​the channel region of the corresponding first active layer and the area of ​​the second channel region of the corresponding second active layer (under positive bias temperature stress of 11 hours).

[0160] As shown in Figures 18 and 19, the thin-film transistor according to Comparative Example 1 has high reliability characteristics, but may not be suitable for low-power display devices due to its low on-current characteristics and low current.

[0161] As shown in Figures 18 and 19, the thin-film transistor according to Comparative Example 2 generates a high current, but may not be suitable for display devices that require high performance due to its low reliability.

[0162] In contrast, the thin-film transistor according to Embodiment 1 has high on-current characteristics, high reliability, and high current generation characteristics, and is therefore suitable for high-performance and high-capacity display devices. In addition, the thin-film transistor of Embodiment 1 is particularly suitable for low-power display panels that require high reliability and high mobility characteristics (high current).

[0163] Meanwhile, in the discussion related to FIG15, it has been described that the dimensions of the first active layer 510 or the second active layer 520 can be changed. In the following, the thin-film transistor characteristics based on the corresponding areas of the channel regions of the first active layer 510 and the second active layer 520 will be discussed with reference to FIGS. 20 and 21.

[0164] Figure 20 is an example diagram of the gate voltage versus drain current of a thin-film transistor based on the area of ​​the first channel region of the corresponding first active layer and the area of ​​the second channel region of the corresponding second active layer (under positive bias temperature stress of 11 hours). Figure 21 is an example diagram showing the current of the thin-film transistor of Figure 20.

[0165] Referring to Figures 20 and 21 and Figures 15 to 17, the thin-film transistor according to Embodiment 2 may have a structure in which the area of ​​the first channel region CH1 of the first active layer 510 is 1 / 3 of the area of ​​the second channel region CH2 of the second active layer 520 (i.e., the ratio of the area of ​​the first channel region CH1 to the area of ​​the second channel region CH2 is 1:3). The thin-film transistor according to Embodiment 3 may have another structure in which the area of ​​the first channel region CH1 of the first active layer 510 is equal to the area of ​​the second channel region CH2 of the second active layer 520 (i.e., the ratio of the area of ​​the first channel region CH1 to the area of ​​the second channel region CH2 is 1:1). The thin-film transistor according to Embodiment 4 may also have another structure in which the area of ​​the first channel region CH1 of the first active layer 510 is three times the area of ​​the second channel region CH2 of the second active layer 520 (i.e., the ratio of the area of ​​the first channel region CH1 to the area of ​​the second channel region CH2 is 3:1).

[0166] Referring to Figure 21, as the area of ​​the first channel region CH1 increases, the current increases. However, as shown in Figure 21, it can be seen that the possibility of degradation may occur due to the increase in bias stress.

[0167] For example, the stability of such thin-film transistors may be reduced when a hump phenomenon, which appears to be a transistor having two threshold voltages, is observed in the gate voltage versus drain current curve.

[0168] The structure of the thin-film transistor of Example 3 shown in Figures 20 and 21 can be the same as the structure of the thin-film transistor of Example 1 shown in Figures 18 and 19.

[0169] When comparing the gate voltage versus drain current curves of the thin-film transistors according to Examples 2 to 4 shown in FIG. 20 with the gate voltage versus drain current curves of the thin-film transistor according to Comparative Example 2 shown in FIG. 18, it can be seen that no peak phenomenon occurs in the thin-film transistors of Examples 2 to 4, but a peak phenomenon occurs in the thin-film transistor of Comparative Example 2. Therefore, although the thin-film transistors according to Examples 2 to 4 have high reliability, the thin-film transistor of Comparative Example 2 may have low reliability.

[0170] When the current of the thin film transistors according to Examples 2 to 4 shown in FIG21 is compared with the current of the thin film transistor according to Comparative Example 1 shown in FIG19, it can be seen that the current of the thin film transistors according to Examples 2 to 4 is higher than the current of the thin film transistor according to Comparative Example 1 shown in FIG19.

[0171] Therefore, when a thin film transistor includes an active layer containing an oxide semiconductor material of a certain type (e.g., the thin film transistors of Comparative Example 1 and Comparative Example 2), the thin film transistor may have characteristics such that although the reliability of the thin film transistor is high, its current is low, or although the reliability is low, its current is high.

[0172] In other words, typical thin-film transistors such as Comparative Example 1 and Comparative Example 2 may not be able to simultaneously have high reliability and high current generation characteristics.

[0173] In contrast, the thin-film transistors according to embodiments of the present disclosure can simultaneously have high reliability and high current generation characteristics through a first active layer 510 and a second active layer 520 comprising different oxide semiconductor materials.

[0174] Specifically, referring to Figures 20 and 21, the ratio of the area of ​​the first channel region CH1 of the first active layer 510 to the area of ​​the second channel region CH2 of the second active layer 520 can be 1:3 to 3:1.

[0175] In an example where the area of ​​the second channel region CH2 is more than three times the area of ​​the first channel region CH1, the current generation characteristics of the corresponding thin-film transistor may be reduced, and therefore the power consumption may increase when such a thin-film transistor is applied to a display device.

[0176] In an example where the area of ​​the second channel region CH2 is less than 1 / 3 of the area of ​​the first channel region CH1, a hump phenomenon may occur and the reliability of the thin-film transistor may be reduced.

[0177] The thin-film transistors according to embodiments of the present disclosure can be used as various thin-film transistors applied to the display device 100.

[0178] For example, the thin-film transistor according to the above embodiment can be used as a driving thin-film transistor, as described below with reference to FIG22.

[0179] FIG22 is an example cross-sectional view showing the structure of a thin-film transistor electrically connected to an organic light-emitting element (e.g., OLED) in a display device 100 according to various aspects of the present disclosure.

[0180] In the following description, for ease of description, some configurations, effects, etc. of the embodiments or examples discussed above may not be repeated. However, it should be understood that the scope of this disclosure includes such omitted configurations already discussed above. Furthermore, in the following description, the same reference numerals will be used for constructions or elements that are the same as, substantially the same as, or nearly the same as, those in the above embodiments or examples.

[0181] Referring to Figure 22, the thin-film transistor TR (see Figure 23), the storage capacitor Cst, and the organic light-emitting element OLED can be disposed on the substrate 600.

[0182] Specifically, the light-shielding member 860 may be disposed on the substrate 600.

[0183] The buffer layer 601 can be set on the light-shielding component 860.

[0184] The first active layer 510, the second active layer 520, and the first storage capacitor electrode 2210 can be disposed on the buffer layer 601. The first storage capacitor electrode 2210 and the first active layer 510 can be disposed on the same layer.

[0185] Referring to FIG22, a portion of the first active layer 510 may be disposed on a portion of the upper surface of the buffer layer 601, and another portion of the first active layer 510 may be disposed on the second active layer 520.

[0186] Referring to FIG22, the first storage capacitor electrode 2210 may be disposed on a portion of the upper surface of the buffer layer 601 and may include the same material as the first active layer 510.

[0187] The gate insulating layer 602 may be disposed on a portion of the upper surface of the first active layer 510, a portion of the upper surface of the second active layer 520, and the first storage capacitor electrode 2210.

[0188] The first electrode 530, the second electrode 540, the third electrode 550, and the second storage capacitor electrode 2150 can be disposed on a substrate 600 on which a gate insulating layer 602 is disposed. The second storage capacitor electrode 2150 can be disposed on the same layer as the first to third electrodes (530, 540, and 550).

[0189] Referring to FIG22, the first electrode 530 may contact a portion of the upper surface of the first active layer 510 disposed on the second active layer 520. The first electrode 530 may be electrically connected to the light shield 860 through a contact hole formed in the buffer layer 601.

[0190] As shown in Figure 22, not only the first storage capacitor electrode 2210 and the second storage capacitor electrode 2150, but also the light-shielding member 860 can be used as a storage capacitor electrode, thereby forming a dual storage capacitor Cst.

[0191] The passivation layer 2203 can be disposed on a substrate 600 on which the first electrode 530, the second electrode 540, the third electrode 550 and the second storage capacitor electrode 2150 are disposed.

[0192] The coating layer 2204 may be disposed on the passivation layer 2203.

[0193] As shown in FIG22, the coating layer 2204 may be disposed in a portion of the non-light-emitting region NEA and may not be disposed in the light-emitting region EA, but the embodiments of this disclosure are not limited thereto. For example, the coating layer 2204 may also be disposed in at least a portion of the light-emitting region EA.

[0194] The anode electrode 2260 of the organic light-emitting element OLED can be disposed on the coating layer 2204 and the passivation layer 2203.

[0195] A dam 2205 defining the light-emitting region EA and the non-light-emitting region NEA may be provided on a portion of the upper surface of the anode electrode 2260 and the coating layer 2204. The area where the dam 2205 is provided may be the non-light-emitting region NEA, and the area where the dam 2205 is not provided may be the light-emitting region EA.

[0196] As shown in FIG22, the anode electrode 2260 can be electrically connected to the second electrode 540 of the thin film transistor disposed in the non-light-emitting region NEA through the contact holes formed in the coating layer 2204 and the passivation layer 2203.

[0197] The emitting layer 2270 of the organic light-emitting element OLED can be disposed on the embankment 2205 and the anode electrode 2260, and the cathode electrode 2280 of the organic light-emitting element OLED can be disposed on the emitting layer 2270.

[0198] In one or more embodiments, one of the anode electrode 2260 and the cathode electrode 2280 may include a reflective electrode, but embodiments of this disclosure are not limited thereto. For example, neither the anode electrode 2260 nor the cathode electrode 2280 may include a reflective electrode.

[0199] In one or more embodiments, at least one of the anode electrode 2260 and the cathode electrode 2280 may be configured with multiple layers, but the embodiments of this disclosure are not limited thereto.

[0200] In one or more embodiments, the thin-film transistor may have a structure in which a plurality of first channel regions CH1 of the first active layer 510 and a plurality of second channel regions CH2 of the second active layer 520 are alternately arranged.

[0201] Refer to Figure 23 for further discussion of this structure.

[0202] FIG23 shows an example structure of a thin-film transistor in a display device 100 according to various aspects of the present disclosure, including a plurality of first channel regions and a plurality of second channel regions.

[0203] In the following description, for ease of description, some configurations, effects, etc. of the embodiments or examples discussed above may not be repeated. However, it should be understood that the scope of this disclosure includes such omitted configurations already discussed above. Furthermore, in the following description, the same reference numerals will be used for constructions or elements that are the same as, substantially the same as, or nearly the same as, those in the above embodiments or examples.

[0204] Referring to FIG23, in one or more embodiments, the thin-film transistor TR may include a first active layer 510, a plurality of second active layers 520, a first electrode 530, a second electrode 540, and a third electrode 550. The first active layer 510 may overlap with the plurality of second active layers 520.

[0205] For example, referring to FIG23, a plurality of second active layers 520 may be configured to be spaced apart from each other below a first active layer 510.

[0206] The thin-film transistor TR includes a first active layer 510 and multiple second active layers 520, which can share a first electrode 530, a second electrode 540 and a third electrode 550.

[0207] Referring to FIG23, each of the plurality of second active layers 520 may include a second channel region CH2. The first channel region CH1 of the first active layer 510 may be disposed among the plurality of second channel regions CH2.

[0208] For example, multiple first channel areas CH1 and multiple second channel areas CH2 can be set alternately.

[0209] The multiple first channel regions CH1 and the multiple second channel regions CH2 can be connected in parallel. In this way, a thin-film transistor TR with a wide channel region can be realized, thereby increasing the current generated by the thin-film transistor TR.

[0210] As described above, since a thin film transistor TR includes a first active layer 510 and a second active layer 520, the reliability of the thin film transistor can also be ensured (see Figures 20 and 21).

[0211] Therefore, the thin-film transistor TR shown in FIG23 can be used as a large-size transistor that requires high current generation characteristics and high reliability characteristics. For example, such a transistor can be used in gate drive circuits.

[0212] In one or more embodiments, the thin-film transistor may have a structure in which the entire remaining second active layer 520, except for the second channel region CH2, overlaps with the first active layer 510.

[0213] This structure will be further discussed with reference to Figures 24 to 28.

[0214] FIG24 shows an example thin-film transistor structure in a display device 100 according to various aspects of the present disclosure, in which the first active layer overlaps with the entire remaining second active layer except for the second channel region of the second active layer. FIG25 to FIG28 schematically illustrate the process of forming the thin-film transistor of FIG24.

[0215] In the following description, for ease of description, some configurations, effects, etc. of the embodiments or examples discussed above may not be repeated. However, it should be understood that the scope of this disclosure includes such omitted configurations already discussed above. Furthermore, in the following description, the same reference numerals will be used for constructions or elements that are the same as, substantially the same as, or nearly the same as, those in the above embodiments or examples.

[0216] Referring to Figures 24 and 25, the buffer layer 601 can be disposed on the substrate 600. The second active layer 520 can be disposed on the buffer layer 601.

[0217] Referring to Figures 24 and 26, the first active layer pattern 2610 may be disposed on the substrate 600 on which the second active layer 520 is disposed. Referring to Figure 26, the first active layer pattern 2610 may be configured such that the first active layer pattern 2610 exposes a portion of the upper surface of the second active layer 520.

[0218] Thereafter, referring to FIG27, the gate insulating layer material 2620 may be disposed on the substrate 600 on which the first active layer pattern 2610 is disposed.

[0219] The electrode material can be disposed on the gate insulating layer material 2620.

[0220] The electrode material can be patterned through a photomask process, thereby forming a first to a third electrode (530, 540 and 550) spaced apart from each other.

[0221] Referring to FIG28, the material of the gate insulating layer 602 can be patterned through a dry etching process, thereby forming a gate insulating layer 602 that exposes a portion of the upper surface of the first active layer 510.

[0222] In the dry etching process, the pattern of the first active layer located in the region where the first to third electrodes (530, 540 and 550) and the gate insulating layer 602 are not provided can become conductive through plasma, thereby forming the first active layer 510.

[0223] The first active layer 510 and the second active layer 520 that overlap with the gate insulating layer 602 can be non-conductive regions.

[0224] Therefore, the first active layer 510 may include the first channel region CH1, and the second active layer 520 may include the second channel region CH2.

[0225] The first channel region CHl of the first active layer 510 may overlap with the gate insulating layer 602 and the third electrode 550, but not with the second active layer 520.

[0226] The second channel region CH2 of the second active layer 520 can overlap with the gate insulating layer 602 and the third electrode 550.

[0227] The embodiments of the present disclosure described above can be briefly discussed as follows.

[0228] A thin-film transistor TR according to an embodiment described herein may include: a first active layer 510 disposed on a substrate 600 and including a first channel region CH1; a second active layer 520 that overlaps a portion of the first active layer 510 and includes a second channel region CH2, but does not overlap the first channel region CH1 of the first active layer 510; a first electrode 530 and a second electrode 540 disposed in corresponding portions of the first active layer 510 and the second active layer 520 and spaced apart from each other; a gate insulating layer 602 disposed in corresponding portions of the upper surfaces of the first active layer 510 and the second active layer 520; and a third electrode 550 disposed on the gate insulating layer 602, wherein the first channel region CH1 of the first active layer 510 and the second channel region CH2 of the second active layer 520 are connected in parallel.

[0229] A thin-film transistor TR according to an embodiment described herein may include: a first active layer 510 disposed on a substrate 600 and including a first channel region CH1; a second active layer 520 that overlaps a portion of the first active layer 510 and includes a second channel region CH2, but does not overlap the first channel region CH1 of the first active layer 510; a first electrode 530 and a second electrode 540 disposed in corresponding portions of the first active layer 510 and the second active layer 520 and spaced apart from each other; a gate insulating layer 602 disposed in corresponding portions of the upper surfaces of the first active layer 510 and the second active layer 520; and a third electrode 550 disposed on the gate insulating layer 602.

[0230] According to the embodiments described herein, the display panel 110 and the display device 100 can be provided with a structure in which one of the thin-film transistors includes an active layer comprising different materials, and the channel regions of the active layer are connected in parallel. Thus, the display panel and the display device can achieve high capability and high performance by including thin-film transistors with high current generation characteristics and high reliability.

[0231] According to the embodiments described herein, the display panel 110 and the display device 100 can be provided with a structure in which one of the transistors is configured to have a plurality of first channel regions and a plurality of second channel regions, which are arranged alternately. Thus, the display panel and the display device can have high capability and produce high performance by including thin-film transistors with high current generation characteristics and high reliability disposed in non-display areas.

[0232] The above description is presented to enable any person skilled in the art to make, use, and practice the technical features of the present invention, and is provided as an example in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of the invention. The above description and figures provide examples of the technical features of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the invention. [Simplified Explanation of the Diagram]

[0011] The drawings are included to provide a further understanding of the disclosure and are incorporated into and constitute a part of the disclosure. The drawings illustrate aspects of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the figures: Figure 1 shows an example system configuration of a display device according to aspects of the present disclosure; Figure 2 shows an example equivalent circuit of a sub-pixel included in a display device according to aspects of the present disclosure; Figure 3 shows another example equivalent circuit of a sub-pixel included in a display device according to aspects of the present disclosure; Figure 4 shows an example light-shielding element included in a sub-pixel of a display device according to aspects of the present disclosure; Figure 5 is a plan view of an example thin-film transistor included in a display panel according to aspects of the present disclosure; Figure 6 is an example cross-sectional view taken along line AB of Figure 5; Figures 7 and 8 are example cross-sectional views taken along line CD of Figure 5; Figures 9 and 10 are example cross-sectional views taken along line EF of Figure 5; Figure 11 is an example cross-sectional view taken along line GH of Figure 5; Figure 12 is an example cross-sectional view taken along line IJ of Figure 5; Figures 13 to 17 show an example process for manufacturing the thin-film transistors shown in Figures 5 and 16; Figures 18 and 19 are example electrical characteristic diagrams showing the thin-film transistors according to Comparative Example 1, Comparative Example 2, and Example 1. Figure 20 is an example diagram of the gate voltage versus drain current of a thin-film transistor based on the area of ​​the first channel region of the corresponding first active layer and the area of ​​the second channel region of the corresponding second active layer (under positive bias temperature stress for 11 hours); Figure 21 is an example diagram showing the current of a thin-film transistor based on the area of ​​the first channel region of the corresponding first active layer and the area of ​​the second channel region of the corresponding second active layer; Figure 22 is an example cross-sectional view showing a structure in a display device according to aspects of the present disclosure where a thin-film transistor is electrically connected to an organic light-emitting element (e.g., OLED); Figure 23 shows an example structure of a thin-film transistor in a display device according to aspects of the present disclosure, including a plurality of first channel regions and a plurality of second channel regions; Figure 24 shows an example thin-film transistor structure in a display device according to aspects of the present disclosure, in which the first active layer overlaps with the entire remaining second active layer except for the second channel region of the second active layer; Figures 25 to 28 schematically illustrate the process of forming the thin-film transistor of Figure 24.

Claims

1. A display device, comprising: A display panel and a driving circuit for driving the display panel, wherein the display panel includes: a substrate; a first active layer disposed on the substrate and including a first channel region; a second active layer overlapping a portion of the first active layer and including a second channel region not overlapping the first channel region of the first active layer; a first electrode and a second electrode respectively disposed in corresponding portions of the first active layer and spaced apart from each other; a gate insulating layer disposed in corresponding portions of the upper surfaces of the first active layer and the second active layer; and a third electrode disposed on the gate insulating layer; wherein the first channel region and the second channel region comprise different oxide semiconductor materials, and wherein the first channel region of the first active layer and the second channel region of the second active layer are electrically connected to each other in parallel between the first electrode and the second electrode.

2. The display device as described in claim 1, wherein, The ratio of the area of ​​the first channel area to the area of ​​the second channel area is 1:3 to 3:

1.

3. The display device as described in claim 1, wherein, The first active layer and the second active layer, which have corresponding channel areas located in different regions, share a first electrode, a second electrode, and a third electrode.

4. The display device as claimed in claim 1, wherein each of the first active layer and the second active layer comprises at least one of the following compounds: indium zinc oxide (IZO), thin transparent tungsten-doped indium zinc oxide (WIZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium gallium tin zinc oxide (IGTZO), zinc oxynitride (ZnON), and indium gallium oxide (IGO).

5. The display device as described in claim 1, wherein, The second active layer is disposed below the first active layer, and the second active layer, except for the second channel area, overlaps with the first active layer.

6. The display device as described in claim 1, wherein, The width of the first channel region is less than the width of the gate insulation layer, and the width of the second channel region is equal to or less than the width of the gate insulation layer.

7. The display device as described in claim 1, wherein, The region of the first active layer, excluding the region overlapping with the first electrode, the second electrode, and the third electrode, is a conductive enabling region.

8. The display device as claimed in claim 1, wherein the first active layer comprises: The first part extends along a first direction and overlaps with the second active layer portion; The second part is spaced apart from the first part and extends along the first direction, and overlaps with the second active layer portion; And a third part, which is disposed between the first part and the second part but does not overlap with the second active layer, and includes the first channel area.

9. The display device as described in claim 8, wherein: The first electrode is disposed on a portion of the first part; The second electrode is disposed on a portion of the second portion; each of the first electrode and the second electrode overlaps with a region of the first active layer disposed on the second active layer and a portion of a region of the first active layer that does not overlap with the second active layer; and the third electrode overlaps with the third portion of the first active layer.

10. The display device as claimed in claim 1, wherein, The first active layer includes: a first portion extending along a first direction and overlapping with the second active layer; a second portion spaced apart from the first portion, extending along the first direction and overlapping with the second active layer; and a third portion disposed between the first portion and the second portion, overlapping with the second active layer, and including the first channel region.

11. The display device as claimed in claim 10, wherein: The first electrode is disposed on a portion of the first part; The second electrode is disposed on a portion of the second portion; and the entirety of each of the first electrode and the second electrode overlaps with the first active layer and the second active layer.

12. The display device as claimed in claim 10, wherein, The first channel region of the first active layer overlaps with the second active layer, and the second channel region of the second active layer does not overlap with the first active layer.

13. The display device as described in claim 1, wherein, The area of ​​the first channel area is 1 / 3 to 3 times the area of ​​the second channel area.

14. The display device as claimed in claim 1, wherein, One first active layer overlaps with multiple second active layers.

15. The display device as described in claim 1, further comprising: At least one insulating layer is disposed on the first electrode, the second electrode, and the third electrode; and an anode electrode disposed on the at least one insulating layer, wherein the anode electrode is electrically connected to the first electrode or the second electrode through a contact hole formed in the at least one insulating layer.

16. The display device as described in claim 1, further comprising: A light-shielding member disposed below the second active layer, wherein the light-shielding member forms a storage capacitor by means of a first storage capacitor electrode disposed on the same layer as the first active layer and a second storage capacitor electrode disposed on the same layer as the first electrode to the third electrode.

17. The display device as claimed in claim 1, wherein, The first active layer comprises indium zinc oxide and has an indium content of 50% to 70%, and the second active layer comprises indium gallium zinc oxide and has an indium content of more than 75% and less than 100%.

18. The display device as claimed in claim 1, wherein, The gate insulation layer is disposed on the portion of the first active layer that overlaps with the second active layer, on the portion of the second active layer that does not overlap with the first active layer, and in a portion of the region below the first active layer that does not overlap with the first active layer.

19. The display device as claimed in claim 1, wherein: The first electrode, the second electrode, and the third electrode are disposed on the substrate at intervals from each other; The second active layer is disposed below the first active layer disposed below the first electrode; the first active layer and the second active layer disposed below the first active layer are disposed in a portion of the region between the first electrode and the third electrode; The first active layer and the second active layer disposed below the first active layer are disposed in a portion of the region between the third electrode and the second electrode; The first active layer and the second active layer disposed below the first active layer are disposed below the second electrode; the entire second channel region of the second active layer overlaps with a portion of the third electrode; The region of the first active layer surrounding the second channel region on the second active layer and overlapping with the third electrode is at least a portion of the remaining region of the first active layer other than the first channel region.

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