Semiconductor device and manufacturing method thereof

Abstract

Some embodiments disclosed herein provide a method for manufacturing a semiconductor device, comprising forming a first dielectric layer on a substrate; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is doped with phosphorus and / or boron; and performing a thermal process on the first dielectric layer and the second dielectric layer such that the second dielectric layer arches upward to form a cavity in the second dielectric layer.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a first dielectric layer on a substrate; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is doped with phosphorus and / or boron; and performing a thermal process on the first dielectric layer and the second dielectric layer to cause the second dielectric layer to arch upward to form a cavity in the second dielectric layer.

2. The method as described in claim 1, wherein the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer before the thermal process is performed.

3. The method as described in claim 1, wherein after the thermal process is performed, the second dielectric layer is annular in a cross-sectional view.

4. The method as described in claim 1, wherein the temperature at which the thermal process is performed is above approximately 1200 degrees Celsius.

5. The method as claimed in claim 1, wherein the substrate has a trench having a sidewall and a bottom, and the first dielectric layer and the second dielectric layer are formed at the bottom of the trench.

6. The method as described in claim 5, wherein after the thermal process is performed, the second dielectric layer contacts the sidewall of the trench.

7. The method as described in claim 5, wherein after the thermal process is performed, the top of the second dielectric layer is lower than the top surface of the substrate.

8. The method as described in claim 5, wherein the width of the second dielectric layer decreases as it moves further away from the bottom of the trench prior to performing the thermal process.

9. A semiconductor device comprising: an epitaxial layer having a trench; a gate dielectric layer in the trench, wherein the gate dielectric layer has a cavity and is annular in a cross-sectional view, and the annular layer has a gap between it and a sidewall of the trench; a gate layer in the trench and on the gate dielectric layer and filling the gap; a source electrode on the epitaxial layer; and a drain electrode under the epitaxial layer.

10. The semiconductor device as claimed in claim 9, wherein the gate dielectric layer is doped with phosphorus and / or boron.

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