Forming method of packaging structure

Abstract

This disclosure provides a method for forming a package structure, comprising: providing a capping layer; disposing a semiconductor element on the capping layer; performing a surface treatment process on the semiconductor element and the capping layer; disposing an encapsulation layer on the semiconductor element and the capping layer; disposing a connector on the encapsulation layer, wherein the connector is electrically connected to the semiconductor element; disposing a substrate on the encapsulation layer; and disposing a bonding pad on the substrate, wherein the bonding pad is electrically connected to the connector.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor technology, and in particular to methods for forming package structures. [Previous Technology]

[0002] As the size of semiconductor devices gradually shrinks, the number of semiconductor devices within a package structure increases dramatically, posing a significant challenge to the manufacturing process. Mass transfer processes can be used to transfer these semiconductor devices from a growth substrate to a carrier substrate, or from a carrier substrate to a circuit board, making them easier to process. However, while existing package structures and their formation methods have gradually met their intended uses, they are not perfect in every aspect. Therefore, there are still some issues regarding package structures and their formation methods that need to be overcome. [Summary of the Invention]

[0003] In some embodiments, a method for forming a package structure is provided. The method for forming a package structure includes: providing a capping layer; disposing a semiconductor element on the capping layer; performing a surface treatment process on the semiconductor element and the capping layer; disposing an encapsulation layer on the semiconductor element and the capping layer; disposing a connector on the encapsulation layer, wherein the connector is electrically connected to the semiconductor element; disposing a substrate on the encapsulation layer; and disposing a bonding pad on the substrate, wherein the bonding pad is electrically connected to the connector.

[0004] The method for forming the packaging structure disclosed herein can be applied to various types of electronic devices. To make the features and advantages of this disclosure more apparent and understandable, various embodiments are described below in detail with reference to the accompanying drawings.

Implementation Method

[0006] The following disclosure provides many different embodiments or examples for implementing the provided apparatus. Specific examples of the components and their configurations are described below to simplify the embodiments of this disclosure and are not intended to limit this disclosure. For example, if the description mentions that a first component is formed on a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, so that the first and second components are not in direct contact. Furthermore, this disclosure may repeat element symbols and / or characters in different embodiments or examples. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or examples discussed.

[0007] In some embodiments disclosed herein, terms such as "setup," "connection," and similar terms, unless specifically defined, may refer to two components in direct contact, or to two components not in direct contact, wherein an additional connecting component is located between the two structures. Terms such as "setup" and "connection" may also include situations where both structures are movable or both structures are fixed.

[0008] In addition, the terms "first", "second" and similar terms mentioned in this specification or the claims are used to name different components or to distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of components, nor to limit the manufacturing order or the order of installation of components.

[0009] In this document, the terms "approximately," "about," and "substantially" generally mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The given quantities are approximate, meaning that the terms "approximately," "about," or "substantially" are implied even without specific mention. The phrase "the range is between the first value and the second value" means that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies that there may be an error between the first value and the second value within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%. If the first direction is perpendicular to the second direction, the angle between the first and second directions can be between 80 and 100 degrees. If the first direction is parallel to the second direction, the angle between the first and second directions can be between 0 and 10 degrees.

[0010] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It is understood that such terms, for example, as defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and shall not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0011] It should be understood that, for clarity, some elements of the apparatus are omitted in the drawings, and only some elements are schematically shown. In some embodiments, additional components may be added to the apparatus described below. In other embodiments, some components of the apparatus described below may be replaced or omitted. It should be understood that, in some embodiments, additional operating steps may be provided before, during, and / or after the method of forming the apparatus. In some embodiments, some of the operating steps may be replaced or omitted, and the order of some of the operating steps is interchangeable.

[0012] This disclosure eliminates the molding, flipping, and de-adhesive removal steps after component transfer by retaining the catch material as a carrier in the transfer process. As a result, the packaging structure disclosed herein significantly simplifies the process, offering advantages such as fewer steps and lower cost.

[0013] Referring to Figures 1 to 3 and Figures 5 to 10, which are cross-sectional views showing different stages of the packaging structure formation method according to some embodiments of the present disclosure. For simplicity, some figures only show a single packaging structure 1 for clarity. In other embodiments, there may be multiple packaging structures 1. For example, there may be two, three, four or more packaging structures 1, and they may be arranged in a matrix.

[0014] As shown in Figure 1, a carrier plate 10 is provided for carrying components (e.g., semiconductor components 13) located thereon. In some embodiments, the carrier plate 10 may include a conductive material or a non-conductive material. For example, conductive materials may include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium phosphide (GaP), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), other suitable materials or combinations thereof, but this disclosure is not limited thereto; non-conductive materials may include glass, quartz, sapphire, diamond (C), ceramics, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials or combinations thereof, but this disclosure is not limited thereto.

[0015] As shown in Figure 1, following the above steps, an adhesive layer 11 is provided on the carrier plate 10, which is used to bond the carrier plate 10 to the supporting material (hereinafter referred to as "cover layer 12"). In some embodiments, the adhesive layer 11 may be a release film, such as thermal release, UV release, a combination thereof, or other suitable materials, but this disclosure is not limited thereto. By providing an adhesive layer 11 that can be decomposed by heat or light, the carrier plate 10, which serves as a temporary substrate, can be effectively removed in subsequent processes.

[0016] As shown in Figure 1, following the above steps, a capping layer 12 is provided on the adhesive layer 11, which serves as a carrier in the transfer process. In some embodiments, the material of the capping layer 12 includes a polymeric silicone compound. For example, the polymeric silicone compound may include polydimethylsiloxane (PDMS), other suitable polymeric silicone compounds, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the material of the capping layer 12 may be selected as needed to give the capping layer 12 a specific Young's modulus, viscosity, mechanical strength, chemical resistance, etc. For example, the capping layer 12 may be made to have hardness or chemical resistance that can withstand subsequent photolithography and / or etching processes. Alternatively, the capping layer 12 may also be made to have a specific light transmittance so that light emitted by semiconductor devices 13, such as micro light-emitted diodes (μLEDs), can pass through. For example, the transmittance of the capping layer 12 in the visible light wavelength range can be greater than or equal to 95%. For example, the transmittance of the capping layer 12 in the visible light wavelength range can be 95%, 96%, 97%, 98%, 99%, or any range of the above values.

[0017] In some embodiments, a capping layer 12 can be formed on the adhesive layer 11 by the following steps. First, a solution including a receiving material can be applied to the adhesive layer 11. The solution may include a receiving material (e.g., dimethylsiloxane), a solvent, a dispersant, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. Next, the solution can be uniformly distributed on the adhesive layer 11 by spin coating. In some embodiments, the solution may be additionally heated to pre-curing the solution, but this disclosure is not limited thereto. Finally, the solution can be cured to form a fully or partially cured capping layer 12. The hardness of the capping layer 12 can be controlled by adjusting the curing conditions, such as adjusting the baking temperature, but this disclosure is not limited thereto. In this way, a capping layer 12 as described above can be obtained. It is worth mentioning that although possible methods for setting the capping layer 12 have been provided above, this disclosure is not limited thereto. In other embodiments, different setup methods or different formation sequences may be used to form the capping layer 12.

[0018] As shown in Figure 1, following the above steps, a semiconductor element 13 is disposed on the capping layer 12, wherein the top surface 13A of the semiconductor element 13 faces the capping layer 12. In some embodiments, the semiconductor element 13 may include a light-emitting diode, a laser diode, a photodiode, a photo detector, an integrated circuit (IC), other suitable semiconductor elements, or combinations thereof, but this disclosure is not limited thereto.

[0019] In some embodiments, the semiconductor element 13 may include a semiconductor stack 131 and a plurality of electrodes 132. In some embodiments where the semiconductor element 13 is a miniature light-emitting diode, the semiconductor stack 131 may include a first semiconductor layer, a light-emitting layer, and a second semiconductor layer, stacked sequentially. In some embodiments, the first semiconductor layer, the light-emitting layer, and the second semiconductor layer may be formed by an epitaxial growth process, but this disclosure is not limited thereto. In some embodiments, the first semiconductor layer may be a P-type semiconductor layer, and the second semiconductor layer may be an N-type semiconductor layer. In other embodiments, the conductivity types of the first semiconductor layer and the second semiconductor layer may be interchanged.

[0020] In some embodiments, the semiconductor stack 131 may include group II-VI materials or group III-V materials. For example, group II-VI materials may include zinc selenide (ZnSe). For example, group III-V materials may include gallium nitride (GaN), aluminum nitride (AlN), indium arsenide (InP), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), aluminum indium gallium nitride (AlInGaN), aluminum indium gallium phosphide (AlInGaP), the likes thereof, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the light-emitting layer may include a quantum well (QW) or a multiple quantum well (MQW). In some embodiments, the P-type semiconductor layer may include a dopant, and the dopant may be such as magnesium (Mg) or carbon (C), but this disclosure is not limited thereto. In some embodiments, the N-type semiconductor layer may include a dopant, and the dopant may be such as silicon (Si) or germanium (Ge), but this disclosure is not limited thereto.

[0021] In some embodiments, the electrode 132 is disposed on the side of the semiconductor stack 131 opposite to the top surface 13A. In some embodiments, the electrode 132 may include a first electrode and a second electrode, and the first electrode and the second electrode may be electrically connected to the semiconductor stack 131. The first electrode may be electrically connected to a first semiconductor layer, and the second electrode may be electrically connected to a second semiconductor layer. In some embodiments, the first electrode and the second electrode may include a conductive material. For example, the conductive material may include a metal, a conductive compound, other suitable conductive materials, or a combination thereof, but this disclosure is not limited thereto. In some embodiments, the metal may be tin (Sn), copper (Cu), gold (Au), silver (Ag), nickel (Ni), indium (In), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), molybdenum (Mo), titanium (Ti), magnesium (Mg), zinc (Zn), alloys of the foregoing, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the conductive compound may include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), titanium nitride (TiN), other suitable conductive compounds, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the first electrode and the second electrode may be formed by electroplating, chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, atomic layer deposition (ALD), other suitable processes, or combinations thereof, but this disclosure is not limited thereto.

[0022] As shown in Figure 1, in some embodiments, the step of placing the semiconductor element 13 on the capping layer 12 further includes: providing a carrier plate 14; placing an adhesive layer 15 on the carrier plate 14; forming (or placing) the semiconductor element 13 on the adhesive layer 15; reducing the adhesion of the adhesive layer 15 so that the semiconductor element 13 and a portion of the adhesive layer 15 detach from the carrier plate 14 and transfer to the capping layer 12. The adhesive layer 15 may be weakened by heating, ultraviolet light irradiation, laser dissociation, other suitable methods or combinations thereof; however, this disclosure is not limited thereto. Alternatively, the semiconductor element 13 may be transferred to the capping layer 12 by a pick-up process. In some embodiments, the carrier plate 14 may include a conductive material or a non-conductive material. For example, conductive materials may include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium phosphide (GaP), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), other suitable materials or combinations thereof, but this disclosure is not limited thereto; non-conductive materials may include glass, quartz, sapphire, diamond (C), ceramics, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials or combinations thereof, but this disclosure is not limited thereto. In some embodiments, a single semiconductor element 13 may be transferred at a time, as shown in Figure 1, but this disclosure is not limited thereto. In other embodiments, multiple semiconductor elements 13 may be transferred at a time, such as three, four, five or more semiconductor elements 13. In some embodiments, the adhesive layer 15 may be a release film, such as thermal release, UV release, laser release, combinations thereof or other suitable materials, but this disclosure is not limited thereto.

[0023] As shown in Figure 2, in some embodiments where the semiconductor element 13 is a miniature light-emitting diode, three semiconductor elements 13 may be disposed on the capping layer 12 by means such as laser dissociation. That is, each package structure 1 subsequently formed may include three semiconductor elements 13. It is worth mentioning that the number of semiconductor elements 13 shown in Figure 2 is merely an example, and this disclosure is not limited thereto. In other embodiments, each package structure 1 may include more than or less than three semiconductor elements 13, such as one, two, four, or more than four.

[0024] In some embodiments, the three semiconductor elements 13 may respectively include a green LED chip, a red LED chip and a blue LED chip, wherein the green LED chip can emit green visible light with a wavelength between 510nm and 570nm, the red LED chip can emit red visible light with a wavelength between 610nm and 750nm, and the blue LED chip can emit blue visible light with a wavelength between 440nm and 470nm, but this disclosure is not limited thereto.

[0025] In some embodiments, different color conversion layers can be disposed on multiple LED chips of the same type (e.g., the same color) to convert single-color light into different colors of light, thereby achieving the same effect as described above. For example, each of the three semiconductor elements 13 may include the same ultraviolet LED chip and respectively include a green conversion layer, a red conversion layer, and a blue conversion layer disposed on the ultraviolet LED chip. Alternatively, this disclosure may also use blue LED chips or LED chips of other colors (wavelengths) as needed, and is not limited to the ultraviolet LED chips described above. By using the same LED chip, the types of LED chips can be simplified. In some embodiments, each color conversion layer may include materials such as phosphors and quantum dots to convert the single-color light emitted by each LED chip into light of a specific color. For example, when used with an ultraviolet LED chip, the red conversion layer or the green conversion layer may include CdSe, so that ultraviolet light can be converted into red visible light or green visible light. For example, when used with an ultraviolet LED chip, the blue conversion layer may include CdS / ZnS, so that ultraviolet light can be converted into blue visible light. The materials and combinations described above are merely examples, and this disclosure is not limited thereto.

[0026] As shown in Figure 2, an adhesive layer 15' may remain on the semiconductor element 13 formed by a process such as laser dissociation, and the adhesive layer 15' covers the electrodes 132 of the semiconductor element 13. As shown in Figure 3, a surface treatment process STP can be performed to remove the adhesive layer 15' on the semiconductor element 13. After undergoing the surface treatment process STP, the remaining adhesive layer 15' is removed from the semiconductor element 13, thereby exposing the electrodes 132 of the semiconductor element 13. In some embodiments, the surface treatment process STP may include inductively coupled plasma clean (ICP clean), other suitable processes, or combinations thereof, but this disclosure is not limited thereto.

[0027] It is worth mentioning that surface treatment processes such as inductively coupled plasma (STP) cleaning can not only remove the adhesive layer 15', but also modify the capping layer 12. Specifically, the capping layer 12 can be divided into a plurality of portions, such as the first portion 121, the second portion 122, and the third portion 123 shown in Figure 3. In some embodiments, the first portion 121 and the second portion 122 are located on the side of the capping layer 12 adjacent to the semiconductor element 13, while the third portion 123 is located on the side of the capping layer 12 away from the semiconductor element 13. In detail, the first portion 121 and the second portion 122 are arranged side by side on the third portion 123, the first portion 121 is located between the semiconductor element 13 and the third portion 123, and the third portion 123 is located between the first portion 121 and the carrier plate 10 and between the second portion 122 and the carrier plate 10. The semiconductor element 13 covers and contacts the first portion 121 of the capping layer 12, while exposing the second portion 122 of the capping layer 12. After undergoing the surface treatment process STP, the second portion 122 of the capping layer 12 that is not covered by the semiconductor element 13 is modified. On the other hand, the first portion 121 of the capping layer 12 is not modified because it is covered by the semiconductor element 13. Similarly, the portion of the capping layer 12 that is far from the semiconductor element 13 (i.e., the third portion 123) is not modified.

[0028] In some embodiments, the thickness of the first portion 121 and the second portion 122 in the vertical direction (i.e., the normal direction of the carrier 10) may be between 0.5 μm and 2.5 μm. For example, the thickness of the first portion 121 and the second portion 122 in the vertical direction may be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, or any value or range between the above values, but this disclosure is not limited thereto. In some embodiments, the thickness of the third portion 123 in the vertical direction may be between 5 μm and 150 μm. For example, the thickness of the third portion 123 in the vertical direction may be 5 μm, 10 μm, 15 μm, 40 μm, 60 μm, 80 μm, 100 μm, 125 μm, 150 μm, or any value or range between the above values, but this disclosure is not limited thereto.

[0029] Referring also to Figure 4, which shows the Fourier transform infrared spectral measurements of different portions of the capping layer 12 according to some embodiments of the present disclosure. As shown in Figure 4, after undergoing a surface treatment process such as inductively coupled plasma cleaning (STP), the material structure of the capping layer 12 changes due to partial modification. Specifically, after performing the STP surface treatment process, the characteristic peaks (located at wavenumber 1070 cm⁻¹) of the network structure SiO₂ in the portion of the capping layer 12 that has undergone the STP surface treatment process (e.g., the second portion 122) become more pronounced compared to the portions of the capping layer 12 that have not undergone the STP surface treatment process and have not been modified (e.g., the first portion 121 and the third portion 123). This indicates an increased ratio of network structure SiO₂, which makes the surface of the capping layer 12 (e.g., the modified second portion 122) more compact, thereby improving resistance to peeling.

[0030] In some embodiments, in the Fourier transform infrared spectroscopy measurement results, the ratio between the maximum intensity of the second portion 122 at wavenumbers of 1060 cm⁻¹ to 1080 cm⁻¹ (representing the characteristic peak of SiO₂ with a network structure) and the maximum intensity of the second portion 122 at wavenumbers of 780 cm⁻¹ to 800 cm⁻¹ (representing the characteristic peak of Si-CH₃) is greater than 0.65. For example, the ratio between the maximum intensities can be any value or range between 0.65, 0.675, 0.7, 0.725, 0.75, 0.775, 0.8, 0.825, and 0.85, but this disclosure is not limited thereto. In contrast, in some embodiments, the ratio between the maximum intensity of the first portion 121 or the third portion 123 at wavenumbers of 1060 cm⁻¹ to 1080 cm⁻¹ (representing the characteristic peaks of SiO₂ with a network structure) and the maximum intensity of the first portion 121 or the third portion 123 at wavenumbers of 780 cm⁻¹ to 800 cm⁻¹ (representing the characteristic peaks of Si-CH₃) is less than 0.65 in the Fourier transform infrared spectroscopy measurement results. For example, the ratio between the maximum intensities can be any value or range between 0.65, 0.625, 0.6, 0.575, 0.55, 0.525, 0.5, 0.475, and 0.45, but this disclosure is not limited thereto.

[0031] As shown in Figure 5, an encapsulation layer 16 may be disposed on the semiconductor element 13 and the capping layer 12. Specifically, the encapsulation layer 16 covers and contacts the semiconductor element 13 and the second portion 122 of the capping layer 12. In some embodiments, the encapsulation layer 16 may be or may include epoxy resin, polyimide (PI), polybenzoxazole (PBO), silicone resin, silicon dioxide, silicon nitride, or combinations thereof, but this disclosure is not limited thereto.

[0032] In some embodiments, the encapsulation layer 16 covers the side surface of the semiconductor element 13 and the electrode 132, but does not contact the top surface 13A of the semiconductor element 13. In some embodiments where the top surface 13A of the semiconductor element 13 is used to emit light, in order to concentrate the light emitted by the light-emitting layer of the semiconductor element 13 toward the top surface 13A and to avoid crosstalk between the light emitted by adjacent semiconductor elements 13, the transmittance of the encapsulation layer 16 in the visible light wavelength range may be less than 5%. For example, the transmittance of the encapsulation layer 16 in the visible light wavelength range may be 5%, 4%, 3%, 2%, 1%, or any range of the above values. In some embodiments, the transmittance of the encapsulation layer 16 may be adjusted by including a material with a light reflectance greater than 90%. For example, the transmittance of the encapsulation layer 16 may be less than 5% by adding black dispersed particles such as carbon black to the encapsulation layer 16, thereby making the encapsulation layer 16 appear black.

[0033] As shown in Figure 6, a connecting portion 17 is provided on the encapsulation layer 16, wherein the connecting portion 17 extends through the encapsulation layer 16 and is electrically connected to the electrode 132 of the semiconductor element 13. Specifically, a portion of the encapsulation layer 16 may be removed first to expose the electrode 132 of the semiconductor element 13, and then the connecting portion 17 is formed on the exposed electrode 132 and the encapsulation layer 16. In some embodiments, the connecting portion 17 may include a conductive material. For example, the conductive material may include metals, conductive compounds, other suitable conductive materials, or combinations thereof, but this disclosure is not limited thereto. For example, the metal may be tin (Sn), copper (Cu), gold (Au), silver (Ag), nickel (Ni), indium (In), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), molybdenum (Mo), titanium (Ti), magnesium (Mg), zinc (Zn), germanium (Ge), or alloys thereof. For example, the conductive compound may be tantalum nitride (TaN), titanium nitride (TiN), tungsten silicon (WSi2), indium tin oxide (ITO), etc. In some embodiments, a portion of the encapsulation layer 16 may be removed by a process such as photolithography, and the connection portion 17 may be formed by a process such as electroplating, sputtering, or vapor deposition, but this disclosure is not limited thereto.

[0034] As shown in Figure 7, a substrate 18 may be disposed on the encapsulation layer 16 and the connecting portion 17. Specifically, the substrate 18 covers the encapsulation layer 16 and the connecting portion 17. In some embodiments, the substrate 18 may include epoxy resin, polyimide (PI), polybenzoxazole (PBO), silicone resin, silicon oxide, silicon nitride, or combinations thereof, but this disclosure is not limited thereto.

[0035] As shown in Figure 8, a bonding pad 19 may be disposed on a substrate 18, wherein the bonding pad 19 extends through the substrate 18 and is electrically connected to the semiconductor element 13 via a connection portion 17. Specifically, a portion of the substrate 18 may be removed first to expose a portion of the connection portion 17, and then the bonding pad 19 may be formed on the exposed connection portion 17 and the substrate 18. In some embodiments, the bonding pad 19 may include a conductive material. For example, the conductive material may include a metal, a conductive compound, other suitable conductive materials, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the material of the bonding pad 19 may be similar to or the same as the material of the connection portion 17, but this disclosure is not limited thereto. In some embodiments, a portion of the encapsulation layer 16 may be removed by a process such as photolithography, and the bonding pad 19 may be formed by a process such as electroplating, sputtering, or vapor deposition, but this disclosure is not limited thereto. In some embodiments, the bonding pad 19 and the connection portion 17 may be collectively referred to as an electrical connection structure or redistribution structure, which extends through the substrate 18 and the encapsulation layer 16 to be electrically connected to the semiconductor element 13.

[0036] As shown in Figure 9, the carrier plate 10 is removable. For example, the carrier plate 10 can be removed by a laser lift-off process, other suitable processes, or a combination thereof, but this disclosure is not limited thereto.

[0037] As shown in Figure 10, the structure obtained by the above steps is flipped over, and the adhesive layer 11 is removed to obtain the package structure 1. For example, the adhesive layer 11 can be removed by etching, heating, photolithography, other suitable processes or combinations thereof, but this disclosure is not limited thereto.

[0038] In some embodiments, the adhesive layer 11 between the carrier plate 10 and the cover layer 12 can be removed simultaneously in the same process. It is worth mentioning that the above methods are merely examples, and this disclosure is not limited thereto. In other embodiments, the adhesive layer 11 or a portion of the carrier plate 10 can be directly removed by physical destruction to separate it from the cover layer 12.

[0039] It is worth mentioning that, although not shown in the figures, in some embodiments, multiple package structures 1 can be formed simultaneously by the above steps. Therefore, before or after the process of removing the adhesive layer 11, a dicing process can be performed to separate the multiple package structures 1 from each other and form a single package structure 1 as shown in Figure 10.

[0040] In summary, by retaining the cap layer 12 as a carrier in the transfer process, the molding, flipping, and de-adhesive removal steps can be omitted after the component transfer. As a result, the packaging structure 1 disclosed herein significantly simplifies the process, offering the advantages of fewer forming steps and lower cost.

[0041] Several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that other processes and structures can be designed or modified based on the embodiments disclosed herein to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] The viewpoints of the embodiments disclosed herein will be better understood through the following detailed description in conjunction with the accompanying drawings. It is worth noting that, according to industry standard practice, some features may not be drawn to scale. In fact, the dimensions of different features may be increased or decreased for clarity of description. Figures 1 to 3 are cross-sectional views showing different stages of the encapsulation structure formation method according to some embodiments of the present disclosure. Figure 4 shows the Fourier-transform infrared spectroscopy (FTIR) measurement results of different portions of the capping layer according to some embodiments of the present disclosure. Figures 5 to 10 are cross-sectional views showing different stages of the encapsulation structure formation method according to some embodiments of the present disclosure.

Claims

1. A method for forming a packaging structure, comprising: Provide a cover layer; A semiconductor element is disposed on the capping layer; a surface treatment process is performed on the semiconductor element and the capping layer, wherein the capping layer includes a first portion and a second portion, the second portion undergoing the surface treatment process, and the first portion being covered by the semiconductor element and not undergoing the surface treatment process; an encapsulation layer is disposed on the semiconductor element and the capping layer; a connecting portion is disposed on the encapsulation layer, wherein the connecting portion is electrically connected to the semiconductor element; a substrate is disposed on the encapsulation layer; and a bonding pad is disposed on the substrate, wherein the bonding pad is electrically connected to the connecting portion.

2. The method for forming a package structure as described in claim 1, wherein the step of disposing the semiconductor element on the capping layer further includes: A carrier board is provided; an adhesive layer is disposed on the carrier board; the semiconductor element is disposed on the adhesive layer; And to transfer the semiconductor element onto the capping layer.

3. The method of forming a package structure as described in claim 2, wherein the step of transferring the semiconductor element to the capping layer further includes a residual portion of the adhesive layer on the semiconductor element, and the surface treatment process further includes removing the residual adhesive layer on the semiconductor element.

4. The method of forming the encapsulation structure as claimed in claim 1, wherein in the Fourier transform infrared spectroscopy measurement results, the ratio between the maximum intensity of the second portion at wavenumber 1060 cm⁻¹ to wavenumber 1080 cm⁻¹ and the maximum intensity of the second portion at wavenumber 780 cm⁻¹ to wavenumber 800 cm⁻¹ is greater than 0.

65.

5. The method of forming the encapsulation structure as claimed in claim 1, wherein in the Fourier transform infrared spectroscopy measurement results, the ratio between the maximum intensity of the first portion at wavenumbers 1060 cm⁻¹ to 1080 cm⁻¹ and the maximum intensity of the first portion at wavenumbers 780 cm⁻¹ to 800 cm⁻¹ is less than 0.

65.

6. A method for forming the encapsulation structure as described in claim 1, wherein the transmittance of the encapsulation layer in the visible light wavelength range is less than 5%.

7. A method for forming the encapsulation structure as described in claim 1, wherein the cover layer has a transmittance of 95% or more in the visible light wavelength range.

8. The method of forming the encapsulation structure as described in claim 1, wherein the step of providing the capping layer further includes: Provide a carrier board; An adhesive layer is applied to the carrier plate; And the cover layer is provided on the adhesive layer.

9. The method of forming the packaging structure as described in claim 8 further includes: After the bonding pad is placed on the substrate, the carrier plate and the adhesive layer are removed.

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