Transistor structure

Abstract

A transistor structure includes a substrate, a semiconductor layer, a gate, a source, a drain, an auxiliary metal layer, and an insulating layer. The semiconductor layer is disposed on the substrate along a stacking direction. The gate overlaps a channel portion of the semiconductor layer. The auxiliary metal layer is disposed between the substrate and the semiconductor layer and overlaps the channel portion. The insulating layer directly contacts at least one side of the auxiliary metal layer, and the maximum thickness of the insulating layer in the stacking direction is less than the maximum thickness of the auxiliary metal layer in the stacking direction.

Claims

1. A transistor structure, comprising: substrate; A semiconductor layer is disposed on the substrate along a stacking direction, and the semiconductor layer includes a channel portion, a first contact portion, and a second contact portion; A gate, overlapping the channel portion of the semiconductor layer, wherein the semiconductor layer is located between the substrate and the gate; a first source / drain, contacting the first contact portion of the semiconductor layer; a second source / drain, contacting the second contact portion of the semiconductor layer; an auxiliary metal layer, disposed between the substrate and the semiconductor layer and overlapping the channel portion; and an insulating layer, directly contacting at least one side of the auxiliary metal layer, wherein the maximum thickness of the insulating layer in the stacking direction is less than the maximum thickness of the auxiliary metal layer in the stacking direction, wherein at least a portion of the vertical projection of the auxiliary metal layer on the substrate does not overlap the vertical projection of the insulating layer on the substrate.

2. The transistor structure as claimed in claim 1, wherein the thickness of the insulating layer in the stacking direction falls within the range of 100 nm to 300 nm.

3. The transistor structure as claimed in claim 1, wherein the thickness of the auxiliary metal layer in the stacking direction falls within the range of 350 nm to 550 nm.

4. The transistor structure as claimed in claim 1, wherein the auxiliary metal layer comprises aluminum.

5. The transistor structure as claimed in claim 1, wherein the auxiliary metal layer is electrically connected to the gate.

6. The transistor structure as claimed in claim 1, wherein the insulating layer comprises SiNx.

7. The transistor structure as claimed in claim 1, wherein the insulating layer overlaps the first contact portion and the second contact portion of the semiconductor layer.

8. The transistor structure as claimed in claim 1, wherein at least a portion of the semiconductor layer does not overlap the insulating layer.

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