Semiconductor structure and method for forming the same

Abstract

A semiconductor device includes: a substrate having a first surface and a second surface. The device also includes a metal stack located on the first surface. The metal stack includes an interleaved adhesion layer and at least one resistance layer. The device also includes an opening formed in the substrate and extending from the second surface to the first surface. The device also includes a conductive metal located in the opening and connected to the metal stack.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a back-side via. Prior Technology

[0002] Electronic components are integrated and formed on a substrate. Such substrates typically include active and passive components. There are many differences between active and passive components, such as their function, energy nature, and power gain. Active devices include pseudomorphic high electron mobility transistors (pHEMTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, and diodes. Passive devices include capacitors, resistors, and inductors.

[0003] While existing semiconductor structures are sufficient for the original purpose, they are not satisfactory in every aspect and need to be improved. Summary of the Invention

[0004] This invention provides a semiconductor structure including: a substrate having a first surface and a second surface. The device also includes a metal stack located on the first surface. The metal stack includes an interleaved adhesion layer and at least one resistance layer. The device also includes an opening formed in the substrate and extending from the second surface to the first surface. The device also includes a conductive metal located in the opening and connected to the metal stack.

[0005] This invention also provides a semiconductor device. The device includes an epitaxial layer located on a substrate. The device also includes a gate structure located on the epitaxial layer. The device also includes a source / drain structure located on opposite sides of the gate structure. The device also includes a field plate located on the gate structure. The device also includes a metal stack located on the epitaxial layer, comprising alternating stacked tantalum and nickel-chromium alloy layers. The device also includes a metal layer located on the metal stack and the source / drain structure. The device also includes a via structure passing through the substrate, the via structure being in direct contact with the metal stack.

[0006] This invention also provides a method for forming a semiconductor device, comprising: forming an epitaxial layer on a substrate. This method further includes depositing a first dielectric layer on the epitaxial layer. This method also includes forming a metal stack through the first dielectric layer, the metal stack comprising alternating layers of tantalum and nickel-chromium alloy on the epitaxial layer. This method also includes forming a first conductive layer on the metal stack. This method also includes forming a second dielectric layer on the first conductive layer. This method also includes patterning the second dielectric layer to form openings exposing the first conductive layer. This method also includes forming a second conductive layer on the second dielectric layer. Simple Explanation of the Diagram

[0007] Figure 1 is a cross-sectional view of a semiconductor structure according to some embodiments. Figure 1A is an enlarged cross-sectional view of a semiconductor structure according to some embodiments. Figure 1B is an enlarged cross-sectional view of a semiconductor structure according to some embodiments. Figure 1C illustrates an enlarged cross-sectional view of a semiconductor structure according to some embodiments. Figure 2 is an enlarged cross-sectional view of a semiconductor structure according to some embodiments. Figure 3 is a cross-sectional view of a semiconductor structure according to some embodiments. Implementation

[0008] The following disclosure provides many different embodiments or examples to implement the various features of this invention. The following disclosure describes specific examples of the various components and their arrangements to simplify the explanation. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the invention describes a first feature formed on or above a second feature, it indicates that it may include embodiments where the first and second feature are in direct contact, or embodiments where an additional feature is formed between the first and second feature, so that the first and second feature may not be in direct contact. Furthermore, repeated reference numerals or designations may be used in different embodiments; these repetitions are only for the purpose of simply and clearly describing the embodiments of the invention and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0009] Furthermore, spatially relative terms may be used, such as "below," "lower," "above," "higher," and similar terms. These spatially relative terms are used to facilitate the description of the relationship between one or more elements or features in the illustration and another element or feature(s). These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the illustration. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0010] Here, the terms "about," "approximately," and "roughly" generally indicate within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without specific mention of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0011] While the steps in some embodiments are performed in a specific order, these steps can also be performed in other logical orders. In different embodiments, some of the described steps may be replaced or omitted, and other operations may be performed before, during, and / or after the steps described in the embodiments of the present invention. Other features may be added to the semiconductor structure in the embodiments of the present invention. In different embodiments, some features may be replaced or omitted.

[0012] This invention provides a semiconductor structure. The semiconductor structure includes a back via structure. A metal stop layer is formed between the front metal and the back via structure. The metal stop layer can reduce over-etching of the front metal during the formation of the back via structure. Therefore, etching power can be enhanced and etching process time can be reduced.

[0013] Figure 1 is a cross-sectional view illustrating a semiconductor structure 10a according to some embodiments. According to some embodiments, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate, a glass substrate, a ceramic substrate, a quartz substrate, a semiconductor-on-insulator (SOI) substrate, or a combination thereof, but is not limited thereto. The material of the substrate 102 may include group III-V semiconductors such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or a combination thereof, but is not limited thereto. The material of the substrate 102 may include group IV semiconductors, such as silicon or germanium. The substrate 102 may include undoped or doped materials. In some embodiments, the substrate 102 includes SiC. In some embodiments, the substrate 102 has a first surface 102f and a second surface 102b opposite to the first surface 102f. The first surface 102f may be referred to as the front side, and the second surface may be referred to as the back side, but is not limited thereto. The following film layers may be formed on the first surface 102f of the substrate 102.

[0014] In some embodiments, as shown in Figure 1, an epitaxial layer 104 is formed on a substrate 102. In some embodiments, the epitaxial layer 104 is a multilayer structure. The epitaxial layer 104 may include, but is not limited to, gallium-faced or nitrogen-faced sublayers. Figure 1A is an enlarged cross-sectional view illustrating the epitaxial layer 104 of a semiconductor structure 10a according to some embodiments. In some embodiments, the epitaxial layer 104 may include a nucleation layer 106, a buffer layer 108, a channel layer 110, a carrier supply layer 112, and a capping layer 114.

[0015] In some embodiments, a buffer layer 108 may be formed over the nucleation layer 106, and a channel layer 110 may be formed over the buffer layer 108. A carrier supply layer 112 may be formed over the channel layer 110, and a capping layer 114 may be formed over the carrier supply layer 112, but this is not limited to these embodiments. In some embodiments not shown in the figures, when it is nitrogen polar, a carrier supply layer 112 may be formed over the buffer layer 108, and a channel layer 110 may be formed over the carrier supply layer 112, but this is not limited to these embodiments. The material of the nucleation layer 106 may include GaAs, AlN, AlGaN, or other materials, but this is not limited to these materials. The material of the buffer layer 108 may include at least one of GaAs, AlGaAs, GaN, AlGaN, and other suitable materials, but this is not limited to these materials. The material of the channel layer 110 may include at least one of GaAs, GaN, AlGaN, InGaAs, and other suitable materials, but this is not limited to these materials. The material of the carrier supply layer 112 may include at least one of AlGaAs, AlGaN, AlGaAsP, InAlGaAs, InGaP, InGaPAs, and AlInGaP, or a combination thereof, but is not limited thereto. The material of the capping layer 114 may include GaAs, GaN, or other suitable materials, but is not limited thereto. The nucleation layer 106, buffer layer 108, channel layer 110, carrier supply layer 112, and capping layer 114 may be formed by molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), other suitable methods, or combinations thereof.

[0016] The band gaps of the channel layer 110 and the carrier supply layer 112 may be different. A heterojunction may be formed at the interface between the channel layer 110 and the carrier supply layer 112. The energy band may be bent at the heterojunction, and an energy well may be formed deep within the conduction band. Electrons supplied by the carrier supply layer may be confined within the quantum well. Therefore, a two-dimensional electron gas (2DEG) may be formed at the interface between the channel layer 110 and the carrier supply layer 112, and the 2DEG may generate a conductive current.

[0017] Next, according to some embodiments, as shown in Figure 1, a source electrode 116 and a drain electrode 118 are formed on the epitaxial layer 104. The source electrode 116 and the drain electrode 118 may respectively comprise Ti, Al, W, Au, Pd, Au, Ge, Ni, Mo, Pt, other available metals, alloys thereof, or combinations thereof, but are not limited thereto. Physical vapor deposition (PVD) processes (e.g., resistance heating evaporation, electron beam evaporation, or sputtering), chemical vapor deposition (CVD) processes (e.g., low-pressure chemical vapor deposition process (LPCVD) or plasma enhanced chemical vapor deposition process (PECVD)), electroplating, atomic layer deposition (ALD), other suitable processes, or combinations thereof can be used to form the source electrode 116 and the drain electrode 118. In some embodiments, the source electrode 116 and the drain electrode 118 are formed by a vapor deposition process.

[0018] Next, according to some embodiments, as shown in Figure 1, a first dielectric layer 120a is formed on the source electrode 116 and the drain electrode 118. The first dielectric layer 120a may be a single layer or multiple layers. The first dielectric layer 120a may be made of silicon nitride, silicon oxide, aluminum nitride, aluminum oxide, other suitable insulating materials, or combinations thereof, but is not limited thereto. In some embodiments, the first dielectric layer 120a includes silicon nitride, silicon oxide, aluminum nitride, aluminum oxide, other suitable insulating materials, or combinations thereof, but is not limited thereto. The first dielectric layer 120a may be formed using a deposition process. Deposition processes may include chemical vapor deposition processes (e.g., low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition (SACVD), or flowable chemical vapor deposition (FCVD), atomic layer deposition processes, other available methods, or combinations thereof).

[0019] Next, according to some embodiments, as shown in Figure 1, an opening is formed through a first dielectric layer 120a between the source electrode 116 and the drain electrode 118. A patterning process can be used to form the opening. The patterning process may include lithography and etching processes. Examples of lithography processes include photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process may include reactive-ion etching (RIE) using inductively coupled plasma (ICP) as the etchant.

[0020] Next, according to some embodiments, as shown in Figure 1, a gate electrode 122 is formed in the opening and on the first dielectric layer 120a. The gate electrode 122 may include Mo, W, WSi, Ti, TiW, Ir, Pd, Pt, Ni, Co, Cr, Ru, Os, Rh, Ta, TaN, Al, Re, Au, other available conductive materials, or combinations thereof. The gate electrode 122 may be formed using physical vapor deposition processes (e.g., resistance heating evaporation, electron beam evaporation, or sputtering), chemical vapor deposition processes (e.g., low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition), electroplating, atomic layer deposition, other suitable processes, or combinations thereof. In some embodiments, the gate electrode 122 is formed by an evaporation process.

[0021] Next, according to some embodiments, as shown in Figure 1, a second dielectric layer 120b is formed over the gate electrode 122, the source electrode 116, and the drain electrode 118. The second dielectric layer 120b may be a single layer or multiple layers. The second dielectric layer 120b may be made of silicon nitride, silicon oxide, aluminum oxide, other suitable insulating materials, or combinations thereof. In some embodiments, the second dielectric layer 120b may include silicon nitride, silicon oxide, aluminum oxide, other suitable insulating materials, or combinations thereof, but is not limited thereto. The second dielectric layer 120b may be formed using a deposition process. The deposition process may include chemical vapor deposition processes (e.g., low-pressure chemical vapor deposition processes, plasma-enhanced chemical vapor deposition processes, subatmospheric pressure chemical vapor deposition processes, or flowable chemical vapor deposition processes), atomic layer deposition processes, other available methods, or combinations thereof.

[0022] Next, according to some embodiments, as shown in Figure 1, an opening is formed through the first dielectric layer 120a and the second dielectric layer 120b. A patterning process can be used to form the opening. The opening is formed above and beside the source electrode 116 and the drain electrode 118. In some embodiments, the source electrode 116 and the drain electrode 118, and the epitaxial layer 104 are exposed from the opening. The patterning process may include lithography and etching processes. Examples of lithography processes include photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process may include reactive ion etching using inductively coupled plasma as an etchant.

[0023] Subsequently, according to some embodiments, as shown in Figure 1, a metal stack 124 may be formed on the epitaxial layer 104 through at least one opening in the first dielectric layer 120a and the second dielectric layer 120b. Figure 1B is an enlarged cross-sectional view illustrating the metal stack 124 of the semiconductor structure 10a according to some embodiments. In some embodiments, the metal stack 124 may include an interleaved attachment layer 126 and at least one resistance layer 130. The material of the attachment layer 126 may include refractory metals, such as Nb, Mo, Ta, W, Re, but is not limited thereto. The material of the resistance layer 130 may include nickel (Ni) and / or nickel alloys, but is not limited thereto. In one example, the material of the resistance layer 130 may include Ni, Cr, alloys including Ni and Cr, other suitable materials, or combinations thereof, but is not limited thereto. For example, the resistance layer 130 may comprise a nickel-chromium alloy (NiCr), and the Ni molar fraction in the NiCr may range from 20% to 80% (20% ≤ Ni mol% ≤ 85%), such as 35%, 50%, 60%, or 80%, but is not limited thereto. In some embodiments, the adhesion layer 126 may comprise Ta, and the resistance layer 130 may comprise a NiCr alloy. The etch rate of the resistance layer 130 may be low, and the resistance layer 130 may serve as an etch stop layer for subsequent etch processes. The adhesion layer 126 may relieve stress caused by the resistance layer 130. The adhesion layer 126 and the resistance layer 130 may be formed using atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other suitable deposition methods.

[0024] It should be noted that the thicknesses of the attachment layer 126 and the resist layer 130 shown in Figure 1B are merely examples and are not limited thereto, depending on the requirements of the manufacturing process. In some embodiments, the bottommost attachment layer 126 may be in direct contact with the epitaxial layer 104. In some embodiments, the thickness of the resist layer 130 may be greater than the thickness of the attachment layer 126. In some embodiments, the ratio of the thickness of the resist layer 130 to the thickness of the attachment layer 126 is in the range of about 3 to about 7 (3 ≤ ratio ≤ 7), for example, 4, 5, or 6. In some embodiments, the bottommost attachment layer 126 may be thicker than any of the upper attachment layers 126. For example, the bottommost attachment layer 126 may be thicker than each of the upper attachment layers 126, but is not limited thereto. In some embodiments, the thickness of the resist layer 130 may be less than about 1000 angstroms (thickness < 1000 angstroms), for example, 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, or 800 angstroms. In some embodiments, the thickness of the adhesion layer 126 may be less than about 500 angstroms. If the adhesion layer 126 and the resistance layer 130 are too thick, the metal stack 124 may peel off.

[0025] It should be noted that although Figure 1B shows three adhesion layers 126 and three resistance layers 130, the number of adhesion layers 126 and resistance layers 130 is not limited to this and depends on performance and process requirements. The top layer of the metal stack 124 may be an adhesion layer 126 or a resistance layer 130. For example, the metal stack 124 may include a plurality of adhesion layers 126 and at least one resistance layer 130. The number of the plurality of adhesion layers 126 may be in the range of 2 to 8 (2 ≤ number ≤ 8), such as 3, 4, 5, 6, or 7, but is not limited thereto. The number of at least one resistance layer 130 may be in the range of 1 to 8 (1 ≤ number ≤ 8), such as 2, 3, 4, 5, 6, or 7, but is not limited thereto. In a specific example, the metal stack 124 may include two adhesion layers 126 and one resistance layer 130.

[0026] Next, according to some embodiments, as shown in Figure 1, a first metal layer 132a may be formed on the metal stack 124, the source electrode 116, and the drain electrode 118. The first metal layer 132a may be a conductive layer 132a. In some embodiments, the first metal layer 132a may be in direct contact with the uppermost layer of the metal stack 124, such as the resistive layer 130. In some embodiments, the first metal layer 132a may cover the top surface and sidewalls of the metal stack 124. The term "cover" may include "complete coverage" and "partial coverage".

[0027] The material of the first metal layer 132a may include Au, Ti, Pt, Ni, Cu, other suitable materials, or combinations thereof. The first metal layer 132a may be formed using electroplating, electron beam evaporation, resistance heating evaporation, sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof. In some embodiments, the first metal layer 132a may be a single-layer or multi-layer structure.

[0028] Next, according to some embodiments, as shown in Figure 1, a second metal layer 132b may be formed on top of the first metal layer 132a. The second metal layer 132b may be a conductive layer 132b. The second metal layer 132b may include Au, Ti, Ni, Pt, Cu, other suitable materials, or combinations thereof. The second metal layer 132b may be formed using electroplating, electron beam evaporation, resistance heating evaporation, sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof.

[0029] Next, a trench 133 is formed over the gate electrode 122 and between the source electrode 116 and the metal stack 124. A second dielectric layer 120b is exposed from the trench 133. The trench 133 can be formed using a patterning process. The patterning process may include lithography and etching processes. Examples of lithography processes include photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may be a dry etching process, a wet etching process, or a combination thereof.

[0030] Next, according to some embodiments, as shown in Figure 1, a field plate 134 is formed on the gate electrode 122. The field plate 134 may include Cu, W, Ag, Sn, Ni, Co, Cr, Ti, Pb, Au, Bi, Sb, Zn, Zr, Mg, In, Te, Ga, other available metallic materials, alloys thereof, or combinations thereof. The field plate 134 may be a single-layer or multi-layer structure.

[0031] Next, according to some embodiments, as shown in Figure 1, a third dielectric layer 120c is formed on the field plate 134 and in the trench. The third dielectric layer 120c may include silicon nitride, silicon oxide, aluminum oxide, other suitable insulating materials, or combinations thereof.

[0032] Next, according to some embodiments, as shown in Figure 1, an opening 135 is formed through a third dielectric layer 120c. The opening 135 can be formed using a patterning process. The opening 135 is formed over a second metal layer 132b, which is formed over the source electrode 116, the drain electrode 118, and / or the metal stack 124. In some embodiments, the second metal layer 132b located on the source electrode 116, the drain electrode 118, and / or the metal stack 124 is exposed from the opening 135.

[0033] Next, according to some embodiments, as shown in Figure 1, a third metal layer 132c may be formed on the second metal layer 132b. The third metal layer 132c may be a conductive layer 132c. The third metal layer 132c may include Au, Ti, Ni, Pt, Cu, other suitable materials, or combinations thereof. The third metal layer 132c may be formed using electroplating, electron beam evaporation, resistance heating evaporation, sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof.

[0034] Next, according to some embodiments, as shown in Figure 1, a trench 137 is formed through a third metal layer 132c. The third dielectric layer 120c on the gate electrode 122 and the field plate 134 can be exposed from the trench 137.

[0035] Next, the reversible semiconductor structure 10a is shown. Figure 1C illustrates an enlarged cross-sectional view of the semiconductor structure 10a according to some embodiments. The back side of the substrate 102 may face upwards, and the front side of the substrate 102 may face downwards. The front side of the substrate 102 may be covered with a protective layer (not shown) before flipping, but is not limited thereto. The first metal layer 132a may include a first layer 132a1 in direct contact with the metal stack 124, a second layer 132a2 on the first layer 132a1, and a third layer 132a3 on the second layer 132a2.

[0036] In some embodiments, the third layer 132a3 may be thicker than the first layer 132a1, and the third layer 132a3 may also be thicker than the second layer 132a2. In some embodiments, the thicknesses of the first layer 132a1 and the second layer 132a2 may be substantially the same, but are not limited thereto.

[0037] The back side of substrate 102 can be planarized. Planarization can be used to thin (reduce the thickness) of substrate 102. In Figure 1, substrate 102 is a planarized substrate. According to different embodiments, the planarization steps can be performed in different sequences. For example, the planarization steps can be performed before growing epitaxial layer 104, after forming first metal layer 132a, and after forming third dielectric layer 120c, but are not limited thereto. The planarization process may include etching process, chemical mechanical polishing process, mechanical polishing process, dry polishing process, or a combination of the above.

[0038] Furthermore, according to some embodiments, as shown in Figures 1 and 1C, a back opening 136 may be formed extending from the second surface 102b to the first surface 102f of the planarized substrate 102 through the planarized substrate 102 and the epitaxial layer 104. A metal stack 124 is exposed from the back opening 136. The back opening 136 may be formed using a patterning process. The patterning process may include lithography and etching processes. A hard mask may be used in the patterning process. In some embodiments, the hard mask may comprise a metal, such as Ni. The etching process may be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process may be an inductively coupled plasma etching process. The hard mask may be removed after the etching process.

[0039] In some embodiments, the sidewalls of the back opening 136 in the substrate 102 may be substantially vertical, and the sidewalls of the back opening 136 in the epitaxial layer 104 may be sloped, but are not limited thereto. In some embodiments, the bottom of the back opening 136 is narrower than the top of the back opening 136. Here, the bottom of the back opening 136 is close to the metal stack 124.

[0040] Because the resist layer 130 is located within the metal stack 124, the metal stack 124 may not be etched through during the etching process that forms the back opening 136. Therefore, etching power can be enhanced, while etching process time can be reduced.

[0041] Next, according to some embodiments, as shown in Figure 1, a metal structure 138 is formed in the back opening 136. The metal structure 138 may be a via structure. The metal structure 138 may be formed through the substrate 102.

[0042] In some embodiments, the metal structure 138 may be connected to the metal stack 124. In some embodiments, the metal structure 138 is in direct contact with the metal stack 124. In some embodiments, the metal structure 138 is in direct contact with the resistance layer 130 of the metal stack 124.

[0043] The metal structure 138 may include a conductive metal. The metal structure 138 may include Au, Ti, Ni, Pt, Cu, other suitable materials, or combinations thereof. In some embodiments, the metal structure 138 includes Au. The metal structure 138 may be formed using electroplating, electron beam evaporation, resistance heating evaporation, sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof.

[0044] Many variations and / or modifications can be made to the embodiments of the present invention. Figure 2 is a cross-sectional view of the semiconductor structure 10b according to some embodiments. Some processes or elements are the same as or similar to those in the above embodiments, and therefore these processes and elements are not repeated here. Unlike the above embodiments, according to some other embodiments, as shown in Figure 2, the metal stack 124 may be partially consumed during the etching process to form the back opening 136.

[0045] Figure 2 is an enlarged cross-sectional view of the dashed frame 140 shown in Figure 1C. In some embodiments, during the etching process that forms the back opening 136, certain layers of the metal stack 124 are etched. Through the resistance layer 130, some of the resistance layer 130 and the adhesion layer 126 remain during the etching process, thus preventing damage to the first metal layer 132a.

[0046] In some embodiments, a portion of the metal stack 124 may surround an extension 138e of the metal structure 138. The extension 138e may refer to the metal structure 138 within the back opening 136 of the metal stack 124. In some embodiments, corresponding to the substrate 102 and / or the epitaxial layer 104, the extension 138e of the metal structure 138 is narrower than the main portion 138m of the metal structure 138.

[0047] In some embodiments, after the etching process, at least three resistance layers 130 and adhesion layers 126 remain. In some embodiments, the etched resistance layers 130 and adhesion layers 126 have sloped sidewalls in the back opening 136. In some embodiments, the metal structure 138 is in direct contact with the resistance layers 130 and adhesion layers 126.

[0048] Many variations and / or modifications can be made to the embodiments of the present invention. Figure 3 is a cross-sectional view of the semiconductor structure 10c according to some embodiments. Some processes or elements are the same as or similar to those in the above embodiments, and therefore these processes and elements are not repeated here. Unlike the above embodiments, according to some other embodiments, as shown in Figure 3, the second metal layer 132b is formed directly on the metal stack 124.

[0049] In some embodiments, the second metal layer 132b is in direct contact with the metal stack 124, the source electrode 116, and the drain electrode 118. The second metal layer 132b may be located above the second dielectric layer 120b. This can reduce process time and cost.

[0050] As described above, this embodiment of the invention provides a semiconductor structure and a method for forming the semiconductor structure. Because the corresponding back openings are staggered to form a resistance layer and an adhesion layer, the etching process of the back openings will not damage the metal layer on the front side of the substrate. Therefore, etching power can be enhanced, while etching process time can be reduced.

[0051] It should be noted that although some benefits and effects are described in the above embodiments, not all embodiments are required to achieve all benefits and effects.

[0052] The foregoing description outlines the feature components of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments; therefore, the scope of protection of the present invention shall be determined by the appended claims. Furthermore, although the present invention has been disclosed above with reference to several preferred embodiments, it is not intended to limit the invention, and not all advantages have been described in detail herein.

[0053] 10a, 10b: Semiconductor structure 102:Substrate 102f: First surface 102b: Second surface 104: Epitaxial layer 106: Nucleation layer 108: Buffer layer 110: Channel Layer 112: Carrier Supply Layer 114: Cap layer 116: Source electrode 118: Drain electrode 120a: First dielectric layer 120b: Second dielectric layer 120c: Third dielectric layer 122: Gate electrode 124: Metal Stacking 126: Adhesion layer 130: Resistance Layer 132a: First metal layer 132a1: First layer 132a2: Second layer 132a3: Third layer 132b: Second metal layer 132c: Third metal layer 133: Trench 134: Field Board 135: Opening 136: Opening on the back 137: Trench 138: Metal Structure 138m: Main part 138e: Extension 140: Dashed border

Claims

1. A semiconductor device, comprising: A substrate having a first surface and a second surface; A metal stack is located on the first surface and includes a plurality of overlapping layers and at least one resistance layer; an opening is formed in the substrate and extends from the second surface to the first surface; and a conductive metal is located in the opening and connected to the metal stack, wherein the overlapping layers include refractory metal.

2. The semiconductor device as claimed in claim 1, wherein the attached layers comprise tantalum (Ta).

3. The semiconductor device as claimed in claim 1, wherein the at least one resistive layer comprises a nickel-chromium alloy.

4. The semiconductor device as claimed in claim 1, wherein the thickness of one of the at least one resistive layers is greater than the thickness of one of the adhesive layers.

5. The semiconductor device as claimed in claim 1, wherein the ratio of the thickness of one of the at least one resistive layers to the thickness of one of the attachment layers is in the range of about 3 to about 7.

6. The semiconductor device as claimed in claim 1, wherein one of the at least one resistive layers has a thickness of less than about 1000 angstroms.

7. The semiconductor device as claimed in claim 1, wherein the conductive metal is in direct contact with one of the at least one resistive layer.

8. The semiconductor device as claimed in claim 1, wherein a portion of the metal stack surrounds an extension of the conductive metal.

9. The semiconductor device as claimed in claim 8, wherein the width of the extension of the conductive metal is smaller than the width of a major portion of the conductive metal.

10. The semiconductor device as claimed in claim 1, wherein the number of the attached layers is in the range of 3 to 8, and the number of the at least one resistive layer is in the range of 3 to 8.

11. A semiconductor device, comprising: An epitaxial layer is located on a substrate; A gate structure is located on the epitaxial layer; The source / drain structure is located on the opposite side of the gate structure; A substrate is located on the gate structure; a metal stack is located on the epitaxial layer and includes alternating stacked tantalum and nickel-chromium alloy layers; a metal layer is located on the metal stack and the source / drain structures; and a via structure passes through the substrate, wherein the via structure is in direct contact with the metal stack.

12. The semiconductor device as claimed in claim 11, wherein the epitaxial layer is in direct contact with one of the tantalum layers of the metal stack.

13. The semiconductor device as claimed in claim 11, wherein a bottommost tantalum layer of the metal stack is thicker than one of the other tantalum layers of the metal stack.

14. The semiconductor device as claimed in claim 11, wherein the metal layer is in direct contact with the nickel-chromium alloy layer of the metal stack.

15. The semiconductor device as claimed in claim 11, wherein the metal layer covers a top surface and sidewalls of the metal stack.

16. A method of forming a semiconductor device, comprising: An epitaxial layer is formed on a substrate; A first dielectric layer is deposited on the epitaxial layer; A metal stack is formed through the first dielectric layer, wherein the metal stack includes tantalum layers and nickel-chromium alloy layers alternately stacked on the epitaxial layer; a first conductive layer is formed on the metal stack; a second dielectric layer is formed on the first conductive layer; the second dielectric layer is patterned to form an opening exposing the first conductive layer; and a second conductive layer is formed on the second dielectric layer.

17. The method of forming a semiconductor device as described in claim 16 further includes: Before the first conductive layer is formed, a third conductive layer is formed on the metal stack.

18. The method of forming a semiconductor device as described in claim 16, further comprising: Before depositing the first dielectric layer, a source / drain structure is formed on the epitaxial layer; And a gate structure is formed on the first dielectric layer.

19. The method of forming a semiconductor device as described in claim 16, further comprising: An opening is formed, passing through the substrate and exposing the metal stack; And fill the opening with a conductive metal.

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