Memory device and operation method

Abstract

A memory device includes a surface-mount (SOM) layer formed of an OTS material. The memory device also includes a first electrode connected to a first surface of the SOM layer through a carbon layer. The memory device also includes a second electrode connected to a second surface of the SOM layer. The area of ​​the first electrode connected to the SOM layer through the carbon layer is asymmetrical with the area of ​​the second electrode connected to the SOM layer. A first forward scan voltage is applied to the first electrode to form a high threshold voltage state of the SOM layer, and a second forward scan voltage is applied to the first electrode to program the SOM layer to a low threshold voltage state. A memory window is formed between the high threshold voltage state and the low threshold voltage state of the SOM layer.

Claims

1. A memory device, comprising: A selector-only memory (SOM) layer is formed of an ovonic threshold switching (OTS) material; a first electrode is connected to a first surface of the SOM layer through a carbon layer; and a second electrode is connected to a second surface of the SOM layer. The carbon layer has a thickness of 10 nm. The area where the first electrode connects to the SOM layer through the carbon layer and the area where the second electrode connects to the SOM layer are asymmetrical. A first forward scan voltage is applied to the first electrode to form a high threshold voltage state of the SOM layer, and a second forward scan voltage is applied to the first electrode to program the SOM layer to a low threshold voltage state. A memory window is formed between the high threshold voltage state and the low threshold voltage state of the SOM layer. The second electrode is cylindrical, comprising a core and a sidewall surrounding the core. The core is formed of a dielectric material, and the sidewalls are formed of at least one of the following: TiN, TaN, and W.

2. The memory device as claimed in claim 1, wherein a reverse scan voltage is applied to the second electrode to program the selector-only memory layer to a reset state, wherein a third forward scan voltage is applied to the first electrode to program the selector-only memory layer from the reset state to the high threshold voltage state, and a fourth forward scan voltage is applied to the first electrode to program the selector-only memory layer to the low threshold voltage state.

3. The memory device as claimed in claim 2, wherein the first forward scan voltage is greater than the third forward scan voltage, the third forward scan voltage is greater than the fourth forward scan voltage, and the fourth forward scan voltage is greater than the second forward scan voltage.

4. The memory device as claimed in claim 1, wherein the bidirectional limit switch material comprises at least one of the following: AsSeGe, AsSeGeIn, AsTeSiGe, AsSeGeSi, Gese, and GeSeCu.

5. The memory device as claimed in claim 1, wherein the first electrode is formed of at least one of the following: TiN, TaN, and W.

6. The memory device as claimed in claim 1, wherein the thickness of the sidewall is 10 nm.

7. The memory device as claimed in claim 1, wherein the memory device is a mushroom-type memory device, a pillar-type memory device, or a memory device having a vertical sidewall structure.

8. The memory device as claimed in claim 1, wherein the thickness of the selector memory layer is 10 nm to 30 nm.

9. An operating method for programming a memory device having a first electrode, an SOM layer, and a second electrode, the operating method comprising: A first forward scanning voltage is applied to the first electrode to form a high threshold voltage state of the SOM layer; A second forward scanning voltage is applied to the first electrode to program the SOM layer to a low threshold voltage state; and a memory window is formed between the high threshold voltage state and the low threshold voltage state of the SOM layer, wherein the SOM layer is formed of an OTS material, wherein the first electrode is connected to a first surface of the SOM layer through a carbon layer, and the second electrode is connected to a second surface of the SOM layer, wherein the area of ​​the first electrode connected to the SOM layer through the carbon layer and the area of ​​the second electrode connected to the SOM layer are asymmetrical, wherein the thickness of the carbon layer is 10 nm, wherein the shape of the second electrode is a cylinder, the cylinder including a core and a sidewall surrounding the core, wherein the core is formed of a dielectric material, and the sidewall is formed of at least one of the following: TiN, TaN, and W.

10. The operating method as described in claim 9 further includes: A reverse scan voltage is applied to the second electrode to program the SOM layer to a reset state; A third positive scan voltage is applied to the first electrode to program the SOM layer from the reset state to the high threshold voltage state; and a fourth positive scan voltage is applied to the first electrode to program the SOM layer to the low threshold voltage state.

11. The operating method as described in claim 10, wherein the first forward scan voltage is greater than the third forward scan voltage, the third forward scan voltage is greater than the fourth forward scan voltage, and the fourth forward scan voltage is greater than the second forward scan voltage.

12. The method of operation as described in claim 9, wherein the OTS material comprises at least one of the following: AsSeGe, AsSeGeIn, AsTeSiGe, AsSeGeSi, Gese, and GeSeCu.

13. The method of operation as described in claim 9, wherein the first electrode is formed of at least one of the following: TiN, TaN, and W.

14. The method of operation as described in claim 9, wherein the thickness of the sidewall is 10 nm.

15. The method of operation as described in claim 9, wherein the memory device is a mushroom-type memory device, a pillar-type memory device, or a memory device having a vertical sidewall structure.

16. The method of operation as described in claim 9, wherein the thickness of the SOM layer is 10 nm to 30 nm.

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