Semiconductor structure and methods of manufacturing the same

Abstract

A semiconductor structure includes a semiconductor device comprising a first substrate and a first bonding structure. The first bonding structure is disposed above the first substrate and includes a first dielectric structure, a second dielectric structure, and a first interconnect structure. The second dielectric structure is disposed above the first dielectric structure and includes a first sublayer and a first warpage control layer above the first sublayer, wherein the first sublayer is located between the first dielectric structure and the first warpage control layer. The first interconnect structure extends through the first and second dielectric structures, wherein the first interconnect structure includes a first via portion extending through the first dielectric structure and a first bonding pad portion extending through the second dielectric structure, and the ratio of the height of the first bonding pad portion to the height of the first via portion is approximately in the range of 0.9 to 1.2.

Claims

1. A semiconductor structure, comprising: A semiconductor device includes: a first substrate; and a first bonding structure disposed above the first substrate, and including: a first dielectric structure; a second dielectric structure disposed above the first dielectric structure, and including a first sublayer and a first warpage control layer located above the first sublayer, wherein the first sublayer is located between the first dielectric structure and the first warpage control layer; and a first connection structure penetrating the first dielectric structure and the second dielectric structure, wherein the first connection structure includes a first via portion penetrating the first dielectric structure and a first bonding pad portion penetrating the second dielectric structure, and the ratio of the height of the first bonding pad portion to the height of the first via portion is approximately in the range of 0.9 to 1.

2.

2. The semiconductor structure as claimed in claim 1, wherein the aspect ratio of the first interconnect structure is approximately in the range of 1.0 to 1.

3.

3. The semiconductor structure of claim 1, wherein the first warpage control layer comprises a silicon nitride layer, a silicon carbide layer, or a silicon nitride-carbonide layer.

4. The semiconductor structure as claimed in claim 1, wherein the material of the first sublayer is different from the material of the first warp control layer.

5. The semiconductor structure of claim 1, wherein the second dielectric structure further includes a second sublayer, and the first warpage control layer is disposed between the first sublayer and the second sublayer, wherein the material of the second sublayer is different from the material of the first warpage control layer.

6. A semiconductor structure, comprising: A base layer includes: a semiconductor device including: a first substrate; a first dielectric structure located above the first substrate; a second dielectric structure located above the first dielectric structure, the first dielectric structure being located between the first substrate and the second dielectric structure, and the second dielectric structure including a first warpage control layer perpendicularly spaced from the first dielectric structure, wherein the first warpage control layer includes a first dielectric layer containing silicon and nitride, and the ratio of silicon content to nitrogen content included in the first warpage control layer is 3:1 to 4:1; and a first interconnect structure penetrating the first dielectric structure and the second dielectric structure; a stacked layer disposed above the base layer and including: a semiconductor die including: a second substrate; and a third dielectric structure located above the second substrate; A fourth dielectric structure, located above the third dielectric structure, the third dielectric structure being located between the second substrate and the fourth dielectric structure, and the fourth dielectric structure including a second warpage control layer perpendicularly spaced from the third dielectric structure; a second connection structure penetrating the third dielectric structure and the fourth dielectric structure, wherein a metal-to-metal bonding interface is located between the second connection structure and the first connection structure; and an insulating package laterally encapsulating the semiconductor die; a redistribution circuit structure disposed above the base layer, wherein the base layer is located between and electrically coupled to the stacked layer and the redistribution circuit structure; and a plurality of conductive terminals disposed above and connected to the redistribution circuit structure, wherein the redistribution circuit structure is located between the plurality of conductive terminals and the base layer.

7. The semiconductor structure as claimed in claim 6, wherein the base layer further comprises: A first device layer is disposed between the first substrate and the first dielectric structure; A first interconnect is disposed between the first device layer and the first dielectric structure; and a plurality of vias penetrating the first substrate and the first device layer and extending further into the first interconnect, wherein the redistribution circuit structure is electrically coupled to the base layer through the plurality of vias, wherein the thickness of the first warp control layer is about 1000 Å to about 15000 Å.

8. The semiconductor structure as claimed in claim 6, wherein the material of the first warp control layer includes SiC or SiCN.

9. The semiconductor structure as claimed in claim 6, wherein the semiconductor die further comprises: The second device layer is disposed between the second substrate and the third dielectric structure; A second interconnect is disposed between the second device layer and the third dielectric structure, wherein the redistribution circuit structure is electrically coupled to the semiconductor die through the base layer, wherein the thickness of the second warpage control layer is from about 1000 Å to about 15000 Å, wherein the second warpage control layer includes a second dielectric layer containing silicon and nitrides, and the ratio of silicon content to nitrogen content included in the first warpage control layer is from 3:1 to 4:1, and wherein the material of the first warpage control layer includes SiC or SiCN.

10. A method for manufacturing a semiconductor structure, comprising: Provide a first substrate; A first dielectric structure is formed above the first substrate; Forming a second dielectric structure above a first dielectric structure includes: forming a first sublayer; and forming a first warpage control layer above the first sublayer; performing a first patterning process to form a first trench opening penetrating a first via opening of the second dielectric structure; performing a second patterning process to form a first via opening penetrating the first via opening of the first dielectric structure, the first via opening being spatially connected to the first trench opening; forming a first connection structure in the first via opening, a first bonding pad portion of the first connection structure being disposed within the first trench opening, a first via portion of the first connection structure being disposed within the first via opening, and the ratio of the height of the first bonding pad portion to the height of the first via portion being approximately in the range of 0.9 to 1.2; providing a semiconductor die above the first connection structure; bonding the semiconductor die to the first connection structure and the second dielectric structure; and encapsulating the semiconductor die in an insulating package.

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