Mixed precision calculation method and device

Abstract

This invention provides a mixed-precision calculation method and apparatus. The mixed-precision calculation apparatus includes a format aligner, a mantissa multiplier, an exponent manager, and a shifter. The format aligner converts a first input floating-point number and a second input floating-point number into first-converted-format floating-point numbers and second-converted-format floating-point numbers with the same floating-point format. The mantissa multiplier uses the mantissa portions of the first-converted-format floating-point numbers and the second-converted-format floating-point numbers to perform a multiplication operation to generate a product value. The exponent manager generates a shift value based on the exponent portions of the first-converted-format floating-point numbers and the second-converted-format floating-point numbers. The shifter performs a shift operation on the product value based on the shift value to generate a shifted product value.

Claims

1. A mixed-precision computing device, comprising: A first format aligner is configured to convert a first input floating-point number having a first floating-point format to a first converted-format floating-point number, and to convert a second input floating-point number having a second floating-point format to a second converted-format floating-point number, wherein the first converted-format floating-point number and the second converted-format floating-point number have the same floating-point format; a first mantissa multiplier is coupled to the first format aligner to receive the first converted-format floating-point number and the second converted-format floating-point number, wherein the first mantissa multiplier performs a multiplication operation using a first mantissa portion of the first converted-format floating-point number and a second mantissa portion of the second converted-format floating-point number to generate a first product value; an exponent manager is coupled to the first format aligner to receive a first exponent portion of the first converted-format floating-point number and a second exponent portion of the second converted-format floating-point number, wherein the exponent manager generates a first shift value based on the first exponent portion and the second exponent portion; And a first shifter coupled to the first mantissa multiplier to receive the first product value, and coupled to the exponent manager to receive the first shift value, wherein the first shifter performs a shift operation on the first product value based on the first shift value to generate a first shifted product value.

2. The mixed-precision calculation apparatus as described in claim 1, further comprising: A format converter, coupled to the first shifter to receive the first shifted product value, wherein the format converter converts the first shifted product value into a product floating-point number having a third floating-point format, an exponent manager generates an exponent compensation value based on a first hidden decimal scale corresponding to the first floating-point format and a second hidden decimal scale corresponding to the second floating-point format, the format converter being coupled to the exponent manager to receive the exponent compensation value, and the format converter compensating an exponent portion of the product floating-point number based on the exponent compensation value to generate a compensated floating-point number; and an accumulator, coupled to the format converter to receive the compensated floating-point number, wherein the accumulator accumulates the compensated floating-point number to an output floating-point number, and the output floating-point number is used as an inner product result.

3. The mixed precision calculation apparatus as claimed in claim 2, wherein the format converter adds the exponent compensation value to the exponent portion of the product floating-point number to generate the compensated floating-point number.

4. The mixed-precision calculation apparatus as claimed in claim 2, wherein the accumulator comprises: An adder, wherein a first input of the adder is coupled to the format converter to receive the compensated floating-point number; And a register, wherein an input of the register is coupled to an output of the adder, an output of the register is coupled to a second input of the adder, and the output of the register generates the output floating-point number.

5. The mixed-precision calculation apparatus as described in claim 1, further comprising: A second format aligner is configured to convert a third input floating-point number having the first floating-point format into a third converted format floating-point number, and to convert a fourth input floating-point number having the second floating-point format into a fourth converted format floating-point number, wherein the third converted format floating-point number and the fourth converted format floating-point number have the same floating-point format; a second mantissa multiplier is coupled to the second format aligner to receive the third converted format floating-point number and the fourth converted format floating-point number, wherein the second mantissa multiplier uses a third mantissa portion of the third converted format floating-point number and a fourth mantissa portion of the fourth converted format floating-point number to perform a multiplication operation to generate a second product value; an exponent manager is coupled to the second format aligner to receive a third exponent portion of the third converted format floating-point number and a fourth exponent portion of the fourth converted format floating-point number, and the exponent manager generates a second shift value based on the third exponent portion and the fourth exponent portion; And a second shifter, coupled to the second mantissa multiplier to receive the second product value, and coupled to the exponent manager to receive the second shift value, wherein the second shifter performs a shift operation on the second product value based on the second shift value to generate a second shifted product value.

6. The mixed-precision calculation apparatus as described in claim 5, further comprising: A summing circuit, coupled to the first shifter to receive the first shifted product value, and coupled to the second shifter to receive the second shifted product value, wherein the summing circuit performs an addition operation using at least the first shifted product value and the second shifted product value to generate a summed value; and a format converter, coupled to an output of the summing circuit to receive the summed value, wherein the format converter converts the summed value into a product floating-point number having a third floating-point format, an exponent manager generates an exponent compensation value based on a first hidden decimal scale corresponding to the first floating-point format and a second hidden decimal scale corresponding to the second floating-point format, the format converter is coupled to the exponent manager to receive the exponent compensation value, and the format converter compensates for an exponent portion of the product floating-point number based on the exponent compensation value to generate a compensated floating-point number.

7. The mixed-precision calculation apparatus as described in claim 6, further comprising: An accumulator, coupled to the format converter, receives the compensated floating-point number, wherein the accumulator accumulates the compensated floating-point number to an output floating-point number, and the output floating-point number is used as an inner product result.

8. The mixed precision calculation apparatus as claimed in claim 6, wherein the summing circuit comprises: A plurality of adder trees, each of which is coupled to the first shifter to receive a corresponding bit portion of the first shifted product value, each of which is coupled to the second shifter to receive a corresponding bit portion of the second shifted product value, an exponent manager generating a plurality of adder tree enable signals to the adder trees based on a plurality of shift values ​​including the first shift value and the second shift value, and each of the adder tree enable signals controlling a corresponding bit portion of the adder trees; and an adder circuit coupled to an output of each of the adder trees, wherein the adder circuit generates the summed value to the format converter.

9. The mixed-precision calculation apparatus as claimed in claim 8, wherein the addition circuit comprises: Multiple pipeline registers, wherein an input of each of the pipeline registers is coupled to the output of a corresponding one of the addition trees; An adder, wherein a first input of the adder is coupled to an output of a first pipeline register of the pipeline registers; And a third shifter, wherein an input of the third shifter is coupled to an output of a second pipeline register of the pipeline registers, a second input of the adder is coupled to an output of the third shifter, and the adder generates the summation value for the format converter.

10. The mixed-precision computing apparatus as claimed in claim 1, wherein the first format aligner uses a sign bit of the first input floating-point number as a sign bit of the first converted-format floating-point number, the first format aligner uses an exponent portion of the first input floating-point number as a least significant bit portion of the first exponent portion of the first converted-format floating-point number, and the remaining bits of the first exponent portion are filled with 0; the first format aligner uses a mantissa portion of the first input floating-point number as a most significant bit portion of the first mantissa portion of the first converted-format floating-point number, and the remaining bits of the first mantissa portion are filled with 0; ... Other bits are filled with 0. The first format aligner uses a sign bit of the second input floating-point number as a sign bit of the second converted floating-point number. The first format aligner uses an exponent of the second input floating-point number as the least significant bit of the second exponent of the second converted floating-point number. Other bits of the second exponent, except for the least significant bit, are filled with 0. The first format aligner uses a mantissa of the second input floating-point number as the most significant bit of the second mantissa of the second converted floating-point number. Other bits of the second mantissa, except for the most significant bit, are filled with 0.

11. The mixed-precision computing apparatus as claimed in claim 1, wherein the first mantissa multiplier comprises: A first OR gate, wherein a plurality of inputs of the first OR gate are coupled to the first format aligner to receive the first exponent portion of the first converted-format floating-point number; a multiplier, wherein a first input of the multiplier receives a first multiplier, a second input of the multiplier receives a second multiplier, an output of the multiplier generates the first product value, a sign bit of the first multiplier is 0, an exponent bit of the first multiplier is the output of the first OR gate, and a mantissa portion of the first multiplier is the first mantissa portion of the first converted-format floating-point number; a second OR gate, wherein a plurality of inputs of the second OR gate are coupled to the first format aligner to receive the second exponent portion of the second converted-format floating-point number, wherein the output of the second OR gate serves as an exponent bit of a third multiplier, a sign bit of the third multiplier is 0, and a mantissa portion of the third multiplier is the second mantissa portion of the second converted-format floating-point number; A mutex gate, wherein a first input of the mutex gate is coupled to the first format aligner to receive a sign bit of the first converted-format floating-point number, and a second input of the mutex gate is coupled to the first format aligner to receive a sign bit of the second converted-format floating-point number; a negative number circuit, wherein the negative number circuit multiplies the third multiplier by -1 to generate a fourth multiplier; and a multiplexer, wherein a first input of the multiplexer receives the third multiplier, a second input of the multiplexer is coupled to an output of the negative number circuit to receive the fourth multiplier, a control terminal of the multiplexer is coupled to an output of the mutex gate, and an output of the multiplexer is coupled to the second input of the multiplier to provide the second multiplier.

12. The mixed-precision calculation apparatus as claimed in claim 1, wherein the index manager comprises: A first shift value generation circuit, coupled to the first format aligner, receives the first exponent portion of the first converted-format floating-point number and the second exponent portion of the second converted-format floating-point number, wherein the first shift value generation circuit generates the first shift value based on the first exponent portion and the second exponent portion and sends it to the first shifter; a first hidden decimal scale table for converting the first floating-point format to a first hidden decimal scale; a second hidden decimal scale table for converting the second floating-point format to a second hidden decimal scale; and a first adder, wherein a first input of the first adder receives the first hidden decimal scale, a second input of the first adder receives the second hidden decimal scale, the first adder generates an exponent compensation value and sends it to a format converter, the format converter converts the first shifted product value to a product floating-point number having a third floating-point format, and the format converter compensates for an exponent portion of the product floating-point number based on the exponent compensation value to generate a compensated floating-point number.

13. The mixed precision calculation apparatus as claimed in claim 12, wherein the first shift value generation circuit comprises: A second adder, wherein a first input of the second adder is coupled to the first format aligner to receive the first exponent of the first converted-format floating-point number, and a second input of the second adder is coupled to the first format aligner to receive the second exponent of the second converted-format floating-point number; a first OR gate, wherein a plurality of inputs of the first OR gate are coupled to the first format aligner to receive the first exponent of the first converted-format floating-point number; a second OR gate, wherein a plurality of inputs of the second OR gate are coupled to the first format aligner to receive the second exponent of the second converted-format floating-point number; a third adder, wherein a first input of the third adder is coupled to an output of the first OR gate, and a second input of the third adder is coupled to an output of the second OR gate; And a subtractor, wherein a first input of the subtractor is coupled to an output of the second adder, a second input of the subtractor is coupled to an output of the third adder, and an output of the subtractor generates the first shift value to the first shifter.

14. The mixed-precision calculation apparatus as claimed in claim 12, wherein the index manager further comprises: A second shift value generation circuit is coupled to a second format aligner of the mixed-precision computing device to receive a third exponent portion of a third converted-format floating-point number and a fourth exponent portion of a fourth converted-format floating-point number. A second mantissa multiplier of the mixed-precision computing device is coupled to the second format aligner to receive the third converted-format floating-point number and the fourth converted-format floating-point number. The second mantissa multiplier uses the third mantissa portion of the third converted-format floating-point number and the fourth mantissa portion of the fourth converted-format floating-point number to perform a multiplication operation to generate a second product value. A second shifter of the mixed-precision computing device is coupled to the second mantissa multiplier to receive the second product value. The second shift value generation circuit generates a second shift value based on the third and fourth exponent portions and sends it to the second shifter. The second shifter performs a shift operation on the second product value based on the second shift value to generate a second shifted product value.

15. The mixed-precision calculation apparatus as claimed in claim 1, wherein the index manager comprises: Multiple shift value generation circuits are used to generate multiple original shift values, wherein the shift value generation circuits include a first shift value generation circuit coupled to the first format aligner to receive the first exponent portion of the first converted format floating-point number and the second exponent portion of the second converted format floating-point number, and the first shift value generation circuit generates a first original shift value among the original shift values ​​based on the first exponent portion and the second exponent portion; A minimum finder circuit coupled to the shift value generating circuits to receive the original shift values, wherein the minimum finder circuit outputs the smallest of the original shift values; and a plurality of subtractors, wherein a first input of each of the subtractors is coupled to an output of a corresponding one of the shift value generating circuits to receive a corresponding one of the original shift values, a second input of each of the subtractors is coupled to an output of the minimum finder circuit to receive the smallest of the original shift values, an output of each of the subtractors generates a corresponding one of the plurality of shift values, and an output of a first subtractor generates the first shift value of the shift values ​​for the first shifter.

16. The mixed-precision calculation apparatus as claimed in claim 15, wherein the index manager further comprises: A first hidden decimal scale is used to convert the first floating-point format into a first hidden decimal scale; A second hidden decimal scale for converting the second floating-point format into a second hidden decimal scale; a first adder, wherein a first input of the first adder receives the first hidden decimal scale, and a second input of the first adder receives the second hidden decimal scale; And a second adder, wherein a first input of the second adder is coupled to an output of the first adder, a second input of the second adder is coupled to the output of the minimum finding circuit to receive the minimum of the original shift values, and an output of the second adder generates an exponential compensation value to a format converter of the mixed precision calculation device.

17. The mixed-precision calculation apparatus as claimed in claim 15, wherein the index manager further comprises: A maximum finder circuit, coupled to the outputs of the subtractors to receive the shifted values, wherein the maximum finder circuit outputs the largest of the shifted values; and a generation circuit, coupled to an output of the maximum finder circuit to receive the largest of the shifted values, wherein the generation circuit generates a plurality of adder tree enable signals based on the largest to a summing circuit, the summing circuit being coupled to a plurality of shifters including the first shifter to receive a plurality of shifted product values ​​including the first shifted product value, the summing circuit performing an addition operation using the shifted product values ​​to generate a summed value, and each of the adder tree enable signals controlling a corresponding one of the plurality of adder trees of the summing circuit.

18. A method for calculating mixed accuracy, comprising: A first input floating-point number having a first floating-point format is converted to a first converted-format floating-point number by a first format aligner; a second input floating-point number having a second floating-point format is converted to a second converted-format floating-point number by the same first format aligner, wherein the first converted-format floating-point number and the second converted-format floating-point number have the same floating-point format; a first mantissa multiplier performs a multiplication operation using a first mantissa portion of the first converted-format floating-point number and a second mantissa portion of the second converted-format floating-point number to generate a first product value, wherein the first mantissa multiplier is coupled to the first format aligner to receive the first converted-format floating-point number and the second converted-format floating-point number; An exponent manager generates a first shift value based on a first exponent portion of the first converted-format floating-point number and a second exponent portion of the second converted-format floating-point number, wherein the exponent manager is coupled to the first format aligner; and a first shifter performs a shift operation on the first product value based on the first shift value to generate a first shifted product value, wherein the first shifter is coupled to the first mantissa multiplier to receive the first product value, and the first shifter is coupled to the exponent manager to receive the first shift value.

19. The method for calculating mixed precision as described in claim 18 further includes: The first shifted product value is converted into a product floating-point number having a third floating-point format by a format converter, wherein the format converter is coupled to the first shifter to receive the first shifted product value; an exponent manager generates an exponent compensation value based on a first hidden decimal scale corresponding to the first floating-point format and a second hidden decimal scale corresponding to the second floating-point format, wherein the format converter is coupled to the exponent manager to receive the exponent compensation value; the format converter compensates an exponent portion of the product floating-point number based on the exponent compensation value to generate a compensated floating-point number; and an accumulator accumulates the compensated floating-point number to an output floating-point number, wherein the accumulator is coupled to the format converter to receive the compensated floating-point number, and the output floating-point number is used as an inner product result.

20. The method for calculating mixed precision as described in claim 19 further includes: The format converter adds the exponent compensation value to the exponent of the product floating-point number to generate the compensated floating-point number.

21. The method for calculating mixed precision as described in claim 18 further includes: A third input floating-point number having the first floating-point format is converted to a third converted-format floating-point number by a second format aligner; a fourth input floating-point number having the second floating-point format is converted to a fourth converted-format floating-point number by the second format aligner, wherein the third converted-format floating-point number and the fourth converted-format floating-point number have the same floating-point format; a second mantissa multiplier performs a multiplication operation using a third mantissa portion of the third converted-format floating-point number and a fourth mantissa portion of the fourth converted-format floating-point number to generate a second product value, wherein the second mantissa multiplier is coupled to the second format aligner to receive the third converted-format floating-point number and the fourth converted-format floating-point number; The exponent manager generates a second shift value based on a third exponent portion of the third converted-format floating-point number and a fourth exponent portion of the fourth converted-format floating-point number, wherein the exponent manager is coupled to the second format aligner; and a second shifter performs a shift operation on the second product value based on the second shift value to generate a second shifted product value, wherein the second shifter is coupled to the second mantissa multiplier to receive the second product value, and the second shifter is coupled to the exponent manager to receive the second shift value.

22. The method for calculating mixed precision as described in claim 21 further includes: A summing circuit generates a summed value by performing an addition operation on at least the first shifted product value and the second shifted product value, wherein the summing circuit is coupled to the first shifter to receive the first shifted product value, and the summing circuit is coupled to the second shifter to receive the second shifted product value; a format converter converts the summed value into a product floating-point number having a third floating-point format, wherein the format converter is coupled to an output of the summing circuit to receive the summed value; an exponent manager generates an exponent compensation value based on a first hidden decimal scale corresponding to the first floating-point format and a second hidden decimal scale corresponding to the second floating-point format, wherein the format converter is coupled to the exponent manager to receive the exponent compensation value; and the format converter compensates an exponent portion of the product floating-point number based on the exponent compensation value to generate a compensated floating-point number.

23. The method for calculating mixed precision as described in claim 22 further includes: An accumulator accumulates the compensated floating-point number to an output floating-point number, wherein the accumulator is coupled to the format converter to receive the compensated floating-point number and the output floating-point number as an inner product result.

24. The method for calculating mixed precision as described in claim 22 further includes: The exponent manager generates multiple adder tree enable signals for multiple adder trees of the summing circuit based on multiple shift values ​​including the first shift value and the second shift value, wherein each of the adder trees is coupled to the first shifter to receive a corresponding bit portion of the first shifted product value, and each of the adder trees is coupled to the second shifter to receive a corresponding bit portion of the second shifted product value; each of the adder tree enable signals controls a corresponding adder tree; and an adder circuit of the summing circuit generates the summed value for the format converter, wherein the adder circuit is coupled to an output of each of the adder trees.

25. The method for calculating mixed precision as described in claim 18 further includes: The first format aligner uses a sign bit of the first input floating-point number as a sign bit of the first converted floating-point number; the first format aligner uses an exponent portion of the first input floating-point number as a least significant bit portion of the first exponent portion of the first converted floating-point number; the first format aligner fills all bits of the first exponent portion except for the least significant bit portion with 0; the first format aligner uses a mantissa portion of the first input floating-point number as a most significant bit portion of the first mantissa portion of the first converted floating-point number; the first format aligner fills all bits of the first mantissa portion except for the most significant bit portion with 0; the first format aligner uses a sign bit of the second input floating-point number as a sign bit of the second converted floating-point number. The first format aligner uses the exponent portion of the second input floating-point number as the least significant bit portion of the second exponent portion of the second converted format floating-point number; the first format aligner fills all bits in the second exponent portion except for the least significant bit portion with 0; the first format aligner uses the mantissa portion of the second input floating-point number as the most significant bit portion of the second mantissa portion of the second converted format floating-point number; and the first format aligner fills all bits in the second mantissa portion except for the most significant bit portion with 0.

26. The method for calculating mixed precision as described in claim 18 further includes: The first mantissa multiplier performs a multiplication operation on a first multiplier and a second multiplier to produce the first product value, wherein a sign bit of the first multiplier is 0, a mantissa part of the first multiplier is the first mantissa part of the first converted format floating-point number, an exponent bit of the first multiplier is the output of a first OR gate of the first mantissa multiplier, and a plurality of inputs of the first OR gate are coupled to the first format aligner to receive the first exponent part of the first converted format floating-point number; A third multiplier is multiplied by -1 by a negative circuit of the first mantissa multiplier to generate a fourth multiplier, wherein a sign bit of the third multiplier is 0, a mantissa portion of the third multiplier is the second mantissa portion of the second converted-format floating-point number, the output of a second OR gate of the first mantissa multiplier is used as an exponent bit of the third multiplier, and multiple inputs of the second OR gate are coupled to the first format aligner to receive the second exponent portion of the second converted-format floating-point number; and the second multiplier is provided to the multiplication by an output of a multiplexer of the first mantissa multiplier. The second input terminal of the multiplexer, wherein a first input terminal of the multiplexer receives the third multiplier, a second input terminal of the multiplexer is coupled to an output terminal of the negative number circuit to receive the fourth multiplier, a control terminal of the multiplexer is coupled to an output terminal of a mutex gate of the first mantissa multiplier, a first input terminal of the mutex gate is coupled to the first format aligner to receive a sign bit of the first converted floating-point number, and a second input terminal of the mutex gate is coupled to the first format aligner to receive a sign bit of the second converted floating-point number.

27. The method for calculating mixed precision as described in claim 18 further includes: A first shift value generation circuit of the exponent manager generates a first shift value based on the first exponent portion and the second exponent portion and sends it to the first shifter, wherein the first shift value generation circuit is coupled to the first format aligner to receive the first exponent portion of the first converted-format floating-point number and the second exponent portion of the second converted-format floating-point number; the first floating-point format is converted to a first hidden decimal scale by a first hidden decimal scale table of the exponent manager; the second floating-point format is converted to a second hidden decimal scale by a second hidden decimal scale table of the exponent manager; a first adder of the exponent manager generates an exponent compensation value and sends it to a format converter, wherein a first input of the first adder receives the first hidden decimal scale, and a second input of the first adder receives the second hidden decimal scale; The format converter converts the first shifted product value into a product floating-point number with a third floating-point format; and the format converter compensates an exponent portion of the product floating-point number based on the exponent compensation value to generate a compensated floating-point number.

28. The method for calculating mixed precision as described in claim 18 further includes: The exponent manager generates multiple original shift values ​​through multiple shift value generation circuits, wherein the shift value generation circuits include a first shift value generation circuit coupled to the first format aligner to receive the first exponent portion of the first converted format floating-point number and the second exponent portion of the second converted format floating-point number, and the first shift value generation circuit generates a first original shift value among the original shift values ​​based on the first exponent portion and the second exponent portion; The exponent manager outputs the smallest of the original shift values ​​through a minimum-finding circuit, wherein the minimum-finding circuit is coupled to the shift value generating circuit to receive the original shift values; and a corresponding value among the multiple shift values ​​is generated by an output of each of the multiple subtractors of the exponent manager, wherein a first input of each of the subtractors is coupled to an output of a corresponding value in the shift value generating circuit to receive the corresponding value among the original shift values, a second input of each of the subtractors is coupled to an output of the minimum-finding circuit to receive the smallest of the original shift values, and an output of a first subtractor of the subtractors generates the first shift value among the shift values ​​for the first shifter.

29. The method for calculating mixed precision as described in claim 28 further includes: The first floating-point format is converted to a first hidden decimal scale by a first hidden decimal scale of the exponent manager, wherein a first input of a first adder of the exponent manager receives the first hidden decimal scale; the second floating-point format is converted to a second hidden decimal scale by a second hidden decimal scale of the exponent manager, wherein a second input of the first adder receives the second hidden decimal scale; and an exponent compensation value is generated by an output of a second adder of the exponent manager for a format converter, wherein a first input of the second adder is coupled to an output of the first adder, and a second input of the second adder is coupled to the output of the minimum finding circuit to receive the smallest of the original shift values.

30. The method for calculating mixed precision as described in claim 28 further includes: The exponent manager outputs the largest of the shifted values ​​via a maximum-finding circuit, wherein the maximum-finding circuit is coupled to the outputs of the subtractors to receive the shifted values; the exponent manager generates a plurality of adder tree enable signals based on the largest of the shifted values ​​and sends them to a summing circuit, wherein the generating circuit is coupled to an output of the maximum-finding circuit to receive the largest, and the summing circuit is coupled to a plurality of shifters including the first shifter to receive a plurality of shifted product values ​​including the first shifted product value; the summing circuit performs an addition operation using the shifted product values ​​to generate a summed value; and each of the adder tree enable signals controls a corresponding one of the plurality of adder trees of the summing circuit.

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