Dynamic amplifier with sequential amplifications

Abstract

This invention discloses a dynamic amplifier comprising: two transistors, two capacitors, and a group of switched capacitors. The source, gate, and drain of the first transistor are respectively coupled to a first node for receiving a first input signal and coupled to a second node. The source, gate, and drain of the second transistor are respectively coupled to the first node for receiving a second input signal and coupled to a third node. The first capacitor is coupled to the second node and a reference voltage. The second capacitor is coupled to the third node and the reference voltage. The group of switched capacitors is coupled to the first node. The dynamic amplifier performs two amplification operations between two consecutive reset phases, and the group of switched capacitors provides first and second equivalent capacitance values ​​respectively during the two amplification operations, and the first and second equivalent capacitance values ​​are not equal.

Claims

1. A dynamic amplifier, comprising: a first transistor having a first source, a first gate, and a first drain, wherein, The first source is coupled to a first node, the first gate receives a first input signal, and the first drain is coupled to a second node; a second transistor has a second source, a second gate, and a second drain, wherein the second source is coupled to the first node, the second gate receives a second input signal, and the second drain is coupled to a third node; a first capacitor has a first terminal and a second terminal, wherein the first terminal is coupled to the second node, and the second terminal is coupled to a reference voltage; a second capacitor has a third terminal and a fourth terminal, wherein the third terminal is coupled to the third node, and the fourth terminal is coupled to the reference voltage; and a group of switched capacitors is coupled to the first node; wherein the dynamic amplifier performs a first amplification operation and a second amplification operation between two consecutive reset phases, and the group of switched capacitors provides a first equivalent capacitance value and a second equivalent capacitance value in the first amplification operation and the second amplification operation, respectively, and the first equivalent capacitance value is not equal to the second equivalent capacitance value.

2. As in request item 1, the dynamic amplifier, wherein, The dynamic amplifier outputs a first output signal and a second output signal from the second node and the third node, and during any reset phase, the first output signal and the second output signal are reset to the same voltage.

3. As in request item 2, the dynamic amplifier, wherein, The reference voltage is a first reference voltage, and the switched capacitor group includes: a third capacitor coupled between a fourth node and a second reference voltage; a fourth capacitor coupled between a fifth node and a third reference voltage; and a first switch coupled between the first node and the fourth node. And a second switch, coupled between the first node and the fifth node.

4. As in request item 3, the dynamic amplifier, wherein, In the first amplification operation, the first switch is on and the second switch is off; and in the second amplification operation, the first switch is off and the second switch is on.

5. As in request item 4, the dynamic amplifier, wherein, The first amplification operation occurs earlier than the second amplification operation, and the capacitance value of the third capacitor is greater than the capacitance value of the fourth capacitor.

6. The dynamic amplifier as described in request item 3, wherein, In the first amplification operation, the first switch is on and the second switch is off; and in the second amplification operation, the first switch is on and the second switch is on.

7. As in request item 6, the dynamic amplifier, wherein, The first amplification operation occurs earlier than the second amplification operation, and the capacitance value of the third capacitor is greater than the capacitance value of the fourth capacitor.

8. A dynamic amplifier, comprising: a first transistor having a first source, a first gate, and a first drain, wherein, The first source is coupled to a first node, the first gate receives a first input signal, and the first drain is coupled to a second node; a second transistor has a second source, a second gate, and a second drain, wherein the second source is coupled to the first node, the second gate receives a second input signal, and the second drain is coupled to a third node; a third transistor has a third source, a third gate, and a third drain, wherein the third source is coupled to a fourth node, the third gate receives the first input signal, and the third drain is coupled to the second node; a fourth transistor has a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the fourth node, the fourth gate receives the second input signal, and the fourth drain is coupled to the third node; a first switched capacitor group is coupled to the first node; and a second switched capacitor group is coupled to the fourth node; The dynamic amplifier performs a first amplification operation and a second amplification operation between two consecutive reset phases. The first switched capacitor group and the second switched capacitor group provide a first equivalent capacitance value and a second equivalent capacitance value respectively during the first amplification operation. The first switched capacitor group and the second switched capacitor group provide a third equivalent capacitance value and a fourth equivalent capacitance value respectively during the second amplification operation. The first equivalent capacitance value is not equal to the third equivalent capacitance value, and the second equivalent capacitance value is not equal to the fourth equivalent capacitance value.

9. The dynamic amplifier as described in request item 8, wherein, The dynamic amplifier outputs a first output signal and a second output signal from the second node and the third node, and during any reset phase, the first output signal and the second output signal are reset to the same voltage.

10. The dynamic amplifier as described in request item 9, wherein, The first equivalent capacitance value is substantially equal to the second equivalent capacitance value, and the third equivalent capacitance value is substantially equal to the fourth equivalent capacitance value.

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