Dice structure and shuttle wafer comprising the same

Abstract

A grain structure includes a substrate, an integrated circuit, a plurality of solder pads, and a plurality of dummy solder pads. The substrate includes a solder pad region and a circuit region. The integrated circuit is located in the circuit region. The plurality of solder pads are located in the solder pad region and are electrically connected to the integrated circuit. The plurality of dummy solder pads are located in the solder pad region and are electrically isolated from the integrated circuit. By applying a voltage to the plurality of dummy solder pads, a binary identification code can be obtained.

Claims

1. A die structure comprising: a substrate including a pad region and a circuit region; an integrated circuit located in the circuit region; a plurality of pads located in the pad region and electrically connected to the integrated circuit; and a plurality of virtual pads located in the pad region and electrically isolated from the integrated circuit, wherein applying a voltage to the plurality of virtual pads can obtain a set of binary identification codes, wherein the plurality of virtual pads includes: a first virtual pad; a second virtual pad electrically isolated from the first virtual pad; a third virtual pad electrically isolated from the first virtual pad and the second virtual pad; and a fourth virtual pad electrically isolated from the first virtual pad and the second virtual pad and electrically connected to the third virtual pad; When the voltage is applied to the first virtual pad, the second virtual pad, the third virtual pad, and the fourth virtual pad, a relative voltage of the first virtual pad and the second virtual pad is used to represent one of 0 and 1; a relative voltage of the third virtual pad and the fourth virtual pad is used to represent the other of 0 and 1.

2. A grain structure, comprising: a substrate including a pad region and a circuit region; an integrated circuit located in the circuit region; a plurality of pads located in the pad region and electrically connected to the integrated circuit; and a plurality of virtual pads located in the pad region and electrically isolated from the integrated circuit, wherein applying a voltage to the plurality of virtual pads can obtain a set of binary identification codes; wherein the plurality of virtual pads includes: a first virtual pad electrically isolated from a ground terminal of the integrated circuit; and a second virtual pad electrically connected to the ground terminal; when the voltage is applied, the first virtual pad has a first resistance value relative to the ground terminal, and the second virtual pad has a second resistance value relative to the ground terminal; an average value of the first resistance value and the second resistance value is used as a preset threshold; when the difference between the first resistance value or the second resistance value and the preset threshold is greater than zero, it represents 1; when the difference is less than or equal to zero, it represents 0.

3. The grain structure as described in claim 2, wherein the ground terminal is one of the plurality of pads.

4. The grain structure as described in claim 2 further includes a third virtual pad, which is electrically connected to or electrically isolated from the ground terminal and electrically isolated from the first virtual pad and the second virtual pad; when the voltage is applied to the third virtual pad, the third virtual pad has a third resistance value relative to the ground terminal, and after comparison with the preset threshold, three binary identification codes can be obtained.

5. The grain structure as described in claim 1, wherein the voltage is applied to the first virtual pad, the second virtual pad, the third virtual pad, and the fourth virtual pad via four external wires, respectively.

6. A shared wafer, comprising: a first grain structure as described in any one of claims 1 to 5; and a second grain structure as described in any one of claims 1 to 5; wherein, The integrated circuit of the first die structure and the integrated circuit of the second die structure have different two-circuit layouts; and by applying the voltage to the first die structure and the second die structure, two different sets of binary identification codes can be obtained respectively.

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