Fuse memory cells improve write speed

Abstract

A fuse memory cell includes a fuse gate, a doped well region, a dielectric layer, a first heavily doped region, and a second heavily doped region. The fuse gate is disposed on a semiconductor region and coupled to a word line. The doped well region is disposed in the semiconductor region and overlaps with a portion of the fuse gate. The dielectric layer is disposed on the semiconductor region, located between the fuse gate and the semiconductor region, and situated on the doped well region. The first heavily doped region and the second heavily doped region are disposed in the semiconductor region. The first heavily doped region and the second heavily doped region are located on opposite sides of the semiconductor region directly below the fuse gate, with the second heavily doped region situated within the doped well region. The first heavily doped region and the second heavily doped region are respectively coupled to a select line and a bit line. The doped well region can be replaced by a lightly doped region penetrating the lightly doped region.

Claims

1. A fuse memory cell disposed in a semiconductor region having a first conductivity type, the fuse memory cell comprising: a fuse gate disposed on the semiconductor region and coupled to a word line; a doped well region having a second conductivity type opposite to the first conductivity type, wherein the doped well region is disposed in the semiconductor region and overlaps a portion of the fuse gate; a dielectric layer disposed on the semiconductor region and located between the fuse gate and the semiconductor region, and located on the doped well region; and a first heavily doped region and a second heavily doped region disposed in the semiconductor region, wherein the first heavily doped region and the second heavily doped region have the second conductivity type, the first heavily doped region and the second heavily doped region are located on opposite sides of the semiconductor region directly below the fuse gate, the second heavily doped region is located in the doped well region, the first heavily doped region and the second heavily doped region are respectively coupled to a select line and a bit line, the bit line intersecting the select line perpendicularly to the word line.

2. The fuse memory cell as described in claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

3. The fuse memory cell as described in claim 2, wherein when the fuse gate, the first heavily doped region, and the second heavily doped region are selected for a write operation, a high voltage or a medium voltage is applied to the bit line, a ground voltage is applied to the word line, and the ground voltage is applied to the select line; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for a write operation, the ground voltage is applied to the bit line, the ground voltage is applied to the word line, and the medium voltage, the ground voltage, or a bias voltage is applied to the select line; the fuse gate, the first heavily doped region, and the second heavily doped region are selected for a write operation; When the doped region and the second heavily doped region are selected for read operation, the bit line is applied with the ground voltage, the word line is applied with the supply voltage, and the select line is applied with the bias voltage; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for read operation, the bit line is applied with the ground voltage, the word line is applied with the ground voltage, and the select line is applied with the ground voltage, the bias voltage, or electrically floated. The high voltage is greater than the medium voltage, the medium voltage is greater than the supply voltage, the supply voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

4. The fuse memory cell as described in claim 2, wherein when the fuse gate, the first heavily doped region, and the second heavily doped region are selected for write operation, a high voltage or a medium voltage is applied to the bit line, a ground voltage is applied to the word line, and the ground voltage is applied to the select line; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for write operation, and the high voltage or the medium voltage is applied to the bit line, the ground voltage is applied to the word line, and the medium voltage or bias voltage is applied to the select line; the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for write operation, and the high voltage or the medium voltage is applied to the bit line, the ground voltage is applied to the word line, and the medium voltage or bias voltage is applied to the select line; When the doped region and the second heavily doped region are selected for read operation, the bit line is applied with the ground voltage, the word line is applied with the supply voltage, and the select line is applied with the bias voltage; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for read operation, and the bit line is applied with the ground voltage, the word line is applied with the supply voltage, and the select line is applied with the ground voltage or electrically floated, the high voltage is greater than the medium voltage, the medium voltage is greater than the supply voltage, the supply voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

5. The fuse memory cell as described in claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

6. The fuse memory cell as described in claim 5, wherein when the fuse gate, the first heavily doped region, and the second heavily doped region are selected for a write operation, the bit line is applied a ground voltage or a medium voltage, the word line is applied a high voltage, and the select line is applied the high voltage; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for a write operation, the bit line is applied the high voltage, the word line is applied the high voltage, and the select line is applied the high voltage, a bias voltage, or the medium voltage; the fuse gate, the first heavily doped region, and the second heavily doped region are selected for a write operation. When the second doped region is selected for a read operation, a supply voltage is applied to the bit line, the ground voltage is applied to the word line, and the ground voltage is applied to the select line; when the fuse gate, the first doped region, and the second doped region are not selected for a read operation, the supply voltage is applied to the bit line, the supply voltage is applied to the word line, and the supply voltage, ground voltage, or electrically floating is applied to the select line. The high voltage is greater than the medium voltage, the medium voltage is greater than the supply voltage, the supply voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

7. The fuse memory cell as described in claim 5, wherein when the fuse gate, the first heavily doped region, and the second heavily doped region are selected for write operation, a ground voltage or a medium voltage is applied to the bit line, a high voltage is applied to the word line, and the high voltage is applied to the select line; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for write operation, and the ground voltage or the medium voltage is applied to the bit line, the high voltage is applied to the word line, and a bias voltage or the medium voltage is applied to the select line; the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for write operation, and the ground voltage or the medium voltage is applied to the bit line, the high voltage is applied to the word line, and the bias voltage or the medium voltage is applied to the select line; the fuse gate, the first heavily doped region, and the second heavily doped region are selected for write operation, and the second heavily doped region is ... When the first doped region and the second doped region are selected for read operation, a supply voltage is applied to the bit line, the ground voltage is applied to the word line, and the ground voltage is applied to the select line; when the fuse gate, the first doped region, and the second doped region are not selected for read operation, and the supply voltage is applied to the bit line, the ground voltage is applied to the word line, the supply voltage is applied to the select line, or it is electrically floated, where the high voltage is greater than the medium voltage, the medium voltage is greater than the supply voltage, the supply voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

8. The fuse memory cell as described in claim 1, wherein the semiconductor region is a semiconductor substrate.

9. The fuse memory cell as described in claim 1, wherein the semiconductor region is a doped well region disposed in a semiconductor substrate.

10. A fuse memory cell disposed in a semiconductor region having a first conductivity type, the fuse memory cell comprising: a fuse gate disposed in the semiconductor region and coupled to a word line; a lightly doped region having a second conductivity type opposite to the first conductivity type, wherein the lightly doped region is disposed in the semiconductor region and overlaps a portion of the fuse gate; A dielectric layer is disposed on the semiconductor region and located between the fuse gate and the semiconductor region, and on the lightly doped region; and a first heavily doped region and a second heavily doped region are disposed in the semiconductor region, wherein the first heavily doped region and the second heavily doped region have the second conductivity type, the first heavily doped region and the second heavily doped region are located on opposite sides of the semiconductor region directly below the fuse gate, the second heavily doped region penetrates the portion of the lightly doped region that does not overlap with the fuse gate, the first heavily doped region and the second heavily doped region are respectively coupled to a select line and a bit line, the bit line and the word line intersecting the select line perpendicularly.

11. The fuse memory cell as described in claim 10, wherein the first conductivity type is P-type and the second conductivity type is N-type.

12. A fuse memory cell as described in claim 11, wherein when the fuse gate, the first heavily doped region, and the second heavily doped region are selected for a write operation, a high voltage or a medium voltage is applied to the bit line, a ground voltage is applied to the word line, and the ground voltage is applied to the select line; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for a write operation, the ground voltage is applied to the bit line, the ground voltage is applied to the word line, and the medium voltage, the ground voltage, or a bias voltage is applied to the select line; the fuse gate, the first heavily doped region, and the second heavily doped region are selected for a write operation; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for a write operation, the ground voltage is applied to the bit line, the ground voltage is applied to the word line, and the medium voltage, the ground voltage, or a bias voltage is applied to the select line; When the doped region and the second heavily doped region are selected for read operation, the bit line is applied with the ground voltage, the word line is applied with the supply voltage, and the select line is applied with the bias voltage; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for read operation, the bit line is applied with the ground voltage, the word line is applied with the ground voltage, and the select line is applied with the ground voltage, the bias voltage, or electrically floated. The high voltage is greater than the medium voltage, the medium voltage is greater than the supply voltage, the supply voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

13. A fuse memory cell as described in claim 11, wherein when the fuse gate, the first heavily doped region, and the second heavily doped region are selected for a write operation, a high voltage or a medium voltage is applied to the bit line, a ground voltage is applied to the word line, and the ground voltage is applied to the select line; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for a write operation, and the high voltage or the medium voltage is applied to the bit line, the ground voltage is applied to the word line, and the medium voltage or bias voltage is applied to the select line; the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for a write operation, and the high voltage or the medium voltage is applied to the bit line, the ground voltage is applied to the word line, and the medium voltage or bias voltage is applied to the select line; When the heavily doped region and the second heavily doped region are selected for read operation, the bit line is subjected to the ground voltage, the word line is subjected to the supply voltage, and the select line is subjected to the bias voltage; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for read operation, and the bit line is subjected to the ground voltage, the word line is subjected to the supply voltage, and the select line is subjected to the ground voltage or electrically floated, the high voltage is greater than the medium voltage, the medium voltage is greater than the supply voltage, the supply voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

14. The fuse memory cell as described in claim 10, wherein the first conductivity type is N-type and the second conductivity type is P-type.

15. A fuse memory cell as described in claim 14, wherein when the fuse gate, the first heavily doped region, and the second heavily doped region are selected for a write operation, the bit line is applied a ground voltage or a medium voltage, the word line is applied a high voltage, and the select line is applied the high voltage; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for a write operation, the bit line is applied the high voltage, the word line is applied the high voltage, and the select line is applied the high voltage, a bias voltage, or the medium voltage; the fuse gate, the first heavily doped region, and the second heavily doped region are selected for a write operation. When the second doped region is selected for a read operation, a supply voltage is applied to the bit line, the ground voltage is applied to the word line, and the ground voltage is applied to the select line; when the fuse gate, the first doped region, and the second doped region are not selected for a read operation, the supply voltage is applied to the bit line, the supply voltage is applied to the word line, the supply voltage is applied to the select line, or the ground voltage, or it is electrically floated, the high voltage is greater than the medium voltage, the medium voltage is greater than the supply voltage, the supply voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

16. A fuse memory cell as described in claim 14, wherein when the fuse gate, the first heavily doped region, and the second heavily doped region are selected for write operations, a ground voltage or a medium voltage is applied to the bit line, a high voltage is applied to the word line, and the high voltage is applied to the select line; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for write operations, and the ground voltage or the medium voltage is applied to the bit line, the high voltage is applied to the word line, and a bias voltage or the medium voltage is applied to the select line; the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for write operations, and the ground voltage or the medium voltage is applied to the bit line, the high voltage is applied to the word line, and the bias voltage or the medium voltage is applied to the select line; When the doped region and the second heavily doped region are selected for read operation, a supply voltage is applied to the bit line, the ground voltage is applied to the word line, and the ground voltage is applied to the select line; when the fuse gate, the first heavily doped region, and the second heavily doped region are not selected for read operation, and the supply voltage is applied to the bit line, the ground voltage is applied to the word line, and the supply voltage is applied to the select line or electrically floated, the high voltage is greater than the medium voltage, the medium voltage is greater than the supply voltage, the supply voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

17. The fuse memory cell as described in claim 10, wherein the semiconductor region is a semiconductor substrate.

18. The fuse memory cell as described in claim 10, wherein the semiconductor region is a doped well region disposed in a semiconductor substrate.

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