System, method, and apparatus for transmitting and receiving data using a complementary die-to-die interface

Abstract

A system includes a first instance and a second instance of an integrated circuit. The integrated circuit includes respective external interfaces having a physical pin layout with transmit and receive pins for a specific bus located at complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for a given I / O signal on the first instance are aligned with the receive and transmit pins for the given I / O signal on the second instance.

Description

Technical Field

[0001] The embodiments described herein relate to systems-on-a-chip (SOC), and more specifically to interfaces for coupling multiple SOCs. Prior Technology

[0002] A system-on-a-chip (SoC) integrated circuit (IC) typically includes one or more processors that act as the system's central processing unit (CPU), along with various other components, a memory controller, and peripheral components. Additional components, including one or more additional ICs, can be incorporated into a specific SoC IC to form a given device. Increasing the number of processors and / or other discrete components included on the SoC IC can increase performance as desired. Additionally, cost savings, besides the SoC IC, can be achieved in the device by reducing the number of other components required to form the device. If more of the overall system is integrated into a single IC, the device can be smaller (smaller in size). Furthermore, reducing the overall device's power consumption can be achieved by integrating more components into the SoC.

[0003] A given System of Cores (SOC) can be used in a variety of applications with different performance, cost, and power considerations. For cost-sensitive applications, performance may not be as critical as cost and power consumption. On the other hand, for performance-oriented applications, cost and power consumption may not be a primary concern. Therefore, a range of SOC designs can be used to support a variety of applications.

[0004] Increasing the reusability of a given SOC design to reduce the costs associated with designing, validating, manufacturing, and evaluating new SOC designs is desirable. Therefore, techniques for scaling up a single SOC design for a range of applications are desirable. Summary of the Invention

[0005] In one embodiment, a system includes a first instance of an integrated circuit having an external interface with a physical pin layout having transmit and receive pins for a given bus located at complementary positions relative to an axis of symmetry. The system further includes a second instance of the integrated circuit having the external interface. The external interfaces of the first and second instances of the integrated circuit are oriented such that the transmit and receive pins for the given bus on the first instance are aligned with the receive and transmit pins for the given bus on the second instance.

[0006] In a further embodiment, the integrated circuit may include a plurality of transmitter circuits and a plurality of receiver circuits corresponding to some of a plurality of transmit pins and a plurality of receive pins. The plurality of transmitter circuits and the plurality of receiver circuits may correspond to a physical layout configuration of the physical pin layout. In another embodiment, the integrated circuit may include a plurality of on-chip routers coupled to a bus circuit supporting on-chip communication and communication between the first instance and the second instance of the integrated circuit. The plurality of on-chip routers may be coupled to different portions of the external interface.

[0007] In one embodiment, the transmit and receive pins of the external interface may be grouped into pin groups. These pin groups may have a common number of pins, and some of the plurality of on-chip routers may be assigned to one or more separate groups of these pin groups. In a further example, a particular on-chip router among the plurality of on-chip routers may include a specific number of pins different from the common number. At least one pin of the respective group of pins assigned to the particular on-chip router may be unused.

[0008] In one example, a first on-chip router among the plurality of on-chip routers may be coupled to the transmit pin for a given I / O signal. A second on-chip router among the plurality of on-chip routers may be coupled to the receive pin for a given I / O signal. The first on-chip router may be coupled to the second on-chip router. In another example, the system may further include an interface wrapper configured to route the transmit pin to a preset pin assignment in the first on-chip router and to route the receive pin to a non-preset pin assignment in the second on-chip router. Simple Explanation of the Diagram

[0009] The following implementation method will refer to the accompanying drawings, which will be briefly described below. [Figure 1] A block diagram illustrating an embodiment of a system having two integrated circuits coupled together. [Figure 2] shows a block diagram of an embodiment of an integrated circuit with an external interface. [Figure 3] A block diagram depicting a system with two integrated circuits that utilize an interface wrapper to route pin assignments of individual external interfaces. [Figure 4] shows a block diagram illustrating an embodiment of an integrated circuit having an external interface utilizing a pin bundle. [Figure 5A] illustrates two examples of two integrated circuits coupled together using complementary interfaces. [Figure 5B] illustrates two additional examples of two integrated circuits coupled together. [Figure 6] A flowchart illustrating an embodiment of a method for transferring data between two coupled integrated circuits. [Figure 7] shows a flowchart of an embodiment of a method for routing signal data between an external interface and an on-chip router within an integrated circuit. [Figure 8] illustrates various embodiments of a system comprising coupled integrated circuits. [Figure 9] shows a block diagram of an example computer-readable medium according to some embodiments.

[0010] While the embodiments described in this disclosure may be subject to various modifications and alternative forms, specific embodiments are presented by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the embodiments to the specific forms disclosed, but are intended to encompass all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims. Implementation

[0011] As described above, a given IC design can be used in a variety of applications with a range of performance and cost considerations. Additionally, reusing existing SOC designs can reduce costs compared to designing, verifying, manufacturing, and evaluating new SOC designs. A technique for scaling a single IC design across a range of applications involves using multiple instances of the IC in applications where performance is more critical than cost, and a single instance of the IC in cost-sensitive applications.

[0012] Utilizing multiple instances of an IC presents several challenges. Some applications and mobile devices, for example, have limited space to accommodate multiple ICs. Furthermore, to reduce latency associated with inter-IC communication, external IC interfaces can include a large number of pins, allowing a large number of bits to be exchanged in parallel between two or more ICs. For example, interfaces for multi-core SoCs may utilize system-wide communication buses with hundreds or even thousands or more parallel-traveling signals. Coupled to two or more of this SoC, interfaces providing access to critical portions of the communication bus may be required, potentially involving hundreds or more pins mounted across two or more dies. Additionally, to match or even approximate the internal communication frequencies of the communication bus, the timing characteristics of the large number of pins on the inter-IC interface must be consistent to avoid different bits of the same data word arriving on different clock cycles. Creating large, high-speed interfaces using a single-pin configuration to couple two or more instances of the same IC die in a small physical space presents a significant challenge for IC designers.

[0013] As will be further explained below, this disclosure describes the use of a "complementary" IC interface. This disclosure recognizes that such IC interfaces support coupling two or more instances of the same IC design in a limited space and provide scalability for the IC design to support a range of applications. This scalable interface may include pin configurations that allow the two ICs to be physically coupled with minimal to no crossover of wiring between them when placed face-to-face or along the common edge of the two dies. To increase the consistency of performance characteristics across the pins of the interface, a single design with a smaller pin count (e.g., sixteen, thirty-two, or similar) can be repeated until the desired pin count is achieved for implementing the interface. This IC interface can enable increased performance by coupling two or more instances of the IC, allowing the IC to be used in a wide range of applications. This interface can further enable two or more ICs to be coupled together in a manner that allows the coupled ICs to be used in mobile applications or other applications where the physical space for multiple ICs is limited.

[0014] When pins with a "complementary function" are positioned such that they have a "complementary layout," the interface between two ICs can be described as "complementary" in the sense of this disclosure. Pins with a "complementary function" are designed to be received by a second pin on another integrated circuit if the first pin on one circuit is designed to receive the data from that second pin on another integrated circuit. Transmission and reception are examples of complementary functions when a transmit pin on one IC that provides an output signal of a specific element of a data word is designed to be coupled to a receive pin on another IC that accepts that specific element of the data word as an input signal. Similarly, a pin carrying a clock signal output can be considered as having a complementary function to an associated pin capable of receiving the clock signal as an input.

[0015] Note that the term "axis of symmetry" is used throughout this disclosure. Various embodiments of the axis of symmetry are shown in Figures 1, 2, 4, 5A, and 5B, and are described below with reference to these figures.

[0016] When pins are positioned relative to the axis of symmetry of an interface such that a first integrated circuit having that interface can be aligned with or coupled to a second instance of that integrated circuit, the pins having complementary functions have a complementary layout. Such pins may also be referred to as being in a "complementary position." An example of a complementary layout would be to position the transmit pins (e.g., bits 0 and 1 of a data bus) on one side of the axis of symmetry at the furthest and second furthest points from the axis, respectively, while placing the complementary receive pins (e.g., bits 0 and 1 of a data bus) on the opposite side of the axis of symmetry at the furthest and second furthest points from the axis. In this embodiment, a first instance of an IC having a complementary interface can be positioned relative to a second instance of an IC having the same inter-IC interface, such that the transmit pins of the first instance are aligned with the receive pins of the second instance, and vice versa. As will be further explained with reference to Figures 5A and 5B, when the perimeters of two identical interfaces are aligned and a straight line perpendicular to the two interfaces can be drawn through the pins of interest, the pins on the two interfaces can be considered "aligned". When the concept of alignment is about the pins of the interface, its relevance to Figures 5A and 5B is further described below.

[0017] This complementary pin layout allows the first and second instances to be coupled via their respective external interfaces without any signal path crossing between the two instances. A pair of interface pins with complementary functions and complementary positions is called a "complementary pin". Transmit and receive pin pairs are used herein to illustrate examples of complementary pins. However, in other embodiments, complementary pins may include bidirectional pin pairs configured such that signals can be transmitted in either direction based on settings of one or more control signals. For example, complementary pins of a data bus may be configurable to transmit or receive data depending on whether the data is being read or written.

[0018] It should be noted that, as referred to herein, an interface can still be considered complementary when only a portion of its complementary pin functions are located in complementary positions. For example, a given inter-IC interface may include pins associated with a plurality of communication buses, such as memory buses, display buses, network buses, and two or more of the like. A given inter-IC interface is considered complementary when pins having complementary functions associated with at least one of the included buses are configured in a complementary layout relative to the axis of symmetry of the given interface. Other buses of the interface and / or other signals not directly related to a particular communication bus may not have pins located in complementary positions.

[0019] It should be noted that the examples described throughout this disclosure refer to the use of two or more ICs of the same design. It is conceivable that ICs of different designs can be coupled using the same external interface with the same physical pin layout. For example, families of different IC designs may include the same external interface design across the family to enable various combinations of instances of two or more ICs. These various combinations can provide highly scalable system solutions across a wide range of applications, allowing, for example, the use of smaller, less expensive members of the family in cost-sensitive applications and the use of more expensive, higher-performance members of the family in performance-focused applications. Members of the family can also be combined with small, low-power members for use in reduced-power modes, and with high-performance members for use when complex procedures and / or many parallel procedures need to be performed.

[0020] In some embodiments, the external interface is physically positioned along one edge of the IC's die. This physical positioning supports various multi-die configurations, such as placing two or more dies on a coplanar surface, including oriented edges of the external interface to be closest to adjacent dies to reduce wiring length when coupling the external interface. In another instance, one die of a pair may be placed face up and the other face down, and then aligned by their respective interfaces. In embodiments comprising only a single IC, positioning the external interface along one edge of the die allows, for example, the external interface to be physically removed during a wafer dicing operation.

[0021] Figure 1 illustrates a block diagram of one embodiment of a system including two instances of ICs coupled via separate external interfaces. As illustrated, system 100 includes integrated circuits 101a and 101b (collectively referred to as integrated circuit 101) coupled via external interfaces 110a and 110b (collectively referred to as external interface 110), respectively. An axis of symmetry 140 is shown as a vertical dashed line perpendicular to and centered on interfaces 110a and 110b. The axis of symmetry provides a reference for the physical layout of pins included in external interface 110, including transmit pins 120a and 120b and receive pins 125a and 125b associated with specific buses. It should be noted that, as shown, the centers of interfaces 110a and 110b are located within integrated circuits 101a and 101b, respectively. However, in other embodiments, the external interfaces may be positioned closer to a specific side of the integrated circuit.

[0022] As shown in the figure, integrated circuit 101a includes an external interface 110a with a physical pin layout having transmit pins 120a and receive pins 125a located at complementary positions 130 relative to the axis of symmetry 140 for a particular bus. Integrated circuit 101a is an IC design that performs any particular function with a limited amount of bandwidth. For example, integrated circuit 101a can be a general-purpose microprocessor or microcontroller, digital signal processor, graphics or audio processor, or other type of system-on-a-chip. In some applications, a single instance of integrated circuit 101 can provide suitable performance bandwidth. In other applications, multiple integrated circuits 101 can be used to increase performance bandwidth. In some applications, multiple integrated circuits 101 can be configured into a single system where the presence of multiple integrated circuits is transparent to the software architecture running on that single system.

[0023] As shown in Figure 1, the receive pin 125b in the external interface 110b is complementary to the transmit pin 120a of the external interface 110a. Therefore, the I / O signal 115a transmitted via the transmit pin 120a and the I / O signal 115a received via the receive pin 125b are common. Similarly, the receive pin 125a in the external interface 110a is complementary to the transmit pin 120b of the external interface 110b. The I / O signal 115b transmitted via the transmit pin 120b is therefore a common signal of the I / O signal 115b received via the receive pin 125a. The I / O signal 115a may, for example, correspond to the data bit 0 of a specific bus in integrated circuits 101a and 101b. Therefore, the I / O signal 115b will also correspond to the data bit 0 of a specific bus in integrated circuits 101a and 101b.

[0024] As illustrated, the complementary pin layout is achieved by placing the transmit pins 120a and receive pins 120a (each pin being the tenth pin from the axis of symmetry 140) in the same order relative to the axis of symmetry 140. In the illustrated embodiment, the transmit pins 120a and receive pins 120a are also shown as being located at a physical distance 135 from the axis of symmetry 140 but on opposite sides. Therefore, two instances of the external interface 110 may be directly coupled to each other. While this physical pin symmetry can facilitate desired pin alignment when the integrated circuit 101b is rotated to a position opposite the integrated circuit 101a, this degree of pin symmetry is not considered a requirement for all embodiments of the complementary interface.

[0025] As illustrated, integrated circuit 101a is coupled to a second instance (integrated circuit 101b). Integrated circuits 101a and 101b are two instances of the same IC, and therefore include the same circuitry, the same features, and, as shown, the same external interface 110. Thus, integrated circuit 101b includes an external interface 110b with a physical pin layout having transmit pins 120b and receive pins 125b located at complementary positions relative to the axis of symmetry 140 for a given input / output (I / O) signal.

[0026] To couple integrated circuit 101, the external interfaces 110 of the first and second instances of integrated circuit 101 are positioned such that the transmit pin 120a and receive pin 125a for I / O signal 115 on integrated circuit 101a are aligned with the receive pin 125b and transmit pin 120b for I / O signal 115 on integrated circuit 101b, respectively. The transmit pin 120a of integrated circuit 101a is physically positioned adjacent to the receive pin 125b of integrated circuit 101b by rotating the die of integrated circuit 101b by 180 degrees and placing the common edges of the two integrated circuits 101 adjacent to each other. Similarly, the receive pin 125a of integrated circuit 101a is physically positioned adjacent to the transmit pin 120b of integrated circuit 101b. As used herein, "adjacent" refers to the physical location of two or more circuit elements configured such that wiring coupling the two elements does not cross wiring of adjacent groups of similar elements. For example, with respect to pins of two external interfaces, adjacent pins indicate that wiring from a given pin of a first instance to a complementary pin of a second instance does not cross wiring used to couple either the adjacent pins of the first instance or the second instance.

[0027] Transmit pin 120a is coupled to receive pin 125b via individual wiring 145, and receive pin 125a is coupled to transmit pin 120b. It should be noted that, as used herein, "wire" refers to any suitable conductive medium that allows signal transfer between the coupled pairs of transmit and receive pins of external interface 110. For example, a wire may correspond to a solder wire attached between transmit pin 120a and receive pin 125b. Additionally, an interposer may be used to couple the pins of external interface 110a to the pins of external interface 110b. In some embodiments, integrated circuit 101a may be flipped and attached face-to-face to integrated circuit 101b with or without an interposer between the two integrated circuit dies.

[0028] Other pins of the external interface 110 can also be configured in similar complementary positions, such that for the transmit pin group of the external interface 110, a complementary group of receive pins positioned in the same order relative to the axis of symmetry 140 is located on the opposite side of the transmit pin group. This arrangement results in a symmetrical pin configuration with complementary functions for pin pairs numbered the same from the axis of symmetry 140 but located on opposite sides; for example, one pin in the pair is a transmit pin and the other is a receive pin.

[0029] Using this complementary pin layout, data is transmitted via integrated circuit 101a, including a portion of the data packet transmitted via transmit pin 120a located at a specific distance from the axis of symmetry 140, and received via integrated circuit 101b via receive pin 125b located at the same specific distance from the axis of symmetry 140. Similarly, the remaining portion of the data packet is transmitted parallel to the first portion via other transmit pins to complementary receive pins positioned equidistant from the axis of symmetry 140. It should be noted that the complementary pin layout also results in wiring 145 connecting external interfaces 110a and 110b being similar in length. This similarity helps facilitate parallel transmission and reception of data packets, thereby reducing skew between different bits of the data packet and between any clock signals used to sample the data packet.

[0030] By utilizing the complementary pin layout described above, external interfaces can be implemented on integrated circuits that allow multiple instances of the integrated circuit to be coupled together in a way that facilitates use in space-constrained applications while meeting the performance requirements of the application. Reusing existing integrated circuits across an expanding range of applications can reduce the design and development costs associated with designing new integrated circuits in other ways to meet the performance requirements of one or more expanding applications.

[0031] It should be noted that system 100 illustrated in FIG1 is merely an example. The illustration in FIG1 has been simplified to emphasize the features relevant to this disclosure. Various embodiments may include different configurations of circuit elements. For example, external interface 110 is shown as having twenty pins. In other embodiments, any suitable number of pins may be included in the external interface, including, for example, more than one thousand pins. Although only two examples of integrated circuits are shown, additional examples are contemplated that may be included in other embodiments. The axis of symmetry 140 is depicted passing through the center of integrated circuits 101a and 101b. In other embodiments, the external interface, and therefore the axis of symmetry, may be positioned off-center from the center of the integrated circuit.

[0032] The integrated circuit illustrated in Figure 1 is shown only with its external interface. Various integrated circuits may include any suitable number of additional circuit blocks. An example of an integrated circuit with additional circuit blocks is shown in Figure 2.

[0033] Turning to Figure 2, a diagram showing an embodiment of an integrated circuit with an external interface is presented. As illustrated, integrated circuit 101 includes an external interface 110 coupled to on-chip routers 240a to 240e, which in turn are coupled to various bus circuits including bus circuits 250, 255, and 258. The various bus circuits are coupled to respective groups of functional circuits 260a to 260f. External interface 110 is shown with a plurality of transmit pins 120 and receive pins 125, and associated transmitter circuits 230 and receiver circuits 235. As shown, integrated circuit 101 corresponds to the IC designs of integrated circuits 101a and 101b in Figure 1.

[0034] As illustrated, bus circuits 250 to 258 are configured to transfer given data among a plurality of functional circuits 260a to 260f (collectively referred to as functional circuits 260). Bus circuits 250, 255, and 258 provide separate communication paths between various groups of functional circuits (including external interface 110 and the respective groups of functional circuits 260). Each of bus circuits 250 to 258 may support the respective group's network protocols and / or specific types of data. For example, bus circuit 258 may be used to transmit graphic data, while bus circuit 250 may support general data, and bus circuit 255 is used for audio data.

[0035] Bus circuits 250, 255, and 258 together form a communication fabric within integrated circuit 101 for transferring data transfers between various functional circuits 260 and additional functional circuits (not shown). For accessing external interface 110, and therefore, for accessing integrated circuit 101 in another instance, each of bus circuits 250 to 258 is coupled to one or more on-chip routers 240, which in turn are coupled to one or more transmitter circuits 230 and receiver circuits 235 included in external interface 110. As shown, on-chip routers 240a and 240d provide different access points to bus circuit 250 and can be physically located at different locations on integrated circuit 101, such as near associated transmitter and receiver circuits. Similarly, on-chip routers 240b and 240c provide different access points to bus circuit 255, and on-chip router 240e provides access points to bus circuit 258.

[0036] As illustrated, a plurality of transmitter circuits 230 in external interface 110 are coupled to specific transmit pin groups 220, and a plurality of receiver circuits 235 are coupled to specific receive pin groups 225. These transmitter circuits 230 and receiver circuits 235 can be physically positioned by their corresponding transmit pin groups 220 and receive pin groups 225. This common positioning of the circuits can reduce the timing skew between the time point at which a given set of transmitter circuits 230 in the first instance of integrated circuit 101 establishes a specific signal level and the later time point at which the corresponding set of receiver circuits in the second instance of integrated circuit 101 receives the established signal level. This timing skew can be increased in IC designs where the transmitter circuits 230 and / or receiver circuits 235 are placed further away from their respective transmit and receive pins.

[0037] A specific transmit pin group 220 is configured in a specific layout relative to the axis of symmetry 140 of the external interface 110. A specific receive pin group 225 is configured in a complementary layout relative to the axis of symmetry 140. Therefore, when two instances of the integrated circuit 101 are placed facing each other, with one instance rotated 180 degrees from the other, a given transmit pin 120 is aligned with the corresponding receive pin 125. The external interface 110 is configured to transfer specific data between bus circuits 250 to 258 and another instance of the integrated circuit 101.

[0038] On-chip router 240 transfers specific data between associated bus circuits 250 to 258 and external interface 110 via a plurality of signals. On-chip router 240 can be configured to queue one or more data packets to be sent to each of the bus circuits 250 to 258 and / or to queue one or more data packets received from each of the respective bus circuits. For example, on-chip router 240a can receive a series of data packets from another instance of integrated circuit 101 via external interface 110. In some embodiments, on-chip router 240a can buffer the series of one or more data packets while waiting for available bandwidth in bus circuit 250 before sending the received data packets. Conversely, on-chip router 240a can also buffer data packets from bus circuit 250 while waiting for bandwidth to send packets to another instance of integrated circuit 101. In other embodiments, the on-chip router 240a may cause functional circuitry 260a or 260b to delay sending data packets until the bandwidth of bus 250 and / or resources in the destination circuitry are available to receive the data packets. Additionally, the on-chip router 240 may include logic circuitry for determining the final destination of received data packets, such as one or more of the functional circuitry 260. In some embodiments, the on-chip router 240 may convert data signals received from external interface 110 using one type of data protocol into a different type of data protocol compatible with the associated bus circuitry.

[0039] As disclosed, integrated circuit 101 includes a plurality of transmitter circuits 230 and a plurality of receiver circuits 235 corresponding to some of a plurality of transmit pins 120 and a plurality of receive pins 125. Transmitter circuits 230 include circuitry for driving data signals to corresponding transmit pins 120. For example, transmitter circuits 230 may include driver circuitry configured to receive a specific voltage level from a signal generated by an associated on-chip router 240, and then generate a corresponding voltage level on the associated transmit pin 120, such that a corresponding receiver circuit 235 in another embodiment of integrated circuit 101 can detect this voltage level. Receiver circuits 235 may, for example, include input circuitry configured to detect that the received voltage level on a corresponding one of the receive pins 125 is higher or lower than a specific voltage threshold, and then generate a corresponding logic level on the signal transmitted to the associated on-chip router 240. As shown in the figure, the transmitter circuit 230 and the receiver circuit 235 are configured with a physical layout relative to the axis of symmetry 140, corresponding to a specific complementary layout.

[0040] The on-chip router 240 includes a pair of on-chip routers (e.g., on-chip routers 240a and 240d) coupled to a common bus circuit (e.g., bus circuit 250). On-chip router 240a is coupled to a specific set of transmit and receive pins on the left side of the axis of symmetry 140 of the external interface 110. On-chip router 240d is coupled to a different set of transmit and receive pins on the right side of the axis of symmetry 140 of the external interface, complementary to the specific set of transmit and receive pins. For example, a given transmit pin 120 coupled to on-chip router 240a has a corresponding complementary receive pin 125 coupled to on-chip router 240d.

[0041] An example of data exchange between a specific functional circuit (e.g., functional circuit 260a) of a first instance of integrated circuit 101 and a different functional circuit (e.g., a second instance of functional circuit 260b) of a second instance of integrated circuit 101 includes the transmission of first data by functional circuit 260a in the first instance via transmit pin group 220 of external interface 110 of the first instance. This transmission includes transmitting a specific signal group to the second instance via external interface 110 using on-chip router 240a. Receiving the first data by the second instance includes receiving the specific signal group by the second instance via receive pin group 225 of on-chip router 240d coupled to the second instance via external interface 110. On-chip router 240d can then route the received first data to the second instance of functional circuit 260b via bus circuit 250 of the second instance.

[0042] Data sent from the functional circuit 260b of the second instance to the functional circuit 260a of the first instance repeats this procedure. The second instance of integrated circuit 101 sends second data via the transmit pin group 220 of the external interface 110 of the second instance, including transmitting different signal groups to the first instance via the external interface 110 using the on-chip router 240a of the second instance. The first instance receives the second data via the receive pin group 225 of the external interface 110 of the first instance, including receiving different signal groups from the second instance via the on-chip router 240d of the first instance via the external interface 110. The received second data is then routed to the functional circuit 260a via the bus circuit 250 of the first instance. Therefore, data can be exchanged between the two instances of integrated circuit 101 using corresponding groups of complementary transmit pins 120 and receive pins 125.

[0043] Furthermore, on-chip router 240a is coupled to on-chip router 240d and transmit pin group 220 via bus circuit 250. Similarly, on-chip router 240d is coupled to receive pin group 225. Therefore, functional circuit 260a in the first embodiment can use the complementary group of on-chip routers 240a and 240d to send and receive data via external interface 110. Functional circuit 260b in the second embodiment can similarly use the complementary group of on-chip routers 240a and 240d in the second embodiment to send and receive data via external interface 110. Therefore, the external interface 110 coupled to the first and second embodiments allows the respective communication structures of the two embodiments to operate as a single coherent communication structure, thereby allowing data packets to be exchanged between functional circuits on opposite dies in a manner similar to the exchange of data packets between two functional circuits on the same die. From a functional point of view, the two embodiments of integrated circuit 101 can be implemented as a single integrated circuit.

[0044] It should be noted that the embodiment in Figure 2 is an example. In other embodiments, different combinations of components may be included. For example, different numbers of bus circuits and / or on-chip routers may be included. Although Figure 2 depicts 26 pins included in the external interface 110, in other embodiments, any suitable number of pins may be included.

[0045] In the descriptions of Figures 1 and 2, the various pin pairs of the external interface 110 are described as complementary. In some embodiments, the bit order of data transmitted across a particular transmit pin group of a first instance of the IC may not be directly aligned with the complementary receive pin group of a second instance of the IC. Figure 3 shows an embodiment of an IC that illustrates how data bit misalignment can be resolved.

[0046] Turning to Figure 3, two examples are shown where integrated circuit 101 is coupled via separate instances of its external interfaces 110. As shown, system 300 depicts an embodiment of misaligned received and transmitted data. System 300 includes integrated circuits 101a and 101b, each having separate external interfaces 110a and 110b and separate pairs of on-chip routers: on-chip routers 340a and 340b in integrated circuit 101a and on-chip routers 340c and 340d on integrated circuit 101b. For the illustrated example, on-chip router 340a of integrated circuit 101a corresponds to on-chip router 340c of integrated circuit 101b. Similarly, on-chip router 340b corresponds to on-chip router 340d. Each of the integrated circuits 101a and 101b further includes one of the interface wrappers 350a and 350b, which are configured to route individual signals between the router and an external interface on the respective chip.

[0047] As illustrated, the transmit and receive pins of external interfaces 110a and 110b are grouped into pin groups comprising individual transmitter and receiver circuitry. These pin groups have a common number of pins, eight in the illustrated example, but any suitable number can be used. This common number of pins can be used to standardize the design of the pin groups. Each pin group may include a common set of signals for controlling clock signals, power, and the like. For example, pins in a given group receive the same gated clock signal and may be coupled to the same gated power node and / or the same gated ground reference node. Using a small number (e.g., one or two) of pins in the design reduces the development time of the external interface and increases the uniformity of pin placement and performance characteristics (e.g., rise and fall times) of external interfaces 110a and 110b. As previously disclosed, although only thirty-two pins are illustrated for each example of external interface 110, external interface 110 may actually include hundreds or thousands of pins. Therefore, standardizing the pin group to be implemented as a unit in the interface design can significantly reduce the time required to design and verify the external interface 110.

[0048] Each of the plurality of on-chip routers 340a to 340d is individually assigned to one or more groups of pin groups. For example, on-chip router 340a is assigned to transmit pin group 320a and receive pin group 325a. Similarly, on-chip routers 340b to 340d are assigned to separate transmit pin groups and separate receive pin groups. In various embodiments, such assignments may be fixed or programmable; for example, pin groups may be assigned by setting specific configuration registers (not shown). It should be noted that in the depicted embodiment, receive and transmit pins are grouped into separate groups. In other embodiments, as will be shown below, pin groups may include transmit and receive pins.

[0049] Additionally, some of the plurality of on-chip routers 340a to 340d are assigned to individual bus circuits and are thus coupled to a plurality of functional circuits included on the same integrated circuit 101. In some embodiments, the physical orientation of the on-chip router 340 may be implemented prior to the specific bus circuit to which the on-chip router is coupled. For example, on-chip routers 340a and 340b may be instantiated such that they are rotated 180 degrees relative to each other to align with a common bus circuit surrounding integrated circuit 101a. In this embodiment, the pins of on-chip router 340b may not be aligned with the receive pin group 325b and / or transmit pin group 320b of external interface 110a. Additionally, interface wrapper 350a may include several instances of the same components instantiated 180 degrees relative to each other. In this case, the transmit and receive pins of interface wrapper 350a may not be aligned with the pins of external interface 110a. Therefore, the ability to reprogram the routing pin signals via the interface wrapper 350a can be expected.

[0050] As shown in the figure, each of the on-chip routers 340a to 340d includes six output signals and six input signals, which differ from the common number (eight) of pins. Therefore, two pins assigned to each pin group 320 and 325 of each on-chip router 340 are unused. Each of the on-chip routers 340a to 340d supports a specific network protocol, as described above in relation to Figure 2. In some cases, such as as shown in Figure 3, a specific network protocol may not include the number of pins aligned with the common number of pins included in the pin group. Because removing additional pins can affect the performance characteristics of the remaining pins (e.g., the parasitic capacitances of the remaining pins may differ, thus affecting rise and fall times), in some embodiments, these irrelevant pins are left in their respective groups.

[0051] As shown, each transmit pin group 320 includes a transmit buffer, and similarly, each receive pin group 325 includes a receive buffer. Since each group includes eight transmit pins or eight receive pins, the respective transmit and receive buffers can be accessed as a byte of data. For example, on-chip router 340a can send data to on-chip router 340d. On-chip router 340a sends six output signals to interface wrapper 350a. Interface wrapper 350a is configured to route transmit pin group 320a to preset pin assignments in on-chip router 340a. As shown, this preset assignment is a pass-through assignment, where bit 0 of transmit pin group 320a is coupled to bit 0 of on-chip router 340a, and so on, bit 5 of transmit pin group 320a is assigned to bit 5 of on-chip router 340a. This bit assignment assumes that bit 0 corresponds to the leftmost pin of the pin group in external interface 110a.

[0052] It should be noted that integrated circuit 101b is rotated 180 degrees relative to integrated circuit 101a. Therefore, bit 0 corresponds to the rightmost pin of the pin group in the external interface 110b. As shown, because wiring 145 directly spans between external interfaces 110 and 110b, bit 0 of transmit pin group 320 is coupled to bit 7 of receive pin group 325d, and similarly, bit 5 of transmit pin group 320a is coupled to bit 2 of receive pin group 325d. Therefore, interface wrapper 350b routes receive pin group 325d to on-chip router 340d using non-preset pin assignments.

[0053] In a similar manner, sending data from on-chip router 340d to on-chip router 340a may include using non-preset pin assignments that route transmit pin group 320d to on-chip router 340d, with the on-chip router 340d sending signals via transmit pin group 320d through external interface 110b. Receiving data from on-chip router 340a via receive pin group 325a through external interface 110a includes using preset pin assignments that route receive pin group 325a to on-chip router 340a.

[0054] In some embodiments, interface wrappers 350a and 350b can adjust routing between a given on-chip router 340 and (a plurality of) transmit and receive pins assigned to pin groups on any given clock cycle during which no data is being transferred by a given on-chip router 340. For example, details of the amount of data can be transmitted between on-chip router 340b and on-chip router 340c. Interface wrapper 350a routes a plurality of signals between on-chip router 340b and transmit pin group 320b for a first portion of specific data using a first pin assignment, and then reroutes a plurality of signals between on-chip router 340b and transmit pin group 320b for a second portion of specific data using a second pin assignment different from the first pin assignment.

[0055] Integrated circuits 101a and 101b, for example, may each include one or more processing cores capable of executing instructions of a specific instruction set architecture. Therefore, instructions of a specific program can cause the cores to modify pin assignments in interface wrappers 350a and / or 350b at specific points in time or for specific types of data. For example, image data can be sent using one pin assignment, and then switched to a different pin assignment for audio data or commands associated with the image data. Additionally, interface wrappers 350a and 350b may be able to re-route pin assignments of different routers on the same IC while an on-chip router is sending or receiving data.

[0056] It should be noted that the example in Figure 3 is for illustrative purposes only. System 300 has been simplified to clearly illustrate the described techniques. In other embodiments, additional transmit and receive pin groups and additional on-chip routers may be included in the external interface. For clarity, other circuit blocks of integrated circuits 101a and 101b have been omitted.

[0057] Figure 3 illustrates how pin groups in an external interface can be implemented and utilized. Various techniques can be used to implement such pin groups. In Figure 3, the pin groups of the external interface are grouped into transmit pin groups, separate from the receive pin groups. Figure 4 illustrates another example of grouping pin groups that include both transmit and receive pins.

[0058] Proceeding to Figure 4, a block diagram of an embodiment of an integrated circuit with an external interface is shown. In the illustrated embodiment, the integrated circuit 101 includes an external interface 410 and on-chip routers 440a to 440d (collectively referred to as on-chip router 440). The external interface 410 includes four bundles 450a to 450d (collectively referred to as bundles 450) whose transmit and receive pins are arranged in a complementary layout relative to the axis of symmetry 140. Each of the illustrated bundles 450a to 450d includes eight pins: four transmit pins and four receive pins.

[0059] As illustrated, the transmit and receive pins of the external interface 410 are grouped into pin groups, bundles 450a to 450d, each bundle 450 having a common number of pins (eight). An on-chip router 440 is assigned to each bundle 450. However, in other embodiments, one or more on-chip routers 440 may be assigned to two or more bundles 450. As described above, the transmit and receive pin groups can be implemented using standardized bundles 450 to increase pin consistency across the external interface 410. Within each bundle 450, the included transmit and receive pins share a common power signal and clock signal.

[0060] Each bundle 450 can be coupled to any suitable power signal and clock signal. As shown, bundles 450a and 450d are coupled to receive power signal 460a and clock signal 465a, while bundles 450b and 450c are coupled to receive power signal 460b and clock signal 465b. In some embodiments, power signal 460a can be controlled independently of power signal 460b, including, for example, using different voltage levels and / or implementing different power gates to enable / disable individual bundles 450. Similarly, clock signal 465a can also be controlled independently of clock signal 465b. The corresponding clock signal 465a can be enabled and / or set to a specific frequency independently of clock signal 465b. In this embodiment, bundles 450a and 450d are a complementary pair, as are bundles 450b and 450c. In addition to using standardized pin bundles to implement each bundle 450, applying common power and clock signals to the complementary pair of bundles 450 can further increase the performance consistency between the two bundles 450 of the complementary pair.

[0061] As shown in the figure, on-chip routers 440a and 440d are assigned to bundles 450a and 450d, respectively. Similarly, on-chip routers 440b and 440c are assigned to bundles 450b and 450c, respectively. On-chip routers 440a and 440d include the same number of transmit and receive pins as those included in the normalized bundles, resulting in no unused pins in bundles 450a and 450d. Conversely, on-chip routers 440b and 440c include fewer transmit and receive pins than the common number included in the normalized bundles, resulting in one unused transmit pin and one unused receive pin in bundles 450b and 450c, respectively.

[0062] As illustrated, on-chip routers 440a and 440d can transmit data packets via bundles 450a and 450d using all the transmit pins of their respective bundles. However, at different times, on-chip routers 440a and 440d can transmit multiple data packets, some of which include a smaller number of bits, resulting in the use of fewer transmit pins than all the transmit pins of each bundle 450. Similarly, when receiving data packets, a given data packet can be received using fewer receive pins than all the receive pins of bundles 450a and 450d.

[0063] It should be noted that Figure 4 is only one example of the disclosed concept. Although four on-chip routers and four pin bundles are shown, other embodiments may include any suitable number. As illustrated, four transmit pins and four receive pins are shown within each pin bundle. In other embodiments, any suitable number of transmit and receive pins may be included. In some embodiments, the number of transmit pins may differ from the number of receive pins. In other embodiments, transmit and receive pins may be implemented in separate bundles.

[0064] In Figures 1 and 3, two integrated circuits are shown coupled via their respective external interfaces. In some embodiments, the two integrated circuits can be placed on a coplanar surface with both ICs facing the same direction and one IC rotated so that the pins of their respective external interfaces are aligned in a manner that allows the pins of the two external interfaces to be coupled without crossing any wiring. In other embodiments, as shown in Figures 5A and 5B, the two ICs can be attached face-to-face with their respective external interfaces aligned. Figure 5B further depicts an example of two dies coupled via misaligned external interfaces.

[0065] Turning now to Figure 5A, two embodiments are depicted where two integrated circuits are attached together via an external interface. In one embodiment, system 500 shows integrated circuit die 501a coupled to integrated circuit die 501b using solder bumps 540. In another embodiment, system 505 shows integrated circuit die 501a coupled to integrated circuit die 501b using an interposer device 530 and two sets of solder bumps 545. In this embodiment, integrated circuit dies 501a and 501b correspond to integrated circuits 101a and 101b in Figure 1.

[0066] As shown in Figure 1, the external interfaces of integrated circuits 101a and 101b can be coupled using wiring (e.g., via solder wire or microstrip conductors deposited on a circuit board), where two dies are placed on coplanar surfaces with their surface faces facing the same direction. This technique enables low-cost assembly solutions but may require a larger surface area of ​​the associated circuit board than the area occupied by the two dies. To reduce this footprint, system 500 includes two integrated circuit dies 501a and 501b placed face-to-face, where the pins of each external interface are aligned with the other and directly soldered to the other using solder bumps 540. For example, transmit pin 120a is directly soldered to receive pin 125b and receive pin 125a is directly soldered to transmit pin 120b. The complementary pin layout described above for the external interface 110 in Figure 1 facilitates this direct soldering between different instances of the same interface. Complementary pairs of pins placed equidistant from the axis of symmetry 140 provide alignment that facilitates direct connection.

[0067] System 505 presents a similar solution to System 500, but incorporates an interposer 530a to provide conductive connections between the external interfaces of the individual dies. In System 505, the transmit pin 120a of the integrated circuit die 501a is soldered to a specific pin of the interposer 530a. This specific pin is then soldered to a receive pin 125b. In a similar manner, the receive pin 125a is soldered to different pins of the interposer 530a, which in turn are soldered to the transmit pin 120b. While the interposer 530a allows pins of the integrated circuit die 501a to be routed to pins of the non-physically aligned integrated circuit die 501b, the complementary pin layout for the external interfaces of the integrated circuit dies 501a and 501b allows the interposer 530a to directly cross conductive paths between the two dies. This direct connection reduces the physical path between the pins of the integrated circuits 501a and 501b compared to routing connections between misaligned pins on the two dies. Using the interposer device 530a may further allow routing of one or more pins or other pins of the external interface of one of the integrated circuit chips 501a and 501b to the interposer device 530, where such pins may be coupled, for example, to the edge of another integrated circuit.

[0068] In Figure 5A, the pins of the external interfaces of integrated circuits 501a and 501b are depicted using complementary pins equidistant from the axis of symmetry 140. In some embodiments, not all pins of the interface may include this equidistant pin layout. Turning now to Figure 5B, two more examples of two coupled ICs are shown. However, the ICs included in systems 510 and 515 do not include pins that are completely equidistant from the axis of symmetry.

[0069] As illustrated, system 510 demonstrates an example of an external interface including complementary pins. Similar to integrated circuit chips 501a and 501b, integrated circuit chips 502a and 502b are two examples of the same integrated circuit design coupled through a common external interface design. The pins of the external interface of integrated circuit chips 502a and 502b include transmit and receive pins for two buses (bus 560 and bus 565). The pins of bus 565 are divided into two segments per chip: buses 565a and 565b on integrated circuit chip 502a and buses 565c and 565d on integrated circuit chip 502b. Each chip also includes individual pins for bus 560 (560a on integrated circuit chip 502a and 560b on integrated circuit chip 502b). The complementary pins of buses 565a and 565d are not equidistant from the axis of symmetry 140, and although the pins are arranged in the same order, a straight line parallel to the edge of the die cannot be drawn through the pins of buses 565a and 565d, similar to the pins of buses 565b and 565c. Therefore, the pins of bus 565 are misaligned.

[0070] As shown in the figure, the complementary pins of bus 560a are not configured to be equidistant from the axis of symmetry 140. However, unlike the pins of bus 565, lines parallel to the edge of the die can be drawn across the complementary pin pairs of buses 560a and 560b. Therefore, the pins of bus 560 are aligned.

[0071] As presented, system 515 illustrates an example of non-complementary external interfaces. Similar to system 510, system 515 includes two instances of the same integrated circuit design, integrated circuit dies 503a and 503b. In system 515, the pins of the external interfaces are misaligned, and therefore, multiple signal paths intersect. For example, the signal path between transmit pin 120a and receive pin 125b intersects with paths from transmit pin 121a and receive pin 126b. On opposite sides of axis of symmetry 140, the signal path between transmit pin 120b and receive pin 125a intersects with paths from transmit pin 121b and receive pin 126a. Due to this misalignment, integrated circuits 503a and 503b are not considered to have complementary interfaces.

[0072] It should be noted that alignment of complementary pins on the external interface can reduce noise coupling between adjacent signals. When two or more signal paths intersect, the wiring of the carrying signals may be close, which can increase the susceptibility of the first signal path to noise coupling from electromagnetic interference from signal transitions on the second signal path. The closer the two signal paths are, the greater the susceptibility to noise transmitted between them. By aligning the pins of the interface, a suitable distance can be maintained between adjacent signal paths, thereby reducing noise susceptibility to an acceptable level. Aligned pin layout can further reduce the length of the signal path through the interposer, which can reduce the impedance between complementary pin pairs, allowing the system to operate at lower voltage levels and / or higher clock frequencies.

[0073] It should be further noted that the examples in Figures 5A and 5B are for illustrative purposes only. Other techniques for coupling two or more IC chips are envisioned. For example, in some embodiments, the pins for each of the two or more IC chips can be directly coupled to the circuit board with the connection route between the chips passing through the circuit board.

[0074] The circuits and techniques described above in relation to Figures 1 through 5 can be used to couple two external interfaces in various ways. Two methods for associating with the coupled interfaces are described below in relation to Figures 6 and 7.

[0075] Turning now to Figure 6, a flowchart illustrates an embodiment of a method for coupling two integrated circuits together. Method 600 can be performed by a system comprising two or more instances of integrated circuits (such as system 100 in Figure 1). Referring together to Figures 1 and 6, method 600 begins at block 610.

[0076] In block 610, method 600 includes transmitting first data from integrated circuit 101a to integrated circuit 101b via a transmission pin group of external interface 110a. As shown, integrated circuits 101a and 101b are two instances of a common integrated circuit design. Therefore, the physical pin layout of the two instances is the same. However, in other embodiments, it is contemplated that separate instances of two different integrated circuits may be used. In FIG. 1, the transmission pins of external interface 110a of integrated circuit 101a are coupled to separate receive pins of external interface 110b of integrated circuit 101b, including transmission pin 120a coupled to receive pin 125b. Therefore, integrated circuit 101a can use external interface 110a to transmit first data to integrated circuit 101b.

[0077] In block 620, method 600 further includes receiving second data from integrated circuit 101b via a set of receive pins of external interface 110a. As illustrated, the receive pins of external interface 110a are coupled to individual receive pins of external interface 110b, including receive pin 125a coupled to transmit pin 120b. The transmit pin set and the receive pin set are located at complementary positions relative to the axis of symmetry 140 of integrated circuit 101. Therefore, transmit pins 120a and 120b correspond to the same transmit pins in a common integrated circuit design. Similarly, receive pins 125a and 125b correspond to the same receive pins in a common integrated circuit design. This complementary pin layout of the external interfaces relative to the axis of symmetry 140 allows two instances of the common integrated circuit design to be coupled via their respective external interfaces without needing to reroute any pins of the external interfaces. Instead, a direct connection between external interfaces 110a and 110b is feasible without crossing any associated wiring. This technique, used for two instances of coupling common integrated circuits, allows for external interfaces with a large number of pins (e.g., more than one thousand pins).

[0078] In some embodiments, method 600 may end at block 620, or in other embodiments, it may be repeated in response to new data to be exchanged between the two integrated circuits 101a and 101b. It should be noted that the method of FIG6 is merely an example for coupling two integrated circuits.

[0079] Turning now to Figure 7, a flowchart illustrates an embodiment of a method for routing signals between pins of an external interface and one or more on-chip routers. In a similar manner to method 600 described above, method 700 can be implemented by a system having two or more integrated circuits (such as system 300 in Figure 3). Referring together to Figures 3 and 7, method 700 begins at block 710.

[0080] In block 710, method 700 includes routing a transmission pin group 320b to an on-chip router 340b using non-preset pin assignments by integrated circuit 101a to transmit first data via the transmission pin group 320a. As shown in FIG3, integrated circuit 101a includes an interface wrapper 350a configured to route signals from on-chip routers 340a and 340b to respective transmission and reception pin groups in external interface 110a. Interface wrapper 350a may use preset pin assignments for routing transmission pin group 320b to output signals from on-chip router 340b. However, in some cases, interface wrapper 350a may be configured to reroute output signals from on-chip router 340b to transmission pin group 320b using non-preset pin assignments. For example, as shown in FIG3, on-chip router 340b has fewer output signals than the number of transmission pins included in transmission pin group 320b. Non-preset pin assignments can be used to adjust where individual bits of the first data are received by the integrated circuit 101b.

[0081] In block 720, method 700 includes routing receive pin group 325a to on-chip router 340a via receive pin group 325a using preset pin assignments by integrated circuit 101a. As illustrated, in some cases, interface wrapper 350a may be further configured to use preset pin assignments to couple receive pin group 325a to on-chip router 340a, for example, when interface wrapper 350b in integrated circuit 101b uses non-preset pin assignments to re-routing pin assignments such that individual bits of the second data arrive in the desired order before the second data is sent from transmit pin group 320d in external interface 110b.

[0082] Such use of preset and non-preset pin assignments increases the flexibility of the external interface of two integrated circuits coupled together. By allowing signals to be rerouted between the external interface and the on-chip router, signal consistency across the two external interfaces can be increased compared to rerouting signals via wiring between the two external interfaces. Additionally, the programmable routing capability of the interface wrapper increases the flexibility of the external interface, potentially allowing the external interface to be used for an increased number of data types to be transferred between integrated circuits without requiring preprocessing of the data to place the transferred data bits in the appropriate bit positions before sending or post-processing the received data.

[0083] It should be noted that the method of Figure 7 is merely an example for routing data between an on-chip router and an external interface. Method 700 can be performed by any example of the integrated circuitry shown in Figures 1 through 5. Variations of the disclosed methods are contemplated, including combinations of the operations of methods 600 and 700. For example, block 710 of method 700 may be executed before block 610 of method 600, and block 720 may be executed before block 620 of method 600.

[0084] Figures 1 through 7 illustrate apparatus and methods for systems that include external interfaces coupling two or more integrated circuits using complementary pin layouts. Any embodiment of the disclosed system may be included in one or more of various computer systems, such as desktop computers, laptops, smartphones, tablets, wearable devices, and the like. In some embodiments, the circuitry described above may be implemented on a system-on-a-chip (SoC) or other types of integrated circuitry. A block diagram illustrating an embodiment of computer system 800 is shown in Figure 8. In some embodiments, computer system 800 may include any of the disclosed embodiments of systems 100, 300, 500, and 505.

[0085] In the illustrated embodiments, system 800 includes at least one instance of a system-on-a-chip (SoC) 806, which may include various types of processing circuitry, such as a central processing unit (CPU), a graphics processing unit (GPU), or otherwise including a communication mesh, and interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 806 include multiple execution channels and instruction dispatch queues. In various embodiments, SoC 806 is coupled to external memory 802, peripheral devices 804, and a power supply 808.

[0086] A power supply 808 is also provided, which supplies supply voltage to the SoC 806 and one or more supply voltages to memory 802 and / or peripheral devices 804. In various embodiments, the power supply 808 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet, or other device). In some embodiments, it includes more than one example of the SoC 806 (and also includes more than one external memory 802).

[0087] The 802 series of memory modules can be any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3, and / or low-power versions of SDRAM such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the devices are mounted using a SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0088] Peripheral device 804 may include any desired circuitry depending on the type of system 800. For example, in one embodiment, peripheral device 804 may include means for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, GPS, etc. In some embodiments, peripheral device 804 may also include additional storage, including RAM, solid-state storage, or hard disk storage. Peripheral device 804 may include user interface devices, such as a display screen (including a touch screen or multi-touch screen), a keyboard, or other input devices, a microphone, a speaker, etc.

[0089] As illustrated, system 800 is shown to have applications in a wide range of fields. For example, system 800 can be used as part of a desktop computer 810, laptop computer 820, tablet computer 830, cellular or mobile phone 840, or television 850 (or a set-top box coupled to a television). A smartwatch and health monitoring device 860 are also illustrated. In some embodiments, the smartwatch may include a variety of general computing-related functions. For example, the smartwatch may provide access to email, telephone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality. For example, the health monitoring device may monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, perform contact tracing, provide communication with emergency services in the event of a health crisis, etc. In various embodiments, the smartwatch mentioned above may or may not include some or any of the health monitoring-related functions. Other wearable devices 870 are also envisioned, such as devices worn around the neck, devices attached to hats or other headgear, devices implanted in the human body, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0090] System 800 can be further used as part of (various) cloud-based services 880. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remote hardware and / or software resources). Figure 8 also illustrates the application of system 800 to various modes of transportation 890. For example, system 800 can be used in the control and / or entertainment systems of aircraft, trains, buses, taxis, private cars, surface vessels from private boats to cruise ships, locomotives (for leasing or ownership), etc. In various cases, system 800 can be used to provide automated navigation (e.g., autonomous vehicles), general system control, and others.

[0091] It should be noted that the diverse range of potential applications for System 800 can include various performance, cost, and power consumption requirements. Therefore, scalable solutions that utilize one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption can be advantageous. These and many other embodiments are feasible and contemplated. It should be noted that the devices and applications illustrated in Figure 8 are illustrative only and are not intended to be limiting. Other devices are feasible and envisioned.

[0092] As illustrated in Figure 8, computer system 800 may include two or more integrated circuits coupled together and included within a personal computer, smartphone, tablet computer, or other type of computing device. The procedure for designing and manufacturing integrated circuits using design information, as shown in Figure 9, is presented below.

[0093] Figure 9 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. The embodiments of Figure 9 can be used in a program to design and manufacture integrated circuits (such as, for example, integrated circuits 101a and 101b shown in the various figures). In the illustrated embodiment, a semiconductor manufacturing system 920 is configured to process design information 915 stored on a non-transitory computer-readable storage medium 910 and manufacture an integrated circuit 930 (e.g., integrated circuit 101) based on the design information 915.

[0094] The non-transitory computer-readable storage medium 910 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 910 may be installation media (e.g., CD-ROM, floppy disk, or magnetic tape device); computer system memory or random access memory (such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.); a non-volatile memory (such as flash memory, magnetic media (e.g., hard disk), or optical storage); a scratchpad or other similar type of memory element. The non-transitory computer-readable storage medium 910 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 910 may include two or more memory media that can reside in different locations (e.g., in different computer systems connected via a network).

[0095] Design information 915 may be specified using any of a variety of suitable computer languages ​​(including hardware description languages), such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 915 may be used by semiconductor manufacturing system 920 to manufacture at least a portion of integrated circuit 930. For example, the format of design information 915 may be recognizable by at least one semiconductor manufacturing system (such as semiconductor manufacturing system 920). In some embodiments, design information 915 may include a wiring lookup table specifying elements of a cell library and their interconnections. One or more cell libraries used during the logic synthesis of circuits included in integrated circuit 930 may also be included in design information 915. Such cell libraries may include device or transistor level wiring lookup tables indicating the circuit elements included in the cell library, masking design data, characterization data, and similar information.

[0096] In various embodiments, the integrated circuit 930 may include one or more custom macro elements, such as memory, analog or mixed-signal circuitry, and the like. In such cases, design information 915 may include information relating to the included macro elements. This information may include, without limitation, a schematic capture database, masking design data, behavioral models, and device or transistor hierarchy lookup tables. As used herein, masking design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0097] The semiconductor manufacturing system 920 may include any of a variety of suitable elements configured to manufacture integrated circuits. For example, this may include elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet light treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 920 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0098] In various embodiments, integrated circuit 930 is configured to operate according to a circuit design specified by design information 915, and may include any of the functionalities performed as described herein. For example, integrated circuit 930 may include any of the various elements shown or described herein. Furthermore, integrated circuit 930 may be configured to perform the various functions described herein in conjunction with other components. Furthermore, the functionalities described herein may be performed by a plurality of interconnected integrated circuits (such as integrated circuits 101a and 101b in Figures 1 and 3).

[0099] As used herein, phrases in the form of "design information specifying a circuit configured to..." do not imply that the circuit in question must be manufactured to satisfy that element. Rather, this phrase indicates that a circuit described in the design information, once manufactured, will be configured to perform the indicated action or will include the specified components. ***

[0100] This disclosure includes references to "embodiments" of non-limiting embodiments of the concepts disclosed. References to "an embodiment," "one embodiment," "a particular embodiment," "some embodiments," "various embodiments," and the like do not necessarily refer to the same embodiment. A large number of feasible embodiments are contemplated, including the detailed embodiments described herein, as well as modifications or alternatives falling within the spirit or scope of this disclosure. Not all embodiments will necessarily exhibit any or all of the potential advantages described herein.

[0101] Unless otherwise stated, the specific embodiments are not intended to limit the scope of the claims drafted based on this disclosure to the disclosed forms, even if only a single instance relates to a particular feature description. The disclosed embodiments are therefore intended to be illustrative rather than restrictive, and there is no statement to the contrary. This application is intended to cover such alternatives, modifications, and equivalents that would be obvious to those skilled in the art to which this disclosure pertains.

[0102] Any particular feature, structure, or characteristic may be combined in any suitable manner consistent with this disclosure. Therefore, this disclosure is intended to include any feature or combination of features disclosed herein (express or implied), or any generalization thereof. Accordingly, during the examination of this application (or the application claiming priority), a new claim may be made for any such combination of features. Specifically, referring to the claims of the appended patent application, features from subsidiary claims and features from independent claims may be combined, and features from individual independent claims may be combined in any suitable manner, not merely the specific combinations listed in the claims of the appended patent application.

[0103] For example, while accompanying subsidiary claims are drafted such that each depends on a single other claim, additional dependencies are also envisioned, including: claim 3 (which may depend on any one of claims 1 to 2); claim 4 (any one of the aforementioned claims); claim 5 (claim 4), etc. Where appropriate, it is also envisioned that a claim drafted for one statutory type (e.g., equipment) may suggest a corresponding claim for another statutory type (e.g., method). ***

[0104] Because this disclosure is a legal document, all terms and phrases used are subject to administrative and judicial interpretation. The following paragraphs and the definitions provided throughout this disclosure are intended to determine how to interpret the scope of any patent application drafted based on this disclosure.

[0105] Unless the context explicitly states otherwise, references to the singular forms (such as "a," "an," or "the") are intended to refer to "one or more." Therefore, mentioning "an item" in a request does not exclude additional instances of that item.

[0106] In this article, the word "may" is used in the sense of permission (i.e., having the possibility or ability to) and not in the sense of mandatory (i.e., being required to).

[0107] The terms “comprising” and “including” and their forms are open-ended, meaning “including, but not limited to”.

[0108] When the term "or" is used in this disclosure with respect to a list of options, it is generally understood to be used in an inclusive sense, unless the context otherwise provides. Therefore, the statement "x or y" is equivalent to "x or y, or both," which includes x but not y, y but not x, and both x and y. On the other hand, expressions such as "either x or y, but not both" clearly indicate that "or" is used in an exclusive sense.

[0109] The statement "w, x, y, or z, or any combination thereof" or "...w, x, y, and z at least one of ... w, x, y, and z" is intended to cover all possibilities involving a single element or at most a total number of elements in the group. For example, given the group [w, x, y, z], these phrases cover any single element of the group (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Therefore, the phrase "...w, x, y, and z" refers to at least one of the elements in the group [w, x, y, z], thus encompassing all possible combinations in this option list. This phrase is not interpreted as requiring at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0110] In this disclosure, various "labels" may precede nouns. Unless the context otherwise provides, different labels used for a feature (e.g., "first circuit," "second circuit," "specific circuit," "given circuit," etc.) refer to different instances of that feature. Unless otherwise stated, the labels "first," "second," and "third," when applied to a particular feature, do not imply any type of order (e.g., spatial, temporal, logical, etc.).

[0111] In this disclosure, different entities (which may be referred to differently as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This notation ("entity" configured to "perform one or more tasks") is used herein to refer to a structure (i.e., a physical object). Specifically, this notation indicates that the structure is configured to perform the one or more tasks during operation. Even if a structure is not currently being operated, it may still be said that the structure is "configured to" perform a task. Therefore, an entity described or stated as being "configured to" perform a task refers to a physical object, such as a device, circuit, or memory storing program instructions executable to perform that task. This term is not used herein to refer to intangible objects.

[0112] Hardware circuitry may include any combination of the following: combinational logic circuit systems, time-controlled storage devices (such as flip-flops, registers, latches, etc.), finite state machines, memory (such as static random access memory or embedded dynamic random access memory), custom-designed circuit systems, analog circuit systems, programmable logic arrays, etc. Similarly, for ease of description, various units / circuits / components may be described as performing one or more tasks. This description should be interpreted as including the phrase "configured to".

[0113] In one embodiment, the hardware circuitry according to this disclosure can be implemented by encoding a description of the circuitry in a hardware description language (HDL) such as Verilog or VHDL. The HDL description can be synthesized based on a component library designed for a given integrated circuitry manufacturing technique and can be modified for timing, power, and other reasons to produce a final design database, which can be sent to a manufacturing plant to create a mask, ultimately producing the integrated circuitry. Some hardware circuitry or portions thereof can also be customized in a schematic editor and transferred to the integrated circuitry design along with the synthesized circuitry system. The integrated circuitry may include transistors and may further include other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnections between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some embodiments. Alternatively, HDL designs can be synthesized into a programmable logic array, such as a field-programmable gate array (FPGA), and implemented within the FPGA.

[0114] The term "configured to" does not necessarily mean "configurable to". For example, an unprogrammed FPGA will not be considered "configured to" performing a specific function. However, this unprogrammed FPGA may be "configurable to" performing that function.

[0115] A clear intent to describe a structure “configured to” perform one or more tasks in the claims of an accompanying patent application does not invoke 35 USC § 112(f) for the claim element. If the applicant intends to invoke section 112(f) during examination, the claim element will be described using the phrase “a component for ‘performing a function’”.

[0116] The term "based on" is used to describe one or more factors that influence a decision. This term does not exclude the possibility that additional factors may influence the decision. That is, a decision may be based solely on a particular factor, or on such a particular factor and other unspecified factors. Consider the term "determine A based on B." This term indicates that B is a factor used to determine A, or that B influences the decision of A. This term does not exclude the possibility that A may also be determined based on other factors such as C. This term is also intended to encompass an embodiment where A is determined solely based on B. As used herein, the term "based on" is synonymous with the term "based at least in part on."

[0117] The phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, an effect may be a response to the stated factor alone, or it may be a response to the stated factor and other unstated factors. Consider the phrase "perform A in response to B." This phrase indicates that B is a factor that triggers the execution of A. This phrase does not exclude the possibility that A may also be performed in response to other factors (such as C). This phrase is also intended to encompass an embodiment where A is performed in response to B alone.

[0118] 100: System 101: Integrated Circuits 101a: Integrated Circuits 101b: Integrated Circuits 110: External Interface 110a: External interface; Interface 110b: External Interface; Interface 115:I / O signal 115a: I / O signal 115b: I / O signals 120: Transmission pin 120a: Transmission pin 120b: Transmission pin 121a: Transmission pin 121b: Transmission pin 125: Receive pin 125a: Receive pin 125b: Receive pin 126a: Receive pin 126b: Receive pin 130: Complementary Positions 135: Entity Distance 140: Axis of symmetry 145: Wiring 220: Transmission Pin Group 225: Receive Pin Group 230: Transmitter Circuit 235: Receiver Circuit 240: On-chip router 240a: On-Chip Router 240b: On-Chip Router 240c: On-Chip Router 240d: On-Chip Router 240e: On-Chip Router 250: Bus circuit; Bus 255: Bus circuit 258: Bus circuit 260: Functional Circuit 260a: Functional Circuit 260b: Functional Circuit 260c: Functional Circuit 260d: Functional Circuit 260e: Functional Circuit 260f: Functional Circuit 300: System 320: Transmission pin group; pin group 320a: Transmission Pin Group 320b: Transmission Pin Group 320d: Transmission pin group 325: Receive pin group; pin group 325a: Receive Pin Group 325b: Receive Pin Group 325d: Receive pin group 340: On-Chip Router 340a: On-Chip Router 340b: On-Chip Router 340c: On-Chip Router 340d: On-Chip Router 350a: Interface Packaging 350b: Interface Packaging 410: External Interface 440: On-Chip Router 440a: On-Chip Router 440b: On-Chip Router 440c: On-Chip Router 440d: On-Chip Router 450: bundle 450a: bundle 450b: bundle 450c: bundle 450d: bundle 460a: Power signal 460b: Power signal 465a: Clock signal 465b: Clock signal 500: System 501a: Integrated circuit die; integrated circuit 501b: Integrated circuit die; integrated circuit 502a: Integrated circuit die 502b: Integrated circuit die 503a: Integrated circuit die; integrated circuit 503b: Integrated circuit die; integrated circuit 505: System 510: System 515: System 530: Intermediate Layer Device 530a: Intermediate layer device 540: Solder bump 545: Solder bump 560: Bus 560a: Busbar 560b: Busbar 565: Busbar 565a: Busbar 565b: Busbar 565c: Busbar 565d: Busbar 600: Method 610: Square 620: Square 700: Method 710: Square 720: Square 800: Computer system; system 802: Memory 804: Peripheral Devices 806: System-on-a-Chip (SoC); SoC 808: Power Supply 810: Desktop computer 820: Laptop 830: Tablet PC 840: Cellular or mobile phone 850: Television 860: Smartwatches and health monitoring devices 870: Wearable devices 880: Cloud-based services 890: Transportation Mode 910: Non-transitory computer-readable storage media 915: Design Information 920: Semiconductor Manufacturing System 930: Integrated Circuits

Claims

1. A system for transmitting and receiving data, comprising: an integrated circuit (IC) die, comprising: A plurality of circuit blocks configured to send and receive data transactions; a plurality of on-chip router circuits configured to transfer data transactions between the plurality of circuit blocks in the IC die; a die-to-die interface including a plurality of pins and configured to provide an access point to a different IC die; and an interface wrapper circuit coupled to the die-to-die interface and the plurality of on-chip router circuits, the interface wrapper circuit being configured to: route signals between the die-to-die interface and the plurality of on-chip router circuits based on a first pin assignment in a first clock cycle; and route signals between the die-to-die interface and the plurality of on-chip router circuits based on a second pin assignment in a second clock cycle.

2. The system of claim 1, wherein the plurality of pins in the die-to-die interface are grouped into a plurality of pin bundles, and wherein one of the plurality of on-chip router circuits is coupled to one or more of the plurality of pin bundles.

3. The system of claim 2, wherein the router circuitry on the given chip is coupled to a first pin bundle including one of a set of transmit pins and a second pin bundle including one of a set of receive pins.

4. The system of claim 2, wherein the difference between the first pin assignment and the second pin assignment includes modifying the pin assignment within each of the plurality of pin bundles.

5. The system of claim 2, wherein a first portion of one of the plurality of pin bundles includes a common number of transmit pins, and a second portion of one of the plurality of pin bundles includes a common number of receive pins.

6. The system of claim 5, wherein the first portion of the pin bundle includes a respective transmit buffer, and the second portion of the pin bundle includes a respective receive buffer.

7. The system of claim 1, wherein the plurality of pins in the die-to-die interface are grouped into a plurality of pin bundles, wherein a first of the plurality of pin bundles receives a first power signal having a first voltage level and a second of the plurality of pin bundles receives a second power signal having a second voltage level different from the first voltage level.

8. The system of claim 7, wherein a particular circuit block of the plurality of circuit blocks is configured to independently control (gate) the first power signal and the second power signal.

9. The system of claim 1, wherein the plurality of pins in the die-to-die interface are grouped into a plurality of pin bundles, one of the plurality of pin bundles receiving a clock signal having a frequency different from a clock signal received by at least one other pin bundle.

10. A method for transmitting and receiving data, comprising: receiving a plurality of signals from a die-to-die interface circuit on an integrated circuit (IC) die via an interface wrapper circuit included in an integrated circuit (IC) die; routing the received signals to a plurality of on-chip router circuits included on the IC die via the interface wrapper circuit based on a first routing assignment; receiving a second routing assignment different from the first routing assignment via the interface wrapper circuit from a processor circuit on the IC die; and routing subsequently received signals to the plurality of on-chip router circuits via the interface wrapper circuit based on the second routing assignment.

11. The method of claim 10, further comprising: transmitting a first set of signals to a first of the plurality of on-chip router circuits via a first pin bundle of a plurality of pin bundles included in the die-to-die interface circuit; and transmitting a second set of signals to a second of the plurality of on-chip router circuits via a second pin bundle of the plurality of pin bundles.

12. The method of request item 11 further includes: modifying one of the assignments of the first pin bundle based on the second routing assignment, but not modifying one of the assignments of the second pin bundle.

13. The method of claim 11, further comprising: receiving a third set of signals from the router circuit on the first chip via a third pin bundle of the plurality of pin bundles; and receiving a fourth set of signals from the router circuit on the second chip via a fourth pin bundle of the plurality of pin bundles.

14. The method of claim 11, further comprising: disabling a first power signal received by the first pin bundle; and enabling a second power signal received by the second pin bundle.

15. An apparatus for transmitting and receiving data, comprising: an integrated circuit (IC) die, comprising: A plurality of circuit blocks configured to transmit and receive data transfers; a plurality of on-chip router circuits configured to transfer data transfers between the plurality of circuit blocks in the IC die; and a die-to-die interface comprising a plurality of pins and configured to provide an access point to a different IC die, wherein the plurality of pins are grouped into a plurality of pin bundles; and wherein some of the plurality of on-chip router circuits are coupled to some of the plurality of pin bundles.

16. The device of claim 15, wherein one of the plurality of on-chip router circuits is coupled to a first and a second of the plurality of pin bundles and a second pin bundle, the first and the second of the plurality of pin bundles including a set of transmit pins and the second pin bundle including a set of receive pins.

17. The device of claim 15, wherein a first portion of one of the plurality of pin bundles is implemented as a common transmit pin bundle design including a common number of transmit pins, and a second portion of one of the plurality of pin bundles is implemented as a common receive pin bundle design including a common number of receive pins.

18. The device of claim 17, wherein the first portion of the pin bundle includes a respective transmit buffer, and the second portion of the pin bundle includes a respective receive buffer.

19. The device of claim 15, wherein a first of the plurality of pin bundles receives a first power signal having a first voltage level, and a second of the plurality of pin bundles receives a second power signal having a second voltage level different from the first voltage level; and wherein a particular circuit block of the plurality of circuit blocks is configured to independently control the first power signal and the second power signal.

20. The device of claim 15, further comprising an interface wrapper coupled between a die-to-die interface and the plurality of on-chip router circuits; and wherein a particular circuit block of the plurality of circuit blocks is configured such that the interface wrapper modifies a pin assignment between the plurality of on-chip router circuits and the die-to-die interface.

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