Defect presentation method for semiconductor device and defect analysis system

Abstract

A defect presentation method and defect analysis system for a semiconductor device. The defect presentation method includes: dividing the semiconductor device into multiple blocks; obtaining multiple defects in the semiconductor device and counting failure bits based on defect counts; determining whether the number of failure bits is greater than a preset value, classifying the defects in the semiconductor device into failure types based on different total counts, generating multiple failure type maps corresponding to the failure types as failure data; and integrating the failure data to generate a wafer defect map. Each block in the wafer defect map includes multiple sub-blocks. Each sub-block corresponds to a failure type. The sub-blocks are distinguished and presented with different colors. Each sub-block presents the corresponding number of defects for the corresponding failure type.

Claims

1. A method for presenting defects in a semiconductor device, comprising: The semiconductor device is divided into a plurality of first blocks, wherein the first blocks in the semiconductor device correspond to a plurality of second blocks in the wafer defect map; Multiple defects in the semiconductor device are obtained, and the number of failure bits in the semiconductor device is counted based on the defects; it is determined whether the number of failure bits in the semiconductor device is greater than a preset value, and the defects in the semiconductor device are classified according to failure types with different total numbers, and multiple failure type maps corresponding to the failure types are generated as failure data. The method integrates the failure data to generate the wafer defect map and displays the wafer defect map using a display device. Each second block in the wafer defect map includes multiple sub-blocks, each sub-block corresponding to the failure type. The sub-blocks are distinguished and presented with different colors, and each sub-block presents the corresponding number of defects of the corresponding failure type.

2. The defect presentation method as described in claim 1, wherein, The step of classifying the defects in the semiconductor device based on different total numbers of the failure types includes: when the number of failure bits is less than the preset value, classifying the defects in the semiconductor device based on multiple first failure types to generate multiple first failure type maps corresponding to the first failure types as failure data; and when the number of failure bits is greater than or equal to the preset value, classifying the defects in the semiconductor device based on multiple second failure types to generate multiple second failure type maps corresponding to the second failure types as failure data, wherein the total number of the first failure types is less than the total number of the second failure types.

3. The defect presentation method as described in claim 1, wherein, The step of classifying the defects in the semiconductor device includes: classifying the defects based on the spatial correlation patterns between the defects on each first block of the semiconductor device to generate the failure data.

4. The defect presentation method as claimed in claim 1, wherein the failure type map in the failure data includes multiple region locations where the failure type appears on the wafer defect map, and the corresponding number of defects of the failure type appearing in each region location.

5. The defect presentation method as described in claim 1 further includes: In the wafer defect map, one or more of the sub-blocks in each second block are selectively shown or hidden.

6. The defect presentation method as described in claim 1, wherein the preset value is generated based on the statistical distribution of the number of historical failed bits of the semiconductor device, or the preset value is generated based on one or a combination of the data storage capacity, the number of bit lines and the number of word lines in the semiconductor device, wherein the preset value is dynamically adjusted according to the machine operation time of the semiconductor device.

7. A defect analysis system, comprising: processor; The processor is coupled to a display device and wherein the processor is configured to: divide a semiconductor device into a plurality of first blocks, wherein the first blocks in the semiconductor device correspond to a plurality of second blocks of a wafer defect map; obtain a plurality of defects in the semiconductor device and count the number of failure bits in the semiconductor device based on the defects; determine whether the number of failure bits in the semiconductor device is greater than a preset value, classify the defects in the semiconductor device based on different failure types with different total counts, and generate a plurality of failure type maps corresponding to the failure types as failure data; The method integrates the failure data to generate the wafer defect map and displays the wafer defect map using the display device. Each second block in the wafer defect map includes multiple sub-blocks, each sub-block corresponding to the failure type. The sub-blocks are distinguished and presented with different colors, and each sub-block presents the corresponding number of defects of the corresponding failure type.

8. The defect analysis system as described in claim 7, wherein, When the number of failure bits is less than the preset value, the processor classifies the defects in the semiconductor device based on multiple first failure types to generate multiple first failure type maps corresponding to the first failure types as failure data. When the number of failure bits is greater than or equal to the preset value, the processor classifies the defects in the semiconductor device based on multiple second failure types to generate multiple second failure type maps corresponding to the second failure types as failure data, wherein the total number of the first failure types is less than the total number of the second failure types.

9. The defect analysis system of claim 7, wherein the processor classifies the defects based on the spatial correlation patterns between the defects on various first blocks of the semiconductor device to generate the failure data.

10. The defect analysis system of claim 7, wherein the failure type map in the failure data includes multiple region locations where the failure type appears on the wafer defect map, and the corresponding number of defects of the failure type appearing in each region location.

11. The defect analysis system as claimed in claim 7, wherein the processor selectively presents or hides one or more of the sub-blocks in the respective second blocks via user input in the wafer defect map.

12. The defect analysis system as claimed in claim 7, wherein the preset value is generated based on the statistical distribution of the number of historical failed bits of the semiconductor device, or the preset value is generated based on one or a combination of the data storage capacity, the number of bit lines and the number of word lines in the semiconductor device, wherein the preset value is dynamically adjusted according to the machine operation time of the semiconductor device.

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