Network transceiver device with vga channel specific equalization and related signal processing method

Abstract

A network transceiver device is provided, comprising at least two variable gain amplifiers (VGAs) and at least two sets of analog-to-digital converters (ADCs), each set of ADCs including an ADC coupled to the output of one of the VGAs, the sets being arranged in a VGA-specific channel. The device includes a plurality of feedforward equalizers (FFEs), each FFE coupled to receive the output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs using a first subset of equalization coefficients and a second subset of equalization coefficients having coefficient values ​​common to all FFEs, the second subset of equalization coefficients being channel-specific and having a first set of coefficient values ​​for a first VGA-specific channel and a second set of coefficient values ​​for a second VGA-specific channel, the sets of coefficient values ​​being calculated independently.

Claims

1. A network transceiver device, comprising: A plurality of variable gain amplifiers (VGAs) configured to amplify received signals; at least two sets of analog-to-digital converters (ADCs), each set including a plurality of ADCs coupled to the respective outputs of one of the plurality of VGAs, wherein a first set of the at least two sets of ADCs is arranged in at least one first VGA-specific channel, and a second set of the at least two sets of ADCs is arranged in at least one second VGA-specific channel; and a clock data recovery (CDR) circuit coupled to each of the plurality of ADCs, wherein the CDR circuit is configured to receive an ADC sample signal from each of the plurality of ADCs, and in response thereto, the CDR circuit is configured to generate a channel timing signal and an ADC timing signal, the channel timing signal alternating between the first VGA-specific channel and the second VGA-specific channel, and the ADC timing signal including pulses added via each of the plurality of ADCs in each of the at least two sets of ADCs.

2. The network transceiver device as claimed in claim 1, wherein the CDR circuitry includes a phase detector configured to detect a phase of a signal received from each of the plurality of ADCs.

3. The network transceiver apparatus as described in claim 2, further comprising: The phase detector of the CDR circuit is configured to determine the timing of a pulse response in the received signal from each of the plurality of ADCs using at least two front vernier coefficients, a main coefficient, and at least two rear vernier coefficients.

4. The network transceiver device as claimed in claim 1, wherein the CDR circuit is configured to correct skew between samples from the ADC, taking into account both the timing errors of the front and rear vertex, for the purpose of correcting sample skew.

5. The network transceiver device as described in claim 4, wherein the CDR circuit operates either in a differential timing mode or in a common timing mode.

6. The network transceiver apparatus as claimed in claim 5, wherein in the differential timing mode, timing differences between each ADC in a specific VGA specific channel within each of the at least two sets of ADCs are corrected.

7. The network transceiver device as claimed in claim 5, wherein, in the common timing mode, the difference between the at least two sets of ADCs is corrected.

8. The network transceiver device as claimed in claim 1, wherein the network transceiver device is configured to operate as a fourth-order pulse amplitude modulation (PAM-4) transceiver.

9. A signal processing method comprising the steps of: amplifying a received signal at a plurality of variable gain amplifiers (VGAs); receiving the amplified signal from the plurality of VGAs at each of at least two sets of analog-to-digital converters (ADCs), each set including a plurality of ADCs coupled to the respective outputs of one of the plurality of VGAs, wherein a first set of the at least two sets of ADCs is arranged in at least one first VGA-specific channel, and a second set of the at least two sets of ADCs is arranged in at least one second VGA-specific channel; and receiving an ADC sampling signal from each of the plurality of ADCs at a clock data recovery (CDR) circuit coupled to each of the plurality of ADCs, and in response thereto generating a channel timing signal and an ADC timing signal, the channel timing signal alternating between the first VGA-specific channel and the second VGA-specific channel, and the ADC timing signal including pulses added via each of the plurality of ADCs in each of the at least two sets of ADCs.

10. The signal processing method as claimed in claim 9, wherein the CDR circuit includes a phase detector configured to detect a phase of a signal received from each of the plurality of ADCs.

11. The signal processing method as described in claim 10 further includes the following steps: using the phase detector of the CDR circuit, determining a timing sequence of a pulse response in the received signal from each ADC by utilizing at least two front vernier coefficients, a main coefficient, and at least two rear vernier coefficients.

12. The signal processing method as described in claim 9 further includes the following steps: correcting the skew between samples from the ADC by means of the CDR circuit, taking into account both the timing errors of the front vernier and the rear vernier, in order to correct the sample skew.

13. The signal processing method as described in claim 12, wherein the CDR circuit operates either in a differential timing mode or in a common timing mode.

14. The signal processing method as claimed in claim 13, wherein in the differential timing mode, timing differences between each ADC in a specific VGA channel of each of the at least two sets of ADCs are corrected.

15. The signal processing method as described in claim 13, wherein, in the common timing mode, the difference between the at least two sets of ADCs is corrected.

16. The signal processing method as described in claim 9 further includes the step of: equalizing the outputs of the plurality of ADCs to generate an equalized digital signal.

17. The signal processing method as described in claim 16 further includes the step of: outputting data including a PAM-4 symbol or data contained within a PAM-4 symbol based on the equalized digital signal.

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