Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and form at least one first column and at least one second column. The first column includes two or more of the terminals arranged in the first direction near the first end edge. The second column includes two or more of the terminals arranged in the first direction near the second end edge.

Claims

1. A semiconductor memory device connectable to a host computer, the semiconductor memory device comprising: a housing having a first surface, a second surface opposite to the first surface, a first end edge extending in a first direction, a second end edge opposite to the first end edge and extending in the first direction, a first side edge extending in a second direction intersecting the first direction, and a first corner portion forming a notch between the first end edge and the first side edge; a non-volatile memory; a controller arranged to control the non-volatile memory; and a plurality of terminals disposed on the first surface, wherein the terminals include a first plurality of terminals, a second plurality of terminals, and a third plurality of terminals, the first plurality of terminals being arranged in the first direction at a distance spaced closer to the first end edge than the second end edge, the third plurality of terminals being arranged in the first direction at a distance spaced closer to the second end edge than the first end edge, the second plurality of terminals being arranged in the first direction at a distance spaced between the first plurality of terminals and the third plurality of terminals, the first plurality of terminals being closer to the first end edge than the second plurality of terminals. The first plurality of terminals includes at least one pair of first signal terminals for a differential data signal compliant with the PCIe standard. The first plurality of terminals includes a first plurality of ground terminals assigned to ground. Each pair of first signal terminals is located between two ground terminals in the first plurality of ground terminals. The second plurality of terminals includes a second plurality of ground terminals assigned to ground. The third plurality of terminals includes a differential clock signal terminal assigned to a differential clock signal having a frequency lower than that of the differential data signal, a single-ended signal terminal assigned to a single-ended signal, a first power supply terminal assigned to a first power supply, and one or more second power supply terminals assigned to a second power supply having a voltage equal to or lower than that of the first power supply. The first power supply may be powered by the host computer, and the second power supply may be powered by the host computer.

2. The semiconductor memory device of claim 1, wherein the plurality of terminals includes a plurality of signal terminals for signal transmission, and the number of at least one of the signal terminals included in the first plurality of terminals and the second plurality of terminals is greater than the number of at least one of the signal terminals included in the third plurality of terminals.

3. The semiconductor memory device of claim 1, wherein a plurality of pairs of the first signal terminals allocated to a plurality of channels of the differential data signal are included in the plurality of terminals.

4. The semiconductor memory device of claim 1, wherein the first direction and the second direction are perpendicular to each other, the length of the semiconductor memory device in the first direction is 14 ± 0.1 mm, and the length of the semiconductor memory device in the second direction is 18 ± 0.1 mm.

5. The semiconductor memory device of claim 1, wherein the housing has a second side edge located on the opposite side of the first side edge and extending in the second direction, and a second corner portion between the first end edge and the second side edge, and the shape of the first corner portion and the shape of the second corner portion are different from each other.

6. The semiconductor memory device of claim 1, wherein the housing has an inclined portion extending in a straight line between the first end edge and the first surface.

7. The semiconductor memory device of claim 1, wherein the one or more second power terminals are arranged adjacent to each other in the first direction.

8. The semiconductor memory device of claim 7, wherein the third plurality of terminals includes a third plurality of ground terminals assigned to ground.

9. The semiconductor memory device of claim 8, wherein the single-ended signal terminal is located between the first power supply terminal and the one or more second power supply terminals.

10. The semiconductor memory device of claim 9, wherein the single-ended signal terminal includes a sideband signal terminal assigned to a sideband signal of the PCIe standard.

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