Solid-state camera components and electronic devices

Abstract

The present invention provides a small solid-state imaging element and an electronic device that can suppress the generation of strong electric fields near transistors. The solid-state imaging element includes: a photoelectric conversion element that performs photoelectric conversion; an element separation that extends from a first main surface of a substrate to a second main surface and is formed between pixels containing the photoelectric conversion element; and a conductor portion that is closely disposed on the first main surface side of the element separation.

Description

Solid-state camera components and electronic devices This disclosure relates to a solid-state camera element and an electronic device. In recent years, solid-state imaging devices with front full trench isolation (FFTI) have been used. In FFTI solid-state imaging devices, pixels are separated by an insulator, and each pixel is electrically isolated. Therefore, each separated pixel needs to have a contact electrode to set the semiconductor substrate to, for example, a ground potential. To reduce the area of ​​the contact electrode when viewed from above, it has been proposed to form a solid-state imaging device with contact electrodes by using a portion of the FFTI as an active area (e.g., Patent Document 1). [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Publication No. 2016-39315 [The problem the invention aims to solve] In this type of solid-state imaging device, to achieve miniaturization, the regions with higher impurity concentrations, which become the impurity regions of the source / drain electrodes of the transistor, are in close proximity to the contact electrodes. This results in a strong electric field being generated between the impurity regions and the contact electrodes. Therefore, the purpose of this disclosure is to provide a small solid-state imaging element and electronic device that can suppress the generation of strong electric fields near transistors. [Technical Means for Solving the Problem] To solve the above problems, the solid-state imaging element disclosed herein is characterized by comprising: a photoelectric conversion element that performs photoelectric conversion; a fully through-type element separation that extends from a first main surface of a substrate to a second main surface and is formed between pixels containing the photoelectric conversion element; and a conductor portion that is closely disposed on the first main surface side of the fully through-type element separation. Furthermore, the other types of electronic devices disclosed herein are characterized by comprising: a solid-state imaging device, comprising: a solid-state imaging element having: a photoelectric conversion element for performing photoelectric conversion; a fully through-type element separator extending from a first main surface of a substrate to a second main surface and formed between pixels including the aforementioned photoelectric conversion element; and a conductor portion closely disposed on the first main surface side of the aforementioned fully through-type element separator; an optical lens for imaging light from a subject onto the imaging surface of the aforementioned solid-state imaging device; and a signal processing circuit for processing signals output from the aforementioned solid-state imaging device. Hereinafter, with reference to Figures 1 to 18, an example of an optical element, optical element array, electronic device, and method for manufacturing an optical element according to an embodiment of the present disclosure will be described. The embodiments of the present disclosure will be described in the following order. However, the present disclosure is not limited to the examples below. Furthermore, the effects described in this specification are illustrative and not limiting; other effects may also be possible. 1. First Embodiment: Solid-State Camera Device (1.1) Overall Structure of Solid-State Camera Device (1.2) Structure of Solid-State Camera Element (1.3) Manufacturing Method of Solid-State Camera Element (1.4) Variation Example 2. Second Embodiment: Solid-State Camera Element (2.1) First Example of Solid-State Camera Element 200 (2.2) Second Example of Solid-State Camera Element 200 (2.3) Third Example of Solid-State Camera Element 200 3. Third Embodiment: Solid-State Camera Element (3.1) Structure of Solid-State Camera Element 4. Fourth Embodiment: Solid-State Camera Element (4.1) Structure of Solid-State Camera Element 5. Fifth Embodiment: Solid-State Camera Element (5.1) Structure of Solid-State Camera Element 6. Sixth Embodiment: Solid-State Camera Element (6.1) Structure of Solid-State Camera Element (6.1.1) First Example of Solid-State Camera Element 600 (6.1.2) Second Example of Solid-State Camera Element 600 7. Seventh Embodiment: Electronic Machine 1. First Embodiment: Solid State Camera Apparatus (1.1) Overall Configuration of Solid State Camera Apparatus The solid state camera apparatus 1 of the first embodiment of this disclosure will be described. Figure 1 is a schematic configuration diagram showing the overall configuration of the solid state camera apparatus 1 of the first embodiment of this disclosure. The solid-state imaging device 1 shown in Figure 1 is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor. As shown in Figure 18, the solid-state imaging device 1 captures image light (incident light 1006) from the subject through an optical lens 1002, and converts the amount of light of the incident light 1006 imaged on the imaging surface into an electrical signal in pixel units in the signal processing circuit 1005, and outputs it as an image signal (pixel signal). As shown in Figure 1, the solid-state imaging device 1 of the first embodiment includes: a substrate 2, a pixel region 3, a vertical driving circuit 4, a horizontal signal processing circuit 5, a horizontal driving circuit 6, an output circuit 7, and a control circuit 8. Pixel region 3 has a plurality of pixels 9 arranged regularly in a two-dimensional array on substrate 2. Pixel 9 has a photoelectric conversion unit 23 as shown in FIG. 2B, and a plurality of pixel transistors (not shown). As the plurality of pixel transistors, four transistors can be used, such as a transmission transistor, a reset transistor, a selection transistor, and an amplification transistor. Alternatively, three transistors other than the selection transistor can also be used. The vertical driving circuit 4 is composed of, for example, a shift register. It selects the desired pixel driving line L1 and supplies pulses to the selected pixel driving line L1 to drive the pixel 9, driving each pixel 9 in column units. That is, the vertical driving circuit 4 sequentially selects each pixel 9 of the scanning pixel region 3 in column units along the vertical direction, and supplies the pixel signal based on the signal charge generated in the photoelectric conversion unit 23 of each pixel 9 corresponding to the amount of light received to the row signal processing circuit 5 through the vertical signal line L2. The row signal processing circuit 5 is configured in each row of pixels 9, and performs signal processing such as noise removal on the signals output from pixels 9 in one column for each pixel row. For example, the row signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog Digital) conversion to remove fixed pattern noise inherent in the pixels. The horizontal drive circuit 6 is composed of, for example, a shift register, which sequentially outputs horizontal scan pulses to the row signal processing circuit 5, and sequentially selects each of the row signal processing circuits 5 to output the processed pixel signals to the horizontal signal line L3. The output circuit 7 processes and outputs the pixel signals sequentially supplied to each of the self-signal processing circuits 5 via the horizontal signal line L3. Signal processing methods include, for example, buffering, black level adjustment, line unevenness correction, and various digital signal processing techniques. The control circuit 8 generates a clock signal or control signal that serves as the operating reference for the vertical drive circuit 4, the horizontal signal processing circuit 5, and the horizontal drive circuit 6, based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock signal. Furthermore, the control circuit 8 outputs the generated clock signal or control signal to the vertical drive circuit 4, the horizontal signal processing circuit 5, and the horizontal drive circuit 6. (1.2) Structure of Solid-State Imaging Element Next, referring to FIGS. 2A and 2B, the detailed structure of the solid-state imaging device 1 of FIG. 1 will be described. FIG. 2A is a top view showing an example of the layout of the solid-state imaging element 100 in the pixel region 3 of the solid-state imaging device 1. FIG. 2B is a cross-sectional view of the pixel 9 of the solid-state imaging element 100 in the A-A' section shown in FIG. 2A. The solid-state imaging device 1 having the solid-state imaging element 100 shown in FIG. 2A and 2B is a back-illuminated CMOS image sensor (CMOS type solid-state imaging device). As shown in Figure 2A, a plurality of pixels 9 (9a, 9b, etc.) are arranged in two dimensions on the substrate 2 in the solid-state imaging element 100. The solid-state imaging element 100 includes a transmission transistor Ttr, a reset transistor Trs, an amplification transistor Tam, and a selection transistor Tsl. The transmission transistor Ttr is a transistor that reads charge from the photoelectric conversion element 22 and transfers the charge to the floating diffusion 41. The reset transistor Trs is a transistor that resets the potential of the floating diffusion 41 to the power supply voltage. The amplification transistor Tam is a transistor that receives the potential of the floating diffusion 41 at its gate and outputs it to the vertical signal line (VSL) as a source follower. The selection transistor Tsl is a transistor that connects the amplification transistor Tam of the readout column to the vertical signal line and disconnects the amplification transistor Tam of the unreadout column from the vertical signal line. As shown in Figures 2A and 2B, the solid-state imaging element 100 is constructed by separating the pixels 9 (9a, 9b, etc.) of the photoelectric conversion element (PD: photodiode) 22, which performs photoelectric conversion on the incident light, from the front full-trench isolation (FFTI) 11. Light is incident on the photoelectric conversion element 22 from the second main surface (the lower surface in Figure 2B), which is opposite to the transistor formation surface of the solid-state imaging element 100, i.e., the first main surface (the upper surface in Figure 2B). Hereinafter, the first main surface will be referred to as the upper surface, and the second main surface as the lower surface. As shown in Figure 2B, the solid-state imaging element 100 includes a substrate 2, an FFTI 11, an embedded conductor portion 12, an insulating portion 13, a well layer 21, and a photoelectric conversion element 22. Furthermore, the solid-state imaging element 100 includes a gate insulating film 31, gate electrodes 32, 33, 34, and 35, a floating diffusion layer 41, and a high-concentration impurity diffusion layer 42. Additionally, in Figures 2A and 2B, a GND contact 50 electrically connected to the embedded conductor portion 12 is also shown. On the lower surface side of the substrate 2, a light-concentrating layer is formed, in which a color filter layer and a wafer lens (not shown) are sequentially stacked. Furthermore, on the transistor formation side (upper surface) of the substrate 2, a wiring layer and a logic substrate (not shown) are sequentially stacked. (Substrate) Substrate 2 is formed of, for example, silicon (Si). On substrate 2, a pixel region 3 is formed, in which a plurality of pixels 9 are arranged. As shown in FIG2B, on substrate 2, a plurality of pixels 9 containing photoelectric conversion elements 22 are formed in pixel region 3 and arranged in a two-dimensional matrix. (Fully Through-Type Component Separation) The fully through-type component separation (FFTI) 11 is formed by extending from the transistor forming side (upper surface) of the substrate 2 to the lower surface, completely separating each pixel 9. The FFTI 11 surrounds the pixel 9 when viewed from above, and through the FFTI 11, each pixel 9 is electrically separated from its adjacent pixels 9. The FFTI 11 has a structure in which a component separation film such as a silicon oxide film or a silicon nitride film is embedded in a trench formed on the substrate 2. Alternatively, the FFTI 11 can be a two-layer structure consisting of a component separation film formed by covering the inner wall of the trench, and a semiconductor film such as silicon embedded within the trench in which the component separation film is formed. (Embedded Conductor Section) The embedded conductor section 12 functions as a contact electrode for the GND contact of the substrate 2 (high-concentration impurity diffusion layer 42). The embedded conductor section 12 can be embedded into a trench formed on the upper surface of the substrate 2. The embedded conductor section 12 is formed by embedding a conductor film into the entire trench on the upper part of the substrate 2 with FFTI 11 as the bottom surface. As described above, in the solid-state imaging element 100, each pixel 9 is electrically separated by FFTI 11. Therefore, in the solid-state imaging element 100, each separated pixel 9 needs to have a potential (reference potential) contact of the well layer 21. In the solid-state imaging element 100, a portion of the transistor formation surface side of FFTI 11 is used as an active region and is set as the embedded conductor section 12, which functions as a contact electrode. Thus, by closely arranging the embedded conductor portion 12 above the FFTI11, the increase in the area of ​​the solid-state imaging element 100 when viewed from above due to the formation of contact electrodes can be suppressed, and the area of ​​the solid-state imaging element 100 can be reduced. In this embodiment, as shown in FIG2A, the embedded conductor portion 12 is disposed on the entire boundary between pixels 9. Furthermore, the GND contact 50 is provided in such a way that it is connected to a portion of the embedded conductor portion 12 disposed on the boundary between pixels 9. The embedded conductor portion 12 is formed above the FFTI 11 (transistor forming surface side) in cross-section. The embedded conductor portion 12 is formed deeper than the insulating portion 13, and is thus closely disposed with the well layer 21 in a region deeper than the insulating portion 13. Herein, the embedded conductor portion 12 and the well layer 21 are ohmically bonded and electrically connected. As shown in FIGS. 2A and 2B, the embedded conductor portion 12 is closely disposed above the FFTI 11 disposed between pixels 9, and is shared as a contact electrode for the GND contact between two adjacent pixels 9. The embedded conductor portion 12 is formed of a conductor film. Preferably, silicon or other semiconductor materials, or metals, doped with P-type or N-type impurities are used as the conductor film. Preferably, the silicon used is, for example, polycrystalline silicon, amorphous silicon, or epitaxially grown silicon. (Insulating portion) The insulating portion 13 is an insulating layer disposed on the upper surface (transistor formation surface side) of the substrate 2, between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42. By providing the insulating portion 13 between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42, the situation where the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42 are in close contact and a strong electric field is generated between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42 is suppressed. The insulating portion 13 is formed of STI (Shallow Trench Isolation) or an insulating film. For the STI, any commonly used material is acceptable, such as silicon oxide. For the insulating film, an oxide film is preferred, and a silicon oxide film is even more preferred. The insulating portion 13 is formed by embedding, for example, an oxide film as an insulating film within trenches formed on the upper surface (transistor forming side) of the substrate 2. By providing this insulating portion 13, the embedded conductor portion 12 is not in close contact with the high-concentration impurity diffusion layer 42 (described later), and the distance between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42 increases. Therefore, it is less likely for a strong electric field to be generated between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42, thus improving the output stability of the solid-state imaging element 100. Furthermore, by providing this insulating portion 13, the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42 are separated relative to the longitudinal direction (depth direction of the substrate 2). Therefore, the size of the solid-state imaging element 100 when viewed from above can be reduced without increasing the size, and the generation of a strong electric field between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42 can be suppressed, thus achieving both a smaller area of ​​the solid-state imaging device 100 and improved output stability. The deeper the insulating portion 13 and the embedded conductor portion 12 are formed, the greater the longitudinal distance between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42. Therefore, for example, an insulating portion 13 and an embedded conductor portion 12 with a depth corresponding to the magnitude of the current flowing in the solid-state imaging element 100 can be formed, and the generation of a strong electric field can be suppressed. (Well Layer) Well layer 21 is a P-type region where P-type impurities (an example of the first conductivity type) diffuse at a low concentration. Well layer 21 is formed in a region deeper than the high-concentration impurity diffusion layer 42 described later. Well layer 21 is disposed in close contact with conductor portion 12 in a region deeper than insulating portion 13. As described later, well layer 21 forms a PN junction with photoelectric conversion element 22. (Photoelectric conversion element) The photoelectric conversion element 22 is a photodiode that converts incident light into a charge corresponding to the amount of light received and accumulates it. The photoelectric conversion element 22 receives light corresponding to the color of the color filter incident through a lens and a color filter disposed on the lower surface of the substrate. The photoelectric conversion elements 22 disposed in each of the pixels 9 are separated by FFTI 11. The photoelectric conversion element 22 is located within each pixel 9, in the P-type region, i.e., the region surrounded by the well layer 21. The photoelectric conversion element 22 is an N-type region diffused at a low concentration with N-type impurities (an example of the second conductivity type), which are different from the impurities diffused into the well layer 21. Thus, a PN junction is formed between the photoelectric conversion element 22 and the well layer 21, providing photoelectric conversion functionality. The photoelectric conversion element 22 functions as the source region of the transmission transistor Ttr. (Gate insulating film) The gate insulating film 31 is an insulating film formed between the photoelectric conversion element 22 and the floating diffusion 41, and between the floating diffusion 41 and the high-concentration impurity diffusion layer 42. The gate insulating film 31 is, for example, a silicon oxide film. (Gate Electrodes) Gate electrodes 32, 33, 34, and 35 are the gate electrodes for the transmission transistor Ttr, the reset transistor Trus, the amplification transistor Tam, and the selection transistor Tsl, respectively. As shown in FIG2B, gate electrodes 32, 33, 34, and 35 are formed by conductive films such as polycrystalline silicon films. In particular, gate electrode 32 is formed in a trench that extends relative to the well layer 21 to the vicinity of the photoelectric conversion element 22. Gate electrode 32 is formed by embedding a conductive film within a trench in which a gate insulating film 31 is disposed on the surface. (Floating Diffusion) Floating diffusion 41 is formed on the surface of the transistor formation side (upper side) of the substrate 2, and temporarily retains the charge read out by the transmission transistor Ttr in the region. Floating diffusion 41 is in the transistor formation region on the upper surface of the substrate 2, for example, in the region where N-type (an example of a second conductivity type) impurities are diffused at a high concentration. Floating diffusion 41 is formed in the well layer 21 in the region containing the boundary between the channel region of the transmission transistor Ttr and the channel region of the reset transistor TRS. Floating diffusion 41 functions as a drain region when the transmission transistor Ttr is driven, and functions as a source region when the reset transistor TRS is driven. (High-concentration impurity diffusion layer) The high-concentration impurity diffusion layer 42 is formed on the transistor formation surface (upper surface) side of the substrate 2, and is, for example, a region where N-type (an example of a second conductivity type) impurities are diffused at a high concentration. The high-concentration impurity diffusion layer 42 is formed shallower than the insulating portion 13. The high-concentration impurity diffusion layer 42 functions as the drain region of the reset transistor TRS. In the first embodiment of the solid-state imaging element 100 described above, the size of the solid-state imaging element 100 when viewed from above can be reduced without increasing the size of the solid-state imaging element 100, while suppressing the generation of a strong electric field between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42, and taking into account both the miniaturization of the solid-state imaging device 100 and the improvement of output stability. (1.3) Manufacturing Method of Solid State Camera Element Referring to FIGS. 3A to 3G, the manufacturing method of the solid state camera element 100 according to the first embodiment will be described. FIGS. 3A to 3G are cross-sectional views showing the steps of the manufacturing method of the solid state camera element 100. In FIGS. 3A to 3G, the step cross-sectional views of pixel 9 (unit pixel) are shown. As shown in Figure 3A, a trench is formed on the first main surface of substrate 2, which serves as the transistor formation surface (the upper surface in Figure 3A), and an insulating material is embedded therein to form STI 13A. Next, as shown in Figure 3B, after forming a trench extending from the first main surface of substrate 2 to the opposite side of substrate 2 (the lower surface in Figure 3B), i.e., the second main surface, a component separation film 11', such as a silicon oxide film or a silicon nitride film, is embedded. At this point, the trench is formed in a manner that penetrates the STI. Next, as shown in FIG3C, a portion of the first main surface of the device separation film 11' embedded in the trench is removed to form a trench. This forms FFTI11 using the device separation film 11'. Alternatively, an etching stop film can be formed on the first main surface of the substrate 2 before removing a portion of the first main surface of the device separation film 11'. As shown in FIG3D, a semiconductor film 12', such as polycrystalline silicon doped with impurities, is formed to cover the formed trench and the first main surface of the substrate 2. The semiconductor film 12' is formed using, for example, a chemical vapor deposition (CVD) method. As shown in Figure 3E, the semiconductor film 12' deposited on the first main surface of the substrate 2 is planarized by chemical mechanical polishing (CMP). This forms the embedded conductor portion 12. As shown in Figure 3F, a semiconductor element is formed within the pixel 9 separated by FFTI 11. First, a P-type region, i.e., a well layer 21, is formed by ion implantation of P-type impurities into the substrate 2. Then, an N-type region, i.e., a photoelectric conversion element 22, is formed by ion implantation of N-type impurities into the region surrounded by the well layer 21. A PN junction is formed between the well layer 21 and the photoelectric conversion element 22. Next, a trench extending from the upper surface of the substrate 2 to near the upper surface of the photoelectric conversion element 22 is formed by thermal oxidation of the substrate 2. Subsequently, a gate insulating film 31 is formed covering the upper surface of the substrate 2 and the surface of the trench. Next, a conductive film is embedded in the trench where the gate insulating film 31 is provided, and a conductive film is formed on the upper surface of the substrate 2. Subsequently, a portion of the conductive film is removed using lithography and etching techniques to form the gate electrode 32 of the transport transistor Ttr and the gate electrode 33 of the reset transistor Trs. Finally, N-type impurities are ion-implanted into a specific area on the upper surface of the substrate 2, and the ion-implanted area is activated by heat treatment. This forms a floating diffusion layer 41 and a high-concentration impurity diffusion layer 42. As shown in Figure 3G, after an interlayer insulating film is formed covering the upper surface of the substrate 2 where each transistor is formed, a contact hole is formed that penetrates the interlayer insulating film and connects to the embedded conductor portion 12. Finally, a GND contact 50 is formed by embedding conductive material into the contact hole. In Figure 3G, the interlayer insulating film is not shown; only the GND contact 50 is shown. (1.4) Variations The following describes seven examples of the solid-state imaging element 100, namely solid-state imaging elements 100A, 100B, 100C, 100D, 100E, 100F, and 100G, with reference to Figures 4 to 9. Solid-state imaging elements 100A to 100G differ from the solid-state imaging element 100 of the first embodiment in that they each have embedded conductor portions 12A to 12G instead of embedded conductor portion 12. Furthermore, for the solid-state imaging elements 100A to 100G that have the same function as the solid-state imaging element 100 in the first embodiment, detailed descriptions and illustrations in Figures 4 to 9 are omitted. That is, detailed descriptions of the FFTI 11, insulating portion 13, well layer 21, photoelectric conversion element 22, gate insulating film 31, gate electrodes 32, 33, 34 and 35, floating diffusion 41 and high-concentration impurity diffusion layer 42 formed in the pixel 9 of the solid-state imaging elements 100A to 100G are omitted. (1.4.1) The first variation, Figure 4, is a cross-sectional view of the pixel 9 of the solid-state imaging element 100A, which is one example of the variation of the solid-state imaging element 100. Figure 4 is a cross-sectional view corresponding to Figure 2B of the first embodiment. As shown in Figure 4, the embedded conductor portion 12A of the solid-state imaging element 100A is a conductor film formed on the surface of a trench provided on the substrate 2 with FFTI11 as the bottom surface. The embedded conductor portion 12A only needs to be the portion that is in close contact with the well layer 21. That is, the embedded conductor portion 12A can also be a shape in which a portion of the trench is embedded by a conductor material (the conductor material is not completely embedded in the trench). As shown in Figure 9, the embedded conductor portion 12B is a conductive film formed on the surface of a trench formed on the upper surface of the substrate 2. An air layer surrounds the sides and bottom of the trench by the conductive film. The embedded conductor portion 12B can also be composed of pure polycrystalline silicon or an oxide film embedded in the trench. (1.4.2) Second Variation Example: Figure 5 is a cross-sectional view of pixel 9 of solid-state image sensor 100B, one example of a variation of solid-state image sensor 100. Figure 5 is a cross-sectional view corresponding to Figure 2B of the first embodiment. As shown in Figure 5, the embedded conductor portion 12B of solid-state image sensor 100B is a conductor film formed on the surface of a trench disposed on the upper part of the substrate 2 with FFTI11 as the bottom surface. The embedded conductor portion 12B only needs to be a portion that is in close contact with the well layer 21. That is, the embedded conductor portion 12A can also be a shape in which a portion of the trench is embedded by a conductor material (the conductor material is not completely embedded in the trench). That is, the embedded conductor portions 12A and 12B can also be shapes in which the conductor material is not completely embedded in the trench. As shown in Figure 5, the embedded conductor portion 12B is a conductive film formed on the surface of a trench formed on the upper surface of the substrate 2. An air layer surrounds the sides and bottom of the trench by the conductive film. The embedded conductor portion 12B can also be composed of pure polycrystalline silicon or an oxide film embedded in the trench. (1.4.3) The third variation, Figures 6A and 6B, are cross-sectional views of the pixel 9 of the solid-state imaging element 100, specifically the solid-state imaging element 100C. Figures 6A and 6B are cross-sectional views corresponding to Figure 2B of the first embodiment. As shown in Figures 6A and 6B, the embedded conductor portions 12C and 12D of the solid-state imaging element 100C are embedded in a trench formed near the upper surface of the substrate 2 with FFTI11 as the bottom surface. The embedded conductor portions 12C and 12D have an inverted conical shape or a conical shape when viewed in cross-section. Here, Figure 6A illustrates the configuration when the embedded conductor portion 12C is a conical shape whose width tapers from the lower surface of the embedded conductor portion 12C to the upper surface. Figure 6B illustrates the configuration when the embedded conductor portion 12D is a conical shape whose width tapers from the upper surface of the embedded conductor portion 12C to the lower surface. To form the embedded conductor portions 12C and 12D, trenches for forming FFTI11 and the embedded conductor portions 12C and 12D are first formed by extending the STI formed through the upper surface of the substrate 2, and an insulating film is embedded in the trenches to form FFTI11. Next, the embedded conductor portions 12C and 12D are formed by embedding the conductor film above the FFTI11 within the trenches. Depending on the etching and other processes used to form the embedded conductor portions 12C and 12D, if the shape of the trench becomes conical, the cross-sectional shape of the embedded conductor portions 12C and 12D also becomes conical. (1.4.4) Fourth variation example: Figure 7 is a cross-sectional view of the pixel 9 of the solid-state camera element 100D, which is one example of the variation example of the solid-state camera element 100D. Figure 7 is a cross-sectional view corresponding to Figure 2B of the first embodiment. As shown in Figure 7, the embedded conductor portion 12E and the insulating portion 13E of the solid-state camera element 100D each have a conical shape in cross-section, which tapers from the lower surface to the upper surface. To form the embedded conductor portion 12E, firstly, a trench is formed on the upper surface of the substrate 2, and an insulating layer (STI) is formed to form the insulating portion 13. Next, a trench is formed through the STI to form an insulating layer (FFTI 11) and the embedded conductor portion 12E, and an insulating film is embedded within the trench to form the FFTI 11. Finally, the embedded conductor portion 12E is formed by embedding a conductor film above the FFTI 11 within the trench. Depending on the etching or other processes used to form the embedded conductor portion 12E, there are cases where both the shape of the trench formed when forming the insulating portion 13 and the shape of the trench formed when forming the embedded conductor portion 12E are conical. In this case, the cross-sectional shapes of the insulating portion 13 and the embedded conductor portion 12E are also conical. (1.4.5) Fifth Variation Example: Figure 8 is a cross-sectional view of the pixel 9 of the solid-state imaging element 100E, which is one example of a variation of the solid-state imaging element 100. Figure 8 is a cross-sectional view corresponding to Figure 2B of the first embodiment. As shown in Figure 8, the embedded conductor portion 12F of the solid-state imaging element 100E is embedded in a trench formed near the upper surface of the substrate 2 with FFTI11 as the bottom surface. The embedded conductor portion 12F has a cylindrical shape in which the diameter gradually increases towards the upper surface of the substrate 2 when viewed in cross-section of multiple stacked segments. To form the embedded conductor portion 12F, firstly, a trench for forming FFTI11 and the embedded conductor portion 12F is formed by penetrating the STI formed on the upper surface of the substrate 2, and an insulating film is embedded in the trench to form FFTI11. Next, the embedded conductor portion 12F is formed by embedding the conductor film above the FFTI11 in the trench. In this case, there are instances where trenches for forming FFTI11 and the embedded conductor portion 12F are formed by multiple etching processes, and the shape of the multiple trench segments is cylindrical. In this case, the cross-sectional shape of the embedded conductor portion 12F also becomes the shape of the multiple cylindrical segments of the stack. (1.4.6) Sixth Variation Example: Figure 9 is a cross-sectional view of the pixel 9 of the solid-state imaging element 100F, one example of a variation of the solid-state imaging element 100. Figure 9 is a cross-sectional view corresponding to Figure 2B of the first embodiment. As shown in Figure 9, the embedded conductor portion 12G of the solid-state imaging element 100F is embedded in a trench formed near the upper surface of the substrate 2 with FFTI 11 as the bottom surface. The embedded conductor portion 12G has a wider width than FFTI 11 when viewed in cross-section. Depending on the etching or other processes used to form the embedded conductor portion 12G, there may be a case where the width of the trench in the portion where the embedded conductor portion 12G is formed is wider than the width of the trench in the portion where FFTI 11 is formed. In this case, the embedded conductor portion 12G has a wider width than FFTI 11 when viewed in cross-section. <Effects of the First Embodiment> The solid-state imaging device 1, solid-state imaging element 100, and solid-state imaging elements 100A to 100G of this embodiment exhibit the following effects: (1) In the solid-state imaging element 100, an embedded conductor portion 12 is provided close to the top of the fully through-type element separator (FFTI) 11 that separates each pixel 9, and functions as a contact electrode. As a result, since it is not necessary to provide contact electrodes within the pixels 9 of the solid-state imaging element 100, the increase in the area of ​​each pixel 9 when viewed from above can be suppressed, thus enabling the solid-state imaging element 100 to be miniaturized. (2) In the solid-state imaging element 100, an insulating portion 13 is provided between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42 when viewed from above. This prevents the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42 from being in close contact, increasing the distance between them. Consequently, it is less likely for a strong electric field to be generated between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42, and the output stability of the solid-state imaging element 100 is improved. (3) In the solid-state imaging element 100, when viewed in cross-section, an insulating portion 13 is provided between the embedded conductor portion 12, which is formed deeper than the insulating portion 13, and the high-concentration impurity diffusion layer 42, which is formed shallower than the insulating portion 13, near the surface of the transistor formation surface of the substrate 2. This separates the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42 longitudinally (in the depth direction of the substrate 2). Therefore, without increasing the size of the solid-state imaging element 100 when viewed from above, it suppresses the generation of a strong electric field between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42, while simultaneously achieving both a smaller area of ​​the solid-state imaging device 100 and improved output stability. 2. Second Embodiment: Solid-State Imaging Element The solid-state imaging element 200 of the second embodiment disclosed herein will be described. The solid-state imaging element 200 is a solid-state imaging element that can replace the solid-state imaging element 100 of the solid-state imaging device 1 described in the first embodiment. In the second embodiment, three examples of the solid-state imaging element 200, namely solid-state imaging elements 200A, 200B, and 200C, will be described with reference to Figures 10 to 12. Furthermore, detailed descriptions and illustrations from Figures 10 to 12 are omitted for parts of the solid-state imaging element 200 that have the same function as the solid-state imaging element 100 of the first embodiment. That is, detailed descriptions are omitted for the well layer 21, photoelectric conversion element 22, gate insulating film 31, gate electrodes 32, 33, 34, and 35, floating diffusion 41, and high-concentration impurity diffusion layer 42 formed within the pixel 9 of the solid-state imaging element 200A. (2.1) First Example of Solid State Imaging Element 200 Figure 10 is a top view showing an example of the layout of a solid state imaging element 200, namely, a solid state imaging element 200A. As shown in Figure 10, the solid state imaging element 200A differs from the solid state imaging element 100 in the first embodiment in that the embedded conductor portion 12 is closely disposed at a point on a portion of the FFTI 11 that is provided at the boundary between the pixels 9. The arrangement of the FFTI 11 and the embedded conductor portion 12, as well as the connection of the GND contact 50, will be described below. As shown in Figure 10, the FFTI11 of the solid-state imaging element 200A is disposed on the entire boundary of each pixel 9. Furthermore, the embedded conductor portion 12 of the solid-state imaging element 200A is disposed only on a portion of the boundary of each pixel 9, particularly at the intersection of the four FFTI11 of adjacent pixels 9 in a 2×2 arrangement (the central portion of the four pixels 9). That is, the embedded conductor portion 12 of the solid-state imaging element 200A is disposed at the four corners of a pixel 9. At the intersection of the four FFTI11, an embedded conductor portion 12 is provided adjacent to each other above the FFTI11 (near the front side in FIG. 10). The embedded conductor portion 12 is formed deeper than the insulating portion 13 and is closely disposed with the well layer 21. On the other hand, in the portion other than the intersection of the four FFTI11, no embedded conductor portion 12 is provided above the FFTI11 (near the front side in FIG. 10), but an FFTI11 is provided extending from the transistor forming side of the substrate 2 (near the front side in FIG. 10) to the lower surface (deep side in FIG. 10). When the embedded conductor portion 12 is disposed above a portion of FFTI11 (the four corners of a pixel 9), the embedded conductor portion 12 may also be a semiconductor material that has been embedded, with the upper part of the embedded semiconductor material removed, and the upper part covered with an insulator such as silicon oxide for sealing. The embedded conductor portion 12 is shared as a contact electrode for GND contact between four adjacent pixels 9. Each pixel 9 has four contact electrodes at its four corners. Therefore, in the solid-state imaging element 200A, even when none of the embedded conductor portions 12 functions as contact electrodes, the other embedded conductor portions 12 also function as contact electrodes, improving the quality of the solid-state imaging device 1 having the solid-state imaging element 200A. (2.2) Second Example of Solid State Imaging Device 200 Figure 11 is a top view showing an example of the layout of a solid state imaging element 200, namely, a solid state imaging element 200B. As shown in Figure 11, the solid state imaging element 200B differs from the solid state imaging element 100 in the first embodiment in that the embedded conductor portion 12 is closely connected to a portion of the FFTI 11 provided at the boundary between the pixels 9. Furthermore, the solid state imaging element 200B differs from the solid state imaging element 200A in that a portion of the embedded conductor portion 12 is connected to the GND contact 50, and only a portion of the embedded conductor portion 12 functions as a contact electrode. Hereinafter, the arrangement of the FFTI 11 and the embedded conductor portion 12, and the connection of the GND contact 50, will be described. As shown in Figure 11, the FFTI11 of the solid-state imaging element 200B is disposed on the entire boundary of each pixel 9. Furthermore, the embedded conductor portion 12 of the solid-state imaging element 200B is disposed only on a portion of the boundary of each pixel 9, particularly at the intersection of the four FFTI11 of adjacent pixels 9 in a 2×2 arrangement (the central portion of the four pixels 9). That is, the embedded conductor portion 12 of the solid-state imaging element 200B is disposed at the four corners of a pixel 9. At the intersection of the four FFTI11 segments, above the FFTI11 (near the front side in FIG11), an embedded conductor portion 12 is provided, which is deeper than the insulating portion 13 and contacts the well layer 21. A GND contact 50 is connected to a portion of the embedded conductor portion 12 at the intersection of the four FFTI11 segments. The GND contact 50 only needs to be electrically connected to an adjacent pixel 9. Therefore, as shown in FIG11, for example, in a pixel 9, it is sufficient to connect the GND contact 50 to only one pair of embedded conductor portions 12 located diagonally. The embedded conductor portion 12, configured as described above, is shared as a contact electrode for GND contacts among four adjacent pixels 9. Each pixel 9 has two contact electrodes at its two corners. Therefore, in the solid-state imaging element 200B, when one embedded conductor portion 12 does not function as a contact electrode, the other embedded conductor portions 12 also function as contact electrodes, improving the quality of the solid-state imaging device 1 equipped with the solid-state imaging element 200B. (2.3) Third Example of Solid State Imaging Device 200 Figure 12 is a top view showing an example of the layout of a solid state imaging element 200, namely, a solid state imaging element 200C. As shown in Figure 12, the solid state imaging element 200C differs from the solid state imaging element 100 in the first embodiment in that the embedded conductor portion 12 is closely disposed at a point on a portion of the FFTI11 that is provided at the boundary between pixels 9. Furthermore, the solid state imaging element 200C differs from the solid state imaging element 200A in that the embedded conductor portion 12 is provided only at a diagonal position (two corners) of one pixel 9. The arrangement of the FFTI11 and the embedded conductor portion 12, as well as the connection of the GND contact 50, will be described below. As shown in Figure 12, the FFTI11 of the solid-state imaging element 200C is disposed on the entire boundary of each pixel 9. Furthermore, the embedded conductor portion 12 of the solid-state imaging element 200C is disposed on a portion of the boundary of each pixel 9. The embedded conductor portion 12 is disposed at a diagonal position of a pair of pixels 9. At a diagonal position of pixel 9, above FFTI11 (near the front side of Figure 12), there is an embedded conductor portion 12 formed in a manner that is deeper than the insulating portion 13 and contacts the well layer 21. The GND contact 50 is connected to each of the embedded conductor portions 12 located at the diagonal position of pixel 9. The embedded conductor portion 12, configured as described above, is shared as a contact electrode for GND contacts among four adjacent pixels 9. Each pixel 9 has two contact electrodes at its two corners. Therefore, in the solid-state imaging element 200C, when one embedded conductor portion 12 does not function as a contact electrode, the other embedded conductor portions 12 also function as contact electrodes, improving the quality of the solid-state imaging device 1 equipped with the solid-state imaging element 200C. Furthermore, as with the solid-state imaging element 200C, the embedded conductor portion 12 is not provided in the areas where GND contacts 50 are not provided, thereby increasing the characteristics of the solid-state imaging element 200C and the yield rate during its manufacturing. Alternatively, the solid-state imaging element 200 may have any of the embedded conductor portions 12A to 12G of the first embodiment variation, in place of the embedded conductor portion 12. <Effects of the Second Embodiment> In addition to the effects described in the first embodiment, the solid-state imaging element 200 of this embodiment also exhibits the following effects: (4) In the solid-state imaging element 200, an embedded conductor portion 12 that functions as a contact electrode is provided at the corner of each pixel 9. Therefore, the embedded conductor portion 12 is shared as a contact electrode for GND contact among four adjacent pixels 9. Even when none of the embedded conductor portions 12 functions as a contact electrode, the other embedded conductor portions 12 still function as contact electrodes. Thus, the quality of the solid-state imaging device 1 having the solid-state imaging element 200A is improved. (5) In the solid-state image sensor 200, the embedded conductor portion 12 is provided only at the two corners (diagonal corners) of each pixel 9. In this way, compared with the case where the embedded conductor portion 12 is provided at all four corners of each pixel 9, the characteristics of the solid-state image sensor 200C or the yield rate during the manufacturing of the solid-state image sensor 200C is improved. 3. Third Embodiment: Solid State Camera The solid state camera 300 of the third embodiment of this disclosure will be described. The solid state camera 300 is a solid state camera that can be used in place of the solid state camera 100 of the solid state camera device 1 described in the first embodiment. (3.1) In the third embodiment of the solid-state imaging element configuration, the solid-state imaging element 300 will be described with reference to FIG13. However, detailed descriptions and illustrations in FIG13 are omitted for parts of the solid-state imaging element 300 that have the same function as the solid-state imaging element 100 in the first embodiment. Specifically, detailed descriptions and illustrations are omitted for the well layer 21, photoelectric conversion element 22, gate insulating film 31, gate electrodes 32, 33, 34 and 35, floating diffusion 41, and high-concentration impurity diffusion layer 42 formed within the pixel 9 of the solid-state imaging element 300. Figure 13 is a cross-sectional view of pixel 9 of the solid-state imaging element 300. Figure 13 is a cross-sectional view corresponding to Figure 2B of the first embodiment. The solid-state imaging element 300 differs from the solid-state imaging element 100 of the first embodiment in that it has an insulating portion 313 instead of an insulating portion 13. As shown in Figure 13, the insulating portion 313 has a two-layer structure of an insulating film and pure polycrystalline silicon or oxide. The insulating film covers the surface of the trench disposed between the embedded conductor portion 12 and the high-concentration impurity diffusion layer 42; the pure polycrystalline silicon or oxide is embedded in the trench. Furthermore, an air layer (air gap) may also be provided in the insulating portion 313 instead of pure polycrystalline silicon or oxide. That is, the insulating portion 313 only needs to be formed with an insulating material at least on its surface. By providing this kind of insulating portion 313, compared with the insulating portion 13, the width of the insulating portion 313 can be narrowed, which is effective for pixel miniaturization. Alternatively, the solid-state imaging element 300 may have any of the embedded conductor portions 12A to 12G of the first embodiment variation, in place of the embedded conductor portion 12. <Effects of the Third Embodiment> In addition to the effects described in the first embodiment, the solid-state imaging element 300 of this embodiment exhibits the following effects: (6) In the solid-state imaging element 300, the insulating portion 313 has a two-layer structure consisting of an insulating film formed on the surface of the trench and a pure polycrystalline silicon or oxide film or an air layer embedded in the trench in which the insulating film is formed. This allows for a narrower width of the insulating portion 313, and is effective in reducing the area of ​​the solid-state imaging element 300. 4. Fourth Embodiment: Solid-State Imaging Element The solid-state imaging element 400 of the fourth embodiment of this disclosure will be described. The solid-state imaging element 400 is a solid-state imaging element that can be used in place of the solid-state imaging element 100 of the solid-state imaging device 1 described in the first embodiment. (4.1) In the fourth embodiment of the solid-state imaging element configuration, the solid-state imaging element 400 will be described with reference to FIGS. 14A to 14C. The solid-state imaging element 400 differs from the solid-state imaging element 100 of the first embodiment in that it has an embedded conductor portion 412 for connecting pixels 9 instead of an embedded conductor portion 12. Furthermore, the solid-state imaging element 400 differs from the solid-state imaging element 100 of the first embodiment in that it has an insulating portion 414. Moreover, the solid-state imaging element 400 differs from the solid-state imaging element 100 of the first embodiment in that it has a contact electrode 460 and an embedded conductor portion 43. Furthermore, detailed descriptions and illustrations in Figures 14A to 14C are omitted for parts of the solid-state imaging element 400 that have the same function as the solid-state imaging element 100 in the first embodiment. That is, detailed descriptions are omitted for the FFTI 11, insulating portion 13, well layer 21, photoelectric conversion element 22, gate insulating film 31, gate electrodes 32, 33, 34 and 35, floating diffusion 41 and high-concentration impurity diffusion layer 42 formed in the pixel 9 of the solid-state imaging element 400. Figure 14A is a top view of an example layout of the solid-state camera element 400. Figure 14B is a cross-sectional view of pixel 9 of the solid-state camera element 400 along the B-B' section shown in Figure 14A. Figure 14B is a cross-sectional view including the transmission transistor Ttr and the reset transistor Trs. Figure 14C is a cross-sectional view of pixel 9 of the solid-state camera element 400 along the C-C' section shown in Figure 14A. Figure 14C is a cross-sectional view including the magnification transistor Tam and the selection transistor Tsl. As shown in FIG14A, the solid-state imaging element 400 has a contact electrode 460 within the pixel 9. Also, as shown in FIG14B and FIG14C, the solid-state imaging element 400 has an embedded conductor portion 412 disposed on the upper part of the FFTI11 and an insulating portion 414 disposed on the upper part of the embedded conductor portion 412. An embedded conductor portion 412 is disposed between the FFTI 11 and the insulating portion 414. The embedded conductor portion 412 is formed deeper than the insulating portion 13 of the substrate 2 and is closely disposed with the well layers 21 of adjacent pixels 9. That is, the embedded conductor portion 412 has the function of electrically connecting each pixel 9. On the other hand, the embedded conductor portion 412 of this embodiment differs from the embedded conductor portion 12 of the first embodiment in that it does not have the function of serving as a contact electrode. The embedded conductor portion 412 is formed of the same material as the embedded conductor portion 12. The embedded conductor portion 412 is formed by embedding the conductor film into the upper part of the FFTI 11 and then removing the upper part of the embedded conductor. An insulating portion 414 is disposed on the upper part of the embedded conductor portion 412 and functions as a cover layer for the insulating portion 414. The insulating portion 414 is formed of, for example, silicon oxide or silicon nitride, or other insulating materials. The insulating portion 414 is formed by embedding the insulating portion into the upper part of the embedded conductor portion 412 within a trench. As shown in Figure 14A, the contact electrode 460 is connected to the GND contact 50 and obtains a contact area. As shown in Figure 14C, the contact electrode 460 is connected to the well layer 21, and the well layer 21 is fixed to the potential input from the GND contact 50. The contact electrode 460 is formed in the pixel 9 area. Alternatively, the contact electrode 460 can be disposed in the pixel 9 area and outside the pixel 9 area (outside pixel area 3 shown in Figure 1). When the contact electrode 460 is formed in the pixel 9 area, one contact electrode 460 is provided for several pixels 9. In this case, the pixel 9 with the contact electrode 460 is preferably a pixel 9 with a blue (B) color filter. This is because, in a pixel 9 incident with short-wavelength blue light, the influence of pattern differences in the transistor formation surface on the opposite side (upper surface in Figure 14B) caused by the optical characteristics of blue light can be suppressed. Therefore, when a contact electrode 460 is provided on a pixel 9 that has a blue (B) color filter, the output unevenness between pixels 9 can be suppressed and the uniformity of the output from each pixel 9 can be improved. Pixel 9 is electrically connected via embedded conductor portion 412. Therefore, a single contact electrode 460 functions as a potential (reference potential) contact for the well layer 21 of each individual pixel 9. Pixel 9 is a region with a high concentration of diffused impurities, where the contact electrode 460 is positioned to make contact with the GND contact 50. As shown in FIG14C, the contact electrode 460 is formed to a depth at which its lower surface makes electrical contact with the well layer 21. The contact electrode 460 is formed by embedding a conductive film within a trench disposed on the substrate 2. The conductive film is preferably made of, for example, silicon or other semiconductor materials doped with P-type impurities, or a metal. As silicon, it is preferably, for example, polycrystalline silicon, amorphous silicon, epitaxially grown silicon, etc. <Effects of the Fourth Embodiment> The solid-state camera element 400 of this embodiment has the following effects. (7) In the solid-state camera element 400, each pixel 9 is electrically connected to the other by an embedded conductor portion 412, and a contact electrode 460 is provided in one of the pixels 9. Therefore, compared with the case where a contact electrode 460 is provided in each pixel 9, the number of contact electrodes 460 is reduced, which is effective for miniaturizing the solid-state camera element 300. (8) In the solid-state imaging element 400, a contact electrode 460 may also be provided on the pixel 9 where a blue (B) color filter is provided and blue light with a shorter wavelength is incident. In this case, the output unevenness between pixels 9 caused by the presence or absence of the contact electrode 460 can be suppressed, and the uniformity of the output from each pixel 9 can be improved. 5. Fifth Embodiment: Solid State Imaging Element The solid state imaging element 500 of the fifth embodiment of this disclosure will be described. The solid state imaging element 500 is a solid state imaging element that can be used in place of the solid state imaging element 100 of the solid state imaging device 1 described in the first embodiment. (5.1) In the fifth embodiment of the solid-state camera element configuration, the solid-state camera element 500 will be described with reference to FIGS. 15A to 15C. As shown in FIG. 15A, the solid-state camera element 500 differs from the solid-state camera element 100 in that the embedded conductor portion 512 is closely disposed at a point on a portion of the FFTI11 of the boundary between pixels 9. When viewed from above, the solid-state camera element 500 has embedded conductor portions 512 in the regions at the four corners of each pixel 9. Furthermore, the solid-state camera element 500 differs from the solid-state camera element 100 in that it has embedded conductor portions 515 respectively disposed on the boundary between two pixels 9. Furthermore, detailed descriptions and illustrations in Figures 15A to 15C are omitted for parts of the solid-state imaging element 500 that have the same function as the solid-state imaging element 100 in the first embodiment. That is, detailed descriptions are omitted for the FFTI 11, insulating portion 13, well layer 21, photoelectric conversion element 22, gate insulating film 31, gate electrodes 32, 33, 34 and 35, floating diffusion 41 and high-concentration impurity diffusion layer 42 formed in the pixel 9 of the solid-state imaging element 500. Figure 15A is a top view showing an example of the layout of the solid-state imaging element 500. Figure 15B is a cross-sectional view of the pixel 9 of the solid-state imaging element 500 along the D-D' section shown in Figure 2A. Figure 15B is a cross-sectional view including the region containing the embedded conductor portion 515 which has an electron capture function. Figure 15C is a cross-sectional view of the pixel 9 of the solid-state imaging element 500 along the E-E' section shown in Figure 2A. Figure 15C is a cross-sectional view including the region containing the embedded conductor portion 512 which functions as a contact electrode. The embedded conductor portions 512 located at the four corners of pixel 9, like the embedded conductor portions 12 in the first embodiment, function as contact electrodes for fixing the potential of the well layer 21. As shown in FIG15A, the FFTI11 of the solid-state imaging element 500 is provided on the entire boundary between pixels 9. Furthermore, the embedded conductor portions 512 of the solid-state imaging element 500 are provided on a portion of the boundary between each pixel 9, particularly including the area where the four FFTI11 that separate adjacent pixels 9 in a 2×2 arrangement intersect (the central portion of the four pixels 9). That is, the embedded conductor portions 512 of the solid-state imaging element 500 are provided at the four corners of a pixel 9. As shown in FIG15B, the embedded conductor portions 512 are provided above the FFTI11 in the area including the four corners of the pixel 9 (upper side of FIG15B) in a manner that is deeper than the insulating portion 13 and contacts the well layer 21. In FIG15A, as an example, the embedded conductor portion 512 is shown as a cross-shaped embedded conductor portion when viewed from above. The embedded conductor portion 512 is formed using the same material and manufacturing method as the embedded conductor portion 12 in the first embodiment. The embedded conductor portion 515 disposed on the boundary between pixels 9 has an electron trapping function to suppress charge overflow to adjacent pixels 9 of the interspersed embedded conductor portion 512 or 515 when there is a large amount of light. The embedded conductor portion 515 is disposed above a portion of the FFTI11 located at the boundary between pixels 9 (upper side of FIG. 15B) in a manner that is deeper than the insulating portion 13 and contacts the well layer 21. The embedded conductor portion 515 is preferably made of, for example, silicon or other semiconductor materials doped with N-type impurities, or metal. As silicon, it is preferably, for example, polycrystalline silicon, amorphous silicon, epitaxially grown silicon, etc. The embedded conductor portion 512 is electrically connected to the GND contact 50. Thus, the embedded conductor portion 512 functions as a contact electrode. The embedded conductor portion 512 is shared as a contact electrode for the GND contact between four adjacent pixels 9. Each pixel 9 has four contact electrodes at its four corners. Therefore, even when none of the embedded conductor portions 512 in the solid-state imaging element 500 functions as a contact electrode, the other embedded conductor portions 512 also function as contact electrodes, improving the image quality of the solid-state imaging device 1 equipped with the solid-state imaging element 500. On the other hand, the embedded conductor portion 515 is electrically connected to a VDD contact 570 to which a positive voltage is applied. The embedded conductor portion 515 is formed of, for example, an N-type semiconductor material and is subjected to a positive voltage, thereby capturing electrons accumulated in the photoelectric conversion element 22. This prevents electrons from flowing to adjacent pixels even when high light intensity causes electrons accumulated in the photoelectric conversion element 22 to overflow to adjacent pixels 9. Thus, the solid-state imaging element 500 can suppress color mixing between adjacent pixels 9 equipped with color filters of different colors. Furthermore, in the solid-state imaging element 500, it is preferable that the barrier from the photoelectric conversion element 22 to the embedded conductor portion 515 and the barrier from the photoelectric conversion element 22 to each transistor such as the transmission transistor Ttr have different strengths. This suppresses the impact of electrons overflowing from the photoelectric conversion element 22 on each transistor under high light intensity. Alternatively, the solid-state imaging element 500 may have any of the embedded conductor portions 12A to 12G of the first embodiment variation, instead of the embedded conductor portion 512. Furthermore, the embedded conductor portion 515 of the solid-state imaging element 500 may also have the same configuration as the embedded conductor portions 12A to 12G of the first embodiment variation. Moreover, the solid-state imaging element 500 may also have the insulating portion 313 of the third embodiment, instead of the insulating portion 13. <Effects of the Fifth Embodiment> In addition to the effects described in the first embodiment, the solid-state imaging element 500 of this embodiment also exhibits the following effects: (9) The solid-state imaging element 500 includes an embedded conductor portion 515 electrically connected to a VDD contact, and a positive voltage is applied to the VDD contact to capture electrons overflowing from the photoelectric conversion element 22. Therefore, under high light conditions, the flow of electrons overflowing from the photoelectric conversion element 22 to adjacent pixels 9 can be suppressed, and color mixing with adjacent pixels 9 can be suppressed. 6. The sixth embodiment of this disclosure will describe the solid-state camera element 600. The solid-state camera element 600 is a solid-state camera element that can be used in place of the solid-state camera element 100 of the solid-state camera device 1 described in the first embodiment. (6.1) In the sixth embodiment of the solid-state imaging element configuration, two examples of the solid-state imaging element 600, namely solid-state imaging elements 600A and 600B, will be described with reference to Figures 16 and 17. However, detailed descriptions and illustrations in Figures 16 and 17 are omitted for parts of the solid-state imaging element 600 that have the same function as the solid-state imaging element 100 in the first embodiment. Specifically, detailed descriptions are omitted for the FFTI 11, insulating portion 13, well layer 21, photoelectric conversion element 22, gate insulating film 31, gate electrodes 32, 33, 34 and 35, floating diffusion 41, and high-concentration impurity diffusion layer 42 formed within the pixels 9 of the solid-state imaging elements 600A and 600B. (6.1.1) First Example of Solid State Imaging Element 600 Figure 16 is a top view showing an example of the layout of a solid state imaging element 600, namely, a solid state imaging element 600A. As shown in Figure 16, the solid state imaging element 600A differs from the solid state imaging element 100 of the first embodiment in that it has an embedded conductor portion 612A instead of an embedded conductor portion 12 in a portion of the area on the boundary between two pixels 9. Furthermore, the solid state imaging element 600A differs from the solid state imaging element 100 of the first embodiment in that it has an embedded conductor portion 615A in the area of ​​the FFTI11 surrounding each pixel, excluding the area where the embedded conductor portion 612A is formed. Hereinafter, the arrangement of the FFTI11, the embedded conductor portion 612A, and the embedded conductor portion 615A, and the connection of the GND contact 50 will be described. The solid-state imaging element 600A is a solid-state imaging element that sets two adjacent pixels 9 as a shared pixel unit. One embedded conductor portion 612A is provided for each pair of adjacent pixels 9. The embedded conductor portion 612A is provided on the upper part (near the front side in FIG16) of the FFTI11 (not shown) provided at the boundary between the two adjacent pixels 9. When viewed from above, the embedded conductor portion 612A is located near the center of the FFTI11 sandwiched between the two pixels 9. The upper surface of the embedded conductor portion 612A is exposed from the embedded conductor portion 615A described later and is connected to the GND contact 50. Like the embedded conductor portion 12 described in the first embodiment, the embedded conductor portion 612A functions as a contact electrode. The embedded conductor portion 612A is formed in the same manner as the embedded conductor portion 12, except for a portion provided on the FFTI11 provided at the boundary between the two adjacent pixels 9. An embedded conductor portion 615A is disposed on the upper part of an FFTI11 (not shown) that is provided at the boundary of each pixel 9. The embedded conductor portion 615A is formed on the FFTI11 in the area excluding the area where the embedded conductor portion 612A is formed. Like the embedded conductor portion 515 described in the fifth embodiment, the embedded conductor portion 615A has an electron trapping function to suppress the overflow of charge to the adjacent pixel 9 of the interposer embedded conductor portion 612A or 615A when there is a large amount of light. The embedded conductor portion 615A is formed in the same way as the embedded conductor portion 515, except that it is disposed in the area surrounding most of each pixel 9. A VDD contact 670, to which a positive voltage is applied, is connected to the embedded conductor portion 615A. By applying a positive voltage through the VDD contact 670, the embedded conductor portion 615A captures electrons overflowing from the photoelectric conversion element 22. The VDD contact 670 is formed using the same material and method as the VDD contact 570 in the fifth embodiment. In this solid-state imaging element 600A, each pixel unit consisting of two pixels 9 shares an embedded conductor portion 612A as an electrode for a GND contact. When a high-brightness light source is incident on the solid-state imaging element 600A, and electrons overflow from the pixels 9 via the embedded conductor portion 612A, although the electrons flow into other pixels 9 within the shared pixel unit via the embedded conductor portion 612A, the flow of electrons into other pixels 9 outside the shared pixel unit is suppressed. Therefore, image quality degradation can be suppressed by processing the same as pixel correction caused by defects in the shared pixel unit. (6.1.2) Second Example of Solid State Imaging Element 600 Figure 17 is a top view showing an example of the layout of solid state imaging element 600, namely solid state imaging element 600B. As shown in Figure 17, solid state imaging element 600B differs from solid state imaging element 100 in the first embodiment in that it has an embedded conductor portion 612B disposed in the area surrounding the boundary of four pixels 9 instead of embedded conductor portion 12. Furthermore, solid state imaging element 600A differs from solid state imaging element 100 in that it has an embedded conductor portion 615B in the area of ​​the FFTI11 surrounding each pixel, excluding the area where the embedded conductor portion 612A is formed. Hereinafter, the arrangement of FFTI11, embedded conductor portion 612B and embedded conductor portion 615B, and the connection of GND contact 50 will be described. The solid-state imaging element 600B is a solid-state imaging element that sets four pixels 9 arranged in a 2×2 matrix as a common pixel unit. One embedded conductor portion 612B is provided for each of the four matrix-arranged pixels 9. The embedded conductor portion 612B is located above the FFTI11 (not shown) at the center of the four pixels 9 (near the front side in Figure 17). The upper surface of the embedded conductor portion 612B protrudes from the embedded conductor portion 615B described later and is connected to the GND contact 50. An embedded conductor portion 615B is disposed on the upper part of an FFTI11 (not shown) that is provided at the boundary of each pixel 9. The embedded conductor portion 615B is formed in the area of ​​the FFTI11 excluding the area where the embedded conductor portion 612B is formed. Like the embedded conductor portion 615A, the embedded conductor portion 615B has an electron trapping function to suppress the overflow of electrons into the adjacent pixels 9 of the intervening embedded conductor portion 612B or 615B when there is a large amount of light. The embedded conductor portion 615B is formed in the same way as the embedded conductor portion 515, except that it is disposed in the area surrounding most of each pixel 9. In this solid-state imaging element 600B, each pixel unit consists of two pixels 9 and shares an embedded conductor portion 612B as an electrode for the GND contact. When a high-brightness light source is incident on the solid-state imaging element 600B and electrons overflow from the pixels 9 via the embedded conductor portion 612B, although the electrons flow into other pixels 9 within the shared pixel unit via the embedded conductor portion 612B, the flow of electrons into other pixels 9 outside the shared pixel unit is suppressed. Therefore, image quality degradation can be suppressed by processing the same as pixel correction caused by defects in the shared pixel unit. <Effects of the Sixth Embodiment> In addition to the effects described in the first embodiment, the solid-state imaging element 600 of this embodiment also exhibits the following effects: (10) The solid-state imaging element 600 includes embedded conductor portions 615A and 615B, which are electrically connected to a VDD contact and a positive voltage is applied to the VDD contact, thereby capturing electrons overflowing from the photoelectric conversion element 22. Therefore, the solid-state imaging element 600 can suppress the flow of electrons overflowing from the photoelectric conversion element 22 to adjacent pixels 9 under high light conditions and suppress color mixing with adjacent pixels 9. (11) When electrons overflow from pixel 9, the solid-state image sensor 600 can also suppress the flow of electrons into other pixels 9 outside the shared pixel unit. Therefore, the solid-state image sensor 600 can suppress image quality degradation by performing the same pixel correction as the defect caused by the shared pixel unit. 7. Seventh Embodiment Next, the electronic device of the seventh embodiment of this disclosure will be described. Figure 18 is a schematic diagram of the electronic device 1000 of the seventh embodiment of this disclosure. The electronic device 1000 of the seventh embodiment includes a solid-state imaging device 1, an optical lens 1002, a shutter device 1003, a drive circuit 1004, and a signal processing circuit 1005. The electronic device 1000 of the seventh embodiment shows an embodiment in which the solid-state imaging device 1 of the first embodiment disclosed herein is used as a solid-state imaging device 1 in an electronic device (e.g., a camera). Optical lens 1002 images the image light (incident light 106) from the subject onto the imaging surface of solid-state imaging device 1. This allows signal charge to accumulate within solid-state imaging device 1 over a certain period. Shutter device 1003 controls the period of light illumination and the period of light blocking onto solid-state imaging device 1. Drive circuit 1004 supplies drive signals to control the transmission operation of solid-state imaging device 1 and the shutter operation of shutter device 1003. Signal transmission of solid-state imaging device 1 is performed using the drive signals (timing signals) supplied by drive circuit 1004. Signal processing circuit 1005 performs various signal processing operations on the signals (pixel signals) output from solid-state imaging device 1. The processed image signals are stored in memory or other memory media, or output to a monitor. Furthermore, the electronic device 1000 applicable to the solid-state camera device 1 is not limited to cameras, but can also be applied to other electronic devices. For example, it can also be applied to camera devices such as camera modules specifically for mobile devices such as mobile phones or tablet terminals. Also, in the seventh embodiment, the solid-state camera device 1 is configured to use the solid-state camera device 1 of the first embodiment in an electronic device, but it can also be configured in other ways. For example, the solid-state camera device 1 of the second embodiment, or a variation thereof, can also be used in an electronic device. Alternatively, this technology can be configured as follows: (1) A solid-state imaging element comprising: a photoelectric conversion element that performs photoelectric conversion; a fully through-type element separation that extends from a first main surface of a substrate to a second main surface and is formed between pixels including the photoelectric conversion element; and a conductor portion that is closely disposed on the first main surface side of the fully through-type element separation. (2) The solid-state imaging element as described in (1) above, wherein the conductor portion is embedded in a first trench formed in the first main surface of the substrate; and further comprising: a high-concentration impurity diffusion layer formed on the first main surface of the substrate; and an insulating portion disposed between the conductor portion and the high-concentration impurity diffusion layer. (3) The solid-state imaging element as described in (2) above, wherein the conductor portion is formed deeper than the insulating portion; and the high-concentration impurity diffusion layer is formed shallower than the insulating portion. (4) A solid-state imaging element as described in (2) or (3) above, comprising: a well layer formed in a region deeper than the high-concentration impurity diffusion layer; and a conductor portion disposed in close contact with the well layer in a region deeper than the insulating portion. (5) A solid-state imaging element as described in (4) above, comprising: a cover layer disposed in close contact with the first main surface side of the conductor portion; and the conductor portion disposed in close contact with the well layer of a plurality of closely connected pixels. (6) A solid-state imaging element as described in any one of (1) to (5) above, wherein the fully penetrating element is disposed surrounding the pixel when viewed from above; and the conductor portion is disposed in close contact with the entire surface or a portion of the surface above the fully penetrating element. (7) A solid-state imaging element as described in (6) above, wherein the conductor portion is disposed above at least one of the above-ground fully penetrating element separation sandwiched between two adjacent pixels and above the above-ground fully penetrating element separation located at the center of four pixels arranged in a 2×2 matrix. (8) A solid-state imaging element as described in any one of (1) to (6) above, wherein the conductor portion is a shape in which a portion or all of the second trench with the bottom surface separated by the fully penetrating element is embedded by means of a conductor material. (9) A solid-state imaging element as described in (2) or (3) above, wherein at least the surface of the insulating portion is formed of an insulating material. (10) A solid-state imaging element as described in (9) above, wherein the insulating portion is a two-layer structure consisting of an insulating film covering the surface of the third trench between the conductor portion and the high-concentration impurity diffusion layer, and a pure polycrystalline silicon or oxide or air layer embedded in the trench. (11) A solid-state imaging element as described in any of (1) to (10) above, wherein the conductor portion is a contact electrode shared by adjacent pixels.(12) An electronic device comprising: a solid-state imaging device including: a solid-state imaging element having: a photoelectric conversion element for performing photoelectric conversion; a fully through-type element separation extending from a first main surface of a substrate to a second main surface and formed between pixels including the photoelectric conversion element; and a conductor portion closely disposed on the first main surface side of the fully through-type element separation; an optical lens for imaging image light from a subject onto the imaging surface of the solid-state imaging device; and a signal processing circuit for processing signals output from the solid-state imaging device. The solid-state imaging element disclosed herein only requires that the FFTI (Fluorescent Identifier), the high-concentration impurity region disposed nearby, the embedded conductor, and the insulating portion be configured as described above, regardless of the configuration of other parts. That is, the configuration of the semiconductor elements within the pixel can be any configuration other than those described above. Furthermore, taking the conductivity type of the impurity diffusion region of the solid-state imaging element disclosed herein as an example, the P-type region and the N-type region can also be formed in reverse order. The scope of this invention is not limited to the exemplary embodiments shown in the figures, but also includes all embodiments that achieve the same effect as the purpose of this invention. Furthermore, the scope of this invention is not limited to the combination of inventive features defined by the technical solution, but can be defined according to all desired combinations of specific features among all disclosed features. 1: Solid-state camera device; 2: Substrate; 3: Pixel area; 4: Vertical drive circuit; 5: Horizontal signal processing circuit; 6: Horizontal drive circuit; 7: Output circuit; 8: Control circuit; 9: Pixel; 9a: Pixel; 9b: Pixel; 11: Fully through-type element separation (FFTI); 11': Element separation film; 12: Embedded conductor portion; 12': Semiconductor film; 12A~12G: Embedded conductor portion; 13: Insulating portion; 13A: STI 13E: Insulating part; 21: Well layer; 22: Photoelectric conversion element; 23: Photoelectric conversion part; 31: Gate insulating film; 32-35: Gate electrode; 41: Floating diffusion; 42: High-concentration impurity diffusion layer; 43: Embedded conductor part; 50: GND contact; 60: Contact electrode; 100: Solid-state imaging element; 100A-100G: Solid-state imaging element; 200: Solid-state imaging element; 200A-200C: Solid-state imaging element; 300: Solid-state imaging element; 313: Insulating part; 400: Solid-state imaging element; 412: Embedded conductor part; 414: Insulating part; 460: Contact electrode; 500: Solid-state imaging element; 512: Embedded conductor part; 51 5: Embedded conductor section 570: VDD contact 600: Solid-state imaging element 600A: Solid-state imaging element 600B: Solid-state imaging element 612A: Embedded conductor section 612B: Embedded conductor section 615A: Embedded conductor section 615B: Embedded conductor section 670: VDD contact 1000: Electronic device 1002: Optical lens 1003: Shutter device 1004: Drive circuit 1005: Signal processing circuit 1006: Incident light L1: Pixel drive wiring L2: Vertical signal line L3: Horizontal signal line Tam: Amplifying transistor Trs: Reset transistor Tsl: Selecting transistor Ttr: Transmitting transistor Figure 1 is a diagram showing the overall structure of the solid-state camera device according to the first embodiment of this disclosure. Figure 2A is a top view showing an example of the layout of the solid-state camera element according to the first embodiment of this disclosure. Figure 2B is a cross-sectional view showing an example of the structure of the solid-state camera element according to the first embodiment of this disclosure. Figure 3A is a cross-sectional view illustrating the steps of the manufacturing method of the solid-state camera element according to the first embodiment of this disclosure. Figure 3B is a cross-sectional view illustrating the steps of the manufacturing method of the solid-state camera element according to the first embodiment of this disclosure. Figure 3C is a cross-sectional view illustrating the steps of the manufacturing method of the solid-state camera element according to the first embodiment of this disclosure. Figure 3D is a cross-sectional view illustrating the steps of the manufacturing method of the solid-state camera element according to the first embodiment of this disclosure. Figure 3E is a cross-sectional view illustrating the steps of the manufacturing method of the solid-state camera element according to the first embodiment of this disclosure. Figure 3F is a cross-sectional view illustrating the steps of the manufacturing method of the solid-state camera element according to the first embodiment of this disclosure. Figure 3G is a cross-sectional view illustrating the steps of the manufacturing method of the solid-state camera element according to the first embodiment of this disclosure. Figure 4 is a cross-sectional view showing another example of the structure of the solid-state camera element according to the first embodiment of this disclosure. Figure 5 is a cross-sectional view showing another example of the structure of the solid-state camera element according to the first embodiment of this disclosure. Figure 6A is a cross-sectional view showing another example of the structure of the solid-state camera element according to the first embodiment of this disclosure. Figure 6B is a cross-sectional view showing another example of the structure of the solid-state camera element according to the first embodiment of this disclosure. Figure 7 is a cross-sectional view showing another example of the structure of the solid-state camera element according to the first embodiment of this disclosure. Figure 8 is a cross-sectional view showing another example of the structure of the solid-state camera element according to the first embodiment of this disclosure. Figure 9 is a cross-sectional view showing another example of the structure of the solid-state camera element according to the first embodiment of this disclosure. Figure 10 is a top view showing an example of the layout of the solid-state camera element according to the second embodiment of this disclosure. Figure 11 is a top view showing an example of the layout of a solid-state camera element according to the second embodiment of this disclosure. Figure 12 is a top view showing an example of the layout of a solid-state camera element according to the second embodiment of this disclosure. Figure 13 is a cross-sectional view showing an example of the configuration of a solid-state camera element according to the third embodiment of this disclosure. Figure 14A is a top view showing an example of the layout of a solid-state camera element according to the fourth embodiment of this disclosure. Figure 14B is a cross-sectional view showing an example of the configuration of a solid-state camera element according to the fourth embodiment of this disclosure. Figure 14C is a cross-sectional view showing an example of the configuration of a solid-state camera element according to the fourth embodiment of this disclosure. Figure 15A is a top view showing an example of the layout of a solid-state camera element according to the fifth embodiment of this disclosure. Figure 15B is a cross-sectional view showing an example of the configuration of a solid-state camera element according to the fifth embodiment of this disclosure. Figure 15C is a cross-sectional view showing an example of the configuration of a solid-state camera element according to the fifth embodiment of this disclosure. Figure 16 is a top view showing an example of the layout of a solid-state imaging element according to the sixth embodiment of this disclosure.Figure 17 is a top view showing an example of the layout of the solid-state imaging element according to the sixth embodiment of this disclosure. Figure 18 is a schematic diagram of the electronic device according to the seventh embodiment of this disclosure. 9 pixels 11: Fully Through-Type Component Decoupling (FFTI) 12: Embedded conductor portion 13: Insulation section 21: Well Formation 22: Photoelectric conversion element 31: Gate insulating film 32: Gate electrode 33: Gate electrode 41: Floating Diffusion 42: High-concentration impurity diffusion layer 50:GND contact 100: Solid-state camera element Tam: Amplifying transistor Trs: Reset transistor Tsl: Select Transistor Ttr: Transmission Transistor

Claims

1. A solid-state imaging element comprising: a photoelectric conversion element for performing photoelectric conversion; a fully through-type element separation extending from a first main surface of a substrate to a second main surface and formed between pixels including the photoelectric conversion element; a first conductor portion disposed in close contact with the first main surface side of the fully through-type element separation; a high-concentration impurity diffusion layer formed on the first main surface of the substrate; and an insulating portion disposed between the first conductor portion and the high-concentration impurity diffusion layer; wherein the first conductor portion is embedded in a trench formed in the first main surface of the substrate.

2. The solid-state imaging element of claim 1, wherein the first conductor portion is formed deeper than the insulating portion; and the high-concentration impurity diffusion layer is formed shallower than the insulating portion.

3. The solid-state imaging element of claim 1, comprising: a well layer formed in a region deeper than the aforementioned high-concentration impurity diffusion layer; and the aforementioned first conductor portion being disposed in close contact with the aforementioned well layer in a region deeper than the aforementioned insulating portion.

4. The solid-state camera element of claim 3, comprising: a cover layer disposed in close contact with the first main surface side of the first conductor portion; and the first conductor portion being disposed in close contact with the well layer of an adjacent plurality of pixels.

5. The solid-state imaging element of claim 4, comprising: a contact electrode electrically connected to the well layer and formed within the pixel; wherein the contact electrode fixes the well layer of the plurality of pixels adjacent to each other through the first conductor portion at an input potential.

6. The solid-state camera element of claim 1, wherein the fully penetrating element is disposed separately from the pixel when viewed from above; and the first conductor portion is disposed in close proximity to the entire surface or a portion of the surface above the fully penetrating element.

7. The solid-state imaging element of claim 6, wherein the first conductor portion is disposed above at least one of the above-mentioned fully through-type element separation sandwiched between two adjacent pixels and above the above-mentioned fully through-type element separation located at the center of four pixels arranged in a 2×2 matrix.

8. The solid-state imaging element of claim 1, wherein the first conductor portion is a shape formed by embedding a portion or all of the groove on the bottom surface of the fully through-type element into a conductor material.

9. The solid-state imaging element of claim 1, wherein at least one surface of the insulating portion is formed of an insulating material.

10. The solid-state imaging element of claim 9, wherein the insulating portion is a two-layer structure consisting of an insulating film covering the surface of the trench disposed between the first conductor portion and the high-concentration impurity diffusion layer, and a pure polycrystalline silicon or oxide or air layer embedded in the trench.

11. The solid-state imaging element of claim 1, wherein the first conductor portion is a contact electrode shared by adjacent pixels.

12. A solid-state imaging element comprising: a photoelectric conversion element for performing photoelectric conversion; a fully through-type element separator extending from a first main surface of a substrate to a second main surface and formed between pixels including the photoelectric conversion element; a first conductor portion disposed close to the first main surface side of the fully through-type element separator; a high-concentration impurity diffusion layer formed on the first main surface of the substrate; an insulating portion disposed between the first conductor portion and the high-concentration impurity diffusion layer; a well layer formed in a region deeper than the high-concentration impurity diffusion layer; and a second conductor portion disposed close to a whole or part of a surface above the fully through-type element separator, configured to be deeper than the insulating portion and in contact with the well layer, attracting and capturing electrons accumulated in the photoelectric conversion element by applying a positive voltage; and the first conductor portion being embedded in a trench formed in the first main surface of the substrate. The first conductor portion is disposed in close contact with the well layer in a region deeper than the insulating portion.

13. An electronic device comprising: a solid-state imaging device, including: a solid-state imaging element having: a photoelectric conversion element for performing photoelectric conversion; a fully through-type element separation extending from a first main surface of a substrate to a second main surface and formed between pixels including the photoelectric conversion element; and a first conductor portion disposed in close contact with the first main surface side of the fully through-type element separation; an optical lens for imaging light from a subject onto the imaging surface of the solid-state imaging device; a signal processing circuit for processing signals output from the solid-state imaging device; a high-concentration impurity diffusion layer formed on the first main surface of the substrate; and an insulating portion disposed between the first conductor portion and the high-concentration impurity diffusion layer; wherein the first conductor portion is embedded in a trench formed in the first main surface of the substrate.

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