Apparatus including package

Abstract

In one embodiment, an apparatus includes a package. The package includes a substrate, a plurality of components on a top surface of the substrate, a plurality of ball pads on a bottom surface of the substrate, a plurality of solder balls, and a plurality of test pads on the bottom surface of the substrate. Individual solder balls of the plurality of solder balls are attached to individual ball pads of the plurality of ball pads.

Description

[Technical Field]

[0001] The various aspects of this case generally relate to semiconductor manufacturing, particularly to the elimination of the need to leave a portion of contacts (e.g., solder balls or pins) on integrated circuits for testing purposes by inkjet printing dedicated test pins for testing purposes. [Previous Technology]

[0002] In semiconductor packaging, dedicated connections (through-holes, etc.) are used for sensing (e.g., testing) power distribution networks (PDNs), power management ICs (PMICs), etc. In a single-chip or multi-chip module, multiple dies are placed together with multiple passive components and other components. The dies can be located on a substrate or within the package.

[0003] To test semiconductors, they are mounted on a test printed circuit board (PCB) and sensed to check voltage levels, current levels, etc., at specific points. Sensing is performed at various points, such as, for example, hard macros (which specify how the required logic elements are interconnected and define the physical paths and wiring patterns between elements), the logic of the PMIC, the logic of the application processor die, etc. A portion of the contacts (e.g., pins or solder balls) are used to expose the points where sensing is performed; these contacts are called test pins. Typically, about 9% of the semiconductor's contacts are dedicated to test pins.

[0004] After testing is complete, the test pins are no longer used. For example, when semiconductors are used in the manufactured product, test pins are not used. Therefore, since test pins are only used during testing, dedicating a portion of pins to test pins is a significant waste of pins. For semiconductor packages with limited pin counts, this is a waste of available pins. [Summary of the Invention]

[0005] The following is a simplified overview relating to one or more of the states disclosed herein. Thus, this overview should not be considered an exhaustive overview relating to all conceived states, nor should it be considered to identify key or decisive elements or illustrations relating to all conceived states that are associated with any particular state. Accordingly, the sole purpose of the following overview is to present, in a simplified form, certain concepts relating to one or more states of the mechanism disclosed herein before the detailed description provided below.

[0006] In a first embodiment, an apparatus includes a package. The package includes a substrate, a plurality of components on a top surface of the substrate, a plurality of ball pads on a bottom surface of the substrate, a plurality of solder balls, and a plurality of test pads on the bottom surface of the substrate. Individual solder balls among the plurality of solder balls are attached to individual ball pads among the plurality of ball pads. In some embodiments (e.g., prior to testing the package), individual test pins may be attached to individual test pads among the plurality of test pads. In other embodiments, solder resist may be applied to the individual test pads among the plurality of test pads to prevent access to the individual test pads.

[0007] In a second embodiment, a method for manufacturing a package may include the steps of: attaching a component to a top surface of a substrate; forming a plurality of ball pads on a bottom surface of the substrate; and attaching the plurality of solder balls to the plurality of ball pads. Individual solder balls among the plurality of solder balls are attached to individual ball pads among the plurality of ball pads. The method includes the step of forming a plurality of test pads on the bottom surface of the substrate. In some embodiments (e.g., before testing the package), individual test pins may be inserted into individual test pads among the plurality of test pads. In other embodiments, solder resist may be applied to the individual test pads among the plurality of test pads to prevent access to the individual test pads.

[0008] Other objectives and advantages associated with the various forms disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.

Implementation Method

[0020] This invention discloses a system and technique for inkjet printing multiple test pins between normal contacts (e.g., leads or solder balls) of a package using conductive paste. As used herein, the term "package" can refer to an element comprising one or more dies coupled to a substrate. In some cases, a package may be configured as one or more functional modules or system-on-a-chip (SoC) elements. Test pins have a height smaller than that of normal contacts. Solder balls (or leads) may have a height between about 135 μm and about 155 μm, while test pins may have a height between about 30 μm and about 50 μm. Test pins may be circular, elliptical, square, or rectangular, and each test pin has a length of about 50 μm to 100 μm and a width of about 50 μm to 100 μm. For ease of understanding, test pins are illustrated as having rectangles to distinguish them from solder balls (which may be circular or elliptical). Test pins may be rectangular (including square) or elliptical (including circular) to allow them to be squeezed into available space. These systems and technologies can be used with semiconductors employing ball grid array (BGA) pitch of 350 micrometers or larger. The advantage of this approach is that all pins in the package can be used to provide functionality, rather than dedicating up to 9% of the pins to testing purposes. Additional pins can be used to provide manufacturers with new functionalities when using the semiconductors in their manufactured products. Furthermore, the form factor of the package can be reduced by removing pins dedicated to testing.

[0021] Test pins are extruded onto the substrate between normal patterns used for contacts. Test pins replace dedicated test sensing pins in conventional semiconductors. Test pins are inkjet printed onto the substrate using conductive paste. Test pins are soldered onto the printed circuit board (PCB) for testing the semiconductor by simultaneously (1) attaching the test pins to the test PCB using a surface grid array (LGA) attachment and (2) using a BGA attachment mechanism for the contacts (e.g., pins or solder balls) of the package. Thus, test pins are generated for the semiconductor package to be tested on the test board. When the semiconductor package is manufactured for use in a product, the test pins are not inkjet printed onto the substrate. Test pads on which test pins are extruded during manufacturing and used to connect internal sensing lines are covered (e.g., using a solder mask or the like). Internally, the test pads are suspended or levitated on the final metal layer. Thus, the extruded test pins are not present in semiconductor packages designed to be included in a product. Thus, all normal contacts (e.g., pins or solder balls) are available for functional use, as no normal contacts are reserved for testing purposes.

[0022] When mounting a semiconductor package with extruded test pins on a test PCB, the test PCB has separate test attachment pads to connect to the extruded test pins. The semiconductor package with extruded test pins is mounted on the test PCB using both reflow and surface mount (SMT) attachments: (a) a BGA attachment mechanism for normal pins or solder balls and (b) an LGA attachment for the extruded test pins. Therefore, a single reflow process can be used to attach both normal package pins or solder balls and the extruded test pins. Semiconductor package contacts (e.g., pins or solder balls) can be added before or after the test pins are extruded onto the substrate.

[0023] Various forms of this case are provided below in the description of various examples provided for illustrative purposes and in the related drawings. Alternative forms may be designed without departing from the scope of this case. In addition, well-known elements in this case will not be described in detail or will be omitted so as not to obscure the relevant details of this case.

[0024] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance or illustration.” Any manner described herein as “exemplary” and / or “example” need not be construed as superior to or better than other manners. Similarly, the term “manners of this case” does not require that all manners of this case include the features, advantages or modes of operation discussed.

[0025] Those skilled in this art will understand that the information and signals described below can be represented using any of a variety of different techniques and skills. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the following description may be represented in part by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, depending on the specific application, the desired design, the corresponding technology, etc.

[0026] Furthermore, many aspects are described in the form of sequences of actions performed by elements of, for example, computing devices. It will be appreciated that the various actions described herein can be performed by special-purpose circuitry (e.g., application-specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, the sequences of actions described herein can be considered to be entirely embodied in any form of non-transitory computer-readable storage medium storing a corresponding set of computer instructions that, upon execution, will cause or instruct the associated processor of the device to perform the functions described herein. Thus, the various aspects of this application can be embodied in several different forms, all of which are contemplated to fall within the scope of the claimed object. Furthermore, for each aspect described herein, a corresponding form of any such aspect can be described herein as, for example, logic configured to perform the described actions.

[0027] As a first example, an apparatus (e.g., including a package, such as a system-on-a-chip) includes a substrate, a plurality of components on a top surface of the substrate, a plurality of ball pads on a bottom surface of the substrate, a plurality of solder balls, a plurality of test pads on the bottom surface of the substrate, and a plurality of test pins. Individual solder balls among the plurality of solder balls are attached to individual ball pads among the plurality of ball pads, and individual test pins are attached to individual test pads among the plurality of test pads. Individual test pins are lower in height than individual solder balls. Individual test pads among the plurality of test pads are located between adjacent solder balls of the plurality of solder balls. Individual test pads are located at approximately equidistant positions from adjacent solder balls. Individual test pins among the plurality of test pins are connected to one or more sensing lines. A surface grid array (LGA) is used to attach the plurality of test pins to a printed circuit board, and a ball grid array (BGA) is used to attach the plurality of solder balls to a printed circuit board. Individual test pins among a plurality of test pins are configured to be accessed to test one or more parameters of one or more of the following: power distribution network (PDN), power management IC (PMIC), or application processor die. The package is included in devices selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablets, computers, wearable devices, Internet of Things (IoT) devices, laptops, servers, base stations, access points, radio frequency (RF) modules, and devices in motor vehicles.

[0028] As a second example, a method for manufacturing a package includes the steps of: attaching a component to a top surface of a substrate; forming a plurality of ball pads on a bottom surface of the substrate; attaching the plurality of solder balls to the plurality of ball pads; forming a plurality of test pads on the bottom surface of the substrate; and attaching a plurality of test pins to the plurality of test pads. Individual solder balls among the plurality of solder balls are attached to individual ball pads among the plurality of ball pads, while individual test pins are attached to individual test pads among the plurality of test pads. The individual test pins are lower in height than the individual solder balls. The method may include the steps of: performing an organic solderability preservative (OSP) finish or performing an electrolytic nickel-gold (Ni-Au) finish (e.g., wherein a layer of gold is plated on an electroplated nickel substrate). The method may include the step of: applying solder resist to a pin attachment layer without covering the plurality of ball pads and the plurality of test pads. The method may include the step of: substantially simultaneously extruding and curing the plurality of test pins to the pin attachment layer. For example, individual test pins can be extruded and cured on top of individual test pads among a plurality of test pads. The method may include the steps of attaching a plurality of solder balls to a pin attachment layer. For example, an individual solder ball among a plurality of solder balls may be attached to an individual ball pad among a plurality of ball pads. In some cases, the test pins may be extruded and cured before attaching the plurality of solder balls, while in other cases, the test pins may be extruded and cured after attaching the plurality of solder balls. Essentially, extruding and curing a plurality of test pins to the pin attachment layer simultaneously may include using the nozzle of an inkjet printer to extrude conductive paste to create the plurality of test pins, and using a laser flash lamp to cure the plurality of test pins as they are extruded. A reflow process can be used to mount the package onto a printed circuit board (PCB). During this reflow, a plurality of test pins are attached to the PCB using an area grid array (LGA) attachment process, while a plurality of solder balls are attached to the PCB using a ball grid array (BGA) attachment process. Individual test pins of the plurality of test pins are connected to one or more sense lines within the package. For example, the package can be mounted on the PCB, and individual test pins can be used to access one or more sense lines. These sense lines can be used to test one or more parameters of at least one of the following: a power distribution network (PDN), a power management integrated circuit (PMIC), or an application processor die.

[0029] FIG1 is a block diagram illustrating a package 100 (e.g., a semiconductor) with inkjet-printed test pins according to various embodiments of the present invention. As used herein, the term "package" refers to an element comprising one or more dies coupled to a substrate. In some embodiments, the package may be configured as one or more functional modules or system-on-a-chip (SoC) elements. Package 100 includes a plurality of elements 102 located on top of substrate 104. Solder resist 106 is located on portions of the bottom surface of package 100. For example, in a location without solder resist 106, the bottom of package 100 includes a plurality of solder balls 108 and a plurality of test pins 110. Each test pin 110 is located approximately equidistant from adjacent solder balls 108. The test pins 110 enable access to sensing lines 112 inside package 100 to enable testing of power distribution networks (PDNs), power management ICs (PMICs), etc. For ease of understanding, test pin 110 is illustrated as having a rectangle to distinguish it from solder ball 108 (which has a circular or elliptical shape). However, it should be understood that test pin 110 can have any type of geometry (e.g., rectangular, elliptical, etc.).

[0030] Each solder ball 108 can be used to provide functionality for components in package 100, wherein none of the solder balls 108 are reserved for sensing or testing. The solder balls 108 can be arranged in a conventional pattern associated with, for example, ball grid array (BGA) or other types of packages. Of course, although solder balls 108 are illustrated in Figure 1, package 100 can also be mounted to a printed circuit board (PCB) using another type of contact (such as a pin).

[0031] Before or after adding solder balls 108 to package 100, test pins 110 are extruded onto the bottom of package 100 using conductive paste via an inkjet printer. The height of each test pin 110 is less than the height of each solder ball 108. Sensing lines 112 are connected from the die / package (e.g., active components) to test features (e.g., for PDN, PMIC, etc.). In some cases, sensing lines 112 may be connected from passive components (e.g., inductors / capacitors) to test features. Sensing lines 112 are illustrated in a cross-sectional view of package 100.

[0032] Therefore, prior to testing, test pins are extruded between the contacts (e.g., solder balls or pins) of the package using an inkjet printer. These test pins enable access to internal sense lines to perform various measurements during package testing. The advantage of using an inkjet printer to extrude test pins for testing is that all contacts of the package can be used to provide functionality and avoids the conventional approach of dedicating a portion (e.g., up to 9%) of the contacts to access internal sense lines. In the conventional approach, reserving a portion of contacts to access internal sense lines results in "reserved" contacts that are not used when the package is incorporated into a product. The extruded test pins can be used with access point (AP) modules, radio frequency (RF) modules, or any process module including a PMIC system. The extruded test pins can be used with single-die packages having PDN test sense lines.

[0033] Figure 2 is a block diagram 200 illustrating the mounting of a semiconductor with inkjet-printed test pins on a test PCB according to various embodiments of this invention. For testing package 100, package 100 can be mounted on a printed circuit board (PCB) specifically designed for testing package 100. The installation procedure is as follows.

[0034] The solder balls 108 of package 100 are aligned with the solder ball holders 204 on PCB 202. Solder paste 208 is printed on the PCB 202 above each of the openings of solder resist 210 on the pin holder 206. Each test pin 110 of package 100 is soldered to the pin holder 206 using solder paste 208.

[0035] Package 100 is mounted on test PCB 202 in a single reflow manner using the following two simultaneous processes: (a) attaching solder balls 108 to solder ball sockets 204 using a ball grid array (BGA) attachment mechanism 212; and (b) attaching extruded test pins 110 to pin headers 206 using an area grid array (LGA) attachment mechanism 214. Test pins 110 enable PCB 202 to access sense lines 112 to test various features of package 100. When package 100 is used in a manufactured product, test pins 110 are absent, thereby preventing access to sense lines 112.

[0036] Therefore, after the extruded test pins are added to the package, the package can be mounted onto the test PCB using both BGA and LGA attachment mechanisms with a simple reflow process. For example, attaching a package with test pins to a test PCB does not involve exotic, unusual, complex or expensive mechanisms.

[0037] Figures 3A, 3B, 3C and 3D illustrate a portion of a process for creating a semiconductor including ball pads and test pads according to various embodiments of the present invention. This process can be performed during the manufacture of a semiconductor package (such as package 100 of Figures 1 and 2).

[0038] FIG. 3A illustrates the construction of substrate 104. Substrate 104 may include multiple layers (e.g., 2 to 20 or more layers in some cases). Each layer of substrate 104 is added via various processes (e.g., cored substrate, coreless substrate, Ajinomoto deposited film (ABF) process, etc.). The construction of substrate 104 may include constructing each layer, such as lamination, patterning on Cu (copper), exposure, development, etc. The construction of substrate 104 may include adding sensing lines 112 to substrate 104.

[0039] Figure 3B illustrates the addition of ball pads 302 and test pads 304. Test pad 304 enables access to the sensing line 112 in the substrate 104. Figure 3C illustrates the addition of solder resist 106 (e.g., solder mask) to various portions of the upper surface of the substrate 104. Specifically, the solder resist 106 does not cover the ball pads 302 and the test pads 304, so that the solder balls and test pins can be attached to the substrate 104 at a later point in this process. Figure 3D illustrates the addition of components 102 on the opposite side to the ball pads 302 and test pads 304.

[0040] A portion of the procedure illustrated in Figures 3A, 3B, 3C, and 3D may be performed using the procedure shown in Figures 4A, 4B, and 4C, or the procedure shown in Figures 5A, 5B, and 5C. For ease of understanding, the sensing line 112 is not illustrated in the remaining figures, but it should be understood that the sensing line 112 is present in Figures 4A, 4B, and 4C, as well as Figures 5A, 5B, and 5C.

[0041] Figures 4A, 4B and 4C illustrate the remainder of the semiconductor building process, in which test pins are squeezed in before the attached solder balls, according to various embodiments of the present invention.

[0042] Figure 4A illustrates the use of an inkjet printer 402 to extrude conductive paste 404 via sintering to create test pins 110 on top of test pads 304. Sintering (also known as etching) is a process that involves compacting and forming a solid block, such as each test pin 110, using the extruded conductive paste 404. Preferably, the test pins 110 are extruded after a surface mount technology (SMT) process. A laser flash lamp 406 is used to cure the test pins 110, for example, without the need for oven curing. The test pins 110 are printed and cured substantially simultaneously so that each test pin 110 can maintain its vertical shape and geometry. The laser flash lamp 406 uses photonic curing, i.e., a process in which the extruded conductive paste 404 is exposed to pulsed light from the laser flash lamp 406 for approximately 1 millisecond (ms).

[0043] The height H1 406 of each test pin 110 is less than the height H2 408 of each solder ball 108. Figure 4B illustrates the printing of solder paste 208 on each pin socket 206 before the package 100 is mounted to the PCB 202. Figure 4C illustrates the package 100 mounted to the test PCB 202, wherein each solder ball 108 is attached to a corresponding solder ball socket 204 (e.g., using BGA attachment mechanism 212) and each test pin 110 is attached to a corresponding pin socket 206 (e.g., using LGA attachment mechanism 214).

[0044] Figures 5A, 5B, and 5C illustrate the remainder of the semiconductor fabrication process according to various embodiments of the present invention, in which test pins are inserted after the solder balls are attached. Figure 5A illustrates attaching each solder ball 108 to each ball pad 302.

[0045] Figure 5B illustrates the use of an inkjet printer 402 to extrude conductive paste 404 via sintering to create test pins 110 on top of test pads 304. Preferably, the test pins 110 are extruded after performing a surface mount technology (SMT) process. A laser flash lamp 406 is used to cure the test pins 110, for example, without the need for oven curing. The test pins 110 are printed and cured substantially simultaneously so that each test pin 110 can maintain its vertical shape and geometry. The height H1 406 of each test pin 110 is less than the height H2 408 of each solder ball 108. Figure 5B illustrates the placement of solder paste 208 on each pin header 206 before mounting the package 100 onto the PCB 202. Figure 5C illustrates package 100 mounted to test PCB 202, wherein each solder ball 108 is attached to a corresponding solder ball socket 204 (e.g., using BGA attachment mechanism 212) and each test pin 110 is attached to a corresponding pin socket 206 (e.g., using LGA attachment mechanism 214).

[0046] Figures 6A and 6B illustrate various embodiments of the present invention involving the application of solder resist during semiconductor manufacturing, while keeping the solder ball attachments open and covering the pin attachments to allow the solder balls to be attached. Figure 6A illustrates the application of solder resist 106 during semiconductor manufacturing, such that the ball pads 302 are open (e.g., uncovered), and the test pads 304 are covered with solder resist 106. This is done during manufacturing, for example, in a package to be incorporated into a product (e.g., not attached to a test PCB for testing purposes). Figure 6B illustrates the attachment of two solder balls 108 to two corresponding ball pads 302. The test pads 304 remain covered with solder resist 106, making the sensing lines (e.g., representative sensing lines 306 such as those in Figure 3B) inaccessible.

[0047] In the flowcharts of Figures 7 and 8, each block represents one or more operations that can be implemented in hardware, software, or a combination thereof. In the context of software, these blocks represent computer-executable instructions that, when executed by one or more processors, cause the processors to perform the operations. Generally, computer-executable instructions include routines, programs, objects, modules, elements, data structures, etc., that perform a particular function or implement a particular type of abstract data. The order in which the blocks are described is not intended to be construed as limiting, and any number of described operations can be combined and / or performed in parallel in any order to implement the programs. For illustrative purposes, programs 700 and 800 described above with reference to Figures 1, 2, 3A-3C, 4A-4C, 5A-5C, and 6A-6B may be implemented using other models, frameworks, systems, and environments.

[0048] Figure 7 illustrates a procedure 700 according to the present invention, which includes attaching a plurality of test pins to a plurality of test pads. This procedure can be executed as part of a semiconductor manufacturing process, the parts of which are described herein.

[0049] At 702, the process attaches the component to the top surface of the substrate. For example, in FIG3D, component 102 is attached to substrate 104.

[0050] At 704, a plurality of ball pads are formed on the bottom surface of the substrate. At 706, the process attaches the plurality of solder balls to the plurality of ball pads (e.g., where individual solder balls are attached to individual ball pads). For example, in Figures 4B and 5A, individual solder balls 108 are formed and attached to individual ball pads in ball pad 302.

[0051] At 708, the process forms a plurality of test pads on the bottom surface of the substrate. For example, in FIG. 3B, test pads 304 are formed on substrate 104. As illustrated in FIG. 6A, if the package is to be used in the manufactured product, the process may cover the test pads 304 with solder resist 106. If the package is to be used for testing, the process may push test pins 110 onto the test pads 304, as illustrated in FIG. 4A and FIG. 5B.

[0052] Therefore, the package is manufactured with test pads. Before testing the package, test pins are extruded between the contacts (e.g., solder balls or leads) of the package using an inkjet printer. When testing the package, the test pins enable access to internal sensing lines to determine various parameters. The technical advantage of using an inkjet printer to extrude test pins for testing is that all contacts of the package can be used to provide functionality, rather than dedicating a portion (e.g., up to 9%) of the contacts to access the internal sensing lines. By not reserving a portion of the contacts for accessing the internal sensing lines, all contacts can be used when the package is incorporated into a product. In some cases, as a further technical advantage, not reserving a portion of the contacts can reduce the number of contacts, thereby reducing the form factor of the package. As the size of consumer products (such as user equipment (UE)) shrinks, the form factor of the package used in the UE can be reduced without reducing functionality. Alternatively, as a further technical advantage, using all contacts in the package can enable the provision of additional functions. The extruded test pins can be used with, for example, access point (AP) modules, radio frequency (RF) modules, or any process module including a PMIC system. The extruded test pins can also be used with, for example, a single die package with PDN test sensing lines. After testing is complete and the package is ready for manufacturing, the test pads are covered with solder resist. The advantage of covering the test pads with solder resist when the package is manufactured for inclusion in a product (e.g., user equipment) is that the solder resist prevents access to the test pads and the internal sensing lines within the package.

[0053] Figure 8 illustrates a process 800 according to the present invention, including printing test pins using inkjet printing. This process can be executed as part of a semiconductor manufacturing process, the parts of which are described herein.

[0054] At 802, the process constructs a semiconductor substrate, including adding a pin attachment layer, electroplating and patterning for the sensing lines and test pads. For example, in FIG3B, a substrate 104 is used to construct the semiconductor and add a pin attachment layer (e.g., a final metal layer), copper (Cu) electroplating, and patterning. The process includes adding test pads 304 and ball pads 302.

[0055] At 804, the procedure deposits a solder mask without covering the ball pads and test pads. At 806, the procedure completes the surface. For example, in Figure 3C, solder resist 106 is added without covering the ball pads 302 and test pads 304. The entire surface is completed using an organic solderability preservative (OSP), an electrolytic nickel-gold finish (e.g., plating a layer of gold on an electroplated nickel substrate), or a similar method.

[0056] At 808, the process adds components and cut-up assemblies to the substrate. For example, in FIG3D, component 102 is added to substrate 104.

[0057] In some cases (e.g., test pins are extruded before attaching solder balls), at 810, the procedure uses inkjet printing to print the test pins to a height H1. At 812, the procedure attaches solder balls to a height H2 (H1 < H2). For example, in Figures 4A and 4B, an inkjet printer 402 is used to extrude conductive paste 404 using sintering to create test pins 110 on test pads 304. The test pins 110 are essentially cured using a laser flash lamp 406 while being printed. After the test pins 110 have been printed and cured, each solder ball 108 is attached to a corresponding ball pad 302.

[0058] In other configurations (e.g., extruding test pins after attaching solder balls), at 814, the procedure attaches solder balls having a height H2. At 816, the procedure is performed via printing test pins having a height H1 (H1 < H2) using an inkjet printer (e.g., extruding test pins using conductive paste). For example, in Figures 5A and 5B, a single solder ball 108 is attached to a corresponding ball pad 302. After the solder ball 108 is attached, an inkjet printer 402 is used to extrude conductive paste 404 using a sintering process to create test pins 110 on the test pads 304. The test pins 110 are essentially cured using a laser flash lamp 406 while being printed.

[0059] At 818, the procedure prints solder paste onto the pin sockets on the test board. At 820, the semiconductor is attached to the test board. At 822, the test is performed by accessing the sensing lines in the semiconductor using test pins. For example, in Figures 4B, 4C, 5B, and 5C, solder paste 208 is applied to each pin socket 206 of the PCB 202. Package 100 is mounted to the test PCB 202, wherein each solder ball 108 is attached to a corresponding solder ball socket 204 (e.g., using BGA attachment mechanism 212) and each test pin 110 is attached to a corresponding pin socket 206 (e.g., using LGA attachment mechanism 214).

[0060] Therefore, a package including test pads is manufactured. Before testing the package, test pins are extruded between the contacts (e.g., solder balls or leads) of the package using an inkjet printer. During package testing, the test pins enable access to internal sense lines to determine various parameters. One technical advantage of using an inkjet printer to extrude test pins is that all contacts of the package can be used to provide functionality, thus avoiding dedicating a portion (e.g., up to 9%) of the contacts to access the internal sense lines. The package size may be reduced when fewer contacts are used, or when the manufacturer provides access to additional functionality via contacts previously reserved for testing. After testing is complete and the package is ready to be manufactured for inclusion in a consumer product (e.g., user equipment), the test pads are covered with solder resist. One technical advantage of the solder resist is that it prevents access to the test pads and internal sense lines.

[0061] FIG9 illustrates an exemplary mobile device incorporated into a System-on-Chip (SOC) 900 according to some embodiments of the present invention. In some cases, the mobile device of FIG9 may be configured as a wireless communication device. As shown, the mobile device of FIG9 includes a processor 901. The processor 901 may be communicatively coupled to memory 932 via a link, which may be a die-to-die or chip-to-chip link. The processor 901 is a hardware device capable of executing logic instructions. The mobile device of FIG9 also includes a display 928 and a display controller 926, wherein the display controller 926 is coupled to the processor 901 and the display 928.

[0062] In some embodiments, FIG9 may include a decoder / decoder (CODEC) 934 (e.g., an audio and / or voice CODEC) coupled to processor 901; a speaker 936 and a microphone 938 coupled to CODEC 934; and a wireless circuit 940 (which may include a modem, RF circuitry, filters, etc., which may be implemented using solder ball socket 204 and pin header 206) coupled to wireless antenna 942 and processor 901.

[0063] In a particular configuration, with one or more of the aforementioned blocks present, the processor 901, display controller 926, memory 932, CODEC 934, and wireless circuitry 940 may be included in the SOC 900, which may be implemented wholly or partially using the pin header 206 and solder ball header 204 disclosed herein. The input device 930 (e.g., a physical or virtual keyboard), power supply 944 (e.g., a battery), display 928, speaker 936, microphone 938, wireless antenna 942, and power supply 944 may be located external to the SOC 900 and may be coupled to components of the SOC 900, such as interfaces or controllers.

[0064] One or more components (such as processor 901, memory 932, display controller 926, wireless circuit 940, and codec 934) can be manufactured using the systems and techniques described herein, for example, when the components are mounted on a test PCB for testing, inkjet-printed test pins are used to access the internal sensing lines of the components. When the components are manufactured and already included in a product (such as the mobile device of FIG. 9), test pins may not be printed.

[0065] It should be noted that although Figure 9 illustrates a mobile device, the processor 901 and memory 932 may also be integrated into a set-top box, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, laptop, tablet computer, communication device, mobile phone or other similar device.

[0066] Figure 10 illustrates various electronic devices that can be integrated with any of the aforementioned integrated components or semiconductor packages according to various embodiments of the present invention. For example, mobile phone device 1002, laptop computer device 1004, and fixed-location terminal device 1006 can each generally be considered as user equipment (UE) and may include the package 1000 described herein. Package 1000 can be, for example, any of the integrated circuit, die, integrated component, integrated component package, integrated circuit element, component package, integrated circuit (IC) package, and stacked package element described herein. Devices 1002, 1004, and 1006 illustrated in Figure 10 are merely exemplary. Other electronic devices may also be characterized by package 1000, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0067] It can be noted that although specific frequencies, integrated circuits (ICs), hardware, and other features are described in the various embodiments herein, the alternative embodiments may be different. That is, the alternative embodiments may utilize additional or alternative frequencies (e.g., in addition to the 60 GHz and / or 28 GHz bands), antenna elements (e.g., antenna element arrays of different sizes / shapes), scanning periods (including static and dynamic scanning periods), electronic devices (e.g., WLAN APs, cellular base stations, smart speakers, IoT devices, mobile phones, tablets, personal computers (PCs), etc.), and / or other features. Such variations will be appreciated by those skilled in the art.

[0068] It should be understood that any reference to elements using designations such as "first," "second," etc., herein does not generally limit the number or order of such elements. Rather, such designations may be used herein as a convenient way to distinguish two or more elements or examples of elements. Therefore, a reference to the first element and the second element does not imply that only two elements may be used herein, or that the first element must in some way precede the second element. Moreover, unless otherwise stated, a group of elements may include one or more elements. Additionally, terms in the form of "at least one of A, B, or C," "one or more of A, B, or C," or "at least one of a group including A, B, and C" as used in the specification or claim indicate "A or B or C or any combination of such elements." For example, this term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, etc.

[0069] In view of the foregoing description and explanation, those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative elements, blocks, modules, circuits, and steps described above are generalized in their functional form. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as deviating from the scope of this work.

[0070] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to suggest that the exemplary clauses have more features than those explicitly mentioned in each clause. Rather, the various forms of this document may include fewer features than those of the individual exemplary clauses disclosed. Therefore, the following clauses should thus be considered as incorporated into this description, where each clause may be a separate instance. Although each dependent clause may refer in its respective clause to a specific combination with one of the other clauses, the form of that dependent clause is not limited to that specific combination. It will be appreciated that other exemplary clauses may also include combinations of the form of a dependent clause with the subject matter of any other dependent or independent clause, or any feature combined with other dependent and independent clauses. The various forms disclosed herein explicitly include such combinations unless explicitly stated or readily inferred that a particular combination is not desired (e.g., contradictory forms, such as defining an element as both an insulator and a conductor). Furthermore, it is intended that various forms of clauses may be included in any other independent clause, even if that clause is not directly subordinate to that independent clause. Examples of implementation are described in the following numbered clauses.

[0071] Clause 1. A method of manufacturing a package, the method comprising the steps of: attaching a component to a top surface of a substrate; forming a plurality of ball pads on a bottom surface of the substrate; attaching a plurality of solder balls to the plurality of ball pads, wherein an individual solder ball among the plurality of solder balls is attached to an individual ball pad among the plurality of ball pads; and forming a plurality of test pads on the bottom surface of the substrate.

[0072] Clause 2. The method of Clause 1 further includes the steps of: attaching a plurality of test pins to a plurality of test pads, wherein an individual test pin is attached to an individual test pad among the plurality of test pads, and wherein the individual test pin is lower in height than an individual solder ball.

[0073] Clause 3. The method of Clause 2 further includes the steps of: applying solder resist to the pin attachment layer, wherein a plurality of ball pads and a plurality of test pads are not covered by solder resist; and substantially simultaneously extruding and curing a plurality of test pins into and onto the pin attachment layer, wherein an individual test pin is extruded and cured on top of an individual test pad among the plurality of test pads.

[0074] Clause 4. The method of Clause 3, wherein substantially simultaneously extruding and curing a plurality of test pins into and onto the pin attachment layer comprises: extruding conductive paste using the nozzle of an inkjet printer to establish a plurality of test pins; and curing the plurality of test pins using a laser flash lamp while the plurality of test pins are being extruded.

[0075] Clause 5. The method of any of Clauses 2 to 4, wherein a reflow process is used to mount the package onto a printed circuit board (PCB), the reflow process comprising: attaching a plurality of test pins to the PCB using a surface grid array (LGA) attachment process; and attaching a plurality of solder balls to the PCB using a ball grid array (BGA) attachment process.

[0076] Clause 6. The method of any one of Clauses 2 to 5, wherein an individual test pin of the plurality of test pins is connected to one or more sensing lines located in the package.

[0077] Clause 7. The method of Clause 6 further includes the steps of: mounting the package on a printed circuit board (PCB); and accessing one or more sensor lines using one or more individual test pins.

[0078] Clause 8. The method of Clause 7 further includes the step of testing one or more parameters of at least one of the following using one or more sensing lines: power distribution network (PDN), power management integrated circuit (PMIC), or application processor die.

[0079] Clause 9. The method of any one of Clauses 2 to 8, wherein each of the plurality of test pins has a height between about 30 micrometers and about 50 micrometers.

[0080] Clause 10. The method of any of Clauses 2 to 9, wherein the plurality of test pins have a generally circular, elliptical, square or rectangular shape.

[0081] Clause 11. The method of any one of Clauses 2 to 10, wherein at least one of the plurality of test pins is located between four adjacent solder balls of the plurality of solder balls.

[0082] Clause 12. The method of any of Clauses 1 to 11 further includes the following steps: performing an organic solderability preservative (OSP) finish or performing an electrolytic nickel-gold (Ni-Au) finish, wherein a layer of gold is plated on an electroplated nickel substrate.

[0083] Clause 13. The method of any of Clauses 1 to 12, wherein each of the plurality of solder balls has a height between about 135 micrometers and about 155 micrometers.

[0084] Clause 14. The method of any of Clauses 1 to 13, wherein the package includes a system-on-a-chip (SOC).

[0085] Clause 15. The method of any one of Clauses 1 to 14, wherein the package is incorporated in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, Internet of Things (IoT) devices, laptops, servers, base stations, and motor-based devices in motor vehicles.

[0086] Accordingly, it will be understood that, for example, a device or any element of a device may be configured (or adapted to operate for or be suited to) provide the functionality taught herein. This may be achieved, for example, by manufacturing (e.g., fabricating) the device or element to provide the functionality; by programming the device or element to provide the functionality; or by using some other suitable implementation technique. As an example, an integrated circuit may be fabricated to provide the necessary functionality. As another example, an integrated circuit may be fabricated to support the necessary functionality and subsequently (e.g., by programming) configured to provide the necessary functionality. As yet another example, processor circuitry may execute code to provide the necessary functionality.

[0087] Furthermore, the methods, sequences, and / or algorithms described herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage media known in the art. Exemplary storage media are coupled to a processor so that the processor can read and write information from / to the storage media. In an alternative, the storage media can be integrated into the processor (e.g., cache memory).

[0088] Although the foregoing disclosure presents various illustrative examples, it should be noted that various changes and modifications may be made to the illustrated examples without departing from the scope defined in the appended claims. This case is not intended to be limited to the specific illustrated examples. For example, unless otherwise stated, the functions, steps, and / or actions in the method claims of the various examples of this case described herein need not be performed in any particular order. Furthermore, although some examples may be described or claimed in the singular, the plural is also contemplated unless explicitly stated to be limited to the singular. [Simplified Explanation of the Diagram]

[0009] The accompanying drawings are provided to aid in describing the various aspects of this application, and are provided merely for illustrative purposes and not for limitation. A more complete understanding of this application can be obtained by referring to the following detailed description in conjunction with the drawings. In the drawings, the leftmost digit(s) of the element symbol indicates the drawing in which the element symbol first appears. Identical element symbols in different drawings indicate similar or identical items.

[0010] Figure 1 is a block diagram illustrating a semiconductor with inkjet-printed test pins according to various states of this case.

[0011] Figure 2 is a block diagram illustrating the mounting of a semiconductor with inkjet-printed test pins on a test PCB according to various states of this case.

[0012] Figures 3A, 3B, 3C and 3D illustrate a part of the procedure for establishing a semiconductor including ball pads and test pads according to various forms of the present invention.

[0013] Figures 4A, 4B and 4C illustrate the remainder of the semiconductor building process, in which test pins are squeezed in before the attached solder balls, according to various embodiments of the present invention.

[0014] Figures 5A, 5B and 5C illustrate the remainder of the semiconductor building process according to various embodiments of the present invention, in which test pins are inserted after the solder balls are attached.

[0015] Figures 6A and 6B illustrate the application of solder resist during semiconductor manufacturing according to various embodiments of the present invention, while keeping the solder ball attachment open and covering the pin attachment so that the solder ball can be attached.

[0016] Figure 7 illustrates a procedure according to the present invention, including attaching a plurality of test pins to a plurality of test pads.

[0017] Figure 8 illustrates the procedure for printing test pins using inkjet printing according to various embodiments of this case.

[0018] Figure 9 illustrates an exemplary mobile device according to one or more states of this case.

[0019] Figure 10 illustrates various electronic devices that can be integrated with integrated components or semiconductor components according to one or more forms of this invention. [Biomaterial Storage]

[0090] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A device comprising an encapsulation, the encapsulation comprising: One substrate; A plurality of elements located on a top surface of the substrate, the elements comprising at least one grain; A plurality of ball pads located on a bottom surface of the substrate; a plurality of solder balls, wherein individual solder balls are attached to individual ball pads among the plurality of ball pads; a plurality of test pads located on the bottom surface of the substrate; a plurality of test pins, wherein individual test pins are attached to individual test pads among the plurality of test pads, and the individual test pins are lower in height than the individual solder balls; and wherein the cross-sectional area of ​​each test pad among the plurality of test pads is smaller than the cross-sectional area of ​​each ball pad among the plurality of ball pads.

2. The apparatus of claim 1, wherein each of the plurality of test pins has a pin height between about 30 micrometers and about 50 micrometers.

3. The apparatus of claim 2, wherein each of the plurality of solder balls has a solder ball height between about 135 micrometers and about 155 micrometers.

4. The apparatus of claim 1, wherein the plurality of test pins includes: Conductive paste.

5. The apparatus of claim 1, wherein the plurality of test pins are configured as a gate array (LGA) and wherein the plurality of solder balls are configured as a ball grid array (BGA).

6. The apparatus of claim 1, wherein each of the plurality of test pins is coupled to an application processor die.

7. The apparatus of claim 1, wherein each of the plurality of test pads has a circular, elliptical, square or rectangular shape.

8. The apparatus of claim 1, wherein at least one of the plurality of test pads is located at equidistant positions of four adjacent solder balls among the plurality of solder balls.

9. The apparatus of claim 1, wherein an individual test pad of the plurality of test pads is connected to one or more sensing lines in the package.

10. The apparatus of claim 1, wherein an individual test pad among the plurality of test pads is coupled to a power distribution network (PDN).

11. The apparatus of claim 1, wherein an individual test pad of the plurality of test pads is coupled to a power management integrated circuit (PMIC).

12. The apparatus of claim 1, wherein the package includes a system-on-a-chip (SoC).

13. The device as claimed in claim 1, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device in a motor vehicle.

14. The apparatus of claim 1, wherein the plurality of test pads are offset relative to the plurality of ball pads in both the vertical and horizontal directions.

15. The apparatus of claim 1, wherein the plurality of test pads are positioned within the standard spacing of the ball pads.

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