Multi-port memory and method of operating the same

Abstract

A multi-port memory is provided that supports conflicts between the read and write ports of the same multi-port bit cell. When the write port of the multi-port bit cell is addressed during the system clock signal, the sense amplifier reads data bits from the multi-port bit cell. If the read port of the multi-port bit cell is addressed during the same system clock signal, the multiplexer selects the output bits from the sense amplifier.

Description

Technical Field

[0001] This case concerns memory, and more specifically, high-speed multi-port memory that supports conflicts. Prior Technology

[0002] Static Random Access Memory (SRAM) bit cells consist of a pair of cross-coupled inverters for storing bits. Each inverter requires two transistors, therefore four transistors are needed to implement these two cross-coupled inverters. In a typical single-port SRAM bit cell, two additional access transistors complete the implementation of the bit cell, bringing the total number of transistors required to six. These two access transistors are controlled by a shared word line, allowing them to form a single read / write port for the bit cell. However, the single-port architecture can be problematic for multiprocessor applications due to contention between multiple processors at a single access port. By adding additional access transistors, multi-port SRAM bit cells can have an access (read) port for each processor.

[0003] While multi-port SRAM is advantageous for multiprocessor architectures, conflicts can occur if write and read operations happen simultaneously at the same multi-port SRAM bit cell. To avoid conflicts, multi-port SRAM bit cells are typically accessed in a "dual-pump" manner relative to the system clock signal that controls memory access. In response to a transition in the system clock signal (e.g., a rising edge), a read operation on one or more access ports can occur during the first part of the system clock cycle. After the read operation is completed, a write operation can then occur in the second part of the system clock cycle. However, dual-pump operation slows down memory speed because write and read operations must occur sequentially within the system clock cycle. Summary of the Invention

[0004] According to one aspect of the present invention, a multi-port memory is provided, comprising: a multi-port bit unit, the multi-port bit unit including a first read port having a first read port bit line, the multi-port bit unit further including a write port bit line pair; a sense amplifier coupled to the write port bit line pair; a first inverter coupled to the first read port bit line; and a first multiplexer configured to: select between data output bits from the sense amplifier and data output bits from the first inverter to provide a selected data output bit.

[0005] According to another aspect of the present case, a method for operating a multi-port memory is provided, comprising: comparing a first read port address with a write port address to detect a first conflict in response to the first read port address matching the write port address and to detect no first conflict in response to the first read port address not matching the write port address; at a first multiplexer, in response to detecting no first conflict, selecting data output bits generated by a single-ended read of the multi-port bit cell via the first read port; and at the first multiplexer, in response to detecting the first conflict, selecting data output bits generated by a differential read of the multi-port bit cell via the write port.

[0006] According to another aspect of the present case, a multi-port memory is provided, comprising: a multi-port bit unit, the multi-port bit unit including a first read port having a first read port bit line and a first read port word line, the multi-port bit unit further including a write port having a write bit line pair; an address comparator configured to: detect a conflict in response to a write port address pointing to the write port and a read port address pointing to the first read port; and a read port word line controller configured to: assert the first read port word line in response to no conflict being detected, and not assert the first read port word line in response to the detection of the conflict.

[0007] According to another aspect of the present invention, a multi-port memory is provided, comprising: an address comparator configured to detect a conflict in response to both a read port address and a write port address pointing to a first multi-port bit cell; a sense amplifier configured to read a first data bit from the first multi-port bit cell via a write port; a write driver configured to write a second data bit to the first multi-port bit cell via the write port after the first data bit has been read; and a multiplexer coupled to the sense amplifier configured to select the first data bit in response to the detection of the conflict.

[0008] These advantages and other benefits can be better understood through the following specific implementation methods. Simple Explanation of the Diagram

[0009] Figure 1 illustrates an exemplary multi-port bit cell for practicing the conflict-supported multi-port memory disclosed herein.

[0010] Figure 2 is a flowchart of an exemplary implementation for conflict support based on the content of this case.

[0011] Figure 3 is a circuit diagram of a multi-port memory configured to provide conflict support, according to the content of this case.

[0012] Figure 4 is a flowchart of a method for conflict support operations based on the content of this case.

[0013] Figure 5 illustrates some exemplary electronic systems that are incorporated into a multi-port system with conflict support, according to the content of this case.

[0014] The embodiments and advantages of this invention are best understood by referring to the following detailed description. It should be understood that similar element symbols are used to identify similar elements shown in one or more of the accompanying drawings. Implementation

[0015] This paper discloses a multi-port SRAM that supports collision avoidance instead of, for example, using dual-pump operation. To support collision avoidance, the memory includes an address comparator for each read port. Each address comparator compares the read port address with the write port address. If the comparison indicates that the read port address points to a first multi-port memory location and the write port address points to a second multi-port memory location, a single-ended read operation is performed on the first multi-port memory location via the read port. Simultaneously, a write operation is performed on the second multi-port memory location via the write port. High-speed operation is enhanced due to the simultaneous operation of the read and write ports (although in different multi-port memory locations).

[0016] However, if the address comparison indicates that the read port address and write port address point to the same multi-port bit cell, the read port is not accessed. To perform a read, multi-port SRAM utilizes the speed difference between single-ended read operations and differential read operations. For this purpose, write operations are delayed until a differential read occurs via the write port. Therefore, this differential read operation occurs every time the write port is accessed. Although the write operation is delayed to allow differential reads to occur first, it does not affect the memory operation speed because single-ended reads via the read port are not as fast as differential reads. Differential read and write operations (which are also differential) can therefore be completed in approximately the same amount of time as single-ended read operations. Note the advantage: if there is no conflict in the multi-port bit cell, single-ended read operations can continue. On the other hand, for multi-port bit cells with conflicts, differential reads occur. Therefore, there is no delay as would occur in the dual-pump method.

[0017] Exemplary multi-port bit cells will now be discussed, but it will be understood that SRAMs with any suitable multi-port bit cell architecture can practice the conflict support disclosed herein. Furthermore, the exemplary multi-port bit cells below have a pair of read ports, but in alternative embodiments, a multi-port bit cell may include only one read port. Therefore, a multi-port SRAM bit cell includes at least one read port in addition to a write port. The write and read ports can be better understood by considering the exemplary three-port SRAM bit cell 100 shown in FIG1. ​​The write port includes a write port access n-type metal-oxide-semiconductor (NMOS) transistor M3 and another write port access NMOS transistor M4. A write word line (WWL) is connected to the gates of the write port access transistors M3 and M4 such that the write port access transistors are turned on when the write word line is charged to the supply voltage. The write port also includes a write bit line pair formed by a true write bit line (WBL) and a complementary write bit line (WBLB). For simplicity, in the following discussion, the true write bit line can also be simply referred to as the write bit line. The write bit line WBL is connected to the drain / source terminals of the write port access transistor M3. The remaining drain / source terminals of the write port access transistor M3 are connected to the Q data output node of the bit cell 100. These terminals are called "drain / source" terminals because which terminal is the source and which is the drain depends on the binary state of the SRAM bit cell 100 before the write operation and also on the binary state of the bits written to the SRAM bit cell 100 during the write operation. The complementary write bit line WBLB is arranged similarly, as it is connected to the drain / source terminals of the write port access transistor M4. The remaining drain / source terminals of the write port access transistor M4 are connected to the complementary data output node QB of the SRAM bit cell 100.

[0018] Before a write operation, write bit lines WBL and WBLB are pre-charged to the supply voltage. The write operation occurs in response to an edge of the system clock signal (e.g., a rising edge). A word line generator or controller (not shown in Figure 1, but discussed further below) responds to the clock edge by charging the write word line WWL to the supply voltage, thus enabling the write port access transistor. With the write word line asserted, the write driver (also not shown in Figure 1, but discussed further below) can then drive the write bit line pair using the data bits to be written to the multi-port bit cell. If the binary value of the data bit is true, the write driver discharges the complementary write bit line WBLB while keeping the true write bit line WBL charged. Conversely, in response to a false data bit, the write driver discharges the true write bit line WBL while keeping the complementary write bit line WBLB charged.

[0019] The specific output node of SRAM cell 100 that is charged to the supply voltage or discharged to ground depends on which write bit line is charged and which is discharged to ground by the write driver. For example, if the write bit line remains charged during a write operation, the Q output node is charged while the complementary QB output node is discharged. The Q output node is also the output node of a first inverter that is cross-coupled to a second inverter in SRAM cell 100. The first inverter includes a p-type metal-oxide-semiconductor (PMOS) transistor P1, the source of which is connected to a supply node to obtain the supply voltage. The drain of transistor P1 is connected to the drain of an NMOS transistor M1. The source of transistor M1 is connected to ground. The drains of transistors P1 and M1 form the output node of the first inverter and also form the Q output node of cell 100.

[0020] The second inverter is similarly arranged and therefore includes a PMOS transistor P2, the source of which is connected to the power supply node and the drain of an NMOS transistor M2, the source of which is connected to ground. The drains of transistors P2 and M2 form the output node of the second inverter and also form the QB output node. To complete the cross-coupling between the inverters, the Q output node is connected to the gates of transistors P2 and M2. Similarly, the QB output node is connected to the gates of transistors P1 and M2. The two inverters thus reinforce each other and latch the bits being written into the SRAM bit cell 100.

[0021] The first read port A of SRAM cell 100 includes an NMOS transistor M5, an NMOS access transistor M6, a read port A bit line A (RBLA), and a read port A word (RWLA). The read port A bit line RBLA is connected to the drain of the access transistor M6. The source of the access transistor M6 is connected to the drain of the transistor M5. The source of the transistor M5 is connected to ground. The Q output node is connected to the gate of the transistor M5. The read port A word line RWLA is connected to the gate of the access transistor M6. Before a read operation on read port A, the read port A bit line RBLA is pre-charged to the power supply voltage. The read port A bit line RBLA is then floated to read port A during a single-ended read operation, so that the bit line voltage may be affected by a single-ended read operation on SRAM cell 100 via read port A. During a single-ended read operation on read port A, the read port A word line RWLA is charged to the power supply voltage to turn on the access transistor M6. If the Q output node has been charged to the supply voltage before the read operation on port A, transistor M5 will be turned on to discharge the source of transistor M6. As access transistor M6 is turned on by the assertion of the read port A word line RWLA, the read port A bit line RBLA will subsequently discharge via transistors M5 and M6. Since the read operation on port A is single-ended (it involves only one read bit line), a sense amplifier for sensing the binary contents of SRAM cell 100 via read port A can be formed by a simple inverter (not shown in Figure 1, but discussed further below). When the read port A bit line RBLA discharges to the switching point of the sense amplifier inverter, the sense amplifier inverter asserts its output signal to the supply voltage to successfully represent the binary one being read from SRAM cell 100. Since the sense amplifier inverters disclosed herein are all formed by inverters acting as sense amplifiers, the sense amplifier inverters can also be simply represented as inverters herein.

[0022] If SRAM bit cell 100 alternatively stores a binary zero, the Q output node will discharge before the read operation. In this case, transistor M5 will be turned off so that the read port A bit line RBLA remains precharged during the read operation on read port A. Therefore, the sense amplifier inverter will continue to discharge its output signal to indicate the binary zero being read from SRAM bit cell 100.

[0023] The remaining read port B is similarly constructed to include NMOS transistors M7 and M8, as well as the read port B word line (RWLB) and read port B bit line (RBLB). The read port B bit line RBLB is connected to the drain of access transistor M8. The source of access transistor M8 is connected to the drain of transistor M7. The source of transistor M7 is connected to ground. The QB output node is connected to the gate of transistor M7. The read port B word line RWLB is connected to the gate of access transistor M8. Before a single-ended read operation on read port B, the read port B bit line RBLB is pre-charged to the supply voltage. The read port B bit line RBLB is then floating so that its voltage may be affected by read operations on SRAM cell 100 via read port B. During a single-ended read operation via read port B, the read port B word line RWLB is charged to the supply voltage to turn on access transistor M8. If the QB output node is already charged to the supply voltage before a read operation on port B, transistor M7 will be turned on to discharge the source of access transistor M8. As access transistor M8 is turned on due to the assertion of the read port B word line RWLB, the read port B bit line RBLB will subsequently discharge via transistors M7 and M8. Conversely, if the QB node discharges, the read port B bit line RBLB remains pre-charged during read port B access.

[0024] Single-ended read operations to read ports A and B are performed only when there is no conflict. A conflict occurs if a write operation to multi-port bit cell 100 via the write port occurs in the same system clock cycle as a read operation to read port A and / or read port B. The read operation attempts to read the binary state of a bit already stored in SRAM bit cell 100, while the write operation potentially alters that binary state. The resulting conflict disrupts the read operation. As previously discussed, conflict mitigation is typically performed using a dual-pump operation that divides the system clock cycle into two parts. In the first part, a read operation occurs to one (or both) of read ports A and B. The write port is not accessed during this first part. In the second part of the system clock cycle, a write operation occurs. If the dual-pump operation is performed correctly, no conflict occurs because no write operation occurs during the read operation. However, this division of the system clock cycle in the dual-pump operation slows down memory operations.

[0025] To avoid timing penalties associated with dual-pump operation, a multi-port memory is provided where the system clock cycle is not divided into separate portions for read and write operations. Instead, an address comparison is performed for each active read port to determine whether the write port of the SRAM bit cell is also addressed by a write operation. If the address comparison indicates that no write operation has occurred to the addressed SRAM bit cell, a single-ended read operation occurs on the corresponding read port. This single-ended read operation occurs, for example, with respect to SRAM bit cell 100. The corresponding read port bit line is thus pre-charged and subsequently floated, while the corresponding read word line is subsequently charged so that the voltage obtained on the read port bit can be sensed by a sense amplifier inverter to generate a read port data output bit or a complementary read port data output bit, depending on whether read port A or B is addressed. However, if the address comparison indicates that the write port of the SRAM bit cell is also being accessed, no read operation occurs on the read port. Since the read port is not used, the corresponding read port bit line is not floated, and the corresponding read word line voltage is not asserted. Alternatively, if the write port of a multi-port SRAM bit cell is accessed during the same system clock cycle of one (or both) of the read ports, the read operation occurs via the write port.

[0026] The difference between read and write ports is utilized by reading operations on the write port. Specifically, it's important to note that write operations on the write port are differential because they involve a pair of write port bit lines, while read operations on either read port A or B are single-ended and occur only on a single read port bit line. Given the differential nature of write port access, differential reads of bits stored in multi-port SRAM bit cells can occur relatively quickly via the write port compared to single-ended reads on a read port. In this context, the threshold voltage of the sense amplifier inverter performing a single-ended read is approximately half the supply voltage. For example, assuming a supply voltage of 0.8V, the threshold voltage for the sense amplifier inverter to perform a single-ended read via the read port could be approximately 400 mV. The pre-charged read port bit line must then discharge from 800 mV to a trigger point of 400 mV before the sense amplifier inverter can make its bit decision. However, differential reads on the write port bit line do not require such relatively large voltage changes before the differential sense amplifier coupled to the write port bit line can make a bit decision.

[0027] If the write port is addressed in a given system clock cycle, the write port bit line driven by the data bits to be written during the write operation is delayed until a differential read operation can occur. Before write port access, the write port bit line can be precharged to a preset state. During a differential read on the write port, one of the write port bit lines will discharge from the preset precharge state, depending on the binary value of the bit stored in the multi-port SRAM bit cell. A voltage difference is then generated between the write port bit lines sensed by the differential sense amplifier. The differential sense amplifier can make a bit decision when the voltage difference is only a fraction of the supply voltage (e.g., 100 mV, 80 mV, or even less) compared to the threshold voltage of the sense amplifier inverter. The voltage difference across the write port bit lines used to make differential bit decisions in the differential sense amplifier is relatively small compared to the threshold voltage of the sense amplifier inverter that makes single-ended bit decisions. Therefore, a sufficient voltage difference across the write port bit lines allows for relatively fast differential reads compared to single-ended read operations.

[0028] Given the relative speed of differential reads, the differential read and write bit line drive to complete the write operation can still be performed in essentially the same amount of time as a single-ended read operation. Therefore, the resulting operating speed is relatively high compared to dual-pump operation because the write operation (and its initial differential read) can begin in essentially the same amount of time as a single-ended read operation would have been performed, unless the address compare indicates that the write port is also being addressed.

[0029] Generally, accessing the read port of a multi-port SRAM cell without conflict is more common. In this case, a single-ended read occurs on the addressed read port. The write port is not accessed, so the write bit line remains in its preset precharge state. However, for a given multi-port SRAM cell, both the read and write ports may be addressed simultaneously within the same system clock cycle. In this case, a single-ended read does not occur on the addressed read port; instead, a differential read operation occurs via the write port before the initiation and completion of the write operation. The differential read operation senses the data bits stored in the multi-port SRAM cell and their complements. Therefore, if the write port is not addressed (no conflict), the multiplexer can select a bit decision from the sense amplifier inverter for the addressed read port, or if the write port is addressed (conflict exists), the multiplexer can select a bit decision from the differential sense amplifier. A latch can then latch the bit decision selection from the multiplexer.

[0030] Figure 2 illustrates a flowchart 200 for conflict mitigation of a multi-port SRAM. For this multi-port SRAM, multiple bit cells 100 are an example of a suitable multi-port bit cell, but it will be understood that the conflict mitigation disclosed herein can be implemented with any suitable multi-port bit cell architecture. Flowchart 200 begins in response to the trigger edge of clock signal 205, which initiates a read and / or write operation. In flowchart 200, the write port is denoted as Port C to distinguish it from read ports A and B. Following the trigger edge of clock signal 205, it is possible that the write port is being addressed, although this is not necessarily the case for each cycle of clock signal 205. If the write port is addressed, the write word line (Port C word line) is asserted in step 220. After the assertion of the write word line, the bits stored in the multi-port bit cell corresponding to write port C are retrieved to write port C via differential read 240 using the write bit line pair. A differential sense amplifier then senses the binary value of the retrieved bits. Once the differential read is complete, the write driver then proceeds in step 265 to drive the data bits to be written via write port C to the corresponding bit cells. With the write operation complete, the write word line can be discharged (closed) to complete step 265.

[0031] To determine whether a conflict at read port A occurred within the same clock cycle, the addresses of read port A and write port C are compared in step 210. If the addresses point to the same multi-port bit cell (e.g., the addresses can be equal), a conflict has occurred, which is represented as a positive determination in flowchart 200. Conversely, if the addresses of read port A and write port C point to different multi-port bit cells, no conflict occurs regarding read port A (represented as a negative determination in flowchart 200). If there is no conflict at read port A, the word line of read port A can be charged in step 225 so that a single-ended read operation can be performed via read port A in step 235. Multiplexer 250 can then (assuming no conflict) select the single-ended read result so that the output bit can be latched in step 260. However, if a conflict exists between ports A and C, the word line of read port A is not asserted and multiplexer 250 selects the output bit produced by the differential read operation in step 240. Therefore, the selection of multiplexer 250 can be controlled by determining whether the conflict between ports A and C is true or false in step 210.

[0032] In step 215, a similar address comparison is performed on read port B. If the addresses of port B and port C point to the same multi-port bit cell, a conflict occurs (affirmative determination). Conversely, if the addresses of read port B and write port C point to different multi-port bit cells, no conflict occurs regarding read port B (negative determination). If there is no conflict at read port B, the word line of read port B can be charged in step 230 so that a single-ended read operation can be performed via read port B in step 245. Multiplexer 255 can then (assuming no conflict) select the single-ended read result of port B so that the complementary output bit can be latched in step 270. However, if there is a conflict between ports B and C, the word line of read port B is not asserted and multiplexer 255 selects the complementary output bit generated by the differential read operation in step 240. Therefore, the selection of multiplexer 255 can be controlled by whether the affirmative determination of the conflict between ports B and C in step 215 is true or false.

[0033] Now, regarding Figure 3, we discuss the SRAM 300 configured for conflict avoidance. Address comparator 305 performs an address comparison between port A and port C addresses in response to the trigger edge of the system clock signal (CLK). If the comparison indicates no conflict between ports A and C, address comparator 305 passes the system clock signal as the clock A signal (CLKA) to the precharge and port A word line controller 310 to trigger an assertion (charging) on ​​the port A word line and to float the precharge of the port A bit line in response to the assertion of the precharge A signal. As will be explained further herein, the state (true or false) of the precharge signal A can control the selection of multiplexer 250.

[0034] Address comparator 315 performs an address comparison between port B and port C addresses in response to the trigger edge of the system clock signal (CLK). If the comparison indicates no conflict between ports B and C, address comparator 315 transmits the system clock signal as the clock B signal (CLKB) to the precharge and port B word line controller 311 to trigger an assertion (charging) on ​​the port B word line and to float the precharge of the port B bit line in response to the assertion of the precharge B signal. As will be further explained herein, the state (true or false) of the precharge signal B can control the selection of multiplexer 255.

[0035] The write port in the multi-port bit cell 100 includes a write word line WWL and write bit lines WBL and WBLB, as previously discussed. A differential sense amplifier 320 is coupled to the write bit lines WBL and WBLB such that when the write word line WWL is asserted to open the write port, the differential sense amplifier 320 can sense the data bits stored in the multi-port bit cell 100 and their complements. The sensed data bit is denoted as Sout, and the sensed complementary data bit is denoted as SoutB. The sense amplifier 320 responds to an assertion of a sense enable signal. The sense amplifier 320 is also integrated with a write driver (Din driver), which can then drive the write bit lines WBL and WBLB using the data bits Din to be written after the differential read operation is completed.

[0036] The precharge A signal drives the gate of PMOS transistor P4, whose source is connected to the power supply voltage node and whose drain is connected to the read port A bit line. The precharge A signal controls whether the read port A bit line is floating or held in its preset precharge state. When the precharge A signal is de-asserted, precharging of the read port A bit line occurs due to the conduction of transistor P4. As used herein, the signal is considered "asserted" when it is true, regardless of whether a logic high or low convention is used. The precharge A signal is active high, therefore it asserts by charging to the power supply voltage. The precharge A signal also controls the floating of the global read port A bit line (GRBLA). For this purpose, the precharge A signal also drives the gate of PMOS transistor P5, whose drain is connected to the global read port A bit line and whose source is connected to the power supply node. The de-assertion of the precharge A signal also forces transistor P5 to turn on to precharge global read bit line A to the supply voltage. Inverter INV C inverts the binary state of the read port A bit line to drive the gate of NMOS transistor M9, whose source is connected to ground and drain is connected to the global read port A bit line. Transistor M9 is therefore turned off when the read port A bit line is precharged. If read port A is addressed, the precharge A signal will be asserted to turn off both transistors P4 and P5, so that both read port A bit line RBLA and global read port A bit line GRBLA are floating. If the data bit stored in multi-port bit cell 100 is binary zero (assuming logic high convention), the precharge state of the RBLA and GRBLA lines will be unaffected, although they are floating. The read port A sense amplifier inverter (INV A) inverts the binary state of the GRBLA line to provide the sensed data output bit selected by multiplexer 250 due to the assertion of the precharge A signal. However, in the event of a collision, the precharge A signal is not asserted, so that multiplexer 250 selects the Sout data bit from the differential sense amplifier 320. The data output latch 325 can then latch the sensed bit (DoutA) regardless of whether it was generated by read port A or write port C.

[0037] The read port B is similar. The precharge B signal drives the gate of PMOS transistor P6, whose source is connected to the power supply voltage node and whose drain is connected to the read port B bit line B (RBLB). The precharge B signal controls whether the read port B bit line is floating or held in its preset precharge state. When the precharge B signal is de-asserted, the precharge of the read port B bit line occurs due to conduction by transistor P6. The precharge B signal also controls the floating of the global read port B bit line (GRBLB). For this purpose, the precharge B signal also drives the gate of PMOS transistor P7, whose drain is connected to the global read port B bit line and whose source is connected to the power supply node. The de-assertion of the precharge B signal thus also forces transistor P7 to turn on to precharge the global read port B bit line to the power supply voltage. Inverter INV D inverts the binary state of the read port B bit line to drive the gate of NMOS transistor M10, whose source is connected to ground and whose drain is connected to the global read port B bit line. Transistor M10 is thus turned off when the read port B bit line is precharged. If read port B is addressed, the precharge B signal is asserted to turn off both transistors P6 and P7, causing both read port B bit line RBLB and global read port B bit line GRBLB to float. If the data bit stored in the multi-port bit cell 100 is binary zero (again, assuming a logic high convention), the precharge state of the RBLB and GRBLB lines will be unaffected, although they are floating. The read port B sense amplifier inverter (INV B) inverts the binary state of the GRBLB line to provide the sensed data output bit selected by multiplexer 255 due to the assertion of the precharge B signal. However, in the event of a collision, the precharge B signal is not asserted, allowing the multiplexer 255 to instead select the complementary data bit SoutB from the differential sense amplifier 320. The data output latch 325 can then latch the sensed bit (DoutB) regardless of whether it was generated by the read port B or the write port C.

[0038] A conflict support method will now be discussed with reference to the flowchart of Figure 4. The method includes action 400: comparing a first read port address with a write port address to detect a first conflict in response to a match between the first read port address and the write port address, and detecting no first conflict in response to a mismatch between the first read port address and the write port address. A comparison in either of the address comparators 305 and 315 is an example of action 400. The method also includes action 405, which occurs at a first multiplexer and includes: selecting data output bits generated by a single-ended read of a multiplexer bit cell via the first read port in response to the detection of no first conflict. Selection at either of the multiplexers 250 or 255 in the absence of conflict is an example of action 405. Finally, the method includes action 410, which also occurs at the first multiplexer and includes: selecting data output bits generated by a differential read of a multiplexer bit cell via the write port in response to the detection of a first conflict. In the event of a conflict, the choice at either multiplexer 250 or 255 is an example of action 410.

[0039] As disclosed herein, conflict-supported multiport memory can be incorporated into a variety of electronic systems. For example, as shown in Figure 5, a cellular phone 500, a laptop computer 505, and a tablet PC 510 can all include conflict-supported multiport memory according to the present invention. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with multiport memory constructed according to the present invention.

[0040] The content of this case will now be summarized in the following series of clauses: Clause 1. A multi-port memory, comprising: The multi-port bit unit includes a first read port having a first read port bit line, and the multi-port bit unit also includes a write port bit line pair; The sense amplifier coupled to the write port bit pair; The first inverter coupled to the first read port bit line; and A first multiplexer is configured to select between data output bits from the sense amplifier and data output bits from the first inverter to provide the selected data output bits. Clause 2. The multi-port memory according to Clause 1, wherein the multi-port bit unit further includes a second read port having a second read port bit line, and the multi-port memory further includes: The second inverter coupled to the second read port bit line; and A second multiplexer is configured to select between complementary data output bits from the sense amplifier and complementary data output bits from the second inverter to provide the selected complementary data output bits. Clause 3. The multi-port memory pursuant to Clause 2 also includes: A data latch configured to latch the selected data output bits and the selected complementary data output bits. Clause 4. The multi-port memory described in any of Clauses 1-3 also includes: An address comparator configured to: detect a conflict in response to the read port address and the write port address being the same, and detect no conflict in response to the read port address and the write port address being different; and A read line controller is configured to assert a read line to the first read port in response to the detection of no conflict, and not assert the read line in response to the detection of a conflict. Clause 5. Multiport memory pursuant to Clause 4, wherein the read line controller is further configured to: assert a precharge signal in response to the detection of no conflict, and not assert the precharge signal in response to the detection of a conflict. Clause 6. The multi-port memory according to Clause 5 further includes: a transistor coupled between the first read port bit line and a power node of the power supply voltage, wherein the transistor is configured to: turn on in response to an assertion of the precharge signal and turn off in response to a non-assertion of the precharge signal. Clause 7. Multiport memory pursuant to Clause 6, wherein the transistor includes a p-type metal-oxide-semiconductor (PMOS) transistor. Clause 8. The multi-port memory described in any of Clauses 1-7 also includes: A write driver configured to drive the write bit pair in response to bits to be written to the multiport bit cell after the sense amplifier has completed its sensing operation. Clause 9. A multi-port memory according to Clause 4, wherein the multi-port bit cell includes a cross-coupled inverter pair configured to drive a data output node and a complementary data output node, and wherein the first read port further includes an access transistor configured to be controlled by the read port word line. Clause 10. Multiport memory according to Clause 9, wherein the first read port further includes a second transistor coupled between ground and the terminal of the access transistor, and wherein the gate of the second transistor is coupled to the data output node, and wherein the multiport memory is integrated into a cellular telephone. Clause 11. A method for operating on multi-port memory, comprising: The first read port address is compared with the write port address to detect a first conflict if the first read port address matches the write port address, and to detect no first conflict if the first read port address does not match the write port address. At the first multiplexer, in response to the detection of no first conflict, the data output bits generated by single-ended reading of the multiplexer bit unit via the first read port are selected; and At the first multiplexer, in response to the detection of the first conflict, data output bits generated by differential reading of the multiple port bit unit via the write port are selected. Clause 12. The method pursuant to Clause 11 also includes: The comparison between the first read port address and the write port address is triggered in response to the edge of the clock signal. Clause 13. The method described pursuant to any of Clauses 11-12 further includes: The second read port address is compared with the write port address to detect a second conflict if the second read port address matches the write port address, and to detect no second conflict if the second read port address does not match the write port address. At the second multiplexer, in response to the detection of no second conflict, complementary data output bits generated by single-ended reading of the multiplexer bit unit via the second read port are selected; and At the second multiplexer, in response to the detection of the second conflict, complementary data output bits generated by differential reading of the multiple port bit unit via the write port are selected. Clause 14. The method described pursuant to any of Clauses 11-13 further includes: Before comparing the first read port address with the write port address, precharge the first bit line in the first read port; and The response is that the first element line is suspended upon detection of the first collision; and In response to the detection of no first conflict, the precharge of the first bit line is maintained. Clause 15. The method pursuant to Clause 14 also includes: The precharge signal is asserted in response to the detection of the absence of the first conflict, wherein the levitation of the first bit line is in response to the assertion of the precharge signal. Clause 16. The method pursuant to Clause 15 also includes: In response to the assertion of the precharge signal, the transistor coupled between the first bit line and the power node of the power supply voltage is turned off. Clause 17. The method pursuant to Clause 16 also includes: In response to the detection of the first conflict, the precharge signal is released assertion to keep the transistor on. Clause 18. The method described pursuant to any of Clauses 11-17 further includes: The data output bits from the first multiplexer are latched. Clause 19. A multi-port memory, comprising: The multi-port bit unit includes a first read port having a first read port bit line and a first read port word line, and the multi-port bit unit also includes a write port having a write port bit line pair; An address comparator, configured to detect a conflict in response to a write port address pointing to the write port and a read port address pointing to the first read port; and A port word line controller is configured to assert the first port word line in response to the absence of a conflict, and not assert the first port word line in response to the detection of a conflict. Clause 20. Multi-port memory pursuant to Clause 19, wherein the read port word line controller is further configured to assert a precharge signal of the first read port in response to the absence of detection of the conflict, and wherein the first read port is further configured to float the first read port bit line in response to the assertion of the precharge signal. Clause 21. The multi-port memory described in any of Clauses 19-20 further includes: A sense amplifier configured to perform differential reads via the write port in response to the write port address pointing to the write port. Clause 22. The multi-port memory pursuant to Clause 21 also includes: The data driver is configured to drive the write port bit pair using the data bits to be written to the multi-port bit cell after the differential read is completed. Clause 23. The multi-port memory pursuant to any of Clauses 21-22 also includes: Inverter coupled to the first read port bit line; and A multiplexer configured to select between the output of the inverter and the output of the sensing amplifier. Clause 24. A multi-port memory, comprising: An address comparator configured to detect a collision in response to both the read port address and the write port address pointing to a first multi-port bit cell; A sensing amplifier configured to read first data bits from the first multi-port bit unit via a write port; A write driver configured to write a second data bit to the first multi-port bit unit via the write port after the first data bit has been read; and A multiplexer coupled to the sensing amplifier is configured to select the first data bit in response to the detection of the collision. Clause 25. The multi-port memory pursuant to Clause 24 also includes: An inverter coupled to a read port bit line in a first read port of the first multi-port bit unit, wherein the multiplexer is further configured to select the output of the inverter in response to the detection of no conflict. Clause 26. The multi-port memory pursuant to Clause 25 also includes: A data latch, configured to latch output bits from the multiplexer. Clause 27. A multi-port memory as described in any of Clauses 25-26, wherein the first multi-port bit unit includes a second read port. Clause 28. The multi-port memory described in any of Clauses 25-27 also includes: A read port word line controller, configured to assert a word line to the first read port in response to the detection of no conflict. Clause 29. Multi-port memory pursuant to Clause 28, wherein the read port word line controller is further configured to assert a precharge signal to the first read port in response to the detection of no conflict. Clause 30. A multi-port memory pursuant to any of Clauses 24-29, wherein the address comparator is configured to be triggered in response to an edge of a clock signal to detect the conflict.

[0041] As will be appreciated by those skilled in the art by this time, and depending on the specific application at hand, many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and method of use of the device in this application without departing from the scope of this application. Therefore, the scope of this application should not be limited to the specific embodiments explained and described herein (as they are merely examples), but should be fully equivalent to the appended claims and their functional equivalents.

[0042] 100: Exemplary three-port SRAM bit cell 200: Flowchart 205: Clock signal 210: Steps 215: Steps 220: Steps 225: Steps 230: Steps 235: Steps 240: Differential Read 245: Steps 250: Multiplexer 255: Multiplexer 260: Steps 265: Steps 270: Steps 300:SRAM 305: Address Comparator 310: Port A-line controller 311: Port B Line Controller 315: Address Comparator 320: Differential Sensing Amplifier 325: Data Output Latch 400: Actions 405: Actions 410: Action 500: Cellular Telephone 505: Laptop 510: Tablet PC CLK: System clock signal CLK A: Clock A signal GRBLA: Global Read Port A-bit Line GRBLB: Global Read Port B-bit Line INV A: Read Port A Sensor Amplifier Inverter INV B: Read Port B Sensing Amplifier Inverter INV C: Inverter INV D: Inverter M1: NMOS transistor M2: NMOS transistor M3: Write port access transistor M4: Write port access transistor M5: NMOS transistor M6: NMOS transistor M7: NMOS transistor M8: NMOS transistor M9: NMOS transistor M10: NMOS transistor P1: p-type metal-oxide-semiconductor (PMOS) transistor P2: PMOS transistor P4: PMOS transistor P5: PMOS transistor P6: PMOS transistor P7: PMOS transistor Q: Output node QB: Complementary Data Output Node RBLA: Read port A bit line A RBLB: Read Port B Bit Line RWLA: Read as A RWLB: Read the B line (for port) WBL: Write Bit Line WBLB: Write Bit Line WWL: Writing Line

Claims

1. A multi-port memory, wherein the multi-port memory is a static random access memory (SRAM), comprising: A multi-port bit unit includes a first read port having a first single-ended read port bit line, the multi-port bit unit also includes a differential write port relating to a write port bit line pair; a differential sense amplifier coupled to the write port bit line pair; a first inverter coupled to the first read port bit line; and a first multiplexer configured to select between a data output bit from the differential sense amplifier (responding to a read port address different from a write port address) and a data output bit from the first inverter (responding to a read port address the same as the write port address) to provide a selected data output bit.

2. The multi-port memory according to claim 1, wherein the multi-port bit unit further includes a second read port having a second read port bit line, and the multi-port memory further includes: A second inverter coupled to the second read port bit line; and a second multiplexer configured to select between a complementary data output bit from the differential sense amplifier and a complementary data output bit from the second inverter to provide a selected complementary data output bit.

3. According to request item 2, the multiport memory also includes: A data latch configured to latch selected data output bits and selected complementary data output bits.

4. According to request item 1, the multiport memory also includes: An address comparator configured to detect a conflict in response to the same read port address and write port address, and to detect no conflict in response to the different read port address and write port address; and a read word line controller configured to assert a read port word line to the first read port in response to the detection of no conflict, and to not assert the read port word line in response to the detection of a conflict.

5. The multi-port memory according to request 4, wherein the read word line controller is further configured to: assert a precharge signal in response to the detection of no conflict, and not assert the precharge signal in response to the detection of conflict.

6. According to request item 5, the multiport memory also includes: A transistor coupled between the first read port bit line and a power node of a power supply voltage, wherein the transistor is configured to turn on in response to an assertion of the precharge signal and turn off in response to an assertion of the precharge signal.

7. The multiport memory according to claim 6, wherein the transistor includes a p-type metal-oxide-semiconductor (PMOS) transistor.

8. According to request item 1, the multiport memory also includes: A write driver configured to drive the write bit pair in response to a bit to be written to the multi-port bit cell after the differential sense amplifier has completed a sensing operation.

9. The multi-port memory according to claim 4, wherein the multi-port bit cell includes a cross-coupled inverter pair configured to drive a data output node and a complementary data output node, and wherein the first read port further includes an access transistor configured to be controlled by the read port word line.

10. The multiport memory according to claim 9, wherein the first read port further includes a second transistor coupled between ground and a terminal of the access transistor, and wherein a gate of the second transistor is coupled to the data output node, and wherein the multiport memory is integrated into a cellular telephone.

11. A method for operating a multi-port memory, the multi-port memory being a static random access memory (SRAM), the method comprising: A first read port address is compared with a write port address to detect a first conflict if the first read port address matches the write port address and to detect no first conflict if the first read port address does not match the write port address; at an inverter, a data output bit generated by a single-ended read of a multi-port bit cell via a first read port is inverted, and at a first multiplexer, an output of the inverter is selected in response to the detection of no first conflict; and at the first multiplexer, a data output bit generated by a differential read of the multi-port bit cell via a write port is selected in response to the detection of the first conflict.

12. The method according to request item 11 further includes: The comparison between the first read port address and the write port address is triggered in response to one edge of a clock signal.

13. The method according to request item 11 further includes: A second read port address is compared with the write port address to detect a second conflict if the second read port address matches the write port address and to detect no second conflict if the second read port address does not match the write port address; at a second multiplexer, in response to the detection of no second conflict, a complementary data output bit generated by a single-ended read of the multi-port bit unit via a second read port is selected; and at the second multiplexer, in response to the detection of the second conflict, a complementary data output bit generated by the differential read of the multi-port bit unit via the write port is selected.

14. The method according to request item 11 further includes: Before comparing the first read port address with the write port address, a first bit line in the first read port is precharged; And in response to the detection of the first collision, the first bit line is suspended; and in response to the detection of the absence of the first collision, the precharge of the first bit line is maintained.

15. The method according to claim 14 further includes: In response to the detection of the absence of the first conflict, an assertion is made regarding a precharge signal, wherein the levitation of the first bit line is in response to an assertion regarding the precharge signal.

16. The method according to claim 15 further includes: In response to the assertion of the precharge signal, a transistor coupled between the first bit line and a power node of a power supply voltage is turned off.

17. The method according to claim 16 further includes: In response to the detection of the first conflict, a release assertion is maintained to keep the precharge signal in a state of being turned on by keeping the transistor in a state of being turned on.

18. The method according to request item 11 further includes: The latch is a data output bit from the first multiplexer.

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