Semiconductor package

Abstract

This invention discloses a semiconductor package comprising: an interposer substrate having a first surface and a second surface opposite to each other and including a wiring layer adjacent to the first surface; a semiconductor wafer on the first surface of the interposer substrate; a passivation layer on the first surface of the interposer substrate and covering the semiconductor wafer; and a redistribution pattern in the passivation layer and connected to the semiconductor wafer. The semiconductor wafer has a third surface and a fourth surface opposite to each other. The third surface of the semiconductor wafer faces the first surface of the interposer substrate. The redistribution pattern is connected to the fourth surface of the semiconductor wafer. The semiconductor wafer includes wafer pads adjacent to the third surface and wafer through-electrodes connected to the wafer pads. Each of the wafer pads is directly bonded to a corresponding one of the wiring patterns in the wiring layer.

Description

Technical Field

[0001] Cross - reference to Related Applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2021 - 0076873, filed on Jun. 14, 2021 with the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package on which a plurality of semiconductor chips are mounted.

Prior Art

[0004] A semiconductor package is provided to implement an integrated circuit chip to be eligible for use in electronic products. Generally, in a semiconductor package, a semiconductor chip is mounted on a printed circuit board (PCB), and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the development of the electronics industry, there may be a need for smaller, lighter, and multi - functional electronic devices. There have been some proposals for multi - chip packages in which multiple chips are stacked in a single semiconductor package or system - in - package in which different types of chips are mounted in a single semiconductor package and operate as a system.

Summary of the Invention

[0005] Some embodiments of the inventive concept provide a semiconductor package in which an interconnection can be easily established between a plurality of semiconductor chips.

[0006] Some embodiments of the inventive concept provide a semiconductor package having improved heat radiation properties.

[0007] According to some embodiments of the inventive concept, a semiconductor package may include: an interposer substrate having a first surface and a second surface opposite to each other, the interposer substrate including a wiring layer adjacent to the first surface; a semiconductor chip on the first surface of the interposer substrate; a passivation layer on the first surface of the interposer substrate, the passivation layer covering the semiconductor chip; and a plurality of redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip may have a third surface and a fourth surface opposite to each other. The third surface of the semiconductor chip may face the first surface of the interposer substrate. The plurality of redistribution patterns may be connected to the fourth surface of the semiconductor chip. The semiconductor chip may include a plurality of chip pads adjacent to the third surface and a plurality of chip vias connected to the plurality of chip pads. Each of the plurality of chip pads may be directly bonded to a corresponding one of the plurality of wiring patterns in the wiring layer.

[0008] According to some embodiments of the inventive concept, a semiconductor package may include: an interposer substrate having a first surface and a second surface opposite to each other, the interposer substrate including a wiring layer adjacent to the first surface; a first semiconductor chip and a second semiconductor chip horizontally spaced apart from each other on the first surface of the interposer substrate; a passivation layer on the first surface of the interposer substrate, the passivation layer covering the first semiconductor chip and the second semiconductor chip; and a plurality of redistribution patterns in the passivation layer. The plurality of redistribution patterns may connect the first semiconductor chip to the second semiconductor chip. The first semiconductor chip may have a third surface and a fourth surface opposite to each other. The first semiconductor chip may include a plurality of first chip pads adjacent to the third surface. The second semiconductor chip may have a fifth surface and a sixth surface opposite to each other. The second semiconductor chip may include a plurality of second chip pads adjacent to the fifth surface. Each of the plurality of first chip pads and the plurality of second chip pads may be directly bonded to a corresponding one of the plurality of wiring patterns in the wiring layer. The plurality of redistribution patterns may be connected to the fourth surface of the first semiconductor chip and the sixth surface of the second semiconductor chip.

Embodiments

[0010] Some embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings.

[0011] FIG. 1 shows a cross-sectional view of a semiconductor package illustrating some embodiments of the inventive concept. FIG. 2 shows an enlarged view of a portion PP of FIG. 1.

[0012] Referring to FIGS. 1 and 2, the semiconductor package 1000 may include an interposer substrate 100 and a plurality of semiconductor chips 200a, semiconductor chip 200b, and semiconductor chip 400 mounted on the interposer substrate 100.

[0013] The interposer substrate 100 may include a base substrate 110, a plurality of vias 120 penetrating the base substrate 110, and a wiring layer 130 on the base substrate 110. The base substrate 110 may be, for example, a silicon substrate. The plurality of vias 120 may be horizontally spaced apart from each other in the base substrate 110, and each of the plurality of vias 120 may penetrate the base substrate 110. The plurality of vias 120 may include a metal, such as copper (Cu).

[0014] The wiring layer 130 may include a wiring pattern 132 on the base substrate 110 and a wiring dielectric layer 134 covering the wiring pattern 132. The wiring pattern 132 may include a metal (such as copper), and the wiring dielectric layer 134 may include a dielectric material (such as silicon oxide, silicon nitride, and / or silicon oxynitride). The plurality of vias 120 may be connected to the wiring layer 130. The plurality of vias 120 may be connected to the lowermost one in the wiring pattern 132. Each of the plurality of vias 120 may be connected to a corresponding one in the lowermost wiring pattern 132.

[0015] The interposer substrate 100 may have a first surface 100a and a second surface 100b opposite to each other, and the wiring layer 130 may be adjacent to the first surface 100a. The second surface 100b of the interposer substrate 100 may correspond to a surface of the base substrate 110. Each of the plurality of vias 120 may extend from the wiring layer 130 toward the second surface 100b.

[0016] The interposer substrate 100 may be provided with conductive pads 140 on its second surface 100b. The conductive pads 140 may be horizontally spaced apart from each other, and each of the plurality of vias 120 may be connected to a corresponding one of the conductive pads 140. The conductive pads 140 may include a conductive material (such as a metal).

[0017] The interposer substrate 100 may be provided with connection bumps 150 correspondingly connected to the conductive pads 140 on its second surface 100b. The connection bumps 150 may be correspondingly disposed on the conductive pads 140. The connection bumps 150 may include a conductive material and may have at least one selected from a solder ball shape, a bump shape, and a column shape.

[0018] A plurality of semiconductor wafers 200a, semiconductor wafer 200b, and semiconductor wafer 400 can be mounted on the first surface 100a of the interposer substrate 100. The plurality of semiconductor wafers 200a, semiconductor wafer 200b, and semiconductor wafer 400 can include a first semiconductor wafer 200a and a second semiconductor wafer 200b that are horizontally spaced apart from each other. According to some embodiments, the first semiconductor wafer 200a and the second semiconductor wafer 200b can be identical to each other. For example, the first semiconductor wafer 200a and the second semiconductor wafer 200b can be memory wafers, logic wafers, application processor (AP) wafers, or system-on-chip (SOC) wafers. According to some embodiments, the first semiconductor wafer 200a and the second semiconductor wafer 200b can be different from each other. For example, the first semiconductor wafer 200a and the second semiconductor wafer 200b can be different wafers among memory wafers, logic wafers, application processor (AP) wafers, or system-on-chip (SOC) wafers.

[0019] The first semiconductor wafer 200a can have a third surface S3 and a fourth surface S4 that face each other, and the third surface S3 of the first semiconductor wafer 200a can face the first surface 100a of the interposer substrate 100. The third surface S3 of the first semiconductor wafer 200a can be in direct contact with the first surface 100a of the interposer substrate 100.

[0020] The first semiconductor wafer 200a can include a first semiconductor substrate 10a, a first circuit layer 20a on the first semiconductor substrate 10a, a first wafer wiring layer 30a on the first circuit layer 20a, a plurality of first wafer through electrodes 15a that penetrate the first semiconductor substrate 10a, a plurality of first wafer pads 50a connected to the plurality of first wafer through electrodes 15a, and a first pad dielectric layer 52a that covers the first wafer pads 50a.

[0021] The first chip pads 50a and the first pad dielectric layer 52a may be disposed adjacent to the third surface S3 of the first semiconductor chip 200a. The first chip pads 50a may be horizontally spaced apart from each other, and the first pad dielectric layer 52a may be inserted between the first chip pads 50a. The first pad dielectric layer 52a may expose the bottom surface of the first chip pads 50a. The first chip pads 50a may comprise a metal (such as copper), and the first pad dielectric layer 52a may comprise a dielectric material (such as silicon oxide, silicon nitride, and / or silicon oxynitride). The first chip pads 50a may be connected to the uppermost one of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100. Each of the first chip pads 50a may be directly bonded to a corresponding one of the uppermost wiring patterns 132. Each of the first chip pads 50a and its corresponding wiring pattern 132 may constitute, for example, a copper-to-copper (Cu-Cu) bond. Since each of the first chip pads 50a is directly bonded to its corresponding wiring pattern 132, the first pad dielectric layer 52a may be in direct contact with the wiring dielectric layer 134 in the wiring layer 130 of the interposer substrate 100.

[0022] The first semiconductor substrate 10a may be disposed on the first chip pads 50a and the first pad dielectric layer 52a. The first semiconductor substrate 10a may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A plurality of first chip through electrodes 15a may be horizontally spaced apart from each other in the first semiconductor substrate 10a and may be connected to the first chip pads 50a. Each of the plurality of first chip through electrodes 15a may penetrate the first semiconductor substrate 10a and may be connected to a corresponding one of the first chip pads 50a. The plurality of first chip through electrodes 15a may comprise a metal (such as copper, tungsten, titanium, tantalum, etc.).

[0023] The first circuit layer 20a may be disposed on the first semiconductor substrate 10a and may comprise a first integrated circuit. The first integrated circuit may comprise a first transistor formed on the first semiconductor substrate 10a. The first transistor may be, for example, a field effect transistor. The plurality of first chip through electrodes 15a may be connected to the first circuit layer 20a. Each of the plurality of first chip through electrodes 15a may be electrically connected to a terminal of a corresponding one of the first transistors.

[0024] The first chip wiring layer 30a may be disposed adjacent to the fourth surface S4 of the first semiconductor chip 200a. The first circuit layer 20a may be disposed between the first chip wiring layer 30a and the first semiconductor substrate 10a, and between the first chip wiring layer 30a and the plurality of first chip vias 15a. The first semiconductor substrate 10a may be disposed between the first circuit layer 20a and the first chip pads 50a, and between the first circuit layer 20a and the first pad dielectric layer 52a. The plurality of first chip vias 15a may be disposed between the first circuit layer 20a and the first chip pads 50a, and are electrically connected to the first circuit layer 20a and the first chip pads 50a.

[0025] The first chip wiring layer 30a may include a first chip wiring pattern 32a on the first circuit layer 20a, a first chip wiring dielectric layer 34a covering the first chip wiring pattern 32a, and a first protective layer 36a on the first chip wiring dielectric layer 34a. The first chip wiring pattern 32a may be connected to the first circuit layer 20a. The first chip wiring pattern 32a may be electrically connected to a first transistor in the first circuit layer 20a. The first chip wiring pattern 32a may include one or more of metals (such as copper, tungsten, titanium, tantalum, etc.) and conductive metal nitrides. For example, the first chip wiring dielectric layer 34a may include one or more of silicon oxide, silicon nitride, and silicon oxynitride, and the first protective layer 36a may include silicon oxide.

[0026] The second semiconductor chip 200b may have a fifth surface S5 and a sixth surface S6 opposite to each other, and the fifth surface S5 of the second semiconductor chip 200b may face the first surface 100a of the interposer substrate 100. The fifth surface S5 of the second semiconductor chip 200b may be in direct contact with the first surface 100a of the interposer substrate 100.

[0027] The second semiconductor chip 200b may include a second semiconductor substrate 10b, a second circuit layer 20b on the second semiconductor substrate 10b, a second chip wiring layer 30b on the second circuit layer 20b, a plurality of second chip vias 15b penetrating the second semiconductor substrate 10b, a plurality of second chip pads 50b connected to the plurality of second chip vias 15b, and a second pad dielectric layer 52b covering the second chip pads 50b.

[0028] The second chip pads 50b and the second pad dielectric layer 52b may be disposed adjacent to the fifth surface S5 of the second semiconductor chip 200b. The second chip pads 50b may be horizontally spaced apart from each other, and the second pad dielectric layer 52b may be inserted between the second chip pads 50b. The second pad dielectric layer 52b may expose the bottom surfaces of the second chip pads 50b. The second chip pads 50b may comprise a metal (such as copper), and the second pad dielectric layer 52b may comprise a dielectric material (such as silicon oxide, silicon nitride, and / or silicon oxynitride). The second chip pads 50b may be connected to the uppermost one of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100. Each of the second chip pads 50b may be directly bonded to a corresponding one of the uppermost wiring patterns 132. Each of the second chip pads 50b and its corresponding wiring pattern 132 may constitute, for example, a copper-to-copper (Cu-Cu) bond. Since each of the second chip pads 50b is directly bonded to its corresponding wiring pattern 132, the second pad dielectric layer 52b may be in direct contact with the wiring dielectric layer 134 in the wiring layer 130 of the interposer substrate 100.

[0029] The second semiconductor substrate 10b may be disposed on the second chip pads 50b and the second pad dielectric layer 52b. The second semiconductor substrate 10b may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A plurality of second chip through electrodes 15b may be horizontally spaced apart from each other in the second semiconductor substrate 10b and may be connected to the second chip pads 50b. Each of the plurality of second chip through electrodes 15b may penetrate the second semiconductor substrate 10b and may be connected to a corresponding one of the second chip pads 50b. The plurality of second chip through electrodes 15b may comprise a metal (such as copper, tungsten, titanium, or tantalum).

[0030] The second circuit layer 20b may be disposed on the second semiconductor substrate 10b and may comprise a second integrated circuit. The second integrated circuit may comprise second transistors formed on the second semiconductor substrate 10b. The second transistors may be, for example, field effect transistors. The plurality of second chip through electrodes 15b may be connected to the second circuit layer 20b. Each of the plurality of second chip through electrodes 15b may be electrically connected to a terminal of a corresponding one of the second transistors.

[0031] The second chip wiring layer 30b may be disposed adjacent to the sixth surface S6 of the second semiconductor chip 200b. The second circuit layer 20b may be disposed between the second chip wiring layer 30b and the second semiconductor substrate 10b, and between the second chip wiring layer 30b and the plurality of second chip vias 15b. The second semiconductor substrate 10b may be disposed between the second circuit layer 20b and the second chip pads 50b, and between the second circuit layer 20b and the second pad dielectric layer 52b. The plurality of second chip vias 15b may be disposed between the second circuit layer 20b and the second chip pads 50b, and are electrically connected to the second circuit layer 20b and the second chip pads 50b.

[0032] The second chip wiring layer 30b may include a second chip wiring pattern 32b on the second circuit layer 20b, a second chip wiring dielectric layer 34b covering the second chip wiring pattern 32b, and a second protective layer 36b on the second chip wiring dielectric layer 34b. The second chip wiring pattern 32b may be connected to the second circuit layer 20b. The second chip wiring pattern 32b may be electrically connected to a second transistor in the second circuit layer 20b. The second chip wiring pattern 32b may include one or more of metals (such as copper, tungsten, titanium, tantalum, etc.) and conductive metal nitrides. For example, the second chip wiring dielectric layer 34b may include one or more of silicon oxide, silicon nitride, and silicon oxynitride, and the second protective layer 36b may include silicon oxide.

[0033] The interposer substrate 100 may be provided with a passivation layer 300 covering the first semiconductor chip 200a and the second semiconductor chip 200b on its first surface. The passivation layer 300 may include at least one selected from polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resin, epoxy resin, silicon oxide, and silicon nitride.

[0034] The redistribution line pattern 320 can be disposed in the passivation layer 300 and on (or above) the first semiconductor wafer 200a and the second semiconductor wafer 200b. The redistribution line pattern 320 can electrically connect the first semiconductor wafer 200a and the second semiconductor wafer 200b to each other. One or more of the redistribution line patterns 320 can be connected to the fourth surface S4 of the first semiconductor wafer 200a, and one or more of the other redistribution line patterns 320 can be connected to the sixth surface S6 of the second semiconductor wafer 200b. One or more of the redistribution line patterns 320 can be connected to corresponding ones of the first chip wiring patterns 32a in the first chip wiring layer 30a of the first semiconductor wafer 200a, and one or more of the other redistribution line patterns 320 can be connected to corresponding ones of the second chip wiring patterns 32b in the second chip wiring layer 30b of the second semiconductor wafer 200b. The redistribution line pattern 320 can include a metal, such as copper, aluminum, titanium, or tungsten. The passivation layer 300 can cover the redistribution line pattern 320 and can cover the top surface of the uppermost one of the redistribution line patterns 320.

[0035] Each of the first chip wiring patterns 32a in the first chip wiring layer 30a, each of the second chip wiring patterns 32b in the second chip wiring layer 30b, and each of the redistribution line patterns 320 can have a thickness in a first direction D1 perpendicular to the first surface 100a of the interposer substrate 100. Each of the redistribution line patterns 320 can have a thickness 320T greater than the thickness 32T of each of the first chip wiring patterns 32a and the second chip wiring patterns 32b. Each of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100 can have a thickness 132T in the first direction D1, and the thickness 320T of each of the redistribution line patterns 320 can be greater than the thickness 132T of each of the wiring patterns 132. The thickness 320T of each of the redistribution line patterns 320 can be in the range of about 1 micron to about 2 microns. For example, a value of about 100 angstroms to about 10,000 angstroms can be given as the thickness 132T of each of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100, and a value of about 100 angstroms to about 10,000 angstroms can be given as the thickness 32T of each of the first chip wiring patterns 32a and the second chip wiring patterns 32b.

[0036] In the base substrate 110, the plurality of vias 120 of the interposer substrate 100 may be horizontally spaced apart from each other along a second direction D2 parallel to the first surface 100a of the interposer substrate 100. Each of the plurality of vias 120 may extend along a first direction D1 to penetrate the base substrate 110. The first die vias 15a of the first semiconductor die 200a may be horizontally spaced apart from each other in the first semiconductor substrate 10a along the second direction D2, and each of the first die vias 15a may extend along the first direction D1 to penetrate the first semiconductor substrate 10a. The second die vias 15b of the second semiconductor die 200b may be horizontally spaced apart from each other in the second semiconductor substrate 10b along the second direction D2, and each of the second die vias 15b may extend along the first direction D1 to penetrate the second semiconductor substrate 10b. Each of the plurality of vias 120 in the interposer substrate 100 may have a size (e.g., length in the first direction D1 and / or width in the second direction D2) greater than the size (e.g., length in the first direction D1 and / or width in the second direction D2) of each of the first die vias 15a and the second die vias 15b.

[0037] The passivation layer 300 may be provided therein with conductive pillars 350 horizontally spaced apart from the first semiconductor die 200a and the second semiconductor die 200b. The first semiconductor die 200a and the second semiconductor die 200b may be spaced apart from each other in the second direction D2, and the conductive pillars 350 may be spaced apart from the first semiconductor die 200a and the second semiconductor die 200b along the second direction D2. The conductive pillars 350 may be connected to the first surface 100a of the interposer substrate 100. The conductive pillars 350 may be connected to the uppermost one of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100. Each of the conductive pillars 350 may penetrate the passivation layer 300 and may be connected to a corresponding one of the uppermost wiring patterns 132. The conductive pillars 350 may comprise a metal (e.g., copper).

[0038] The conductive pillars 350, the first semiconductor die 200a, and the second semiconductor die 200a may each have a thickness in the first direction D1. Each of the conductive pillars 350 may have a thickness 350T greater than the thickness 200T of each of the first semiconductor die 200a and the second semiconductor die 200b. The thickness 200T of each of the first semiconductor die 200a and the second semiconductor die 200b may be in a range of, for example, about 15 micrometers to about 800 micrometers, and the thickness 350T of each of the conductive pillars 350 may be in a range of, for example, about 15 micrometers to about 800 micrometers.

[0039] The third semiconductor wafer 400 may be included on the passivation layer 300 with multiple semiconductor wafers 200a, semiconductor wafer 200b, and semiconductor wafer 400. The third semiconductor wafer 400 may be the same as or different from the first semiconductor wafer 200a and the second semiconductor wafer 200b.

[0040] According to some embodiments, the third semiconductor wafer 400 may include multiple sub-semiconductor wafers 410 vertically stacked in a first direction D1, multiple sub-through electrodes 420 penetrating the multiple sub-semiconductor wafers 410, multiple sub-bumps 430 between the multiple sub-semiconductor wafers 410, and a molding layer 440 covering the multiple sub-semiconductor wafers 410. The multiple sub-semiconductor wafers 410 may include multiple memory wafers. For example, the lowermost one of the multiple sub-semiconductor wafers 410 may include a logic circuit, a memory circuit, or a combination thereof, and the remaining ones of the multiple sub-semiconductor wafers 410 may be the same memory wafers. The sub-bumps 430 may be disposed between adjacent ones of the multiple sub-semiconductor wafers 410 and may be connected to the sub-through electrodes 420 of the adjacent sub-semiconductor wafers 410. The multiple sub-semiconductor wafers 410 may be electrically connected to each other via the sub-bumps 430 and the sub-through electrodes 420. The third semiconductor wafer 400 may be, for example, a high bandwidth memory (HBM) wafer. In some embodiments, the third semiconductor wafer 400 may be an HBM wafer compliant with the high bandwidth memory (HBM) standard and future evolutions / releases of the HBM standard issued by the Joint Electron Device Engineering Council (JEDEC). The molding layer 440 may cover the multiple sub-semiconductor wafers 410 and may extend between the multiple sub-semiconductor wafers 410 to thereby cover the sub-bumps 430. The sub-bumps 430 and the sub-through electrodes 420 may include a conductive material, and the molding layer 440 may include a dielectric material.

[0041] Multiple bumps 450 may be disposed between the third semiconductor wafer 400 and the conductive posts 350. The bumps 450 may be connected to the lowermost one of the sub-semiconductor wafers 410 included in the third semiconductor wafer 400. Each of the bumps 450 may be connected to a corresponding one of the sub-through electrodes 420 penetrating the lowermost sub-semiconductor wafer 410. The bumps 450 may be disposed on the corresponding conductive posts 350 and connected to the corresponding conductive posts 350. The bumps 450 may include a conductive material and may have at least one selected from a solder ball shape, a bump shape, and a column shape.

[0042] The first semiconductor wafer 200a can be electrically connected via the first chip pad 50a to a corresponding one of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100. The corresponding wiring pattern 132 connected to the first semiconductor wafer 200a can constitute, for example, a power delivery network (PDN) that supplies power or ground to the first semiconductor wafer 200a. The second semiconductor wafer 200b can be electrically connected via the second chip pad 50b to a corresponding one of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100. The corresponding wiring pattern 132 connected to the second semiconductor wafer 200b can constitute, for example, a power delivery network (PDN) that supplies power or ground to the second semiconductor wafer 200b.

[0043] The third semiconductor wafer 400 can be connected to the first surface 100a of the interposer substrate 100 via the bumps 450 and the conductive pillars 350. The third semiconductor wafer 400 can be electrically connected via the bumps 450 and the conductive pillars 350 to a corresponding one of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100.

[0044] According to the inventive concept, one or more of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100 can constitute a power delivery network (PDN) that supplies power or ground to the first semiconductor wafer 200a and the second semiconductor wafer 200b. The first chip pads 50a and the second chip pads 50b of the first semiconductor wafer 200a and the second semiconductor wafer 200b can be directly bonded to corresponding ones of the wiring patterns 132, and the first semiconductor wafer 200a and the second semiconductor wafer 200b can be electrically connected to each other via the redistribution wiring patterns 320 on the first semiconductor wafer 200a and the second semiconductor wafer 200b. Since the first chip pads 50a and the second chip pads 50b are directly bonded to the corresponding wiring patterns 132, heat generated from the first semiconductor wafer 200a and the second semiconductor wafer 200b can be easily discharged via the interposer substrate 100 (e.g., the base substrate 110). In addition, since the first semiconductor wafer 200a and the second semiconductor wafer 200b are electrically connected to each other via the redistribution wiring patterns 320 on the first semiconductor wafer 200a and the second semiconductor wafer 200b, the first semiconductor wafer 200a and the second semiconductor wafer 200b can easily achieve their mutual connection.

[0045] Therefore, it is possible to provide a semiconductor package in which mutual connection is easily established between a plurality of semiconductor wafers and which exhibits improved heat radiation properties.

[0046] Figures 3 to 10 show cross-sectional views illustrating a method of manufacturing a semiconductor package according to some embodiments of the concepts of the present invention. For the sake of brevity, repeated descriptions of the features / components previously discussed in Figures 1 and 2 may be given briefly or omitted.

[0047] Referring to Figure 3, a semiconductor substrate 10 may be provided. The semiconductor substrate 10 may include a first semiconductor layer 11, a second semiconductor layer 12, and a third semiconductor layer 13 stacked in sequence. For example, the first semiconductor layer 11 and the third semiconductor layer 13 may each be a silicon layer, and the second semiconductor layer 12 may be a silicon-germanium (SiGe) layer. A circuit layer 20 may be formed on the semiconductor substrate 10. The circuit layer 20 may include an integrated circuit, and the integrated circuit may include transistors formed on the semiconductor substrate 10 (such as the third semiconductor layer 13). The circuit layer 20 may be provided with a wafer wiring pattern 32 formed thereon to be connected to the circuit layer 20. The wafer wiring pattern 32 may be electrically connected to the transistors formed in the circuit layer 20. A wafer wiring dielectric layer 34 may be formed on the circuit layer 20 to cover the wafer wiring pattern 32.

[0048] Referring to Figure 4, a protective layer 36 may be formed on a carrier substrate CW. The carrier substrate CW may be a semiconductor substrate (such as a silicon substrate), and the protective layer 36 may include silicon oxide. The semiconductor substrate 10 on which the circuit layer 20, the wafer wiring pattern 32, and the wafer wiring dielectric layer 34 are formed may be inverted such that the semiconductor substrate 10 may be disposed on the carrier substrate CW, and the wafer wiring dielectric layer 34 may be disposed adjacent to the protective layer 36. The carrier substrate CW and the semiconductor substrate 10 may be bonded by a wafer-to-wafer bonding method. For example, the wafer wiring dielectric layer 34 and the protective layer 36 may be directly bonded to each other.

[0049] The wafer wiring layer 30 may be provided by the wafer wiring pattern 32, the wafer wiring dielectric layer 34, and the protective layer 36. The wafer wiring layer 30 may be disposed between the carrier substrate CW and the semiconductor substrate 10, and the circuit layer 20 may be disposed between the wafer wiring layer 30 and the semiconductor substrate 10.

[0050] Referring to FIG. 5, an upper portion of the removable semiconductor substrate 10 can be removed. Removing the upper portion from the semiconductor substrate 10 can include, for example, performing a wet etching process to etch the first semiconductor layer 11 of the semiconductor substrate 10, and performing a dry etching process or a wet etching process to etch the second semiconductor layer 12 of the semiconductor substrate 10. The second semiconductor layer 12 can act as an etch stop layer during the etching of the first semiconductor layer 11. The etching of the second semiconductor layer 12 can expose the third semiconductor layer 13 of the semiconductor substrate 10. After the etching of the second semiconductor layer 12, the third semiconductor layer 13 can remain on the circuit layer 20. In the following description, the third semiconductor layer 13 can be referred to as the semiconductor substrate 10.

[0051] Referring to FIG. 6, a plurality of wafer through electrodes 15 can be formed in the semiconductor substrate 10 (or the third semiconductor layer 13). The formation of the plurality of wafer through electrodes 15 can include, for example, forming a plurality of wafer through holes penetrating the semiconductor substrate 10 (or the third semiconductor layer 13), forming a conductive layer filling the plurality of wafer through holes, and then planarizing the conductive layer. The planarization can locally form the plurality of wafer through electrodes 15 in the corresponding wafer through holes. The plurality of wafer through electrodes 15 can be connected to the circuit layer 20. Each of the plurality of wafer through electrodes 15 can penetrate the semiconductor substrate 10 (or the third semiconductor layer 13) and be connected to a terminal of a corresponding one of the transistors formed in the circuit layer 20.

[0052] A plurality of wafer pads 50 can be formed on the semiconductor substrate 10 (or the third semiconductor layer 13) and on the plurality of wafer through electrodes 15. The formation of the wafer pads 50 can include, for example, forming a pad conductive layer on the semiconductor substrate 10 (or the third semiconductor layer 13), and then patterning the pad conductive layer. The wafer pads 50 can be formed to be horizontally spaced apart from each other. Each of the wafer pads 50 can be electrically connected to a corresponding one of the plurality of wafer through electrodes 15. A pad dielectric layer 52 can be formed on the semiconductor substrate 10 (or the third semiconductor layer 13) and between the wafer pads 50. The pad dielectric layer 52 can expose the surfaces of the wafer pads 50.

[0053] Referring to FIG. 7, the carrier substrate CW and the semiconductor substrate 10 (or the third semiconductor layer 13) that are bonded to each other can be inverted such that the carrier substrate CW and the semiconductor substrate 10 can be disposed on the support substrate SS, and the wafer pads 50 and the pad dielectric layer 52 can be disposed adjacent to the support substrate SS. The semiconductor substrate 10 (or the third semiconductor layer 13) on which the plurality of wafer through electrodes 15 are formed can be disposed adjacent to the wafer pads 50 and the pad dielectric layer 52, and the circuit layer 20 can be disposed between the wafer wiring layer 30 and the semiconductor substrate 10 (or the third semiconductor layer 13). The wafer wiring layer 30 can be disposed between the circuit layer 20 and the carrier substrate CW.

[0054] The carrier substrate CW can be subjected to a grinding process to remove the upper portion of the carrier substrate CW. Thereafter, a sawing process can be performed on the support substrate SS, and thus a plurality of semiconductor wafers 200 can be formed. Each of the plurality of semiconductor wafers 200 can include a semiconductor substrate 10 (or a third semiconductor layer 13), a circuit layer 20 on one surface of the semiconductor substrate 10, a wafer pad 50 and a pad dielectric layer 52 on the other surface of the semiconductor substrate 10, a plurality of wafer through electrodes 15 penetrating the semiconductor substrate 10, a wafer wiring layer 30 on the circuit layer 20, and a residual carrier substrate CW on the wafer wiring layer 30.

[0055] Referring to FIG. 8, an interposer substrate 100 can be provided. The interposer substrate 100 can include a base substrate 110, a plurality of through electrodes 120 penetrating the base substrate 110, and a wiring layer 130 on the base substrate 110. The wiring layer 130 can include a wiring pattern 132 on the base substrate 110 and a wiring dielectric layer 134 covering the wiring pattern 132. The interposer substrate 100 can have a first surface 100a and a second surface 100b opposite to each other, and the wiring layer 130 can be adjacent to the first surface 100a. A plurality of conductive pads 140 can be disposed on the second surface 100b of the interposer substrate 100, and a plurality of connection bumps 150 can be disposed on the second surface 100b of the interposer substrate 100 and on the corresponding conductive pads 140.

[0056] A plurality of semiconductor wafers 200 can be mounted on the first surface 100a of the interposer substrate 100. The plurality of semiconductor wafers 200 can include a first semiconductor wafer 200a and a second semiconductor wafer 200b. According to some embodiments, the first semiconductor wafer 200a and the second semiconductor wafer 200b can be identical to each other.

[0057] The first semiconductor wafer 200a can include a first semiconductor substrate 10a, a first circuit layer 20a on one surface of the first semiconductor substrate 10a, a first wafer pad 50a and a first pad dielectric layer 52a on the other surface of the first semiconductor substrate 10a, a plurality of first wafer through electrodes 15a penetrating the first semiconductor substrate 10a, a first wafer wiring layer 30a on the first circuit layer 20a, and a residual first carrier substrate CWa on the first wafer wiring layer 30a. The first wafer wiring layer 30a can include a first wafer wiring pattern 32a on the first circuit layer 20a, a first wafer wiring dielectric layer 34a covering the first wafer wiring pattern 32a, and a first protective layer 36a on the first wafer wiring dielectric layer 34a.

[0058] The second semiconductor wafer 200b may include a second semiconductor substrate 10b, a second circuit layer 20b on one surface of the second semiconductor substrate 10b, second wafer pads 50b and a second pad dielectric layer 52b on the other surface of the second semiconductor substrate 10b, a plurality of second wafer through electrodes 15b penetrating the second semiconductor substrate 10b, a second wafer wiring layer 30b on the second circuit layer 20b, and a residual second carrier substrate CWb on the second wafer wiring layer 30b. The second wafer wiring layer 30b may include a second wafer wiring pattern 32b on the second circuit layer 20b, a second wafer wiring dielectric layer 34b covering the second wafer wiring pattern 32b, and a second protective layer 36b on the second wafer wiring dielectric layer 34b.

[0059] The first semiconductor substrate 10a and the second semiconductor substrate 10b, the first circuit layer 20a and the second circuit layer 20b, the first wafer pads 50a and the second wafer pads 50b, the first pad dielectric layer 52a and the second pad dielectric layer 52b, the first wafer through electrodes 15a and the second wafer through electrodes 15b, the first wafer wiring layer 30a and the second wafer wiring layer 30b, and the residual first carrier substrate CWa and the residual second carrier substrate CWb may be the same as or substantially the same as the semiconductor substrate 10 (or the third semiconductor layer 13), the circuit layer 20, the wafer pads 50, the pad dielectric layer 52, the wafer through electrodes 15, the wafer wiring layer 30, and the residual carrier substrate CW discussed with reference to FIGS. 3 to 7, respectively.

[0060] Each of the first semiconductor wafer 200a and the second semiconductor wafer 200b can be mounted on the interposer substrate 100 using a die-to-wafer bonding method. For example, the first wafer pads 50a of the first semiconductor wafer 200a can be connected to the uppermost one of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100. Each of the first wafer pads 50a can be directly bonded to the corresponding one of the uppermost wiring patterns 132. Each of the first wafer pads 50a and its corresponding wiring pattern 132 can form, for example, a copper-to-copper (Cu-Cu) bond. Since each of the first wafer pads 50a is directly bonded to its corresponding wiring pattern 132, the first pad dielectric layer 52a can be in direct contact with the wiring dielectric layer 134 in the wiring layer 130 of the interposer substrate 100. The second wafer pads 50b of the second semiconductor wafer 200b can be connected to the uppermost one of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100. Each of the second wafer pads 50b can be directly bonded to the corresponding one of the uppermost wiring patterns 132. Each of the second wafer pads 50b and its corresponding wiring pattern 132 can form, for example, a copper-to-copper (Cu-Cu) bond. Since each of the second wafer pads 50b is directly bonded to its corresponding wiring pattern 132, the second pad dielectric layer 52b can be in direct contact with the wiring dielectric layer 134 in the wiring layer 130 of the interposer substrate 100.

[0061] Referring to FIG. 9, an etching process can be performed on each of the first semiconductor wafer 200a and the second semiconductor wafer 200b mounted on the interposer substrate 100. The etching process can remove the residual first carrier substrate CWa and the residual second carrier substrate CWb of the first semiconductor wafer 200a and the second semiconductor wafer 200b. The etching process can be, for example, a dry etching process. The removal of the residual first carrier substrate CWa and the residual second carrier substrate CWb can expose the first protective layer 36a and the second protective layer 36b of the first semiconductor wafer 200a and the second semiconductor wafer 200b.

[0062] Referring to FIG. 10, a passivation layer 300 may be formed on a first surface 100a of the interposer substrate 100, thereby covering the first semiconductor wafer 200a and the second semiconductor wafer 200b. A plurality of redistribution line patterns 320 may be formed in the passivation layer 300 and on (or above) the first semiconductor wafer 200a and the second semiconductor wafer 200b. The redistribution line patterns 320 may electrically connect the first semiconductor wafer 200a and the second semiconductor wafer 200b to each other. One or more of the redistribution line patterns 320 may be connected to corresponding one or more of the first wafer wiring patterns 32a in the first wafer wiring layer 30a of the first semiconductor wafer 200a, and another or more of the redistribution line patterns 320 may be connected to corresponding one or more of the second wafer wiring patterns 32b in the second wafer wiring layer 30b of the second semiconductor wafer 200b. The formation of the redistribution line patterns 320 may include, for example, forming a portion of the passivation layer 300 covering the first semiconductor wafer 200a and the second semiconductor wafer 200b on the first surface 100a of the interposer substrate 100, forming a redistribution line conductive layer on the said portion of the passivation layer 300, patterning the redistribution line conductive layer to form the redistribution line patterns 320, and forming the remaining portion of the passivation layer 300 covering the redistribution line patterns 320 on the redistribution line patterns 320.

[0063] A plurality of vertical holes 350H may be formed in the passivation layer 300 and horizontally spaced apart from the first semiconductor wafer 200a and the second semiconductor wafer 200b. The vertical holes 350H may expose the uppermost one of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100. Each of the vertical holes 350H may penetrate the passivation layer 300 and expose a corresponding one of the uppermost wiring patterns 132. The formation of the vertical holes 350H may include, for example, forming a mask pattern on the passivation layer 300 that defines an area in which the vertical holes 350H will be formed, and etching the passivation layer 300 using the mask pattern as an etching mask.

[0064] Referring back to FIG. 1, a plurality of conductive pillars 350 may be correspondingly formed in the vertical holes 350H. The formation of the conductive pillars 350 may include, for example, forming a conductive layer that fills the vertical holes 350H on the passivation layer 300, and planarizing the conductive layer until the passivation layer 300 is exposed. The planarization may locally form the conductive pillars 350 in the corresponding vertical holes 350H. Each of the conductive pillars 350 may penetrate the passivation layer 300 and be connected to a corresponding one of the uppermost wiring patterns 132 in the wiring layer 130 of the interposer substrate 100.

[0065] The third semiconductor wafer 400 may be disposed on the passivation layer 300. The third semiconductor wafer 400 may include a plurality of sub-semiconductor wafers 410 stacked vertically, a plurality of sub-through electrodes 420 penetrating the plurality of sub-semiconductor wafers 410 correspondingly, a plurality of sub-bumps 430 between the plurality of sub-semiconductor wafers 410, and a molding layer 440 covering the plurality of sub-semiconductor wafers 410. The plurality of sub-semiconductor wafers 410 may be electrically connected to each other via the sub-bumps 430 and the sub-through electrodes 420. The third semiconductor wafer 400 may be, for example, a high bandwidth memory (HBM) wafer.

[0066] A plurality of bumps 450 may be formed on the bottom surface of the third semiconductor wafer 400. The bumps 450 may be connected to the lowermost one of the sub-semiconductor wafers 410 included in the third semiconductor wafer 400. Each of the bumps 450 may be connected to a corresponding one of the sub-through electrodes 420 penetrating the lowermost sub-semiconductor wafer 410. The third semiconductor wafer 400 may be disposed on the passivation layer 300 to allow the bumps 450 to be connected to the corresponding conductive pillars 350. The third semiconductor wafer 400 may be electrically connected to the corresponding one of the wiring patterns 132 in the wiring layer 130 of the interposer substrate 100 via the bumps 450 and the conductive pillars 350.

[0067] FIG. 11 shows a cross-sectional view of a semiconductor package illustrating some embodiments according to the inventive concept. The following semiconductor package is similar to the semiconductor packages discussed with reference to FIGS. 1 and 2, and thus, for brevity of description, the main differences between the semiconductor packages will be described below.

[0068] Referring to FIG. 11, the semiconductor package 1100 may further include a lower substrate 500 and a heat radiation structure 550 on the lower substrate 500. The components of the semiconductor package 1000 discussed with reference to FIGS. 1 and 2 may be disposed on the lower substrate 500 and within the heat radiation structure 550.

[0069] The lower substrate 500 may include a first substrate pad 510 adjacent to the first surface 500a of the lower substrate 500, and may also include a second substrate pad 520 adjacent to the bottom surface 500b of the lower substrate 500. The first substrate pad 510 may be electrically connected to the second substrate pad 520 via internal wiring in the lower substrate 500. The first substrate pad 510 and the second substrate pad 520 may include a conductive material. The lower substrate 500 may be provided with lower bumps 530 correspondingly connected to the second substrate pad 520 on its bottom surface 500b. The lower bumps 530 may include a conductive material and may have at least one selected from a solder ball shape, a bump shape, and a column shape. The lower substrate 500 may be, for example, a printed circuit board, a lower semiconductor wafer, or a lower semiconductor package.

[0070] The interposer substrate 100 can be mounted on the top surface 500a of the lower substrate 500. The conductive pads 140 can be disposed on the first substrate pads 510 of the lower substrate 500, and the connection bumps 150 can be disposed between the conductive pads 140 and the first substrate pads 510. Each of the conductive pads 140 can be connected to a corresponding one of the first substrate pads 510 via a corresponding one of the connection bumps 150. The interposer substrate 100 can be electrically connected to the lower substrate 500 via the conductive pads 140, the connection bumps 150, and the first substrate pads 510.

[0071] The lower underfill layer 540 can be disposed between the interposer substrate 100 and the lower substrate 500, and can cover the conductive pads 140 and the connection bumps 150. The lower underfill layer 540 can include a dielectric polymer material such as epoxy resin.

[0072] The lower substrate 500 can be provided with a thermal radiation structure 550 on its top surface 500a for covering the components of the semiconductor package 1000 discussed with reference to FIGS. 1 and 2. The thermal radiation structure 550 can include a heat conductive material. The heat conductive material can include a metal material (e.g., copper and / or aluminum) or a carbon-containing material (e.g., graphene, graphite, and / or carbon nanotubes). For example, the thermal radiation structure 550 can include a single metal layer or multiple stacked metal layers. As another example, the thermal radiation structure 550 can include a heat sink or a heat pipe. As another example, the thermal radiation structure 550 can be configured to use water cooling.

[0073] The semiconductor package 1100 can further include a heat conductive layer 560 inserted between the passivation layer 300 and the thermal radiation structure 550 and between the third semiconductor wafer 400 and the thermal radiation structure 550. The heat conductive layer 560 can include a thermal interface material (TIM). The thermal interface material can include, for example, a polymer and heat conductive particles. The heat conductive particles can be dispersed in the polymer. The heat generated from the plurality of semiconductor wafers 200a, the semiconductor wafer 200b, and the semiconductor wafer 400 can be transferred to the thermal radiation structure 550 via the heat conductive layer 560.

[0074] According to an embodiment of the present invention concept, the interposer substrate can include a power delivery network (PDN) for supplying power or ground to the semiconductor wafers mounted on the interposer substrate. A plurality of wafer pads of the semiconductor wafers can be directly bonded to corresponding ones of the wiring patterns included in the interposer substrate, so that the semiconductor wafers can be connected to the power delivery network (PDN). In addition, the semiconductor wafers can be electrically connected to each other via a redistribution wiring pattern formed on (or above) the semiconductor wafers.

[0075] Since the chip pads are directly bonded to the corresponding wiring patterns of the interposer substrate, the heat generated from the semiconductor chip can be easily discharged through the interposer substrate. In addition, since the semiconductor chips are electrically connected to each other via the redistribution wiring patterns on the semiconductor chips, the interconnections can be easily established between the semiconductor chips.

[0076] Therefore, it is possible to provide a semiconductor package in which interconnections are easily established between a plurality of semiconductor chips and which exhibits improved heat radiation properties.

[0077] Although some embodiments explaining the inventive concept have been described, the inventive concept is not limited to the embodiments described above. Those of ordinary skill in the art should understand that form and detail changes can be made therein without departing from the spirit and scope of the inventive concept as set forth in the claims.

Brief Description of the Drawings

[0009] FIG. 1 shows a cross-sectional view of a semiconductor package illustrating some embodiments according to the inventive concept. FIG. 2 shows an enlarged view of part PP of FIG. 1. FIGS. 3 to 10 show cross-sectional views of a method of manufacturing a semiconductor package illustrating some embodiments according to the inventive concept. FIG. 11 shows a cross-sectional view of a semiconductor package illustrating some embodiments according to the inventive concept.

Claims

1. A semiconductor package, comprising: An interposer substrate having a first surface and a second surface opposite to each other, the interposer substrate including a wiring layer adjacent to the first surface and a plurality of through electrodes penetrating the interposer substrate and connected to the wiring layer, each of the plurality of through electrodes extending from the wiring layer toward the second surface; a semiconductor wafer on the first surface of the interposer substrate; and a passivation layer on the first surface of the interposer substrate, the passivation layer covering the semiconductor wafer. The semiconductor wafer includes a plurality of redistribution patterns in the passivation layer and connected to the semiconductor wafer, wherein the semiconductor wafer has a third surface and a fourth surface opposite to each other, the third surface of the semiconductor wafer facing the first surface of the interposer substrate, and the plurality of redistribution patterns connected to the fourth surface of the semiconductor wafer, wherein the semiconductor wafer includes: a plurality of wafer pads adjacent to the third surface; a semiconductor substrate located on the plurality of wafer pads such that the plurality of wafer pads are located between the semiconductor substrate and the interposer substrate; a plurality of through-wafer electrodes penetrating the semiconductor substrate and connected to the plurality of wafer pads; a circuit layer located on the semiconductor substrate; and a wafer wiring layer located on the circuit layer and adjacent to the fourth surface, wherein each of the plurality of wafer pads is directly bonded to a corresponding one of the plurality of wiring patterns in the wiring layer of the interposer substrate, and wherein the plurality of redistribution patterns are connected to the plurality of wafer wiring patterns in the wafer wiring layer.

2. The semiconductor package of claim 1, wherein the circuit layer is located between the wafer wiring layer and the plurality of through-wafer electrodes, and wherein the plurality of through-wafer electrodes and the plurality of wafer wiring patterns in the wafer wiring layer are connected to the circuit layer.

3. The semiconductor package as claimed in claim 2, wherein the plurality of wafers have through electrodes between the circuit layer and the plurality of wafer pads.

4. The semiconductor package of claim 1, wherein each of the plurality of redistribution patterns and the plurality of wafer wiring patterns in the wafer wiring layer has a thickness in a direction perpendicular to the first surface of the interposer substrate, and wherein the thickness of each of the plurality of redistribution patterns is greater than the thickness of each of the plurality of wafer wiring patterns.

5. The semiconductor package of claim 1, wherein each of the plurality of redistribution patterns and the wiring layer of the interposer substrate has a thickness in a direction perpendicular to the first surface of the interposer substrate, and wherein the thickness of each of the plurality of redistribution patterns is greater than the thickness of each of the plurality of wiring patterns.

6. The semiconductor package of claim 1, wherein the size of each of the plurality of through electrodes contained in the interposer substrate is greater than the size of each of the plurality of wafer through electrodes contained in the semiconductor wafer.

7. The semiconductor package of claim 1, wherein the wiring layer of the interposer substrate includes a wiring dielectric layer covering the plurality of wiring patterns, and the semiconductor wafer further includes a pad dielectric layer covering the plurality of wafer pads, wherein the pad dielectric layer is in direct contact with the wiring dielectric layer in the wiring layer.

8. A semiconductor package, comprising: An interposer substrate has a first surface and a second surface opposite to each other, the interposer substrate including a wiring layer adjacent to the first surface; A first semiconductor wafer and a second semiconductor wafer are horizontally spaced apart from each other on the first surface of the interposer substrate; a passivation layer is provided on the first surface of the interposer substrate, and the passivation layer covers the first semiconductor wafer and the second semiconductor wafer. The first semiconductor wafer comprises a plurality of redistribution patterns in the passivation layer connecting the first semiconductor wafer to the second semiconductor wafer. The first semiconductor wafer has a third surface and a fourth surface opposite to each other. The first semiconductor wafer includes: a plurality of first wafer pads adjacent to the third surface; a first semiconductor substrate located on the plurality of first wafer pads such that the plurality of first wafer pads are located between the first semiconductor substrate and the interposer substrate; a plurality of first wafer through electrodes penetrating the first semiconductor substrate and connected to the plurality of first wafer pads; and a first circuit layer located on the first semiconductor substrate. The second semiconductor wafer has a fifth surface and a sixth surface opposite to each other. The second semiconductor wafer includes: a plurality of second wafer pads adjacent to the fifth surface; a second semiconductor substrate located on the plurality of second wafer pads such that the plurality of second wafer pads are located between the second semiconductor substrate and the interposer substrate; a plurality of second wafer through electrodes spaced apart from each other in the second semiconductor substrate, penetrating the second semiconductor substrate and connected to the plurality of second wafer pads; and a second circuit layer located on the second semiconductor substrate. Each of the plurality of first wafer pads and the plurality of second wafer pads is directly bonded to a corresponding one of the plurality of wiring patterns in the wiring layer of the interposer substrate, and the plurality of redistribution patterns are connected to the fourth surface of the first semiconductor wafer and the sixth surface of the second semiconductor wafer.

9. The semiconductor package of claim 8, wherein the interposer substrate further includes a plurality of through electrodes penetrating the interposer substrate, and wherein each of the plurality of through electrodes is connected to the wiring layer and extends from the wiring layer toward the second surface.

10. The semiconductor package of claim 9, wherein the first semiconductor wafer further includes a first wafer wiring layer adjacent to the fourth surface, the first circuit layer being between the first wafer wiring layer and the first semiconductor substrate, and the second semiconductor wafer further includes a second wafer wiring layer adjacent to the sixth surface, the second circuit layer being between the second wafer wiring layer and the second semiconductor substrate, the plurality of first wafer through electrodes being located between the first circuit layer and the plurality of first wafer pads, and the plurality of second wafer through electrodes being located between the second circuit layer and the plurality of second wafer pads.

11. The semiconductor package of claim 10, wherein the plurality of redistribution patterns are connected to a plurality of first wafer wiring patterns in the first wafer wiring layer of the first semiconductor wafer and to a plurality of second wafer wiring patterns in the second wafer wiring layer of the second semiconductor wafer.

12. The semiconductor package of claim 8, wherein the plurality of first wafer through electrodes are connected to the first circuit layer, and the plurality of second wafer through electrodes are connected to the second circuit layer.

13. The semiconductor package of claim 9, wherein the size of each of the plurality of through electrodes included in the interposer substrate is greater than the size of each of the plurality of first wafer through electrodes and the plurality of second wafer through electrodes.

14. The semiconductor package of claim 8, wherein each of the plurality of redistribution patterns and the wiring layer of the interposer substrate has a thickness in a direction perpendicular to the first surface of the interposer substrate, and wherein the thickness of each of the plurality of redistribution patterns is greater than the thickness of each of the plurality of wiring patterns.

15. The semiconductor package as claimed in claim 8, wherein the first semiconductor wafer and the second semiconductor wafer are identical to each other.

16. The semiconductor package as described in claim 8, further comprising: A third semiconductor wafer is disposed on the passivation layer; And a plurality of conductive pillars beneath the third semiconductor wafer, the plurality of conductive pillars penetrating the passivation layer and connected to the wiring layer of the interposer substrate, wherein the plurality of conductive pillars are connected to corresponding ones of the plurality of wiring patterns in the wiring layer.

17. The semiconductor package of claim 16, wherein the first semiconductor wafer and the second semiconductor wafer are identical to each other, and the third semiconductor wafer is different from the first semiconductor wafer and the second semiconductor wafer.

18. The semiconductor package of claim 16, wherein the first semiconductor wafer, the second semiconductor wafer, and each of the plurality of conductive pillars have a thickness in a direction perpendicular to the first surface of the interposer substrate, and wherein the thickness of each of the plurality of conductive pillars is greater than the thickness of each of the first semiconductor wafer and the second semiconductor wafer.

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