Semiconductor memory device and manufacturing method of semiconductor memory device

Abstract

This disclosure provides a semiconductor memory device and a method for manufacturing the semiconductor memory device. The semiconductor memory device includes a conductive gate contact extending through a contact region of a stepped stacked structure, the stepped stacked structure including multiple interlayer insulating layers and multiple conductive patterns stacked alternately.

Description

[Technical Field]

[0001] This disclosure generally relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device, and more specifically to a three-dimensional semiconductor memory device and a method for manufacturing a three-dimensional semiconductor memory device. Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0076983, filed with the Korean Intellectual Property Office on June 14, 2021, the entire disclosure of which is incorporated herein by reference. [Previous Technology]

[0003] A semiconductor memory device includes memory cells capable of storing data. A three-dimensional semiconductor memory device includes a three-dimensional array of memory cells.

[0004] To improve the integration of a three-dimensional memory cell array, the number of stacked memory cells can be increased. As the number of stacked memory cells increases, the manufacturing process of the three-dimensional semiconductor memory device may become more complex, and the structural stability of the three-dimensional semiconductor memory device may deteriorate. [Summary of the Invention]

[0005] According to one embodiment of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a first conductive gate contact; a first contact insulating pattern surrounding the first conductive gate contact; a first conductive pattern surrounding the first contact insulating pattern; and a second conductive pattern disposed above the first conductive pattern and surrounding the first conductive gate contact, wherein the second conductive pattern comprises: a first edge portion overlapping the first contact insulating pattern and contacting the first conductive gate contact; and a first base portion spaced apart from the first conductive gate contact portion by the first edge portion, extending away from the first conductive gate contact portion from the first edge portion, and the first base portion being thicker than the first edge portion.

[0006] According to another embodiment of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a horizontally doped semiconductor pattern; a stepped stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked on the horizontally doped semiconductor pattern, the stepped stack structure including a cell region overlapping the horizontally doped semiconductor pattern and a contact region extending from the cell region; a cell channel layer in contact with the horizontally doped semiconductor pattern and penetrating the cell region of the stepped stack structure; a plurality of conductive gate contacts penetrating the contact region of the stepped stack structure and extending to the height at which the horizontally doped semiconductor pattern is disposed; and a protective layer penetrating the sidewall of each of the conductive gate contacts.

[0007] According to another embodiment of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a stepped stack structure, the stepped stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked, the stepped stack structure including a cell region and a contact region extending from the cell region; a horizontally doped semiconductor pattern disposed below the cell region of the stepped stack structure; a lower insulating layer disposed below the contact region of the stepped stack structure, the lower insulating layer being substantially at the height at which the horizontally doped semiconductor pattern is disposed; a plurality of lower contacts penetrating the lower insulating layer; a cell channel layer contacting the horizontally doped semiconductor pattern, the cell channel layer penetrating the cell region of the stepped stack structure; and a plurality of conductive gate contacts connected to the plurality of lower contacts, the plurality of conductive gate contacts penetrating the contact region of the stepped stack structure.

[0008] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor memory device is provided, the method comprising the steps of: forming a preliminary stepped stacked structure, the preliminary stepped stacked structure including a lower interlayer insulating layer, an intermediate interlayer insulating layer, an upper interlayer insulating layer, a lower sacrificial layer, and an upper sacrificial layer, the lower sacrificial layer including a lower base portion located between the lower interlayer insulating layer and the intermediate interlayer insulating layer, and a lower edge portion protruding further to the side from the lower base portion relative to the intermediate interlayer insulating layer and being thinner than the lower base portion, the upper sacrificial layer including a lower base portion located between the intermediate interlayer insulating layer and the upper sacrificial layer. The upper base between the upper interlayer insulation layers and the upper edge portion that protrudes further from the upper base relative to the upper interlayer insulation layer and is thinner than the upper base portion; a filler insulation layer is formed, which covers the initial stepped stacked structure; a contact hole is formed, which penetrates the filler insulation layer, the upper edge portion, the middle interlayer insulation layer, the lower base and the lower interlayer insulation layer; the upper edge portion is replaced by a sacrificial pad through the contact hole; a portion of the lower base portion is replaced by a contact portion insulation pattern through the contact hole; and a support structure surrounded by the contact portion insulation pattern and the sacrificial pad is formed in the contact hole.

[0009] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor memory device is provided, the method comprising the steps of: forming a lower stacked structure in which horizontal layers and protective layers are stacked; isolating the lower stacked structure into a preliminary horizontal pattern and a preliminary contact structure; forming a preliminary stepped stacked structure by stacking a lower interlayer insulating layer, a lower sacrificial layer, an intermediate interlayer insulating layer, an upper sacrificial layer and an upper interlayer insulating layer over the preliminary horizontal pattern and the preliminary contact structure; forming a support structure through the preliminary stepped stacked structure, the support structure extending into the interior of the preliminary contact structure; replacing each of the lower sacrificial layer and the upper sacrificial layer with a conductive pattern; and replacing the horizontal layer and the support structure of the preliminary contact structure with a conductive gate contact.

[0010] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor memory device is provided, the method comprising: forming a lower stacked structure in which horizontal layers and protective layers are stacked; isolating the lower stacked structure into a preliminary horizontal pattern and a preliminary contact structure; forming a lower contact portion through the preliminary contact structure; forming a preliminary stepped stacked structure including a plurality of alternately stacked interlayer insulating layers and a plurality of sacrificial layers above the lower structure including the preliminary horizontal pattern, the preliminary contact structure and the lower contact portion; etching the preliminary stepped stacked structure to form slits through the preliminary stepped stacked structure in a cell region overlapping with the horizontal layers, and contact holes through the preliminary stepped stacked structure in a contact region overlapping with the lower contact portion; forming a support structure disposed in the contact holes, the support structure extending between the interlayer insulating layers; replacing each of the sacrificial layers with a conductive pattern; and replacing a portion of the support structure in the contact holes with a conductive gate contact portion connected to the lower contact portion.

Implementation Method

[0029] The specific structural and functional descriptions disclosed herein are merely illustrative and intended to describe embodiments of the concept according to this disclosure. Embodiments of the concept according to this disclosure can be implemented in various forms and should not be construed as limited to the specific embodiments described herein.

[0030] In the following text, the terms “first” and “second” are used to distinguish one component from another and are not intended to imply a specific number or order of parts. These terms can be used to describe various components, but components are not limited by these terms. It should be understood that when an element is referred to as “coupled” or “connected” to another element, the one element can be directly coupled or connected to the other element, or there may be intermediate elements therein. Conversely, it should be understood that when an element is referred to as “directly coupled” or “directly connected” to another element, there are no intermediate elements.

[0031] The embodiments provide a semiconductor memory device and a method for manufacturing a semiconductor memory device, which can improve structural stability and manufacturing process stability.

[0032] FIG1 is a diagram showing a schematic structure of a semiconductor memory device according to one embodiment of the present disclosure.

[0033] Referring to FIG1, a semiconductor memory device may include a memory cell array 20 and peripheral circuitry 30 for controlling the memory cell array 20. The memory cell array 20 may be disposed above the peripheral circuitry 30. Therefore, in one embodiment, the area of ​​the substrate occupied by the memory cell array 20 and the peripheral circuitry 30 can be reduced.

[0034] The memory cell array 20 may include multiple memory blocks. Each memory block may be connected to the peripheral circuitry 30 via bit line BL1 or BL2, word line WL, source select line SSL, drain select line DSL1 or DSL2, and common source pattern CSL.

[0035] Each memory block may include multiple bit lines. These multiple bit lines may include a first bit line BL1 and a second bit line BL2. The number of bit lines is not limited to the number shown in the attached diagram.

[0036] Multiple memory cell strings can be connected in parallel to each bit line BL1 or BL2. Each memory block may include a first memory cell string CS1, a second memory cell string CS2, a third memory cell string CS3, and a fourth memory cell string CS4 connected in parallel to the common source pattern CSL. In one embodiment, the first memory cell string CS1 and the third memory cell string CS3 may be connected in parallel to the first bit line BL1, and the second memory cell string CS2 and the fourth memory cell string CS4 may be connected in parallel to the second bit line BL2. The number of memory cell strings connected to each bit line BL1 or BL2 and the number of memory cell strings connected to the common source pattern CSL are not limited to the numbers shown in the figures.

[0037] The first memory unit string CS1, the second memory unit string CS2, the third memory unit string CS3, and the fourth memory unit string CS4 can be connected to multiple character lines WL. The first memory unit string CS1, the second memory unit string CS2, the third memory unit string CS3, and the fourth memory unit string CS4 can be connected together to each character line WL.

[0038] The first memory cell string CS1, the second memory cell string CS2, the third memory cell string CS3, and the fourth memory cell string CS4, which are commonly connected to each character line WL, can be individually connected to two or more source select lines isolated from each other, or individually connected to two or more drain select lines isolated from each other. In one embodiment, the first memory cell string CS1, the second memory cell string CS2, the third memory cell string CS3, and the fourth memory cell string CS4 can be commonly connected to the source select line SSL. The first memory cell string CS1 and the second memory cell string CS2, which are respectively connected to the first character line BL1 and the second character line BL2, can be commonly connected to the first drain select line DSL1, and the third memory cell string CS3 and the fourth memory cell string CS4, which are respectively connected to the first character line BL1 and the second character line BL2, can be commonly connected to the second drain select line DSL2. However, this disclosure is not limited to this, and the connection structure of the memory cell strings, drain select lines, and source select lines can be various.

[0039] Each memory cell string CS1, CS2, CS3, or CS4 may include a source select transistor SST, a drain select transistor DST, and multiple memory cells MC connected in series with each other. Each memory cell string CS1, CS2, CS3, or CS4 may be connected to a common source pattern CSL via the source select transistor SST. Each memory cell string CS1, CS2, CS3, or CS4 may be connected to its corresponding bit line BL1 or BL2 via the drain select transistor DST. Multiple memory cells MC may be connected in series between the source select transistor SST and the drain select transistor DST through a cell channel layer.

[0040] The gate of the source-select transistor SST can be connected to the source-select line SSL. The gate of the drain-select transistor DST can be connected to the drain-select line DSL1 or DSL2. The gate of the memory cell MC can be connected to its corresponding word line WL.

[0041] Peripheral circuitry 30 may include source driver SD, page buffer PB, and column decoder RD.

[0042] The source driver SD can be connected to the memory cell array 20 via a common source pattern CSL. The source driver SD can transfer the voltage required for the operation of the memory cell array 20 to the common source pattern CSL.

[0043] The column decoder RD can be connected to the memory cell array 20 via multiple word lines WL, source select line SSL, and first drain select line DSL1 and second drain select line DSL2. The column decoder RD can be configured to transmit operating voltage to the multiple word lines WL, source select line SSL, first drain select line DSL1 and second drain select line DSL2 in response to a column address signal.

[0044] The page buffer PB can be connected to the memory cell array 20 via the first bit line BL1 and the second bit line BL2. The page buffer PB can selectively precharge the first bit line BL1 and the second bit line BL2 according to the external data input to it, so as to store the data in the memory cell. The page buffer PB can sense the current or voltage of the first bit line BL1 and the second bit line BL2 to read data from the memory cell MC.

[0045] The source driver SD, page buffer PB and column decoder RD can be connected to multiple word lines WL, source select line SSL, first drain select line DSL1 and second drain select line DSL2, as well as first bit line BL1 and second bit line BL2 via interconnects.

[0046] FIG2 is a plan view showing a portion of a semiconductor memory device according to one embodiment of the present disclosure.

[0047] Referring to FIG2, the semiconductor memory device may include a plurality of stepped stacked structures ST isolated from each other by a plurality of slits SI. Each stepped stacked structure ST may include a cell region CAR, a contact region CTR, and an extension region ER.

[0048] The element region CAR of the stepped stacked structure ST can be penetrated by multiple element plugs CPL. The multiple element plugs CPL can be arranged in a zigzag pattern on the XY plane of the XYZ coordinate system. The arrangement of the multiple element plugs CPL is not limited to this. Each element plug CPL can extend along the Z-axis direction of the XYZ coordinate system. The element plugs CPL can have various cross-sectional shapes, including circular, elliptical, polygonal, and square shapes.

[0049] The contact area CTR of the stepped stacked structure ST can extend from the cell area CAR. The contact area CTR of the stepped stacked structure ST can be penetrated by multiple conductive gate contacts 181A. Each conductive gate contact 181A can extend in the Z-axis direction. The conductive gate contact 181A can have various cross-sectional shapes, including circular, elliptical, polygonal, and square shapes. The conductive gate contact 181A can be formed to have an area wider than that of the cell plug CPL in the XY plane.

[0050] The extension region ER of the stepped stacked structure ST can extend from the contact region CTR. The extension region ER of the stepped stacked structure ST can be penetrated by multiple dummy contacts 181B. The dummy contacts 181B can have various cross-sectional shapes, including circular, elliptical, polygonal, and square shapes. Each dummy contact 181B can be formed to have an area wider than the area of ​​the unit plug CPL in the XY plane. In one embodiment, the dummy contact 181B can be formed to have an area in the XY plane that is substantially equal to the area of ​​the conductive gate contact 181A.

[0051] At least one drain isolation slit DSI can be disposed between adjacent slits SI. The first drain selection line DSL1 and the second drain selection line DSL2 shown in FIG1 can be isolated from each other by the drain isolation slit DSI. The drain isolation slit DSI can be embedded in a stepped stack structure ST. In the Z-axis direction, the drain isolation slit DSI can be shorter than the slit SI.

[0052] Figures 3A, 3B, and 3C are cross-sectional views of the semiconductor memory device shown in Figure 2. Figure 3A shows a cross-section of the cell region CAR of the stepped stacked structure ST taken along line A-A' shown in Figure 2. Figure 3B shows a cross-section of the contact region CTR of the stepped stacked structure ST taken along line B-B' shown in Figure 2. Figure 3C shows a cross-section of the extension region ER of the stepped stacked structure ST taken along line C-C' shown in Figure 2.

[0053] Referring to Figures 3A to 3C, a stepped stacked structure ST can be disposed on a first lower insulating layer 101, which is penetrated by a plurality of lower contact portions 103A and a plurality of lower dummy contact portions 103B. The plurality of lower contact portions 103A and the plurality of lower dummy contact portions 103B can be formed of various conductive materials.

[0054] The semiconductor memory device may include a horizontal source layer 10 and a second lower insulating layer 104 located between a first lower insulating layer 101 and a stepped stacked structure ST.

[0055] The horizontal source layer 10 may include a first semiconductor pattern 105A, a horizontally doped semiconductor pattern 173H, and a second semiconductor pattern 111A stacked on the first lower insulating layer 101. Each of the first semiconductor pattern 105A, the horizontally doped semiconductor pattern 173H, and the second semiconductor pattern 111A may include at least one of n-type impurities and p-type impurities. In one embodiment, each of the first semiconductor pattern 105A, the horizontally doped semiconductor pattern 173H, and the second semiconductor pattern 111A may include an n-type impurity. The horizontal source layer 10 may overlap with the cell region CAR of the stepped stacked structure ST.

[0056] The second lower insulating layer 104 may be disposed at a height substantially equal to the height of the horizontal source layer 10. In one embodiment, the second lower insulating layer 104 is disposed below the contact region CTR of the stepped stack structure ST, at a height substantially equal to the height of the horizontally doped semiconductor pattern 173H. The second lower insulating layer 104 may be disposed between the first lower insulating layer 101 and each of the contact region CTR and the extension region ER of the stepped stack structure ST.

[0057] The cell plug CPL may extend into the interior of the horizontal source layer 10. In one embodiment, the cell plug CPL may penetrate the second semiconductor pattern 111A and the horizontally doped semiconductor pattern 173H, and extend into the interior of the first semiconductor pattern 105A. The cell plug CPL may include a channel structure CH and a memory pattern 151A surrounding the channel structure CH.

[0058] The horizontally doped semiconductor pattern 173H can penetrate the memory pattern 151A to contact the channel structure CH. The memory pattern 151A can be isolated into a first memory pattern 151P1 and a second memory pattern 151P2 by the horizontally doped semiconductor pattern 173H. The first memory pattern 151P1 can be disposed between the channel structure CH and the stepped stacked structure ST. The second memory pattern 151P2 can be disposed between the channel structure CH and the first semiconductor pattern 105A.

[0059] In one embodiment, the memory pattern 151A may include a tunneling insulating layer, a data storage layer, and a first barrier insulating layer. The tunneling insulating layer may extend along the surface of the channel structure CH and includes an insulating material through which charge can tunnel. The data storage layer may extend along the surface of the channel structure CH and have the tunneling insulating layer interposed therebetween. The data storage layer may include a material layer capable of storing data altered using Fowler-Nordheim tunneling. In one embodiment, the data storage layer may include a nitride layer therein capable of trapping charge. However, this disclosure is not limited thereto, and the data storage layer may include phase change materials, nanodots, etc. The first barrier insulating layer may extend along the surface of the channel structure CH and have the tunneling insulating layer and the data storage layer interposed therebetween. The first barrier insulating layer may include an insulating material capable of blocking charge movement.

[0060] The channel structure CH may include a cell channel layer 153A, a core insulating pattern 155A, and a capping pattern 157. The cell channel layer 153A serves as a channel for memory cell strings. The cell channel layer 153A may be connected to the horizontally doped semiconductor pattern 173H of the horizontal source layer 10.

[0061] A cell channel layer 153A may be disposed on a memory pattern 151A. The cell channel layer 153A may be formed of a semiconductor material. For example, the cell channel layer 153A may include silicon. A core insulating pattern 155A and a capping pattern 157 may fill the central region of the channel structure CH. The core insulating pattern 155A may include an oxide. The capping pattern 157 may be disposed on the core insulating pattern 155A and includes a sidewall surrounded by the upper end of the cell channel layer 153A. The capping pattern 157 may include a doped semiconductor layer, which includes at least one of n-type impurities and p-type impurities.

[0062] The stepped stacked structure ST may include multiple interlayer insulating layers IL and multiple conductive patterns CP that are alternately stacked in the Z-axis direction.

[0063] Multiple conductive patterns CP can be used as source select lines SSL, multiple word lines WL, and drain select lines DSL1 or DSL2 as shown in FIG1. ​​In one embodiment, the bottommost layer of the multiple conductive patterns CP can be used as the source select line SSL as shown in FIG1, the topmost layer of the multiple conductive patterns CP can be used as the drain select lines DSL1 or DSL2 as shown in FIG1, and multiple intermediate layers located between the bottommost and topmost layers of the multiple conductive patterns CP can be used as the multiple word lines WL as shown in FIG1.

[0064] Multiple conductive patterns CP extend from the cell region CAR of the stepped stacked structure ST toward the contact region CTR and the extension region ER. The multiple contact patterns CP can form a stepped structure in the contact region CTR and the extension region ER. Therefore, the multiple conductive patterns CP can extend to have a longer length as they move closer to the second lower insulating layer 104 in the contact region CTR and the extension region ER. In one embodiment, the multiple conductive patterns CP can extend to have a longer length in the X-axis direction as they move closer to the second lower insulating layer 104 in the contact region CTR and the extension region ER.

[0065] Each conductive pattern CP may include an edge portion CE and a base portion CB extending from the edge portion CE. Multiple edge portions CE of multiple conductive patterns CP may form a stepped structure in the contact region CTR and the extension region ER. Multiple base portions CB of multiple contact patterns CP may extend from multiple edge portions CE to the cell region CAR to surround the cell plug CPL.

[0066] The stepped stacked structure ST may be covered by a filling insulating layer 131. The filling insulating layer 131 may include a first filling insulating layer 131A and a second filling insulating layer 131B located on the first filling insulating layer 131A. The first filling insulating layer 131A may overlap with the contact area CTR and the extension area ER of the stepped stacked structure ST to cover multiple edges CE of multiple conductive patterns CP. The second filling insulating layer 131B may extend to cover the cell area CAR, the contact area CTR, and the extension area ER of the stepped stacked structure ST. The filling insulating layer 131 may be penetrated by cell plugs CPL and slits SI.

[0067] The filling insulating layer 131 and the plurality of edge portions CE may be penetrated by a plurality of conductive gate contacts 181A and a plurality of dummy contacts 181B. The plurality of conductive gate contacts 181A may respectively penetrate the plurality of edge portions CE in the contact region CTR, and the plurality of dummy contacts 181B may respectively penetrate the plurality of edge portions CE in the extension region ER. Each of the conductive gate contacts 181A and the dummy contacts 181B may be surrounded by at least one of a plurality of conductive patterns CP and at least one of a plurality of interlayer insulating layers IL. At least one of the plurality of conductive gate contacts 181A and the plurality of dummy contacts 181B may penetrate the base CB of at least one of the plurality of conductive patterns CP.

[0068] The plurality of conductive gate contacts 181A and the plurality of dummy contacts 181B can not only be spaced apart from the plurality of bases CB of the plurality of conductive patterns CP, but can also be insulated from the plurality of conductive patterns CP by the plurality of contact insulating patterns 141. The plurality of contact insulating patterns 141 may include a first contact insulating pattern 141A and a second contact insulating pattern 141B. The first contact insulating pattern 141A may be disposed between the conductive gate contact 181A and the bases CB of the conductive pattern CP. The first contact insulating pattern 141A may surround the sidewall of its corresponding conductive gate contact 181A. The second contact insulating pattern 141B may be disposed between the dummy contact 181B and the bases CB of the conductive pattern CP. The second contact insulating pattern 141B may surround its corresponding dummy contact 181B.

[0069] The plurality of conductive gate contacts 181A and the plurality of dummy contacts 181B may extend to the height at which the horizontal source layer 10 is disposed. For example, the plurality of conductive gate contacts 181A and the plurality of dummy contacts 181B may extend through the second lower insulating layer 104. At least one recess filled with a protective layer may be defined at the sidewalls of the conductive gate contacts 181A and the sidewalls of the dummy contacts 181B. In one embodiment, the semiconductor memory device may include a first protective layer 107 and a second protective layer 109, which are spaced apart from each other in the Z-axis direction at the height at which the horizontal source layer 10 and the second lower insulating layer 104 are disposed. The first protective layer 107 and the second protective layer 109 may extend through the sidewall of the conductive gate contact 181A or through the sidewall of the dummy contact 181B. Each of the first protective layer 107 and the second protective layer 109 may surround the sidewall of its corresponding conductive gate contact 181A or dummy contact 181B.

[0070] The slit SI can be filled using a sidewall insulating layer 171 and a conductive vertical contact 173VC. The sidewall insulating layer 171 can extend along the sidewalls of the plurality of conductive patterns CP and the plurality of interlayer insulating layers IL. The slit SI and the sidewall insulating layer 171 can extend through the second semiconductor pattern 111A. The conductive vertical contact 173VC can be disposed on the sidewall insulating layer 171 and in the central region of the slit SI. The conductive vertical contact 173VC can not only be spaced apart from the plurality of conductive patterns CP, but also be insulated from the plurality of conductive patterns CP by the sidewall insulating layer 171. The conductive vertical contact 173VC can extend from the horizontally doped semiconductor pattern 173H in the Z-axis direction parallel to the cell channel layer 153A. In one embodiment, the conductive vertical contact 173VC can be integrated with the horizontally doped semiconductor pattern 173H and formed of the same material as the horizontally doped semiconductor pattern 173H. However, the embodiments of this disclosure are not limited thereto. In another embodiment, the conductive vertical contact 173VC may include a conductive material different from the conductive material of the horizontally doped semiconductor pattern 173H. For example, the conductive vertical contact 173VC may include a metal. The conductive vertical contact 173VC and the horizontally doped semiconductor pattern 173H can be used as the common source pattern CSL shown in FIG. 1.

[0071] The semiconductor memory device may include a second barrier insulating layer 161 extending along the surface of each conductive pattern CP. The second barrier insulating layer 161 may include an insulating material with a dielectric constant higher than that of the first barrier insulating layer of the memory pattern 151A. In one embodiment, the first barrier insulating layer may include silicon oxide, and the second barrier insulating layer 161 may include a metal oxide such as aluminum oxide.

[0072] The second barrier insulating layer 161 may include a first opening OP1 facing the sidewall insulating layer 171, a second opening OP2 facing each conductive gate contact 181A, and a third opening OP3 facing each dummy contact 181B. The conductive pattern CP can contact the sidewall insulating layer 171 through the first opening OP1. The conductive pattern CP can contact its corresponding conductive gate contact 181A through the second opening OP2. The conductive pattern CP can contact its corresponding dummy contact 181B through the third opening OP3.

[0073] Each conductive gate contact 181A may contact and be surrounded by its corresponding edge portion CE. Each dummy contact 181B may contact and be surrounded by its corresponding edge portion CE. The base CB of the conductive pattern CP may be thicker than the edge portion CE of the conductive pattern CP. Therefore, the width of each of the second opening OP2 and the third opening OP3 in the Z-axis direction may be narrower than the width of the first opening OP1 in the Z-axis direction.

[0074] The filler insulating layer 131 may be covered by the upper insulating layer UI. The upper insulating layer UI may include a first upper insulating layer 191 above the filler insulating layer 131 and a second upper insulating layer 195 above the first upper insulating layer 191.

[0075] The cover pattern 157 of the unit plug CPL can be connected to the bit line BL via the bit line contact portion 193A. The bit line BL can be disposed at the height at which the second upper insulating layer 195 is disposed. That is, the bit line BL can be disposed on the first upper insulating layer 191. The bit line contact portion 193A can penetrate the first upper insulating layer 191 and connect the cover pattern 157 and the bit line BL to each other.

[0076] Multiple conductive gate contacts 181A can be connected to multiple upper lines UL via multiple upper contacts 193B. A first upper insulating layer 191 can be filled between the multiple upper contacts 193B. A second upper insulating layer 195 can be filled between the multiple upper lines UL. The multiple upper lines UL, multiple upper contacts 193B, multiple conductive gate contacts 181A, and multiple lower contacts 103A can be used as interconnects for connecting multiple conductive patterns CP to the column decoder RD shown in FIG1.

[0077] The plurality of lower dummy contacts 103B and the plurality of dummy contacts 181B can be retained as floating patterns that are not electrically connected to the peripheral circuit 30 shown in FIG1. ​​For this purpose, the top surface of the plurality of dummy contacts 181B can be covered by the upper insulating layer UI.

[0078] According to embodiments of this disclosure, the contact region CTR and the extension region ER are formed with similar structures to each other. Therefore, the manufacturing process for providing the extension region ER can be performed using the manufacturing process for providing the contact region CTR. Thus, the manufacturing process of semiconductor memory devices can be simplified according to embodiments of this disclosure.

[0079] Figure 4 is an enlarged cross-sectional view of region AR1 shown in Figure 3B.

[0080] Referring to FIG4, the plurality of conductive gate contacts 181A may include a first conductive gate contact A1 surrounded by a relatively large number of conductive patterns CP and a second conductive gate contact A2 surrounded by a relatively small number of conductive patterns CP. The first conductive gate contact A1 and the second conductive gate contact A2 may be spaced apart from each other.

[0081] The plurality of conductive patterns CP may include a first conductive pattern CP1 disposed at a relatively lower portion and a second conductive pattern CP2 disposed at a relatively higher portion. That is, the second conductive pattern CP2 may be disposed above the first conductive pattern CP1. One of the plurality of interlayer insulating layers IL may be disposed between the first conductive pattern CP1 and the second conductive pattern CP2.

[0082] The first conductive pattern CP1 and the second conductive pattern CP2 may extend parallel to each other to surround the first conductive gate contact portion A1. A first contact portion insulating pattern 141A may be disposed between the first conductive gate contact portion A1 and the first conductive pattern CP1. The first conductive pattern CP1 may be insulated from the first conductive gate contact portion A1 by the first contact portion insulating pattern 141A. The first conductive pattern CP1 may extend to surround the second conductive gate contact portion A2.

[0083] The second barrier insulating layer 161 may surround the sidewall of the first contact insulating pattern 141A. The second barrier insulating layer 161 may extend along the surface of each of the first conductive pattern CP1 and the second conductive pattern CP2 facing the first filling insulating layer 131A, and along the surface of each of the first conductive pattern CP1 and the second conductive pattern CP2 facing the interlayer insulating layer IL. The second opening OP2 of the second barrier insulating layer 161 may be aligned at each of the heights at which the first conductive pattern CP1 and the second conductive pattern CP2 are located. The edge portion CE of each of the first conductive pattern CP1 and the second conductive pattern CP2 may contact the corresponding conductive gate contact portion 181A through the second opening OP2.

[0084] For example, the second conductive pattern CP2 may include a first edge portion E1 that contacts the first conductive gate contact portion A1 and a first base portion B1 extending from the first edge portion E1. The first conductive pattern CP1 may include a second edge portion E2 that contacts the second conductive gate contact portion A2 and a second base portion B2 extending from the second edge portion E2. As described with reference to FIGS. 3A to 3C, the thickness D2 of each of the first edge portion E1 and the second edge portion E2 may be less than the thickness D1 of each of the first base portion B1 and the second base portion B2.

[0085] The first edge portion E1 of the second conductive pattern CP2 may overlap with the first contact insulating pattern 141A. The first edge portion E1 may surround the first conductive gate contact portion A1. The first filling insulating layer 131A may be inserted between the first edge portion E1 of the second conductive pattern CP2 and the second conductive gate contact portion A2.

[0086] The first contact insulating pattern 141A that overlaps with the first edge portion E1 among the plurality of first contact insulating patterns 141A may be surrounded by the second base portion B2 of the first conductive pattern CP1. The second conductive gate contact portion A2 may be spaced apart from the first contact insulating pattern 141A that overlaps with the first edge portion E1. The second conductive gate contact portion A2 may have a sidewall that contacts the second edge portion E2 of the first conductive pattern CP1. The second edge portion E2 may extend from the second base portion B2 and surround the second conductive gate contact portion A2.

[0087] FIG5 is a cross-sectional view illustrating a semiconductor memory device according to one embodiment of the present disclosure. More specifically, FIG5 is a cross-sectional view illustrating a variant embodiment of a stepped stacked structure. FIG5 shows the contact region CTR' of a stepped stacked structure ST' according to one embodiment of the present disclosure. The contact region CTR' shown in FIG5 can extend from the cell region CAR shown in FIG3A. Although not shown in the figure, the extension region of the stepped stacked structure ST' extending from the contact region CTR' shown in FIG5 can be formed as a structure similar to that of the contact region CTR' shown in FIG5. FIG6 is an enlarged cross-sectional view of the region AR2 shown in FIG5. In the following, for the sake of simplicity, descriptions overlapping with those shown in FIG3A to 3C and FIG4 will be omitted.

[0088] Referring to Figures 5 and 6, a second lower insulating layer 104 may be disposed on a first lower insulating layer 101 through which a plurality of lower contacts 103A penetrate. The second lower insulating layer 104 may be penetrated by a plurality of conductive gate contacts 181A' respectively connected to the plurality of lower contacts 103A. The plurality of conductive gate contacts 181A' may penetrate a stepped stacked structure ST'. A first protective layer 107 and a second protective layer 109 may be embedded in each conductive gate contact 181A'.

[0089] The multiple conductive patterns CP' and multiple interlayer insulating layers IL of the stepped stacked structure ST' can be alternately arranged in the Z-axis direction. Each conductive pattern CP' may include an edge portion CE' and a base portion CB extending from the edge portion CE'. The multiple edge portions CE' of the multiple conductive patterns CP' can form a stepped structure in the contact area CTR'. The base portion CB can contact the sidewall insulating layer 171 through the first opening OP1 of the second barrier insulating layer 161 as shown in FIG. 3A, and the edge portion CE' can contact the corresponding conductive gate contact portion 181A' through the second opening OP2' of the second barrier insulating layer 161 as shown in FIG. 5 and 6. The thickness D2' of the edge portion CE' can be greater than the thickness D1 of the base portion CB. Furthermore, the width of the second opening OP2' in the Z-axis direction shown in FIG. 5 and 6 can be further greater than the width of the first opening in the Z-axis direction shown in FIG. 3A.

[0090] Multiple edges CE' of multiple conductive patterns CP' may be spaced apart from the sidewalls of multiple interlayer insulating layers IL. The first filling insulating layer 131A of the filling insulating layer 131 may extend between the interlayer insulating layers IL and the edges CE' that are adjacent to each other at the same height.

[0091] Each conductive gate contact 181A' may extend in the Z-axis direction to penetrate the stepped stacked structure ST', the first filling insulating layer 131A, and the second filling insulating layer 131B. The edge CE' of the conductive pattern CP' may surround its corresponding conductive gate contact 181A'.

[0092] The contact insulating pattern 141 may overlap with the edge CE' of the conductive pattern CP' and be surrounded by the base CB of another conductive pattern CP' disposed below the edge CE' of the conductive pattern CP'. The conductive gate contact 181A' may be insulated from the base CB by the contact insulating pattern 141.

[0093] Hereinafter, a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure will be described.

[0094] Figures 7A and 7B are cross-sectional views illustrating a process of isolating a lower stacked structure into multiple patterns according to one embodiment of the present disclosure.

[0095] Referring to Figures 7A and 7B, the lower stacked structure may include a first protective layer 107, a horizontal layer 201 located on the first protective layer 107, and a second protective layer 109 located on the horizontal layer 201.

[0096] Prior to forming the lower stacked structure, a process for forming a first lower insulating layer 101 through which a plurality of lower contacts 103A and a plurality of lower dummy contacts 103B penetrate, and a process for stacking a first semiconductor layer on the first lower insulating layer 101, may be performed. Although not shown in the figures, the first lower insulating layer 101 may be formed on a peripheral circuit structure including the source driver SD, page buffer PB, and column decoder RD shown in FIG1. ​​The first semiconductor layer is a layer for a plurality of first semiconductor patterns 105A, 105B, and 105C, and may include at least one of n-type impurities and p-type impurities. In one embodiment, the first semiconductor layer may include an n-type impurity.

[0097] The first protective layer 107, the horizontal layer 201, and the second protective layer 109 of the lower stacked structure can be stacked on the first semiconductor layer. The horizontal layer 201 can be selected from materials that have etch selectivity relative to the first protective layer 107 and the second protective layer 109. The first protective layer 107 and the second protective layer 109 can include the same material. In one embodiment, the first protective layer 107 and the second protective layer 109 can include silicon oxide, and the horizontal layer 201 can include undoped silicon.

[0098] After forming the lower stacked structure, a second semiconductor layer may be formed on the second protective layer 109. The second semiconductor layer is a layer for a plurality of second semiconductor patterns 111A, 111B, and 111C, and may be an undoped semiconductor layer or a doped semiconductor layer including at least one of n-type impurities and p-type impurities. In one embodiment, the second semiconductor layer may include an n-type impurity.

[0099] Subsequently, the second semiconductor layer, the lower stacked structure, and the first semiconductor layer can be etched using an etching process employing photolithography. Therefore, the second semiconductor layer can be isolated into multiple second semiconductor patterns 111A, 111B, and 111C. Furthermore, the lower stacked structure can be isolated into a preliminary horizontal pattern 200A, multiple preliminary contact structures 200B, and multiple preliminary dummy structures 200C. Additionally, the first semiconductor layer can be isolated into multiple first semiconductor patterns 105A, 105B, and 105C. The multiple first semiconductor patterns 105A, 105B, and 105C can overlap with the preliminary horizontal pattern 200A, the multiple preliminary contact structures 200B, and the multiple preliminary dummy structures 200C, respectively. The preliminary horizontal pattern 200A can overlap with the first lower insulating layer 101. The multiple preliminary contact structures 200B can overlap with multiple lower contact portions 103A, respectively. The multiple preliminary dummy structures 200C can overlap with multiple lower dummy contact portions 103B, respectively. Multiple second semiconductor patterns 111A, 111B and 111C can overlap with the initial horizontal pattern 200A, multiple initial contact structures 200B and multiple initial dummy structures 200C, respectively.

[0100] Figures 8A, 8B, 9A, 9B, 10A and 10B are cross-sectional views illustrating a method for forming a preliminary stepped stacked structure according to one embodiment of the present disclosure.

[0101] Referring to Figures 8A and 8B, the second lower insulating layer 104 can fill the space between a plurality of first semiconductor patterns 105A, 105B and 105C. The second lower insulating layer 104 can fill the space between the preliminary horizontal pattern 200A, a plurality of preliminary contact structures 200B and a plurality of preliminary dummy structures 200C, and between a plurality of second semiconductor patterns 111A, 111B and 111C.

[0102] Subsequently, a plurality of first material layers 221 and a plurality of second material layers 223 may be alternately stacked along the Z-axis direction on the second lower insulating layer 104 and a plurality of second semiconductor patterns 111A, 111B and 111C.

[0103] Subsequently, a plurality of first preliminary vias H1A, H1B, and H1C can be formed, penetrating the plurality of first material layers 221 and the plurality of second material layers 223 and extending into the interior of the plurality of first semiconductor patterns 105A, 105B, and 105C. The plurality of first preliminary vias H1A, H1B, and H1C may include a first preliminary channel via H1A, a plurality of first preliminary contact vias H1B, and a plurality of first preliminary dummy vias H1C. The first preliminary channel via H1A may penetrate the second semiconductor pattern 111A and the preliminary horizontal pattern 200A and extend into the interior of the first semiconductor pattern 105A. Each first preliminary contact via H1B may penetrate its corresponding second semiconductor pattern 111B and its corresponding preliminary contact structure 200B and extend into the interior of its corresponding first semiconductor pattern 105B. Each first preliminary dummy via H1C may penetrate its corresponding second semiconductor pattern 111C and its corresponding preliminary dummy structure 200C and extend into the interior of its corresponding first semiconductor pattern 105C. Each of the widths W2 of the first initial contact hole H1B and W3 of the first initial dummy hole H1C can be made wider than the width W1 of the first initial channel hole H1A. The widths W2 of the first initial contact hole H1B and W3 of the first initial dummy hole H1C can be the same or different from each other.

[0104] When performing an etching process for forming a plurality of first preliminary holes H1A, H1B and H1C, a plurality of first semiconductor patterns 105A, 105B and 105C can be used as an etch stop layer.

[0105] Subsequently, multiple sacrificial posts 225A, 225B, and 225C can be used to fill the first preliminary holes H1A, H1B, and H1C, respectively. The multiple sacrificial posts 225A, 225B, and 225C may include a first sacrificial post 225A, multiple second sacrificial posts 225B, and multiple third sacrificial posts 225C. The first sacrificial post 225A can fill the first preliminary channel hole H1A. Each second sacrificial post 225B can fill its corresponding first preliminary contact hole H1B. Each third sacrificial post 225C can fill its corresponding first preliminary dummy hole H1C.

[0106] Referring to Figures 9A and 9B, a plurality of third material layers 227 and a plurality of fourth material layers 229 can be alternately stacked along the Z-axis direction on a stacked structure of a plurality of first material layers 221 and a plurality of second material layers 223 and a plurality of sacrificial pillars 225A, 225B and 225C.

[0107] The lowest third material layer 227 in the stacked structure of multiple third material layers 227 and multiple fourth material layers 229 may contact the highest first material layer 221 in the stacked structure of multiple first material layers 221 and multiple second material layers 223. The multiple third material layers 227 may be made of the same material as the multiple second material layers 223, and the multiple fourth material layers 229 may be made of the same material as the multiple first material layers 221.

[0108] The plurality of first material layers 221 and the plurality of fourth material layers 229 may be composed of an insulating material for interlayer insulation. The plurality of second material layers 223 and the plurality of third material layers 227 may be composed of a material having etch selectivity relative to the plurality of first material layers 221 and the plurality of fourth material layers 229. In one embodiment, the plurality of second material layers 223 and the plurality of third material layers 227 may include silicon nitride. The plurality of sacrificial pillars 225A, 225B and 225C may be composed of a material having etch selectivity relative to the plurality of first material layers 221, the plurality of second material layers 223, the plurality of third material layers 227 and the plurality of fourth material layers 229. In one embodiment, the plurality of sacrificial pillars 225A, 225B and 225C may include a metal such as tungsten.

[0109] Referring to Figures 10A and 10B, a plurality of first material layers 221, a plurality of second material layers 223, a plurality of third material layers 227, and a plurality of fourth material layers 229 can be etched to define a preliminary stepped stack structure 220. The preliminary stepped stack structure 220 may be composed of a plurality of interlayer insulating layers IL and a plurality of sacrificial layers SC alternately arranged in the Z-axis direction. The plurality of interlayer insulating layers IL may be composed of a plurality of remaining first material layers 221 and a plurality of remaining fourth material layers 229. The plurality of sacrificial layers SC may be composed of a plurality of remaining second material layers 223 and a plurality of remaining third material layers 227. Each of the plurality of interlayer insulating layers IL and the plurality of sacrificial layers SC may have a plate-like shape extending in the XY plane.

[0110] The preliminary stepped stack structure 220 may include a cell region CAR, a contact region CTR extending from the cell region CAR, and an extension region ER extending from the contact region CTR. The preliminary stepped stack structure 220 may form a stepped structure in the contact region CTR and the extension region ER. For this purpose, a plurality of sacrificial layers SC may be patterned to have a longer length in the contact region CTR and the extension region ER as they get closer to the second lower insulating layer 104. In one embodiment, the plurality of sacrificial layers SC may have a longer length in the X-axis direction in the contact region CTR and the extension region ER as they get closer to the second lower insulating layer 104.

[0111] Each sacrificial layer SC may include a base SB and an edge SE extending from the base SB. The base SB may be disposed between interlayer insulating layers IL that are adjacent to each other along the Z-axis direction, and the top surface of the edge may be open.

[0112] Multiple bases SB of multiple sacrificial layers SC can overlap with the initial horizontal pattern 200A in the cell region CAR.

[0113] Multiple edge portions SE of the multiple sacrificial layers SC can form a stepped structure in the contact region CTR and the extension region ER. For example, multiple interlayer insulating layers IL may include a lower interlayer insulating layer LIL, an intermediate interlayer insulating layer MIL, and an upper interlayer insulating layer UIL stacked in the Z-axis direction. Multiple sacrificial layers SC may include a lower sacrificial layer LSC located between the lower interlayer insulating layer LIL and the intermediate interlayer insulating layer MIL, and an upper sacrificial layer USC located between the intermediate interlayer insulating layer MIL and the upper interlayer insulating layer UIL. The lower sacrificial layer LSC may include a lower base portion LB located between the lower interlayer insulating layer LIL and the intermediate interlayer insulating layer MIL, and a lower edge portion LE protruding further to the side from the lower base portion LB relative to the intermediate interlayer insulating layer MIL. The upper sacrificial layer USC may include an upper base portion UB located between the intermediate interlayer insulating layer MIL and the upper interlayer insulating layer UIL, and an upper edge portion UE protruding further to the side from the upper base portion UB relative to the upper interlayer insulating layer UIL.

[0114] The first sacrificial pillar 225A may be embedded in the unit region CAR of the initial stepped stacked structure 220. Some of the plurality of edge portions SE may overlap with some of the plurality of second sacrificial pillars 225B and the plurality of third sacrificial pillars 225C, and some of the plurality of second sacrificial pillars 225B and the plurality of third sacrificial pillars 225C may further protrude in the Z-axis direction relative to some of the plurality of edge portions SE.

[0115] Subsequently, a portion of each of the plurality of edge portions SE can be etched such that the plurality of edge portions SE has a thickness D22 that is thinner than the thickness D11 of the plurality of base portions SB. Therefore, each of the upper edge portion UE and the lower edge portion LE can have a thinner thickness than each of the upper base portion UB and the lower base portion LB.

[0116] Figures 11A, 11B, 12A, 12B, 13A and 13B are cross-sectional views illustrating a method for forming contact holes and dummy holes according to one embodiment of the present disclosure.

[0117] Referring to Figures 11A and 11B, a filler insulating layer 131 may be formed over the initial stepped stack structure 220. The filler insulating layer 131 may include a first filler insulating layer 131A covering the contact region CTR and the extension region ER of the initial stepped stack structure 220, and a second filler insulating layer 131B located on the first filler insulating layer 131A. The surface of the first filler insulating layer 131A may be substantially planarized. The second filler insulating layer 131B may extend to cover the cell region CAR of the initial stepped stack structure 220.

[0118] Referring to Figures 12A and 12B, a filling insulating layer 131 and a preliminary stepped stack structure 220 overlapping with a plurality of second sacrificial pillars 225B and a plurality of third sacrificial pillars 225C can be etched. Therefore, a plurality of second preliminary contact holes H2B and a plurality of second preliminary dummy holes H2C exposing the plurality of second sacrificial pillars 225B and the plurality of third sacrificial pillars 225C can be formed.

[0119] Each second preliminary contact hole H2B can penetrate the contact area CTR of the filling insulating layer 131 and the preliminary stepped stack structure 200 that overlaps with its corresponding second sacrificial post 225B. Each second preliminary dummy hole H2C can penetrate the extension area ER of the filling insulating layer 131 and the preliminary stepped stack structure 220 that overlaps with its corresponding third sacrificial post 225C. The width of the second preliminary contact hole H2B can be equal to or different from the width of the second preliminary dummy hole H2C. The width of each of the second preliminary contact hole H2B and the second preliminary dummy hole H2C can be configured to be greater than the width of the first preliminary channel hole H1A.

[0120] Referring to Figures 13A and 13B, the plurality of second sacrificial posts 225B and the plurality of third sacrificial posts 225C shown in Figures 12A and 12B can be removed through the plurality of second preliminary contact holes H2B and the plurality of second preliminary dummy holes H2C. Therefore, the plurality of first preliminary contact holes H1B and the plurality of first preliminary dummy holes H1C can be opened. The plurality of first preliminary contact holes H1B can be connected to the plurality of second preliminary contact holes H2B respectively, thus defining the plurality of contact holes HB. The plurality of first preliminary dummy holes H1C can be connected to the plurality of second preliminary dummy holes H2C, thus defining the plurality of dummy holes HC.

[0121] Multiple edges SE of the multiple sacrificial layers SC can be penetrated by multiple contact holes HB and multiple dummy holes HC, respectively. Each contact hole HB can penetrate the contact area CTR of the initial stepped stack structure 220, the corresponding second semiconductor pattern 111B, and the corresponding initial contact structure 200B, and extend into the interior of the corresponding first semiconductor pattern 105B. Each dummy hole HC can penetrate the extension area ER of the initial stepped stack structure 220, the corresponding second semiconductor pattern 111C, and the corresponding initial dummy structure 200C, and extend into the interior of the corresponding first semiconductor pattern 105C. The width of the contact hole HB can be equal to or different from the width WC of the dummy hole HC.

[0122] In the following description, the structure of a contact hole penetrating the upper sacrificial layer USC, the intermediate interlayer insulating layer MIL, the lower sacrificial layer LSC, and the lower interlayer insulating layer LIL, defined with reference hole R in a plurality of contact holes HB, will be described in more detail. The reference hole R may be spaced apart from the upper interlayer insulating layer UIL. The reference hole R may penetrate the upper edge UE of the upper sacrificial layer USC and the lower base LB of the lower sacrificial layer LSC.

[0123] Figures 14A, 14B, 15A, 15B, 16A, 16B, 17A and 17B are cross-sectional views illustrating a method for forming a sacrificial pad and a contact insulation pattern according to one embodiment of the present disclosure.

[0124] Referring to Figures 14A and 14B, multiple edge portions SE of the multiple sacrificial layers SC shown in Figures 13A and 13B can be removed via contact holes HB and dummy holes HC. Therefore, multiple first recessed regions 231 can be defined in the region where the multiple edge portions SE have been removed. When removing the multiple edge portions SE, multiple base portions SB can be etched via contact holes HB and dummy holes HC. Therefore, multiple second recessed regions 233 can be defined in the region where the multiple base portions SB have been removed. Due to the thickness difference between the edge portions SE and the base portions SB, the first recessed regions 231 can be defined to be narrower in the Z-axis direction than the second recessed regions 233.

[0125] Referring to Figures 15A and 15B, a sacrificial pad layer 241 may be formed along the surfaces of the first recessed region 231, the second recessed region 233, the contact hole HB, and the dummy hole HC. The sacrificial pad layer 241 may extend along the surface of the filling insulating layer 131.

[0126] The sacrificial pad layer 241 may be formed of the same material as the plurality of sacrificial layers SC. The sacrificial pad layer 241 may fill a plurality of first recessed regions 231 having a relatively narrow width. The sacrificial pad layer 241 may extend along the surface of a plurality of second recessed regions 233. The second recessed regions 233 having a relatively wide width are not completely filled by the sacrificial pad layer 241, but the central region of the second recessed regions 233 may be left open.

[0127] Referring to Figures 16A and 16B, the sacrificial pad layer 241 shown in Figures 15A and 15B can be etched to isolate it into a plurality of sacrificial pads 241P. Each sacrificial pad 241P can be retained in its corresponding first recessed region 231. A plurality of second recessed regions 233 can be opened by the etching process of the sacrificial pad layer 241.

[0128] Referring to Figures 17A and 17B, a plurality of second recessed regions 233 can be filled by a plurality of contact insulating patterns 141 through contact holes HB and dummy holes HC. The plurality of contact insulating patterns 141 may include a material having etch selectivity relative to the plurality of sacrificial layers SC and the plurality of sacrificial pads 241P.

[0129] As described above, the edge SE of the sacrificial layer SC shown in Figures 13A and 13B can be replaced by the sacrificial pad 241P shown in Figures 17A and 17B, and a portion of the base SB of the sacrificial layer SC shown in Figures 13A and 13B can be replaced by the contact insulating pattern 141. The contact insulating pattern 141 can be automatically aligned at the target location using the thickness difference between the base SB and the edge SE of the sacrificial layer SC shown in Figures 13A and 13B. More specifically, the contact insulating pattern 141 can be automatically aligned to overlap with the sacrificial pad 241P. Furthermore, the contact insulating pattern 141 can be automatically aligned between the interlayer insulating layers IL. In addition, the contact insulating pattern 141 can be automatically aligned on the sidewalls of the base SB of the sacrificial layer SC facing each of the contact holes HB and dummy holes HC.

[0130] FIG18 is a cross-sectional view showing a method for forming a channel hole according to one embodiment of the present disclosure.

[0131] Referring to FIG18, the filler insulating layer 131 and the cell region CAR of the preliminary stepped stack structure 220 overlapping with the first sacrificial pillar 225A shown in FIG17A can be etched. Therefore, a second preliminary channel hole H2A exposing the first sacrificial pillar 225A shown in FIG17A can be formed.

[0132] Subsequently, the first sacrificial post 225A shown in FIG17A can be removed through the second preliminary channel hole H2A. Therefore, the first preliminary channel hole H1A can be opened. The second preliminary channel hole H2A can be connected to the first preliminary channel hole H1A, thus defining the channel hole HA. The channel hole HA can penetrate not only the multiple bases SB of the multiple sacrificial layers SC and the multiple interlayer insulating layers IL, but also the corresponding second semiconductor pattern 111A. In addition, the channel hole HA can penetrate the preliminary horizontal pattern 200A and extend into the interior of the corresponding first semiconductor pattern 105A. The width WA of the channel hole HA can be narrower than the width WB of the contact hole HB and the width WC of the dummy hole shown in FIG17B.

[0133] Figures 19A, 19B, 20A, 20B, 21, 22A and 22B are cross-sectional views illustrating a method for forming a preliminary memory pattern, a channel structure, a first support structure and a second support structure according to one embodiment of the present disclosure.

[0134] Referring to Figures 19A and 19B, the memory layer 151 can be formed along the surface of each of the channel hole HA, the plurality of contact holes HB, and the plurality of dummy holes HC. The first barrier insulating layer, the data storage layer, and the tunneling insulating layer can be stacked sequentially to form the memory layer 151. The sidewalls of the contact insulating pattern 141 and the sidewalls of the sacrificial pad 241P can be covered by the memory layer 151.

[0135] Subsequently, a channel layer 153 may be formed along the surface of the memory layer 151. The central region of each of the channel holes HA, the plurality of contact holes HB, and the plurality of dummy holes HC is not completely filled by the channel layer 153, but a portion of the central region may be left open.

[0136] Subsequently, a process for forming an insulating material on the surface of the channel layer 153 and a process for planarizing the insulating material to expose the channel layer 153 can be performed. Therefore, the insulating material can be isolated into a preliminary core insulating pattern 155PA in the channel hole HA, a plurality of first dummy core insulating patterns 155B in the plurality of contact holes HB, and a plurality of second dummy core insulating patterns 155C in the plurality of dummy holes HC. The central region of the channel hole HA can be filled by the preliminary core insulating pattern 155. Because the contact hole HB is formed to be wider than the channel hole HA, the central region of the contact hole HB is not completely filled by the first dummy core insulating pattern 155B, but a portion of the central region can be left open. Because the dummy hole HC is formed to be wider than the channel hole HA, the central region of the dummy hole HC is not completely filled by the second dummy core insulating pattern 155C, but a portion of the central region can be left open.

[0137] Referring to Figures 20A and 20B, a first upper protective layer 261 may be formed on the channel layer 153. The first upper protective layer 261 can be formed using a deposition process with low step coverage, thereby defining a void 263 in the central region of each of the contact hole HB and the dummy hole HC. In one embodiment, the first upper protective layer 261 may be formed by plasma-enhanced chemical vapor deposition (PECVD). For example, the first upper protective layer 261 may be formed by plasma-enhanced tetraethyl orthosilicate (PETEOS). Embodiments disclosed herein are not limited thereto.

[0138] Referring to FIG21, the portion of the first upper protective layer 261 that overlaps with the cell region CAR of the preliminary stepped stack structure 220 can be removed. For this purpose, a masking pattern (not shown) that opens the cell region CAR of the preliminary stepped stack structure 220 and blocks the contact region CTR and extension region of the preliminary stepped stack structure 220 can be used as an etching barrier. Therefore, a portion of the preliminary core insulating pattern 155PA shown in FIG20A can be exposed. Subsequently, the exposed portion of the preliminary core insulating pattern can be removed, thereby defining the core insulating pattern 155A and the core trench 265. The masking pattern can be removed after the core insulating pattern 155A is formed.

[0139] The first dummy core insulation pattern 155B penetrating the contact area CTR of the preliminary stepped stacked structure 220 and the second dummy core insulation pattern 155C penetrating the extension area ER of the preliminary stepped stacked structure 220 shown in FIG. 20B can be protected by the first upper protective layer.

[0140] Referring to Figures 22A and 22B, a capping pattern 157 can be formed to fill the core trench 265 shown in Figure 21. The process of forming the capping pattern 157 may include a process of filling the core trench 265 shown in Figure 21 with a doped semiconductor material, and a process of planarizing the doped semiconductor material to expose the filling insulating layer 131. By planarizing to remove the first upper protective layer 261 shown in Figure 21, the central region of each of the contact hole HB and the dummy hole HC can be opened.

[0141] Through planarization, the channel layer 153 shown in FIG21 can be isolated into a unit channel layer 153A, a plurality of first dummy channel layers 153B, and a plurality of second dummy channel layers 153C. Through planarization, the memory layer 151 shown in FIG21 can be isolated into a memory pattern 151A, a plurality of first dummy memory patterns 151B, and a plurality of second dummy memory patterns 151C.

[0142] Through the above process, the channel hole HA can be filled with the memory pattern 151A and the channel structure CH. The channel structure CH may include a cell channel layer 153A, a core insulating pattern 155A and a capping pattern 157. In addition, a first support structure 150[1] can be formed in the contact hole HB. The first support structure 150[1] may include a first dummy memory pattern 151B, a first dummy channel layer 153B and a first dummy core insulating pattern 155B. In addition, a second support structure 150[2] can be formed in the dummy hole HC. The second support structure 150[2] may include a second dummy memory pattern 151C, a second dummy channel layer 153C and a second dummy core insulating pattern 155C.

[0143] The first support structure 150[1] can penetrate the contact area CTR of the preliminary stepped stacked structure 220 and extend into the interior of the corresponding preliminary contact structure 200B. The second support structure 150[2] can penetrate the extension area ER of the preliminary stepped stacked structure 220 and extend into the interior of the corresponding preliminary dummy structure 200C. Each of the first support structure 150[1] and the second support structure 150[2] can be surrounded by a contact insulating pattern 141 and a sacrificial pad 241P. By forming the first support structure 150[1] and the second support structure 150[2] using a process that forms a memory pattern 151A and a channel structure CH, the manufacturing process of the semiconductor memory device can be simplified.

[0144] Figures 23A, 23B, 24A, 24B, 25A and 25B are cross-sectional views illustrating a method for forming a barrier insulating layer and a conductive pattern according to one embodiment of the present disclosure.

[0145] Referring to Figures 23A and 23B, a second upper protective layer 271 may be formed over the filling insulating layer 131. The second upper protective layer 271 may be formed by a deposition process with low step coverage, thereby defining a void 273 in the central region of each of the contact hole HB and the dummy hole HC. The second upper protective layer 271 may cover the channel structure CH, the memory pattern 151A, the first support structure 150[1] and the second support structure 150[2].

[0146] Referring to Figures 24A and 24B, multiple interlayer insulating layers IL and multiple sacrificial layers SC can be etched in the cell region CAR of the preliminary stepped stacked structure 220 shown in Figure 23A to form a first preliminary slit SI1. Subsequently, the multiple sacrificial layers SC and multiple sacrificial pads 241P shown in Figures 23A and 23B can be selectively removed through the first preliminary slit SI1. Thus, multiple gate regions 275 can be opened. Each gate region 275 can be defined between interlayer insulating layers IL that are adjacent to each other along the Z-axis direction and extends between fill insulating layers 131 and interlayer insulating layers IL that are adjacent to each other along the Z-axis direction. The contact insulating pattern 141, the first support structure 150[1] and the second support structure 150[2] can be exposed through the multiple gate regions 275.

[0147] The plurality of gate regions 275 may include an upper gate region 275U and a lower gate region 275L. The upper gate region 275U may be defined in the region where the upper sacrificial layer USC and the sacrificial pad 241P of the same height as shown in FIG. 23A have been removed, and the lower gate region 275L may be defined in the region where the lower sacrificial layer LSC and the sacrificial pad 241P of the same height as shown in FIG. 23A have been removed.

[0148] Referring to Figures 25A and 25B, a second barrier insulating layer 161 may be formed along the surface of the gate region 275 shown in Figures 24A and 24B. The second barrier insulating layer 161 may have a first opening OP1 facing the first preliminary slit SI1. The second barrier insulating layer 161 may extend along the sidewall of each of the first support structure 150[1] and the second support structure 150[2]. The second barrier insulating layer 161 may extend along the sidewall of the contact insulating pattern 141.

[0149] Subsequently, the central region of the gate region 275, opened by the second barrier insulating layer 161, can be filled with a first conductive material. The first conductive material can be introduced into the gate region 275 shown in Figures 24A and 24B through the first opening OP1. Subsequently, the first conductive material in the first preliminary slit SI1 can be removed, thereby forming a plurality of conductive patterns CP disposed in the plurality of gate regions 275 and isolated from each other in the Z-axis direction. The plurality of conductive patterns CP may include the upper conductive pattern UCP in the upper gate region 275U shown in Figure 24A and the lower conductive pattern LCP in the lower gate region 275L shown in Figure 24A.

[0150] Each conductive pattern CP may include a base CB and an edge portion CE that is thinner than the base CB. The base CB may surround the channel structure CH and the memory pattern 151A. The edge portion CE may surround the corresponding first support structure 150[1] and second support structure 150[2].

[0151] Through the first support structure 150[1] and the second support structure 150[2], the gap between the interlayer insulation layers IL that are adjacent to each other in the Z-axis direction can be stably maintained.

[0152] Figures 26, 27, 28A, 28B, 29A, 29B, 30A, 30B, 31A, 31B, 32A and 32B are cross-sectional views illustrating a method for forming a common source pattern, a conductive gate contact, and a dummy contact according to one embodiment of the present disclosure.

[0153] Referring to FIG26, a second preliminary slit SI2 can be formed connected to the first preliminary slit SI1. The second preliminary slit SI2 can extend through the second semiconductor pattern 111A. Slit SI can be defined by the first preliminary slit SI1 and the second preliminary slit SI2 connected to each other.

[0154] Referring to FIG27, a sidewall insulating layer 171 can be formed on the sidewall of the slit SI. When etching the sidewall insulating layer 171 to expose the bottom surface of the slit SI, a portion of the second protective layer 109 of the preliminary horizontal pattern 200A shown in FIG26 can be removed. Therefore, the horizontal layer 201 of the preliminary horizontal pattern 200A shown in FIG26 can be exposed.

[0155] Subsequently, the horizontal layer 201 of the preliminary horizontal pattern 200A shown in FIG. 26 can be selectively removed through the slit SI. Therefore, the first protective layer 107 and the second protective layer 109 of the preliminary horizontal pattern 200A shown in FIG. 26 can be exposed. Subsequently, a portion of the memory pattern 151A can be removed via the area where the preliminary horizontal pattern 200A has been removed, thereby exposing the cell channel layer 153A.

[0156] When removing a portion of the memory pattern 151A, the first protective layer 107 and the second protective layer 109 of the preliminary horizontal pattern 200A shown in FIG26 can be removed. Therefore, the first semiconductor pattern 105A and the second semiconductor pattern 111A can be exposed.

[0157] Through the above process, the horizontal space 277 between the first semiconductor pattern 105A and the second semiconductor pattern 111A can be opened. In addition, the memory pattern 151A can be isolated into the first memory pattern 151P1 and the second memory pattern 151P2 through the horizontal space 277.

[0158] Referring to Figures 28A and 28B, a doped semiconductor layer 173 may be formed to fill the horizontal space 277 and slit SI shown in Figure 27. The doped semiconductor layer 173 may include n-type impurities. The doped semiconductor layer 173 may extend to overlap with the second upper protective layer 271 and to contact the cell channel layer 153A.

[0159] Referring to Figures 29A and 29B, the portion of the doped semiconductor layer 173 shown in Figures 28A and 28B above the first support structure 150[1] and the second support structure 150[2], as well as a portion of the second upper protective layer 271, can be removed. For this purpose, the doped semiconductor layer 173 can be masked in the cell region CAR, and a masking pattern (not shown) of the doped semiconductor layer 173 in the exposed contact region CTR and the extended region ER can be used as an etching barrier. The doped semiconductor layer 173 and the second upper protective layer 271 can be etched to expose the first support structure 150[1] and the second support structure 150[2] shown in Figures 28A and 28B. The masking pattern can be removed after etching the doped semiconductor layer 173 and the second upper protective layer 271.

[0160] Subsequently, the first support structure 150[1] and the second support structure 150[2] shown in FIG28A and FIG28B can be removed. Therefore, the contact hole HB and the dummy hole HC can be opened. The second barrier insulation layer 161 and the contact insulation pattern 141 can be exposed through the contact hole HB and the dummy hole HC.

[0161] Figure 30A is an enlarged cross-sectional view of region AR3 shown in Figure 29A.

[0162] Referring to FIG30A, when the first support structure 105[1] shown in FIG28A is removed, the second barrier insulation layer 161 and the contact insulation pattern 141 can be exposed through the contact hole HB.

[0163] Although not shown in the enlarged cross-sectional view, when the second support structure 150[2] shown in FIG28B is removed, the second barrier insulation layer 161 and the contact insulation pattern 141 can be exposed through the dummy hole HC shown in FIG29B.

[0164] FIG30B illustrates one embodiment of a subsequent process that continues after the process described with reference to FIG29A, FIG29B and FIG30A.

[0165] Referring to FIG30B, the exposed portion of the second barrier insulating layer 161 can be removed through the contact hole HB. Therefore, the second opening OP2 can be defined. The edge portion CE of the conductive pattern CP can be exposed through the second opening OP2.

[0166] Although not shown in the enlarged cross-sectional view, the exposed portion of the second barrier insulating layer 161 can be removed through the dummy hole HC shown in FIG. 29B. Therefore, the third opening OP3 can be defined as shown in FIG. 31B, and the edge portion CE of the conductive pattern CP corresponding to the third opening OP3 can be exposed through the third opening OP3.

[0167] Although a portion of the second barrier insulation layer 161 is removed, the contact insulation pattern 141 can be retained to overlap with the edge portion CE of the conductive pattern CP.

[0168] Referring to Figures 31A and 31B, the horizontal layer 201 of the preliminary contact structure 200B shown in Figure 29A and the horizontal layer 201 of the preliminary dummy structure 200C shown in Figure 29B can be removed through the contact hole HB and the dummy hole HC. Furthermore, the first semiconductor pattern 105B and the second semiconductor pattern 111B overlapping with the preliminary contact structure 200B shown in Figure 29A, and the first semiconductor pattern 105C and the second semiconductor pattern 111C overlapping with the preliminary dummy structure 200C shown in Figure 29B can be removed.

[0169] A first recessed region 283A may be defined in the region where each of the first semiconductor patterns 105B and 105C shown in FIG. 29A and FIG. 29B has been removed; a second recessed region 283B may be defined in the region where the horizontal layer 201 shown in FIG. 29A and FIG. 29B has been removed; and a third recessed region 283C may be defined in the region where each of the second semiconductor patterns 111B and 111C shown in FIG. 29A and FIG. 29B has been removed. When removing the first semiconductor patterns 105B and 105C, the horizontal layer 201, and the second semiconductor patterns 111B and 111C shown in FIG. 29A and FIG. 29B, the portion of the doped semiconductor layer 173 disposed above the second upper protective layer 271 may be removed.

[0170] The first protective layer 107 and the second protective layer 109 may be retained at the boundary between the first recessed region 283A, the second recessed region 283B and the third recessed region 283C.

[0171] Referring to Figures 32A and 32B, the contact hole HB, dummy hole HC, first recessed region 283A, second recessed region 283B, and third recessed region 283C shown in Figures 31A and 31B can be filled with a second conductive material. Subsequently, the second conductive material can be etched to expose the filling insulating layer 131. Therefore, the conductive gate contact portion 181A and the dummy contact portion 181B can be defined.

[0172] The doped semiconductor layer 173 shown in FIG31A can be planarized using a planarization process for forming conductive gate contacts 181A and dummy contacts 181B. Therefore, the doped semiconductor layer 173 shown in FIG31A can be retained as a common source pattern CSL. The common source pattern CSL may include a horizontal doped semiconductor pattern 173H and a conductive vertical contact 173VC. The horizontal doped semiconductor pattern 173H may contact the unit channel layer 153A of the channel structure CH and is disposed between the first doped semiconductor pattern 105A and the second doped semiconductor pattern 111A. The conductive vertical contact 173VC can extend from the horizontal doped semiconductor pattern 173H in the Z-axis direction. The conductive vertical contact 173VC can be insulated from multiple conductive patterns CP through a sidewall insulating layer 171.

[0173] The conductive gate contact portion 181A can not only fill the contact hole HB shown in FIG31A, but also fill the first recessed region 283A, the second recessed region 283B, and the third recessed region 283C connected to the contact hole HB shown in FIG31A. The conductive gate contact portion 181A can contact the edge portion CE of the corresponding conductive pattern CP through the second opening OP2. The base portion CB of the conductive pattern CP can be spaced apart from the conductive gate contact portion 181A by the remaining contact insulating pattern 141.

[0174] The dummy contact portion 181B can not only fill the dummy hole HC shown in FIG31B, but also fill the first recessed region 283A, the second recessed region 283B, and the third recessed region 283C connected to the dummy hole HC shown in FIG31B. The dummy contact portion 181B can contact the edge portion CE of the corresponding conductive pattern CP through the third opening OP3. The base portion CB of the conductive pattern CP can be spaced apart from the dummy contact portion 181B through the remaining contact insulating pattern 141.

[0175] In the process of replacing the horizontal layer 201 of the first support structure 150[1] shown in FIG28A and the preliminary contact structure 200B shown in FIG29A with the conductive gate contact portion 181A, and replacing the horizontal layer 201 of the second support structure 150[2] shown in FIG28B and the preliminary dummy structure 200C shown in FIG29A with the dummy contact portion 181B, the first protective layer 107 and the second protective layer 109 are not removed, but can be retained.

[0176] Subsequently, subsequent processes for forming the upper insulating layer UI, bit line contact 193A, upper contact 193B, bit line BL and upper line UL shown in FIG3A, FIG3B and FIG3C can be performed.

[0177] Figures 33A to 33J are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to one embodiment of the present disclosure. Figures 33A to 33J are cross-sectional views illustrating a variant embodiment of the process for forming a sacrificial pad. Figures 33A to 33J show the contact region CTR' of a preliminary stepped stack structure 320. Although not shown in the figures, the preliminary stepped stack structure 320 may include an extension region extending from the contact region CTR', and the process for the extension region may be performed similarly to the process for the contact region CTR', which will be described later.

[0178] Referring to FIG33A, a first lower insulating layer 101, a plurality of preliminary contact structures 200B, and a second lower insulating layer 104 can be formed through a plurality of lower contact portions 103A as described with reference to FIGS. 7A and 7B.

[0179] Subsequently, as described with reference to Figures 8A, 8B, 9A, 9B, 10A, and 10B, a preliminary stepped stack structure 320 is formed above the second lower insulating layer 104. The preliminary stepped stack structure 320 may be composed of a plurality of interlayer insulating layers 1L and a plurality of sacrificial layers SC' alternately disposed above the second lower insulating layer 104. A plurality of sacrificial pillars 225B may be embedded in a portion of the contact area CTR' of the preliminary stepped stack structure 320. The plurality of sacrificial pillars 225B may extend into the interior of each of the plurality of preliminary contact structures 200B.

[0180] Multiple sacrificial layers SC' can be patterned to have a longer lateral length in the contact region CTR' as they get closer to the second lower insulating layer 104. Each sacrificial layer SC' may include a base SB' and an edge SE' extending from the base SB'. The base SB' may be disposed between interlayer insulating layers IL adjacent to each other along the Z-axis direction, and the top surface of the edge SE' may be open. The multiple edge SE's of the multiple sacrificial layers SC' may form a stepped structure in the contact region CTR'. The sacrificial layers SC' may be made of a material that has etch selectivity relative to the interlayer insulating layer IL.

[0181] Subsequently, a spacer pattern 301 may be formed. The spacer pattern 301 may be disposed on the edge SE' of each of the steps constituting the initial stepped stack structure 320 and the sidewall of the interlayer insulating layer IL. The spacer pattern 301 may be made of a material having etch selectivity relative to the sacrificial layer SC'. Each of the plurality of edge SE' may include an area overlapping the spacer pattern 301 on its top and an area that does not overlap with the spacer pattern 301 but is exposed.

[0182] For example, the plurality of interlayer insulating layers IL may include a lower interlayer insulating layer LIL, an intermediate interlayer insulating layer MIL, and an upper interlayer insulating layer UIL stacked in the Z-axis direction. The plurality of sacrificial layers SC' may include a lower sacrificial layer LSC' located between the lower interlayer insulating layer LIL and the intermediate interlayer insulating layer MIL, and an upper sacrificial layer USC' located between the intermediate interlayer insulating layer MIL and the upper interlayer insulating layer UIL. The lower sacrificial layer LSC' may include a lower base LB' located between the lower interlayer insulating layer LIL and the intermediate interlayer insulating layer MIL, and a lower edge portion LE' that further protrudes laterally from the lower base LB' relative to the intermediate interlayer insulating layer MIL. The upper sacrificial layer USC' may include an upper base UB' located between the intermediate interlayer insulating layer MIL and the upper interlayer insulating layer UIL, and an upper edge portion UE' that further protrudes laterally from the upper base UB' relative to the upper interlayer insulating layer UIL. At least one of the plurality of spacing patterns may be disposed on the lower edge portion LE'. A portion of the top surface of the lower edge portion LE' may overlap with the spacing pattern 301, and another portion of the top surface of the lower edge portion LE' may be exposed without overlapping with the spacing pattern 301. The spacing pattern 301 that overlaps with a portion of the top surface of the lower edge portion LE' may extend along the sidewall of the intermediate interlayer insulation layer MIL and the sidewall of the upper edge portion UE'.

[0183] Referring to FIG33B, the first sacrificial pad 303 may be formed on a plurality of edge portions SE' respectively. The first sacrificial pad 303 may be made of the same material as the sacrificial layer SC'.

[0184] The first sacrificial pad 303 may overlap with the portion of the top surface of the edge SE' of the sacrificial layer SC' exposed by the spacing pattern 301. The first sacrificial pad 303 may be spaced apart from the sacrificial layer SC' by the spacing pattern 301.

[0185] The process for forming the first sacrificial pad 303 is not limited to the above example, and can be various.

[0186] Referring to FIG33C, the spacer pattern 301 shown in FIG33B can be removed. Subsequently, as described with reference to FIGS. 11A and 11B, a first filling insulating layer 131A can be formed. The first filling insulating layer 131A can cover the initial stepped stack structure 320 and includes a protrusion 131P that fills the area where the spacer pattern 301 shown in FIG33B has been removed. However, this disclosure is not limited thereto. In one embodiment, the spacer pattern 301 made of insulating material can be retained, and the first filling insulating layer 131A can cover the retained spacer pattern 301.

[0187] Referring to FIG33D, as described with reference to FIGS. 11A and 11B, a second filling insulating layer 131B can be formed on the first filling insulating layer 131A. Therefore, a filling insulating layer 131 including the first filling insulating layer 131A and the second filling insulating layer 131B can be formed above the preliminary stepped stacked structure 320.

[0188] Subsequently, the filling insulating layer 131 overlapping with the plurality of sacrificial pillars 225B shown in FIG33C and the preliminary stepped stack structure 320 can be etched. Subsequently, the plurality of sacrificial pillars 225B shown in FIG33C can be removed. Thus, a plurality of contact holes HB' can be formed.

[0189] Multiple edges SE' of multiple sacrificial layers SC' can be penetrated by multiple contact holes HB' respectively. Each contact hole HB' can penetrate the contact area CTR' of the preliminary stepped structure 320 and the corresponding second semiconductor pattern 111B and preliminary contact structure 200B, and extend into the interior of the corresponding first semiconductor pattern 105B. The first sacrificial pad 303 can be penetrated by multiple contact holes HB' respectively.

[0190] As described with reference to FIG13A, the reference hole R' among the plurality of contact holes HB' may be spaced apart from the upper interlayer insulating layer UIL and penetrate the intermediate interlayer insulating layer MIL, the upper sacrificial layer USC', the lower sacrificial layer LSC', and the lower interlayer insulating layer LIL. For example, the reference hole R' may penetrate the upper edge UE' of the upper sacrificial layer USC' and the lower base LB' of the lower sacrificial layer LSC'.

[0191] Referring to FIG33E, multiple edge portions SE' of the multiple sacrificial layers SC' shown in FIG33D and multiple first sacrificial pads 303 can be removed through multiple contact holes HB'. Therefore, multiple first recessed regions 311 can be defined. When removing the multiple first sacrificial pads 303 and multiple edge portions SE' shown in FIG33D, multiple base portions SB' can be etched through multiple contact holes HB'. Therefore, multiple second recessed regions 313 can be defined in the region where the multiple base portions SB' have been removed. Due to the removal of the first sacrificial pads 303, the first recessed regions 311 can be defined to have a wider width in the Z-axis direction than the second recessed regions 313.

[0192] Referring to FIG33F, a contact insulating layer 141L may be formed along the surfaces of the first recessed region 311, the second recessed region 313, and the contact hole HB'. The contact insulating layer 141L may extend along the surface of the filling insulating layer 131. The contact insulating layer 141L may be formed of a material having etch selectivity relative to the sacrificial layer SC'.

[0193] The contact insulating layer 141L can fill the second recessed region 313, which has a relatively narrow width. The first recessed region 311, which has a relatively wide width, is not completely filled by the contact insulating layer 141L, but the central region of the first recessed region 311 can be left open.

[0194] Referring to FIG33G, the contact insulating layer 141L shown in FIG33F can be etched to isolate it into a plurality of contact insulating patterns 141. Each contact insulating pattern 141 can be retained in its corresponding second recessed region 313. The plurality of first recessed regions 311 can be opened by the etching process of the contact insulating layer 141L.

[0195] Referring to FIG33H, multiple first recessed regions 311 can be filled by multiple second sacrificial pads 331 through multiple contact holes HB'. The second sacrificial pads 331 can be formed of the same material as the sacrificial layer SC'. The second sacrificial pads 331 can be formed to be thicker than the sacrificial layer SC' in the Z-axis direction.

[0196] As described above, a portion of the base SB' of the sacrificial layer SC' shown in FIG. 33D can be replaced by the contact insulating pattern 141, and the edge SE' and the first sacrificial pad 303 of the sacrificial layer SC' shown in FIG. 33D can be replaced by the second sacrificial pad 331. The contact insulating pattern 141 can be automatically aligned at the target position by the difference between the total thickness of the edge SE' and the first sacrificial pad 303 of the sacrificial layer SC' shown in FIG. 33D and the thickness of the base SB' of the sacrificial layer SC'.

[0197] Referring to FIG33I, a support structure 150[1] can be formed in the contact hole HB' by using the process described above with reference to FIG19A, FIG19B, FIG20A, FIG20B, FIG21, FIG22A and FIG22B. The support structure 150[1] may include a dummy memory pattern 151B, a dummy channel layer 153B and a dummy core insulating pattern 155B.

[0198] Subsequently, as described with reference to Figures 23A and 23B, an upper protective layer 271 may be formed over the filling insulating layer 131, thereby defining a gap 273 in the contact hole HB'.

[0199] Referring to FIG33J, the plurality of sacrificial layers SC' and the plurality of second sacrificial pads 331 shown in FIG33I can be removed by using the process described with reference to FIGS. 24A and 24B. Therefore, the plurality of gate regions 375 can be opened.

[0200] Then, the process described with reference to Figures 25A, 25B, 26, 27, 28A, 28B, 29A, 29B, 30A, 30B, 31A, 31B, 32A and 32B can be performed.

[0201] Figures 34A to 34O are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to one embodiment of the present disclosure. Figures 34A to 34O illustrate a method of manufacturing a portion of a semiconductor memory device, the regions corresponding to the cell region "CAR" and contact region "CTR" of a gate stack structure. Although not shown in the following figures, the gate stack structure may include an extended region as described with reference to FIG2, and the manufacturing process in the extended region may be performed similarly to the manufacturing process in the contact region "CTR" which will be described later. In the following, overlapping descriptions of components identical to those shown in FIG7A to 32B will be omitted.

[0202] Referring to FIG34A, a first semiconductor layer, a lower stacked structure, and a second semiconductor layer may be stacked on the first lower insulating layer 101. As described with reference to FIG7A and FIG7B, the lower stacked structure may include a first protective layer 107, a horizontal layer 201 located on the first protective layer 107, and a second protective layer 109 located on the horizontal layer 201.

[0203] Subsequently, as described with reference to FIGS. 7A and 7B, the second semiconductor layer, the lower stack structure, and the first semiconductor layer can be etched. Therefore, the first semiconductor layer can be isolated into a plurality of first semiconductor patterns 105A and 105B overlapping the first lower insulating layer 101. The second semiconductor layer can be isolated into a plurality of second semiconductor patterns 111A and 111B overlapping the plurality of first semiconductor patterns 105A and 105B, respectively. Furthermore, the lower stack structure can be isolated into a preliminary horizontal pattern 200A and a plurality of preliminary contact structures 200B. The preliminary horizontal pattern 200A can be disposed between the first semiconductor pattern 105A and the second semiconductor pattern 111A in the cell region "CAR", and the plurality of preliminary contact structures 200B can be disposed between the plurality of first semiconductor patterns 105B and the plurality of second semiconductor patterns 111B in the contact region "CTR".

[0204] Subsequently, the space between the plurality of first semiconductor patterns 105A and 105B can be filled using the second lower insulating layer 104. The second lower insulating layer 104 can fill the space between the initial horizontal pattern 200A and the plurality of initial contact structures 200B, as well as between the plurality of second semiconductor patterns 111A and 111B.

[0205] Subsequently, a plurality of lower contact portions 403A may be formed. Each lower contact portion 403A may penetrate the second semiconductor pattern 111B, the preliminary contact structure 200B, the first semiconductor pattern 105B and the first lower insulating layer 101 in the contact area CTR”.

[0206] Referring to FIG34B, as described with reference to FIG8A and FIG8B, a plurality of first material layers 221 and a plurality of second material layers 223 may be alternately stacked along the Z-axis direction on the second lower insulating layer 104 and the plurality of second semiconductor patterns 111A and 111B.

[0207] Subsequently, a first preliminary channel hole H1A may be formed, which penetrates multiple first material layers 221 and multiple second material layers 223 and extends into the interior of the first semiconductor pattern 105A in the cell region CAR. The first preliminary channel hole H1A may penetrate the second semiconductor pattern 111A and the preliminary horizontal pattern 200A and extend into the interior of the first semiconductor pattern 105A.

[0208] Subsequently, as described with reference to Figures 8A and 8B, the first preliminary channel hole H1A can be filled using the sacrificial pillar 225A. When forming the first preliminary channel hole H1A and the sacrificial pillar 225A, the plurality of first material layers 221 and the plurality of second material layers 223 can be maintained in a state where the plurality of first material layers 221 and the plurality of second material layers 223 overlap with the plurality of lower contact portions 403A in the contact area CTR”.

[0209] Subsequently, as shown with reference to Figures 9A and 9B, a plurality of third material layers 227 and a plurality of fourth material layers 229 on the sacrificial pillar 225A may be alternately stacked on top of the stacked structure of a plurality of first material layers 221 and a plurality of second material layers 223 and the sacrificial pillar 225A.

[0210] Referring to FIG34C, an etch stop layer 410 may be formed over a stacked structure of multiple third material layers 227 and multiple fourth material layers 229. The etch stop layer 410 may include a nitride layer. After forming the etch stop layer 410, the etch stop layer 410, the multiple third material layers 227, and the multiple fourth material layers 229 overlapping with the sacrificial pillar 225A shown in FIG34B may be etched to form a second preliminary via H2A. The second preliminary via H2A may expose the sacrificial pillar 225A shown in FIG34B while penetrating the etch stop layer 410, the multiple third material layers 227, and the multiple fourth material layers 229.

[0211] Subsequently, the sacrificial pillar 225A shown in FIG34B can be removed through the second preliminary channel hole H2A. Therefore, the first preliminary channel hole H1A can be opened. The second preliminary channel hole H2A can be connected to the first preliminary channel hole H1A, thus defining the channel hole HA". The channel hole HA” can penetrate multiple first material layers 221, multiple second material layers 223, multiple third material layers 227, multiple fourth material layers 229, second semiconductor layer 111A and preliminary horizontal pattern 200A in the cell region CAR. In addition, the channel hole HA” can extend into the interior of the first semiconductor pattern 105A. When forming the channel hole HA”, the multiple first material layers 221, multiple second material layers 223, multiple third material layers 227 and multiple fourth material layers 229 can be maintained in a state where the multiple first material layers 221, multiple second material layers 223, multiple third material layers 227 and multiple fourth material layers 229 overlap with multiple lower contact portions 403A in the contact region CTR”.

[0212] Subsequently, a memory pattern 151A and a channel structure CH can be formed in the channel hole HA. The channel structure CH may include a cell channel layer 153A, a core insulating pattern 155A, and a capping pattern 157.

[0213] The process of forming the memory pattern 151A and the channel structure CH may include a process of forming a memory layer by sequentially stacking a first barrier insulating layer, a data storage layer and a tunneling insulating layer along the surface of the channel hole HA”, a process of forming a channel layer along the surface of the memory layer, a process of filling the central region of the channel hole HA” with a core insulating pattern 155A and a capping pattern 157, and a process of removing a portion of each of the memory layer and the channel layer by performing a planarization process to expose the etch stop layer 410.

[0214] Referring to FIG34D, and as described with reference to FIGS. 10A and 10B, a plurality of first material layers 221, a plurality of second material layers 223, a plurality of third material layers 227, and a plurality of fourth material layers 229 may be etched to define an initial stepped stacked structure 220. The plurality of first material layers 221 and the plurality of fourth material layers 229 may be retained as a plurality of interlayer insulating layers IL, and the plurality of second material layers 223 and the plurality of third material layers 227 may be retained as a plurality of sacrificial layers SC. As described with reference to FIGS. 10A and 10B, each sacrificial layer SC may include a base SB and an edge SE extending from the base SB. The edge SE may be retained to be thinner than the base SB.

[0215] Subsequently, the remaining portion of the etch stop layer 410 shown in FIG. 34C can be removed. Subsequently, a fill insulating layer 420 can be formed to cover the cell region "CAR" and contact region "CTR" of the initial stepped stack structure 220.

[0216] Referring to FIG34E, the filling insulating layer 420 and the preliminary stepped stacked structure 220 can be etched to define the first preliminary slit SI1 and the plurality of contact holes HB". When forming the first preliminary slit SI1 and the plurality of contact holes HB", the second semiconductor pattern 111A of the cell region CAR and the plurality of lower contacts 403A of the contact region CTR can be used as etch stop layers. By defining the plurality of contact holes HB" by using the process of forming the first preliminary slit SI1, the manufacturing method of the semiconductor memory device can be simplified.

[0217] The first preliminary slit SI1 can penetrate the filling insulating layer 420 and the preliminary stepped stacking structure 220 in the unit region CAR”. The first preliminary slit SI1 can penetrate the multiple bases SB of the multiple sacrificial layers SC. The multiple contact holes HB” can penetrate the filling insulating layer 420 and the preliminary stepped stacking structure 220 in the contact region CTR” to expose multiple lower contact portions 403A respectively. The multiple edge portions SE of the multiple sacrificial layers SC can be penetrated by the multiple contact holes HB” respectively.

[0218] Referring to FIG34F, a first upper protective layer 431 may be formed over the filling insulating layer 420. The first upper protective layer 431 may be formed by using a deposition process with low step coverage, thereby defining a void 433 in the central region of each of the first preliminary slit SI1 and the plurality of contact holes HB”.

[0219] Referring to FIG34G, the portion of the first upper protective layer 431 that overlaps with the contact area CTR” of the preliminary stepped stacked structure 220 can be removed. Therefore, the multiple contact holes HB” can be opened, and the multiple edges SE of the multiple sacrificial layers SC can be exposed through the multiple contact holes HB” respectively.

[0220] Referring to FIG34H, as described with reference to FIG14A and FIG14B, multiple sacrificial layers SC can be etched through multiple contact holes HB” to define multiple first recessed regions 231 and multiple second recessed regions 233.

[0221] Each first recessed region 231 may be defined in the region where the edge portion SE of the sacrificial layer SC shown in FIG34G has been removed. Each second recessed region 233 may be defined in the region where the portion of the base SB of the sacrificial layer SC located below the edge portion SE shown in FIG34G has been removed.

[0222] Subsequently, by using the processes described with reference to FIG15A and FIG15B and the processes described with reference to FIG16A and FIG16B, a sacrificial pad 241P can be formed in the first recessed region 231.

[0223] Referring to FIG34I, a contact insulating layer 441 may be formed along the surface of the contact hole HB”. The contact insulating layer 441 may fill the second recessed region 233. The central region of the contact hole HB” is not filled by the contact insulating layer 441, but may be left open. The contact insulating layer 441 may extend along the surface of the filling insulating layer 420 in the contact region CTR”, and along the top surface of the first upper protective layer 431 in the cell region CAR”. The contact insulating layer 441 may be formed of a material having etch selectivity relative to the sacrificial layer SC. In one embodiment, the contact insulating layer 441 may include an oxide layer.

[0224] Subsequently, an inner liner 443 may be formed over the contact insulating layer 441. The inner liner 443 may include a material that is etch-selective relative to the contact insulating layer 441. In one embodiment, the inner liner 443 may include silicon. The central region of the contact hole HB is not filled by the inner liner 443, but may be left open.

[0225] Referring to FIG34J, a second upper protective layer 445 can be formed on the inner liner 443. The second upper protective layer 445 can be formed by using a deposition process with low step coverage, thereby defining a void 451 in the central region of the plurality of contact holes HB”.

[0226] Referring to FIG34K, the portion of each of the second upper protective layer 445, the inner liner layer 443, and the contact insulating layer 441 that overlaps with the cell region "CAR" of the initial stepped stack structure 220 can be removed. Subsequently, a portion of the first upper protective layer 431 can be removed, thereby opening the first initial slit SI1. For this purpose, a masking pattern (not shown) that opens the cell region "CAR" of the initial stepped stack structure 220 and blocks the contact region "CTR" can be used as an etching barrier. After the first initial slit SI1 is opened, the masking pattern can be removed.

[0227] Referring to FIG34L, multiple sacrificial layers SC and multiple sacrificial pads 241P of the preliminary stepped stacked structure 220 shown in FIG34K can be removed through the first preliminary slit SI1. Therefore, multiple gate regions 275 can be defined as shown in FIGS. 24A and 24B. The contact insulating layer 441 and the inner liner layer 443 retained in the multiple contact holes HB” can be used as a support structure, which stably maintains the gap between adjacent interlayer insulating layers IL in the Z-axis direction. The contact insulating layer 441 of the support structure can extend between adjacent interlayer insulating layers IL.

[0228] Subsequently, as described with reference to FIGS. 25A and 25B, a second barrier insulating layer 161 and a plurality of conductive patterns CP can be formed. As described with reference to FIGS. 25A and 25B, each conductive pattern CP can be exposed through a first opening OP1 in the second barrier insulating layer 161. As described with reference to FIGS. 25A and 25B, each conductive pattern CP may include a base CB and an edge portion CE that is thinner than the thickness of the base CB. The base CB may surround the channel structure CH and the memory pattern 151A.

[0229] Referring to FIG34M, as described with reference to FIG26, a second preliminary slit SI2 can be formed through the second semiconductor pattern 111A, thereby defining the slit SI. Subsequently, as described with reference to FIG27, after the sidewall insulating layer 171 is formed on the sidewall of the slit SI, some portions of the preliminary horizontal pattern 200A shown in FIG34L and the memory pattern 151A shown in FIG34L can be removed. Therefore, the horizontal space 277 can be opened, and the first memory pattern 151P1 and the second memory pattern 151P2 can be isolated from each other through the horizontal space 277. Furthermore, the sidewall of the cell channel layer 153A can be exposed through the horizontal space 277.

[0230] Subsequently, as described with reference to Figures 28A and 28B, a doped semiconductor layer 173 may be formed to fill the horizontal space 277 and the slit SI. The doped semiconductor layer 173 may extend to cover the first upper protective layer 431 and the second upper protective layer 445.

[0231] Referring to FIG34N, a portion of the doped semiconductor layer 173, the upper protective layer 445, and the inner liner layer 443 shown in FIG34M can be removed by using an etching process. This etching process uses a masking pattern (not shown) that blocks the cell region CAR” and opens the contact region CTR” as an etching barrier. Subsequently, a portion of the contact insulating layer 441 shown in FIG34M can be removed by an etching process such as back etching, thereby exposing a portion of the second barrier insulating layer 161. The portion of the second barrier insulating layer 161 facing the sidewall of the contact hole HB” shown in FIG34M can be exposed, and the portion of the contact insulating layer 441 shown in FIG34M located between the interlayer insulating layers IL can be retained as the contact insulating pattern 441P in the second recessed region. In addition, the plurality of contact holes HB” can be opened.

[0232] Subsequently, as described with reference to Figures 30A and 30B, a portion of the second barrier insulating layer 161 can be removed, thereby defining the second opening OP2. The edge portion CE of the conductive pattern CP can be exposed through the second opening OP2 of the second barrier insulating layer 161. The masking pattern can be removed after the second opening OP2 is formed.

[0233] Referring to FIG340, after filling the plurality of contact holes HB” shown in FIG34M with conductive material, a planarization process can be performed to expose the filling insulating layer 420. Therefore, a plurality of conductive gate contacts 181A respectively connected to a plurality of lower contacts 403A can be formed. The second semiconductor pattern 111B, the preliminary contact structure 200B and the first semiconductor pattern 105B can be retained to surround each lower contact 403A in the contact region CTR”.

[0234] Through the planarization process described above, the doped semiconductor layer 173 shown in FIG34M can be retained as a common source pattern CSL. As described with reference to FIG32A, the common source pattern CSL can be divided into a horizontal doped semiconductor pattern 173H and a conductive vertical contact portion 173VC, and is in contact with the cell channel layer 153A.

[0235] Subsequently, subsequent processes for forming the upper insulating layer UI, bit line contact 193A, upper contact 193H, bit line BL and upper line UL shown in FIG3A, FIG3B and FIG3C can be performed.

[0236] Figures 34A to 34M illustrate one embodiment of a method for manufacturing a conductive pattern CP, the conductive pattern CP including a base CB and an edge portion CE that is thinner than the base CB. However, the embodiments disclosed herein are not limited thereto. In another embodiment, by using the process shown in Figures 33A to 33J, the edge portion of the conductive pattern can be formed to be thicker than the base portion of the conductive pattern.

[0237] Figure 35 is a block diagram showing the construction of a memory system according to one embodiment of the present disclosure.

[0238] Referring to FIG35, the memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0239] The memory device 1120 may be a multi-chip package comprising multiple flash memory chips. The memory device 1120 may include multiple conductive patterns stacked in a stepped shape, and a conductive gate contact extending through and contacting the edge of one of the conductive patterns. The multiple conductive patterns may include a lower conductive pattern disposed below the edge of the conductive pattern contacting the conductive gate contact, and the conductive gate contact may extend through the lower conductive pattern. The conductive gate contact may be insulated from the lower conductive pattern by a contact insulating pattern. Furthermore, the memory device 1120 may include a horizontally doped semiconductor pattern disposed below the multiple conductive patterns, and a cell channel layer connected to the horizontally doped semiconductor pattern and extending to be surrounded by the multiple conductive patterns. The conductive gate contact may extend to the height of the horizontally doped semiconductor pattern and have a groove into which a protective layer is inserted at the height of the horizontally doped semiconductor pattern. Alternatively, the conductive gate contact may extend to contact a lower contact extending to the height of the horizontally doped semiconductor pattern.

[0240] The memory controller 1110 is configured to control the memory device 1120 and may include static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory of the CPU 1112, which performs overall control operations for data exchange with the memory controller 1110. The host interface 1113 includes a data exchange protocol for the host connected to the memory system 1100. The ECC circuit 1114 detects and corrects errors included in the data read from the memory device 1120, while the memory interface 1115 provides an interface connection to the memory device 1120. The memory controller 1110 may also include ROM or similar components for storing code data for interface connection with the host.

[0241] The memory system 1100 configured as described above can be a memory card or a solid-state drive (SSD), wherein the memory device 1120 is combined with the controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1100 can communicate with an external (e.g., a host) via one of various interface protocols, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, Fast PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol.

[0242] Figure 36 is a block diagram showing the construction of a computing system according to one embodiment of the present disclosure.

[0243] Referring to FIG36, the computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for providing operating voltage to the computing system 1200, and may also include an application chipset, a camera image processor (CIS), mobile D-RAM, etc.

[0244] The memory system 1210 may be composed of a memory device 1212 and a memory controller 1211.

[0245] The memory device 1212 may be configured in the same way as the memory device 1120 described with reference to FIG35.

[0246] According to one embodiment, by using the thickness difference of the sacrificial material included in at least one of the sacrificial layer and sacrificial pad, the contact insulation pattern can be automatically aligned at the target location. Therefore, the stability of the manufacturing process can be improved.

[0247] According to one embodiment, the support structure is provided with a conductive gate contact portion, thereby reducing the area occupied by the conductive gate contact portion and the support structure. Furthermore, in one embodiment, although no separate support structure is provided around the conductive gate contact portion, structural stability and manufacturing process stability can be improved by pre-forming a support structure in the area where the conductive gate contact portion will be provided.

[0248] According to one embodiment, although some support structures provided around the conductive gate contact portion are omitted, the stability of the manufacturing process can be improved. Therefore, in one embodiment, the area of ​​the conductive gate contact portion can be increased to correspond to the area of ​​the omitted support structures. [Simplified Explanation of the Diagram]

[0011] [Figure 1] is a diagram showing a schematic structure of a semiconductor memory device according to one embodiment of the present disclosure.

[0012] [Figure 2] is a plan view showing a portion of a semiconductor memory device according to one embodiment of the present disclosure.

[0013] [Figures 3A, 3B and 3C] are cross-sectional views of the semiconductor memory device shown in Figure 2.

[0014] [Figure 4] is an enlarged cross-sectional view of region AR1 shown in Figure 3B.

[0015] [Figure 5] is a cross-sectional view showing a semiconductor memory device according to one embodiment of the present disclosure.

[0016] [Figure 6] is an enlarged cross-sectional view of region AR2 shown in Figure 5.

[0017] [Figures 7A and 7B] are cross-sectional views illustrating a process of isolating a lower stacked structure into multiple patterns according to one embodiment of the present disclosure.

[0018] [Figures 8A, 8B, 9A, 9B, 10A and 10B] are cross-sectional views illustrating a method for forming a preliminary stepped stacked structure according to one embodiment of the present disclosure.

[0019] [Figures 11A, 11B, 12A, 12B, 13A and 13B] are cross-sectional views illustrating a method for forming contact holes and dummy holes according to one embodiment of the present disclosure.

[0020] [Figures 14A, 14B, 15A, 15B, 16A, 16B, 17A and 17B] are cross-sectional views illustrating a method for forming a sacrificial pad and a contact insulation pattern according to one embodiment of the present disclosure.

[0021] [Fig. 18] is a cross-sectional view showing a method for forming a channel hole according to one embodiment of the present disclosure.

[0022] [Figures 19A, 19B, 20A, 20B, 21, 22A and 22B] are cross-sectional views illustrating a method for forming a preliminary memory pattern, a channel structure, a first support structure and a second support structure according to one embodiment of the present disclosure.

[0023] [Figures 23A, 23B, 24A, 24B, 25A and 25B] are cross-sectional views illustrating a method for forming a barrier insulating layer and a conductive pattern according to one embodiment of the present disclosure.

[0024] [Figures 26, 27, 28A, 28B, 29A, 29B, 30A, 30B, 31A, 31B, 32A and 32B] are cross-sectional views illustrating a method for forming a common source pattern, a conductive gate contact, and a dummy contact according to one embodiment of the present disclosure.

[0025] [Figures 33A, 33B, 33C, 33D, 33E, 33F, 33G, 33H, 33I and 33J] are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure.

[0026] [Figures 34A, 34B, 34C, 34D, 34E, 34F, 34G, 34H, 34I, 34J, 34K, 34L, 34M, 34N and 34O] are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure.

[0027] [Figure 35] is a block diagram showing the construction of a memory system according to one embodiment of the present disclosure.

[0028] [Figure 36] is a block diagram showing the construction of a computing system according to one embodiment of the present disclosure.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: First conductive gate contact; The first contact portion insulation pattern surrounds the first conductive gate contact portion; A first conductive pattern surrounds an insulating pattern at the first contact portion. The second conductive pattern is disposed above the first conductive pattern and surrounds the first conductive gate contact portion. The second conductive pattern includes: a first edge portion that overlaps with the insulating pattern of the first contact portion and contacts the first conductive gate contact portion; and a first base portion that is spaced apart from the first conductive gate contact portion by the first edge portion, extends away from the first conductive gate contact portion from the first edge portion, and is thicker than the first edge portion.

2. The semiconductor memory device according to claim 1, wherein, The first conductive pattern includes: a second base portion that overlaps with the first edge portion of the second conductive pattern, the second base portion being thicker than the first edge portion; and a second edge portion that extends from the second base portion, the second edge portion being thinner than the second base portion.

3. The semiconductor memory device according to claim 2, the semiconductor memory device further comprising a second conductive gate contact portion surrounded by a second edge portion of the first conductive pattern, the second conductive gate contact portion having a sidewall that contacts the second edge portion.

4. The semiconductor memory device according to claim 1, further comprising: An interlayer insulating layer is located between the first conductive pattern and the second conductive pattern; A sidewall insulating layer extending along the sidewalls of the first conductive pattern, the second conductive pattern, and the interlayer insulating layer; a conductive vertical contact portion located on the sidewall insulating layer; And a barrier insulating layer that extends along the surface of each of the first conductive pattern and the second conductive pattern.

5. The semiconductor memory device according to claim 4, wherein, The barrier insulating layer includes a first opening facing the sidewall insulating layer and a second opening facing the first conductive gate contact, wherein the second opening is narrower than the first opening.

6. The semiconductor memory device according to claim 1, further comprising: A dummy contact portion is provided, which penetrates both the first conductive pattern and the second conductive pattern; The second contact insulating pattern is disposed between the dummy contact and at least one of the first conductive pattern and the second conductive pattern. And an upper insulating layer, which is located on the top surface of the dummy contact portion.

7. A semiconductor memory device, the semiconductor memory device comprising: Horizontally doped semiconductor patterns; A stepped stacked structure includes multiple interlayer insulating layers and multiple conductive patterns alternately stacked on a horizontally doped semiconductor pattern. The stepped stacked structure includes a cell region overlapping the horizontally doped semiconductor pattern and a contact region extending from the cell region; a cell channel layer that contacts the horizontally doped semiconductor pattern and penetrates the cell region of the stepped stacked structure; and multiple conductive gate contacts that penetrate the contact region of the stepped stacked structure and extend to the height of the horizontally doped semiconductor pattern. And a protective layer that penetrates the sidewall of each of the plurality of conductive gate contacts and is located at the height provided by the horizontally doped semiconductor pattern.

8. The semiconductor memory device according to claim 7, wherein, The plurality of conductive gate contacts include a first conductive gate contact and a second conductive gate contact spaced apart from each other, and wherein the plurality of conductive patterns include: a first conductive pattern surrounding the first conductive gate contact and the second conductive gate contact; and a second conductive pattern disposed above the first conductive pattern and spaced apart from the second conductive gate contact.

9. The semiconductor memory device according to claim 8, wherein, The second conductive pattern includes a first edge portion surrounding the first conductive gate contact portion and a first base portion extending from the first edge portion toward the cell channel layer, wherein the first conductive pattern includes a second base portion overlapping the first edge portion of the second conductive pattern and surrounding the first conductive gate contact portion, and a second edge portion extending from the second base portion to surround the second conductive gate contact portion, wherein the first edge portion of the second conductive pattern includes a sidewall contacting the first conductive gate contact portion, and wherein the second edge portion of the first conductive pattern includes a sidewall contacting the second conductive gate contact portion.

10. The semiconductor memory device according to claim 9, wherein, The first edge portion and the second edge portion are thinner than the first base portion and the second base portion.

11. The semiconductor memory device according to claim 9, wherein, The first edge portion and the second edge portion are thicker than the first base portion and the second base portion.

12. The semiconductor memory device according to claim 9, the semiconductor memory device further comprising a contact insulating pattern disposed between the first conductive pattern and the first conductive gate contact.

13. The semiconductor memory device according to claim 7, further comprising: A conductive vertical contact portion extends from the horizontally doped semiconductor pattern parallel to the cell channel layer; A sidewall insulating layer is located between the conductive vertical contact and the stepped stacked structure; And a barrier insulating layer extending along the surface of each of the plurality of conductive patterns, wherein the barrier insulating layer includes a first opening facing the sidewall insulating layer and a second opening facing a corresponding conductive gate contact of the plurality of conductive gate contacts.

14. The semiconductor memory device according to claim 13, wherein, The width of the second opening is narrower than the width of the first opening.

15. The semiconductor memory device according to claim 13, wherein, The width of the second opening is wider than the width of the first opening.

16. The semiconductor memory device according to claim 7, wherein, The stepped stacked structure also includes an extension region extending from the contact region.

17. The semiconductor memory device according to claim 16, further comprising: Multiple upper contact portions, the multiple upper contact portions being connected to the multiple conductive gate contact portions; Multiple upper lines, the multiple upper lines being connected to the multiple upper contacts; Multiple dummy contacts extend through the extended region of the stepped stacked structure and extend to the height of the horizontally doped semiconductor pattern. And an upper insulating layer, which is located between the plurality of upper contacts and between the plurality of upper lines, and covers the plurality of dummy contacts.

18. A semiconductor memory device, the semiconductor memory device comprising: A stepped stacked structure includes multiple alternately stacked interlayer insulating layers and multiple conductive patterns, the stepped stacked structure including a cell region and a contact region extending from the cell region; a horizontally doped semiconductor pattern disposed below the cell region of the stepped stacked structure; a lower insulating layer disposed below the contact region of the stepped stacked structure, the lower insulating layer being located at the height of the horizontally doped semiconductor pattern; multiple lower contacts penetrating the lower insulating layer; a cell channel layer contacting the horizontally doped semiconductor pattern, the cell channel layer penetrating the cell region of the stepped stacked structure; and multiple conductive gate contacts connected to the multiple lower contacts, the multiple conductive gate contacts penetrating the contact region of the stepped stacked structure.

19. The semiconductor memory device according to claim 18, further comprising: A first protective layer, a horizontal layer, and a second protective layer, wherein the first protective layer, the horizontal layer, and the second protective layer surround each of the plurality of lower contacts and the lower insulating layer, wherein the first protective layer, the horizontal layer, and the second protective layer are stacked in a direction in which the plurality of interlayer insulating layers and the plurality of conductive patterns are stacked; and a first semiconductor pattern, wherein the first semiconductor pattern is disposed below the first protective layer and surrounds each of the plurality of lower contacts. And a second semiconductor pattern disposed on the second protective layer, the second semiconductor pattern surrounding each of the plurality of lower contacts.

20. The semiconductor memory device according to claim 18, wherein, The plurality of conductive gate contacts include a first conductive gate contact and a second conductive gate contact spaced apart from each other, and wherein the plurality of conductive patterns include: a first conductive pattern surrounding the first conductive gate contact and the second conductive gate contact; and a second conductive pattern disposed above the first conductive pattern and spaced apart from the second conductive gate contact.

21. The semiconductor memory device according to claim 20, wherein, The second conductive pattern includes a first edge portion surrounding the first conductive gate contact portion and a first base portion extending from the first edge portion toward the cell channel layer, wherein the first conductive pattern includes a second base portion overlapping the first edge portion of the second conductive pattern and surrounding the first conductive gate contact portion, and a second edge portion extending from the second base portion to surround the second conductive gate contact portion, wherein the first edge portion of the second conductive pattern includes a sidewall contacting the first conductive gate contact portion, and wherein the second edge portion of the first conductive pattern includes a sidewall contacting the second conductive gate contact portion.

22. The semiconductor memory device according to claim 21, wherein, The thicknesses of the first edge portion and the second edge portion are different from the thicknesses of the first base portion and the second base portion.

23. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A preliminary stepped stacked structure is formed, comprising a lower interlayer insulating layer, an intermediate interlayer insulating layer, an upper interlayer insulating layer, a lower sacrificial layer, and an upper sacrificial layer. The lower sacrificial layer includes a lower base portion located between the lower interlayer insulating layer and the intermediate interlayer insulating layer, and a lower edge portion that protrudes further to the side from the lower base portion relative to the intermediate interlayer insulating layer and is thinner than the lower base portion. The upper sacrificial layer includes an upper base portion located between the intermediate interlayer insulating layer and the upper interlayer insulating layer, and an upper edge portion that protrudes further to the side from the upper base portion relative to the upper interlayer insulating layer and is thinner than the upper base portion. A filling insulating layer is formed, covering the preliminary stepped stacked structure. A contact hole is formed, the contact hole penetrating the filling insulation layer, the upper edge portion, the intermediate interlayer insulation layer, the lower base portion, and the lower interlayer insulation layer; the upper edge portion is replaced by a sacrificial pad through the contact hole; a portion of the lower base portion is replaced by a contact portion insulation pattern through the contact hole; and a support structure surrounded by the contact portion insulation pattern and the sacrificial pad is formed in the contact hole.

24. The method according to claim 23, the method further comprising the steps of: forming a channel hole penetrating the upper interlayer insulating layer, the upper base, the intermediate interlayer insulating layer, the lower base, and the lower interlayer insulating layer; and forming a memory layer along the surface of the channel hole; A channel layer is formed along the surface of the memory layer; The central region of the channel hole is filled using a core insulating pattern and a capping pattern on the core insulating pattern.

25. The method according to request item 24, wherein, The support structure includes the memory layer and the channel layer extending into the interior of the contact hole, and a dummy core insulating pattern disposed on the channel layer in the contact hole.

26. The method according to claim 25, the method further comprising the step of: forming an upper protective layer covering the support structure and the cap pattern, such that a gap is defined in the contact hole; A slit is formed, the slit penetrating the upper protective layer, the upper interlayer insulation layer, the upper base, the middle interlayer insulation layer, the lower base, and the lower interlayer insulation layer; Remove the lower sacrificial layer, the upper sacrificial layer, and the sacrificial pad to expose the support structure and the contact insulation pattern; A barrier insulating layer is formed along the surface of the lower gate region where the lower sacrificial layer has been removed and the upper gate region where the upper sacrificial layer and the sacrificial pad have been removed; And the central region of each of the lower gate region and the upper gate region is filled with a conductive pattern.

27. The method according to request item 26, further comprising the following steps: The contact insulation pattern and a portion of the barrier insulation layer are exposed by removing the support structure. Remove the exposed portion of the barrier insulation layer to expose the edge portion of the conductive pattern that overlaps with the contact insulation pattern; The area where the support structure has been removed is filled with conductive gate contacts to make contact with the edge of the conductive pattern.

28. A method of manufacturing a semiconductor memory device, the method comprising the steps of: forming a lower stacked structure in which horizontal layers and protective layers are stacked; isolating the lower stacked structure into a preliminary horizontal pattern and a preliminary contact structure; forming a preliminary stepped stacked structure by stacking a lower interlayer insulating layer, a lower sacrificial layer, an intermediate interlayer insulating layer, an upper sacrificial layer, and an upper interlayer insulating layer over the preliminary horizontal pattern and the preliminary contact structure; forming a support structure through the preliminary stepped stacked structure, the support structure extending into the interior of the preliminary contact structure; replacing each of the lower sacrificial layer and the upper sacrificial layer with a conductive pattern; and replacing the horizontal layer and the support structure of the preliminary contact structure with a conductive gate contact.

29. The method according to claim 28, wherein, The protective layer of the lower stacked structure is retained in the conductive gate contact portion.

30. The method according to claim 28, wherein, The lower sacrificial layer includes a lower base portion located between the lower interlayer insulation layer and the intermediate interlayer insulation layer, and a lower edge portion protruding further to the side from the lower base portion relative to the intermediate interlayer insulation layer, wherein the upper sacrificial layer includes an upper base portion located between the intermediate interlayer insulation layer and the upper interlayer insulation layer, and an upper edge portion protruding further to the side from the upper base portion relative to the upper interlayer insulation layer.

31. The method according to claim 30, wherein, The lower edge portion is formed to be thinner than the lower base portion, and the upper edge portion is formed to be thinner than the upper base portion.

32. The method according to claim 31, wherein, The steps of forming the support structure include the following steps: forming a contact hole that penetrates the upper edge portion, the intermediate interlayer insulation layer, the lower base portion, and the lower interlayer insulation layer; removing a portion of the lower base portion and the upper edge portion through the contact hole; A sacrificial pad is formed to fill the first recessed area of ​​the upper edge; a contact insulating pattern is formed to fill the second recessed area of ​​the lower base; a memory layer is formed along the sidewall of the contact hole to cover the sidewall of each of the sacrificial pad and the contact insulating pattern; a channel layer is formed along the surface of the memory layer; and a dummy core insulating pattern is formed on the channel layer.

33. The method according to claim 32, wherein, The step of replacing each of the lower sacrificial layer and the upper sacrificial layer with the conductive pattern includes the following steps: forming an upper protective layer covering the support structure such that a gap is defined in the contact hole; A slit is formed, the slit penetrating the upper protective layer, the upper interlayer insulation layer, the upper base of the upper sacrificial layer, the intermediate interlayer insulation layer, the lower base of the lower sacrificial layer, and the lower interlayer insulation layer; The lower sacrificial layer, the upper sacrificial layer, and the sacrificial pad are removed through the slit to expose the support structure and the contact insulation pattern; A barrier insulating layer is formed along the surface of each of the lower gate region where the lower sacrificial layer has been removed and the upper gate region where the upper sacrificial layer and the sacrificial pad have been removed; And the central region of each of the lower gate region and the upper gate region is filled with a first conductive material.

34. The method according to request item 33, wherein, The step of replacing the horizontal layer and the support structure of the initial contact structure with the conductive gate contact includes the following steps: exposing the contact insulation pattern and a portion of the barrier insulation layer by removing the support structure; Remove a portion of the barrier insulating layer to expose the edge of the conductive pattern that overlaps with the contact insulating pattern; The area where the support structure has been removed is filled with a second conductive material to contact the edge of the conductive pattern.

35. The method according to claim 30, the method further comprising the step of forming a first sacrificial pad on the upper edge.

36. The method according to request item 35, wherein, The steps of forming the support structure include: forming a contact hole penetrating the first sacrificial pad, the upper edge, the intermediate interlayer insulation layer, the upper base, and the lower interlayer insulation layer; removing a portion of the lower base, the upper edge, and the first sacrificial pad through the contact hole; forming a second sacrificial pad to fill the first recessed area where the upper edge and the first sacrificial pad have been removed; forming a contact insulation pattern to fill the second recessed area where the portion of the lower base has been removed; forming a memory layer along the sidewall of the contact hole to cover the sidewall of each of the second sacrificial pad and the contact insulation pattern; forming a channel layer along the surface of the memory layer; and forming a dummy core insulation pattern on the channel layer.

37. The method according to claim 36, wherein, The step of replacing each of the lower sacrificial layer and the upper sacrificial layer with the conductive pattern includes the following steps: forming an upper protective layer covering the support structure such that a gap is defined in the contact hole; Remove the lower sacrificial layer, the upper sacrificial layer, and the second sacrificial pad to expose the support structure and the contact insulation pattern; A barrier insulating layer is formed along the surface of each of the lower gate region where the lower sacrificial layer has been removed and the upper gate region where the upper sacrificial layer and the second sacrificial pad have been removed; And the central region of each of the lower gate region and the upper gate region is filled with a first conductive material.

38. The method according to claim 30, the method further comprising the steps of: forming a channel hole penetrating the upper interlayer insulating layer, the upper base, the intermediate interlayer insulating layer, the lower base, and the lower interlayer insulating layer, the channel hole extending into the interior of the horizontal layer of the preliminary horizontal pattern; forming a memory layer along the surface of the channel hole; A channel layer is formed along the surface of the memory layer; the central region of the channel hole is filled using a core insulating pattern and a capping pattern on the core insulating pattern; a slit is formed through the initial stepped stack structure, the slit exposing the horizontal layer of the initial horizontal pattern; The horizontal layer of the initial horizontal pattern is removed through the slit to expose a portion of the memory layer; Remove the exposed portion of the memory layer to expose a portion of the channel layer; And the region where the horizontal layer has been removed is filled with a doped semiconductor layer to make contact with the channel layer.

39. A method of manufacturing a semiconductor memory device, the method comprising the steps of: forming a lower stacked structure in which horizontal layers and protective layers are stacked; isolating the lower stacked structure into a preliminary horizontal pattern and a preliminary contact structure; forming a lower contact portion through the preliminary contact structure; forming a preliminary stepped stacked structure above the lower structure including the preliminary horizontal pattern, the preliminary contact structure, and the lower contact portion, comprising a plurality of alternately stacked interlayer insulating layers and a plurality of sacrificial layers; etching the preliminary stepped stacked structure to form slits through the preliminary stepped stacked structure overlapping with the horizontal layers and contact holes through the preliminary stepped stacked structure overlapping with the lower contact portion; forming a support structure disposed in the contact holes, the support structure extending between the interlayer insulating layers; replacing each of the sacrificial layers with a conductive pattern; and replacing a portion of the support structure in the contact holes with a conductive gate contact portion connected to the lower contact portion.

40. The method according to claim 39, wherein, One of the plurality of sacrificial layers includes an edge portion that overlaps with the lower contact portion and a base portion that extends from the edge portion toward the unit region of the initial stepped stacked structure and has a thickness different from that of the edge portion, wherein the contact hole penetrates the edge portion.

41. The method according to request item 40, wherein, The steps of forming the support structure include: forming a first upper protective layer that overlaps with the unit region of the initial stepped stacked structure to define a gap in the slit; removing a portion of the lower sacrificial layer overlapping the edge and the edge portion through the contact hole; and filling the first recessed area of ​​the removed edge portion with a sacrificial pad. A contact insulating layer is formed along the sidewall of the contact hole to fill the second recessed area where a portion of the lower sacrificial layer has been removed; and an inner liner layer is formed on the contact insulating layer.

42. The method according to claim 41, wherein, The step of replacing each of the sacrificial layers with the conductive pattern includes the following steps: forming a second upper protective layer that overlaps with the contact area of ​​the initial stepped stack structure; Remove a portion of the first upper protective layer to open the slit; The plurality of sacrificial layers and the sacrificial pad are removed through the slit; And each of the regions where the plurality of sacrificial layers and the sacrificial pads have been removed is filled with a conductive material.

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