Digitally controlled oscillator insensitive to changes in process, voltage, temperature and digital phase locked loop including same

Abstract

A digitally controlled oscillator (DCO) includes: a current mirror configured to generate a supply current in response to a bias voltage matching a reference current; a variable resistor connected to the current mirror via a first node that outputs the reference current and configured to provide variable resistance in response to a first control signal; an oscillation circuit connected to the current mirror via a second node that outputs the supply current and configured to generate an oscillation signal in response to the supply current; and a feedback circuit configured to control the bias voltage in relation to at least one of the voltage at the first node and the voltage at the second node.

Description

Technical Field

[0001] The present inventive concept relates to a digitally controlled oscillator (DCO), and more particularly, to a DCO including a current mirror. [Cross-reference to related applications]

[0002] This application claims the priority of Korean Patent Application No. 10-2021-0069533, filed with the Korean Intellectual Property Office on May 28, 2021, the entire subject matter of which is incorporated herein by reference.

Background Art

[0003] In integrated circuits, various oscillation signals (e.g., clock signals) can be used in various ways. For example, operations related to digital signals in an integrated circuit can be synchronized with one or more oscillation signals. Oscillation signals can also be used in different ways to process analog signals (e.g., radio frequency (RF) signals). To generate oscillation signals, various digital circuits (e.g., a phase locked loop (PLL)) can be used. Some of these digital circuits use a DCO to ensure appropriate performance characteristics.

[0004] However, the DCO itself is not without problems. For example, due to certain structural aspects, the DCO can exhibit variable performance in response to changes in process, voltage, and / or temperature (PVT) (hereinafter referred to singly or collectively as PVT). And such variability can cause problems such as frequency fluctuations of the oscillation signal.

Summary of the Invention

[0005] The present inventive concept provides a DCO capable of stably providing an oscillation signal having a desired frequency, which is relatively insensitive to changes in PVT.

[0006] According to aspects of the present invention concept, a digitally controlled oscillator (DCO) is provided, the DCO including: a current mirror configured to generate a supply current in response to matching a bias voltage with a reference current; a variable resistor connected to the current mirror via a first node outputting a reference current and configured to provide a variable resistance in response to a first control signal; an oscillation circuit connected to the current mirror via a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current; and a feedback circuit configured to control the bias voltage in relation to at least one of the voltage at the first node and the voltage at the second node.

[0007] According to aspects of the present invention concept, a digitally controlled oscillator (DCO) is provided, the DCO including: a current mirror including a third node and configured to generate a supply current in response to matching a bias voltage with a reference current; a variable resistor connected to the current mirror via a first node outputting a reference current and configured to provide a variable resistance; an oscillation circuit connected to the current mirror via a second node outputting the supply current and configured to receive the supply current; and an amplifier including a first input, a second input, and an output, the first input connected to the first node to receive the voltage at the first node, the second input connected to the second node to receive the voltage at the second node, the output connected to the third node, wherein the amplifier is configured to generate a feedback in response to a difference between the voltage at the first node and the voltage at the second node and provide the feedback to the third node.

[0008] According to aspects of the present invention concept, a digital phase-locked loop (PLL) is provided, the digital PLL including: a frequency divider configured to divide a clock signal and output a divided signal; a time-to-digital converter configured to compare the divided signal with a reference signal and output a comparison signal; a digital loop filter configured to output a control signal in response to the comparison signal; and a digitally controlled oscillator (DCO) configured to output a clock signal, the frequency of the clock signal being adjusted in response to the control signal. The DCO includes: a current mirror including a third node and configured to generate a supply current in response to matching a bias voltage with a reference current; a variable resistor connected to the current mirror via a first node; an oscillation circuit connected to the current mirror via a second node outputting the supply current; and an amplifier including a first input terminal connected to the first node, a second input terminal connected to the second node, and an output terminal connected to the third node.

Embodiments

[0010] Throughout the written description and the drawings, the same reference numerals and labels are used to refer to the same or similar elements, components, and / or method steps.

[0011] FIG. 1 is a block diagram showing a digital controlled oscillator (DCO) 10 according to an embodiment of the inventive concept. In some embodiments, the DCO 10 may be implemented as an integrated circuit (IC) manufactured according to a semiconductor process and may include at least one semiconductor package and a board (e.g., a printed circuit board (PCB) or a PCB) on which the semiconductor package is mounted.

[0012] The DCO 10 may generate an output signal OUT that oscillates at a frequency that is adjusted (or defined) according to a digital control signal CTR including at least one bit. As shown in FIG. 1, the DCO 10 may include a current mirror 11, a feedback circuit 12, a reference current source 13, and an oscillation circuit 14. The current mirror 11 may be connected to the feedback circuit 12, the reference current source 13, and the oscillation circuit 14 and may generate a supply current ISUP in response to (based on) a reference current IREF. The reference current source 13 may draw the reference current IREF from the current mirror 11, and the oscillation circuit 14 may generate an output signal OUT whose frequency changes (varies) according to the supply current ISUP. The level (or magnitude) of the reference current IREF and / or the supply current ISUP may change according to the control signal CTR. Accordingly, the frequency of the output signal OUT may be adjusted in relation to the control signal CTR. In this regard, the term “output signal OUT” is generally used to refer to an oscillation signal (e.g., a clock signal or a similar signal), where the frequency of the output signal OUT may be referred to as the “output frequency”.

[0013] Since there are often minute defects or variations in the semiconductor process used to manufacture an IC, a reduction in the power supply voltage and / or an increase in the leakage current may occur. Generally, it is difficult to design an analog circuit that exhibits acceptable performance for the generation of an oscillation signal. Accordingly, digital circuits have largely replaced analog circuits in this regard. In fact, one or more digital circuits for generating corresponding oscillation signals for different purposes may be significantly present in contemporary and emerging integrated circuits. For example, a digital phase locked loop (PLL) may be used to replace an analog charge pump PLL (CPPLL) circuit. However, the performance of a digital PLL may depend on the performance of an associated DCO.

[0014] Recognizing this fact and referring to FIG. 1, the bias voltage of the current mirror 11 can change according to the change (or variation) of PVT, which can cause the reference current IREF and / or the supply current ISUP to change, thereby affecting the stability of the output frequency of the output signal OUT. Such instability of the output frequency can have a negative impact on the performance of the DCO 10. Therefore, the stability of the bias voltage of the current mirror 11 is a factor that affects the generation of the supply current ISUP (see, for example, FIGS. 3A, 3B, and 4).

[0015] In this regard, the feedback circuit 12 can be used to suppress the change in the bias voltage of the current mirror 11 caused by the change in PVT. In some embodiments, the feedback circuit 12 can be connected to the current mirror 11 via the first node N1 and the second node N2. The first node N1 can be the node to which the current mirror 11 and the reference current source 13 are connected, and the second node N2 can be the node to which the current mirror 11 and the oscillation circuit 14 are connected. The feedback circuit 12 receives the first voltage present at the first node N1 and the second voltage present at the second node N2. The feedback circuit 12 can generate a feedback FB based on the first voltage and the second voltage. Then the feedback FB can be applied to the current mirror 11 to control the bias voltage of the current mirror 11. For example, the feedback FB can suppress the change in the bias voltage caused by the change in PVT. That is, the feedback FB can be used as negative feedback regarding the bias voltage applied to the current mirror 11.

[0016] Regarding FIG. 1, embodiments have been described in which the bias voltage of the current mirror 11 changes in relation to the change in PVT. However, the inventive concept is not limited thereto, and other embodiments of the inventive concept can also apply other parameters (such as the power supply voltage VDD) that change according to the change in PVT.

[0017] Therefore, the DCO 10 in FIG. 1 uses the negative feedback provided by the feedback circuit 12 to compensate for the change in the bias voltage of the current mirror 11 caused by the change in PVT, thereby generating an output signal OUT that is relatively insensitive to the change in PVT. More importantly, the DCO 10 does not require additional circuitry (consuming additional power) other than the feedback circuit 12, thereby ensuring that the DCO 10 operates with relatively low power consumption.

[0018] FIG. 2 is a flowchart showing a method of operating a DCO according to an embodiment of the inventive concept.

[0019] Referring to FIG. 2, the DCO can detect the change in the bias voltage of the current mirror according to the change in PVT (S100). In some embodiments, the DCO can detect the change in the bias voltage by monitoring the voltage of the node that provides (or outputs) the reference current generated by the current mirror (e.g., change detection). Then the DCO can generate a negative feedback that suppresses (or compensates for) the change in the bias voltage based on the change detection (S110). Then the DCO can adjust the bias voltage by applying the negative feedback to the current mirror.

[0020] FIGS. 3A and 3B are circuit diagrams showing corresponding comparative example DCOs.

[0021] That is, FIG. 3A shows a DCO 20a in which the frequency of the output signal OUT is adjusted according to the resistance of the variable resistor VR21, and FIG. 3B shows a DCO 20b including a β multiplier reference circuit (BMR).

[0022] Referring to FIG. 3A, the DCO 20a includes transistors T21 and T22 that form a current mirror, where the variable resistor VR21 determines the magnitude of the reference current IREF, and the oscillation circuit OC21 generates the output signal OUT according to the supply current ISUP. The current mirror (i.e., transistors T21 and T22) can be P-channel field-effect transistors (FETs) and share the bias voltage VBIAS. In some embodiments, the FET can be a Metal-Oxide-Semiconductor FET (MOSFET). As the resistance of the variable resistor VR21 decreases, the reference current IREF increases - thereby, the frequency of the output signal OUT increases as the supply current ISUP increases. And as the resistance value of the variable resistor VR21 increases, the reference current IREF decreases - thereby, the frequency of the output signal OUT decreases as the supply current ISUP decreases.

[0023] The DCO 20a in FIG. 3A is sensitive to changes in the power supply voltage VDD or the bias voltage VBIAS. That is, the power supply voltage VDD or the bias voltage VBIAS can change according to the change in PVT, and the reference current IREF can change according to the change in the voltage at either end of the variable resistor VR21. Therefore, the frequency of the output signal OUT will change due to the change in the power supply voltage VDD.

[0024] Referring to FIG. 3B and contrary to the embodiment of FIG. 3A, the DCO 20b may employ the BMR 21. Referring to FIG. 3B, the DCO 20b may include an oscillator circuit OC22 and a P-channel transistor T24 that supplies a supply current ISUP to the oscillator circuit OC22.

[0025] The BMR 21 may include two P-channel transistors T25 and T23, two N-channel transistors T27 and T26, and a variable resistor VR32. When the reference current IREF increases due to changes in PVT, the voltage at the source of the N-channel transistor T26 can be increased by the variable resistor VR32. Thereby, the gate-source voltage of the N-channel transistor T26 can be reduced. The reduced gate-source voltage can reduce the drain current of the N-channel transistor T26, i.e., the reference current IREF. Therefore, the BMR 21 can provide negative feedback.

[0026] The reference current IREF can be stably held by the BMR 21, but the BMR 21 may exhibit poor performance characteristics (e.g., high noise sensitivity and significant power consumption). For example, when the supply current ISUP is obtained by amplifying a relatively small reference current IREF according to the ratio of the sizes of two P-channel transistors T23 and T24 forming a current mirror, the noise caused by the BMR 21 can also be amplified, and thus, the output signal OUT generated by the oscillator circuit OC22 may be unstable. In addition, when a relatively large reference current IREF is employed, the DCO 20b may have a relatively high power consumption due to the BMR 21.

[0027] When compared with the DCO 20a of FIG. 3A and the DCO 20b of FIG. 3B, the DCO according to an embodiment of the inventive concept operates at a relatively low power consumption and is still capable of generating an output signal that is very insensitive to changes in PVT.

[0028] FIG. 4 is a circuit diagram showing a DCO 30 according to an embodiment of the inventive concept. Referring to FIG. 4, the DCO 30 may include a current mirror 31, a feedback circuit 32, a variable resistor 33, and an oscillator circuit 34.

[0029] The current mirror 31 can be used to generate a supply current ISUP based on matching the bias voltage VBIAS with the reference current IREF, and supply the supply current ISUP to the oscillation circuit 34. The current mirror 31 can include a first transistor T31 and a second transistor T32. The first transistor T31 can generate the bias voltage VBIAS based on the reference current IREF, and the second transistor T32 can generate the supply current ISUP based on the bias voltage VBIAS. The ratio of the supply current ISUP to the reference current IREF can be determined according to the ratio between the size (e.g., channel width) of the second transistor T32 and the size of the first transistor T31.

[0030] One end of the variable resistor 33 can be connected to the current mirror 31 via the first node N1, and the other end of the variable resistor 33 can be connected to ground. Similar to the reference current source 13 in FIG. 1, the variable resistor 33 in FIG. 4 can provide a variable resistance (RVAR) to the DCO 30. In some embodiments, the variable resistor 33 can include a plurality of resistors and a plurality of switches, where each of the switches can be selectively turned on / off according to one or more bits of a control signal to electrically connect / disconnect the corresponding resistor associated with the variable resistor 33. The reference current IREF can pass through the variable resistor 33, and the voltage present at the first node N1 is the reference voltage, and the magnitude of the reference voltage can be determined according to the magnitude of the reference current IREF and the resistance of the variable resistance RVAR provided by the variable resistor 33. A possible example of the variable resistor 33 will be described in more detail with reference to FIG. 11A below.

[0031] The oscillation circuit 34 can receive the supply current ISUP via the second node N2 and generate an output signal OUT whose output frequency changes according to the supply current ISUP. That is, the oscillation circuit 34 can receive the supply current ISUP such that a variable voltage exists at the second node N2. Possible examples of the oscillation circuit 33 will be described in more detail with reference to FIGS. 5A and 5B below.

[0032] In some embodiments, the feedback circuit 32 may include an amplifier AMP. The amplifier AMP may include: a first input terminal connected to a first node N1 that receives a reference current IREF; a second input terminal connected to a second node N2 that receives a supply current ISUP; and an output terminal connected to a third node N3 (e.g., an internal node associated with the current mirror 31). The first node N1 may be connected to a variable resistor 33 such that the voltage present at the first node N1 may vary sensitively according to the magnitude of the reference current IREF. The second node N2 may be connected to an oscillation circuit 34 such that the voltage present at the second node N2 may vary insensitively according to the magnitude of the supply current ISUP. Thereby, a change in the difference between the voltage at the first node N1 and the voltage at the second node N2 may indicate a change in the reference current IREF, and thus may indicate a change in the bias voltage VBIAS.

[0033] In some embodiments, the amplifier AMP may compare the voltage at the first node N1 with the voltage at the second node N2 to generate feedback based on the comparison result. That is, the amplifier AMP may amplify the difference between the voltage at the first node N1 and the voltage at the second node N2, and then output the amplified voltage as feedback. The amplification ratio of the amplifier AMP may be appropriately set in relation to the level of the bias voltage VBIAS. For example, a calibration operation associated with the DCO 30 may be used to set the amplification ratio of the amplifier AMP.

[0034] In some embodiments, the amplifier AMP may provide feedback to the third node N3 via the output terminal. The amplifier AMP may reduce the change in the bias voltage VBIAS associated with the change in PVT by providing feedback to the current mirror 31. Therefore, even when PVT changes, the current mirror 31 may also generate a constant reference current IREF and / or supply current ISUP.

[0035] For example, when the bias voltage VBIAS decreases due to a change in PVT, the amplifier AMP may generate feedback for increasing the bias voltage VBIAS in response to an increase in the voltage at the first node N1, and when the bias voltage VBIAS increases due to a change in PVT, the amplifier AMP may generate feedback for decreasing the bias voltage VBIAS in response to a decrease in the voltage at the first node N1.

[0036] In this way, for example, compared with the DCO 20a of FIG. 2A and the DCO 20b of FIG. 2B, the DCO 30 may generate an output signal OUT that is insensitive to changes in PVT. In addition, the DCO 30 does not need to include an additional path for the reference current IREF to flow through, thereby reducing power consumption.

[0037] FIG. 5A is a circuit diagram showing an example of the oscillator circuit 40a and the oscillator circuit 40b according to an embodiment of the concept of the present invention, and FIG. 5B is a block diagram showing an example of the oscillator circuit 40a and the oscillator circuit 40b according to an embodiment of the concept of the present invention. Here, each of the oscillator circuit 40a in FIG. 5A and the oscillator circuit 40b in FIG. 5B can be used to generate an output signal OUT whose output frequency changes according to the supply current ISUP.

[0038] Referring to FIG. 5A, the oscillator circuit 40a may include a ring oscillator. As shown in FIG. 5A, the oscillator circuit 40a may include a series of inverters, which may include (for example) INV1, INV2, INV3, INV4, and INV5 (hereinafter collectively referred to as "INV1 to INV5"), and each of the inverters INV1 to INV5 receives the supply current ISUP. Each of the inverters INV1 to INV5 may provide a delay that changes according to the supply current ISUP. Therefore, the output frequency of the output signal OUT can change according to the supply current ISUP.

[0039] Referring to FIG. 5B, the oscillator circuit 40b may include a delay line 41 (for example, a delay line of a delay locked loop (DLL)). As shown in FIG. 5B, the delay line 41 may include a series of delay cells (for example, D1, D2,..., Dn, where "n" is an integer greater than 2). Each of the delay cells D1, D2,..., Dn may receive the supply current ISUP, such that each of the delay cells D1, D2,..., Dn can provide a delay that changes according to the supply current ISUP. That is, the second (or output) signal SIG2 can be variably delayed in relation to the first (or input) signal SIG1.

[0040] FIG. 6 is a block diagram showing a DCO 50 according to an embodiment of the concept of the present invention. As shown in FIG. 6, the DCO 50 may include a current mirror 51, a feedback circuit 52, a reference current source 53, an oscillator circuit 54, and a calibration circuit 55. Only the substantial differences between the embodiment of FIG. 6 and the description provided previously related to FIG. 1 will be emphasized.

[0041] Here, the voltage at the first node N1 can change according to the change in temperature. In some embodiments, this can be attributed to the fact that the reference current source 53 is implemented similarly to the variable resistor 33 in FIG. 4, where the resistance RVAR of the variable resistor 33 may be affected by temperature. Thereby, the change in the voltage at the first node N1 caused by the change in temperature can make the output frequency of the output signal OUT unstable.

[0042] Referring to FIG. 6, the calibration circuit 55 may be connected in parallel with the reference current source 53 between the first node N1 and ground. In some embodiments, the calibration circuit 55 may generate a calibration current that substantially eliminates (or compensates for) the voltage change at the first node N1 caused by a change in temperature. That is, the calibration circuit 55 may adjust the magnitude of the calibration current drawn from the first node N1 to ensure that the voltage at the first node N1 is substantially insensitive to changes in temperature.

[0043] In this way, the DCO 50 of FIG. 6 may provide an output signal OUT with a stable output frequency by using the calibration circuit 55 to compensate for the voltage change at the first node N1, such that the output frequency is insensitive to changes in temperature.

[0044] FIG. 7 is a flowchart showing a method of operating a DCO according to an embodiment of the inventive concept.

[0045] Referring to FIG. 7, the DCO may generate a calibration current corresponding to the change in voltage present at a first node between the current mirror and the reference current source due to a change in temperature (S200). In some embodiments, the calibration current may be the current drawn from the first node and may increase in response to an increase in the voltage at the first node, or may decrease in response to a decrease in the voltage at the first node. Then, the DCO may use the calibration current to adjust the voltage at the first node (S210). In this way, the DCO may compensate for the change in voltage at the first node to provide an output signal OUT whose output frequency is substantially insensitive to changes in temperature.

[0046] FIG. 8 is a block diagram showing a DCO 60 according to an embodiment of the inventive concept. The DCO 60 may include a current mirror 61, a feedback circuit 62, a variable resistor 63, an oscillation circuit 64, and a calibration circuit 65. Only the substantial differences between the embodiment of FIG. 8 and the descriptions provided previously related to FIGS. 1 and 6 will be emphasized.

[0047] Referring to FIG. 8, the calibration circuit 65 may include a calibration current source CS_PTAT connected in parallel with the variable resistor 63 between the first node N1 and ground. In some embodiments in this regard, the variable resistor 63 may be characterized by a Proportional-To-Absolute-Temperature (PTAT) in which the resistance increases as the temperature increases. Thus, as the temperature increases, the voltage at the first node N1 (e.g., the voltage applied to the variable resistor 63) may increase. Thereby, the calibration current source CS_PTAT can generate an increasing calibration current in response to the increasing voltage at the first node N1, which reduces the voltage at the first node N1 by drawing an increasing calibration current from the first node N1. In addition, as the temperature decreases, the voltage at the first node N1 may decrease. Thereby, the calibration current source CS_PTAT can generate a decreasing calibration current in response to the decreasing voltage at the first node N1, and increases the voltage at the first node N1 by drawing a decreasing calibration current from the first node N1.

[0048] In some embodiments, the calibration current source CS_PTAT may have the same PTAT characteristics as the variable resistor 63. That is, the calibration current source CS_PTAT can generate an increasing calibration current as the temperature increases.

[0049] In some other embodiments, assuming the variable resistor 63 is characterized by Complementary-To-Absolute-Temperature (CTAT) characteristics, the calibration current source CS_PTAT may have CTAT characteristics.

[0050] FIGS. 9A and 9B are corresponding block diagrams showing different variants of the DCO 70 according to an embodiment of the inventive concept. Only the substantial differences between the embodiments of FIGS. 9A and 9B and the descriptions provided previously related to FIGS. 1 and 6 will be emphasized.

[0051] Referring to FIG. 9A, the DCO 70 can receive a control signal CTR including a first control signal CTR1 and a second control signal CTR2, and generate an output signal OUT whose output frequency changes according to the control signal CTR. The DCO 70 in FIG. 9A can include a current mirror 71, a feedback circuit 72, a reference current source 73, and an oscillation circuit 74. The first control signal CTR1 can include at least one bit and can be jointly provided to the current mirror 71 and the reference current source 73. In addition, the second control signal CTR2 including at least one bit can be provided to the current mirror 71. The current mirror 71 and the reference current source 73 can determine the magnitude of the reference current IREF based on the first control signal CTR1. In addition, the current mirror 71 can determine the magnitude of the supply current ISUP based on the second control signal CTR2 and the reference current IREF.

[0052] In some embodiments, the first control signal CTR1 can be used to roughly adjust the frequency of the output signal OUT, while the second control signal CTR2 can be used to finely adjust the frequency of the output signal OUT. As will be described in more detail below with reference to FIG. 10, the first control signal CTR1 can be provided not only to the reference current source 73 but also to the current mirror 71, such that the reference current IREF can increase / decrease according to the first control signal CTR1 with a convex function rather than a linearly increasing / decreasing function.

[0053] Referring to FIG. 9B, the first control signal CTR1 can be jointly provided to the current mirror 71 and the reference current source 73, the second control signal CTR2 can be provided to the current mirror 71, and a third control signal CTR3 including at least one bit can be provided to the calibration circuit 75. The calibration circuit 75 can determine the magnitude of the calibration current based on the third control signal CTR3.

[0054] In some embodiments, the DCO 70 can receive a control signal CTR with a specific value to generate an output signal OUT with a desired frequency. In addition, the DCO 70 can use the feedback circuit 72 to suppress the change in the bias voltage of the current mirror 71 according to the change in PVT, and use the calibration circuit 75 to suppress the change in the voltage of the first node N1 according to the change in temperature.

[0055] FIG. 10 is a block diagram showing the DCO 80 according to an embodiment of the inventive concept. Similar to the description given with FIGS. 9A and 9B, the DCO 80 may receive a first control signal CTR1, a second control signal CTR2, and a third control signal CTR3, and generate an output signal OUT whose frequency varies according to the first control signal CTR1 to the third control signal CTR3. As shown in FIG. 10, the DCO 80 may include a current mirror 81, a feedback circuit 82, a variable resistor 83, an oscillation circuit 84, and a calibration circuit 85. The feedback circuit 82 according to an embodiment may include an amplifier AMP, and the calibration circuit 85 may include a calibration current source CS_PTAT.

[0056] Referring to FIG. 10, the current mirror 81 may receive the first control signal CTR1 together with the variable resistor 83, and may receive the second control signal CTR2 alone. The magnitude of the first reference current IREF may be determined according to the first control signal CTR1, and the magnitude of the supply current ISUP may be determined according to the reference current IREF and the second control signal CTR2. As shown in FIG. 10, the current mirror 81 may include a bias circuit 81_1 and a current source circuit 81_2.

[0057] The bias circuit 81_1 may receive the first control signal CTR1, provide the reference current IREF from the power supply voltage VDD, and generate a bias voltage VBIAS based on the first control signal CTR1 and the reference current IREF. The bias circuit 81_1 may provide the bias voltage VBIAS to the current source circuit 81_2 via a third node N3.

[0058] For example, when the current source circuit 81_2 outputs a decreasing supply current ISUP in response to an increase in the bias voltage VBIAS, the bias circuit 81_1 may decrease the bias voltage VBIAS in response to the first control signal CTR1 that decreases the resistance RVAR of the variable resistor 83. In addition, the bias circuit 81_1 may increase the bias voltage VBIAS in response to the first control signal CTR1 that increases the resistance RVAR of the variable resistor 83. An example of the bias circuit 81_1 will be described later with reference to FIG. 11B.

[0059] The current source circuit 81_2 may generate a supply current ISUP based on the bias voltage VBIAS and the second control signal CTR2. For example, the current source circuit 81_2 may increase the supply current ISUP in response to a decreasing bias voltage VBIAS. In some embodiments, the current source circuit 81_2 may generate a supply current ISUP whose magnitude is proportional or inversely proportional to the value of the second control signal CTR2. An example of the current source circuit 81_2 will be described later with reference to FIG. 11C.

[0060] The variable resistor 83 can provide a resistance RVAR that varies according to a first control signal CTR1 including at least one bit. In some embodiments, the variable resistor 83 can provide a resistance RVAR that decreases as the value of the first control signal CTR1 increases. For example, the resistance RVAR of the variable resistor 83 can be inversely proportional to the value of the control signal CTR1. When the resistance RVAR of the variable resistor 83 decreases according to the first control signal CTR1, the reference current IREF can increase, and when the resistance RVAR of the variable resistor 83 increases according to the first control signal CTR1, the reference current IREF can decrease. An example of the variable resistor 83 will be described later with reference to FIG. 11A. In addition, the calibration circuit 85 can provide a calibration current that varies according to a third control signal CTR3 including at least one bit.

[0061] FIGS. 11A, 11B, and 11C are circuit diagrams respectively showing the variable resistor 83, the bias circuit 81_1, and the current source circuit 81_2 of FIG. 10 according to embodiments of the inventive concept. In FIGS. 11A and 11B, the first control signal CTR1 includes five (5) bits, but this is only a selected example. In addition, it is assumed that a bit value of "1" corresponds to a "high" level voltage, and a bit value of "0" corresponds to a "low" level voltage.

[0062] Referring to FIG. 11A, the variable resistor 91 can include N-channel transistors respectively connected in series with corresponding resistors. Here, the gate of each of the N-channel transistors can receive one bit of the first control signal CTR1. When one bit of the first control signal CTR1 is "1", the N-channel transistor is turned on and the corresponding resistor connected in series with this N-channel transistor is electrically connected between the opposite ends of the variable resistor 91. With this configuration, the variable resistor 91 can selectively provide a unit resistance (RUNIT) multiplied by 21-k between the current mirror and the ground voltage according to the k-th bit CTR1[k] of the first control signal CTR1, where "k" is a positive integer. For example, when the k-th bit CTR1[k] of the first control signal CTR1 is "1", a resistor with a resistance of "RUNIT / 2k-1" can be electrically connected to the two ends of the variable resistor 91. For example, when the second bit CTR1[2] of the first control signal CTR1 is "1", a resistor with a resistance of "RUNIT / 2" can be electrically connected to the two ends of the variable resistor 91. Therefore, the resistance of the variable resistor 91 in FIG. 11A can be inversely proportional to the value of the first control signal CTR1.

[0063] Referring to FIG. 11B, the bias circuit 92 may include an upper P-channel transistor and a lower P-channel transistor connected in series. The lower P-channel transistor may include a gate that receives one bit of the first control signal CTR1, and the upper P-channel transistor may include a gate to which a bias voltage VBIAS is applied. When one bit of the first control signal CTR1 is "0", the P-channel transistor may be turned on, and the P-channel transistor connected in series with the turned-on P-channel transistor may be enabled.

[0064] The bias circuit 92 may selectively enable / disable P-channel transistors of 2k-1 times the unit size according to the k-th bit CTR1[k] of the first control signal CTR1. The enabled P-channel transistors may transfer at least a part of the reference current IREF, and may contribute to the generation of the bias voltage VBIAS. For example, when the k-th bit CTR1[k] of the first control signal CTR1 is "0", P-channel transistors of size "2k-1·X1" may be enabled. The size of the P-channel transistor may correspond to the width of the P-channel, and the larger the size of the P-channel transistor, the stronger the current driving ability. For example, when the second bit CTR1[2] of the first control signal CTR1 is "0", P-channel transistors of size "X2" may be enabled.

[0065] Further referring to FIG. 11C, the current source circuit 93 may generate a supply current ISUP based on the bias voltage VBIAS and the second control signal CTR2. The current source circuit 93 may receive the inverted second control signal / CTR2, and the inverted second control signal / CTR2 is shown to include 11 bits, but it should be understood that embodiments of the inventive concept are not limited thereto.

[0066] The current source circuit 93 may enable / disable P-channel transistors of 2k times the unit size according to the k-th bit CTR2[k] of the second control signal CTR2. The enabled P-channel transistors may transfer at least a part of the supply current ISUP according to the bias voltage VBIAS. For example, when the k-th bit CTR2[k] of the second control signal CTR2 is "1", the k-th bit ( / CTR2[k]) of the inverted second control signal / CTR2 may be "0", and P-channel transistors of size "2k·X1" may be enabled.

[0067] FIG. 12 is a block diagram showing a digital PLL 1000 according to an embodiment of the inventive concept.

[0068] Referring to FIG. 12, the digital PLL 1000 may include a time-to-digital converter 1010, a digital loop filter 1020, a DCO 1030, and a frequency divider 1040.

[0069] The frequency divider 1040 can divide the output signal FOUT received from the DCO 1030. As an example, the frequency divider 1040 can be a multi - coefficient divider. The time - to - digital converter 1010 can receive the divided signal FDIV from the frequency divider 1040 and receive an externally provided reference frequency signal FREF. The time - to - digital converter 1010 can compare the phase of the frequency - divided signal FDIV with the phase of the reference frequency signal FREF and generate a comparison signal RS indicating the comparison result. The comparison signal RS is a signal including at least one bit and can indicate the phase difference between the divided signal FDIV and the reference frequency signal FREF. The digital loop filter 1020 can generate a control signal CNTL including a phase error signal between the divided signal FDIV and the reference frequency signal FREF based on the comparison signal RS. The DCO 1030 can generate the output signal FOUT based on the control signal CNTL.

[0070] Consistent with the foregoing, the DCO 1030 of FIG. 12 can use a feedback circuit to generate negative feedback regarding the change in the bias voltage of the current mirror caused by the change in PVT, thereby suppressing the change in the bias voltage. In some embodiments, the DCO 1030 can further use a calibration circuit to generate a calibration current that suppresses the voltage change caused by the temperature change at the node between the current mirror and the reference current source.

[0071] Therefore, the digital PLL 1000 can output an output signal FOUT whose output frequency is substantially insensitive to the change in PVT.

[0072] FIG. 13 is a block diagram showing an electronic device 2000 according to an embodiment of the inventive concept.

[0073] Referring to FIG. 13, the electronic device 2000 may include an antenna 2011, a receiver 2012, a transmitter 2016, a communication module 2020, an input / output (I / O) device 2040, and a reference oscillator 2042. The receiver 2012 may include a PLL 2014 including a DCO consistent with an embodiment of the inventive concept. The transmitter 2018 may also include a PLL 2014 including a DCO consistent with an embodiment of the inventive concept. The receiver 2012 may use the output signal of the PLL 2014 to convert an analog signal received from the outside by the antenna 2011 into a digital signal, and then provide the digital signal to the communication module 2020. The transmitter 2016 may use the output signal of the PLL 2018 to convert the digital signal received from the communication module 2020 into an analog signal, and then output the analog signal to the outside by the antenna 2011.

[0074] The communication module 2020 may include a modem processor 2022, a reduced instruction set computer / digital signal processor (RISC / DSP) 2024, a controller / processor 2026, a memory 2028, an I / O device 2030, and a PLL 2032.

[0075] The modem processor 2022 may perform processing operations such as encoding, modulating, demodulating, and decoding for data transmission and data reception. The RISC / DSP 2024 may perform general processing operations or dedicated processing operations in the communication device 2000. The controller / processor 2026 may control blocks in the communication module 1020. The memory 2028 may store data and various command codes. The I / O device 2030 may communicate with the external I / O device 2040. The PLL 2032 may include a DCO according to an embodiment of the inventive concept. The reference oscillator 2042 may be implemented as a crystal oscillator (XO), a voltage controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), etc. The communication module 2020 (e.g., the modem processor 2022 or the controller / processor 2026) may use the output signal generated by the PLL 2032 to perform processing operations required for communication.

[0076] FIG. 14 is a block diagram showing an integrated circuit 3000 according to an embodiment of the inventive concept. In some embodiments, the integrated circuit 3000 may include, for example, at least some of the following integrated circuits: an Application Processor (AP), a Timing Controller (TCON), a semiconductor memory device, an Internet of Things (IoT) component, a Subscriber Identification Module (SIM) card, a biometric sensor, a communication device, and the like. As shown in FIG. 14, the integrated circuit 3000 may include a controller 3010, a first DCO 3020, and a second DCO 3030, and in some embodiments, the integrated circuit 3000 may include three or more DCOs.

[0077] In some embodiments, the integrated circuit 3000 may include DCOs to generate clock signals. For example, the first DCO 3020 may generate a first clock signal CK1, and the second DCO 3030 may generate a second clock signal CK2. Each of the first clock signal CK1 and the second clock signal CK2 may have a different transition level and / or frequency, and may be supplied to other components included in the integrated circuit 3000 or may be output to the outside of the integrated circuit 3000. The controller 3010 may provide a control signal C1 including a plurality of bits and a control signal C2 to the first DCO 3020 and the second DCO 3030, respectively, to set the frequencies of the first clock signal CK1 and the second clock signal CK2. As described above with reference to the drawings, each of the first DCO 3020 and the second DCO 3030 includes a feedback circuit and a calibration circuit according to an embodiment of the inventive concept to output the first clock signal CK1 and the second clock signal CK2 that are insensitive to changes in PVT.

[0078] Although the inventive concept has been specifically shown and described with reference to some embodiments of the inventive concept, it should be understood that various changes in form and detail may be made thereto without departing from the spirit and scope of the following claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] With reference to the following detailed description in conjunction with the accompanying drawings, the conceptual embodiments of the present invention can be more clearly understood. In the drawings: FIG. 1 is a block diagram showing a digital control oscillator (DCO) according to a conceptual embodiment of the present invention. FIG. 2 is a flowchart showing a method of operating a DCO according to a conceptual embodiment of the present invention. FIGS. 3A and 3B are corresponding circuit diagrams showing comparative examples of a DCO. FIG. 4 is a circuit diagram showing a DCO according to a conceptual embodiment of the present invention. FIG. 5A is a circuit diagram showing an oscillation circuit according to a conceptual embodiment of the present invention and FIG. 5B is a block diagram showing the oscillation circuit according to a conceptual embodiment of the present invention. FIG. 6 is a block diagram showing a DCO according to a conceptual embodiment of the present invention. FIG. 7 is a flowchart showing a method of operating a DCO according to a conceptual embodiment of the present invention. FIG. 8 is a block diagram showing a DCO according to a conceptual embodiment of the present invention. FIGS. 9A and 9B are corresponding block diagrams showing different variants of a DCO according to a conceptual embodiment of the present invention. FIG. 10 is a block diagram showing a DCO according to a conceptual embodiment of the present invention. FIGS. 11A, 11B, and 11C are circuit diagrams respectively showing a variable resistor 83, a bias circuit 81_1, and a current source circuit 81_2 of FIG. 10 according to a conceptual embodiment of the present invention. FIG. 12 is a block diagram showing a digital phase-locked loop (PLL) according to a conceptual embodiment of the present invention. FIG. 13 is a block diagram showing an electronic device according to a conceptual embodiment of the present invention. FIG. 14 is a block diagram showing an integrated circuit according to a conceptual embodiment of the present invention.

Claims

1. A digitally controlled oscillator (DCO), comprising: A current mirror is configured to generate a supply current in response to matching the bias voltage with the reference current; A variable resistor, connected to the current mirror via a first node that outputs the reference current, and configured to provide variable resistance in response to a first control signal; an oscillation circuit, connected to the current mirror via a second node that outputs the supply current, and configured to generate an oscillation signal in response to the supply current; and a feedback circuit, configured to control the bias voltage in relation to at least one of the voltage at the first node and the voltage at the second node. And a calibration circuit configured to calibrate the voltage at the first node in response to changes in the resistance of the variable resistor due to temperature variations, wherein the calibration circuit includes: a calibration current source having characteristics matching the temperature variation characteristics of the variable resistor, the calibration current source being connected in parallel with the variable resistor between the first node and ground, and the calibration current source being configured to generate a calibration current for calibrating the voltage at the first node.

2. The digitally controlled oscillator as claimed in claim 1, wherein the feedback circuit is further configured to increase the bias voltage in response to an increase in the voltage at the first node, and to decrease the bias voltage in response to a decrease in the voltage at the first node.

3. The digitally controlled oscillator as claimed in claim 1, wherein the feedback circuitry comprises: An amplifier is configured to amplify the difference between the voltage at the first node and the voltage at the second node to generate feedback and provide the feedback to the current mirror.

4. The digitally controlled oscillator as claimed in claim 3, wherein the bias voltage is adjusted in response to the feedback.

5. The digitally controlled oscillator as claimed in claim 1, wherein the feedback circuitry comprises: The first input terminal is connected to the first node; The second input terminal is connected to the second node; And the output terminal, connected to the third node associated with the current mirror.

6. The digitally controlled oscillator as claimed in claim 5, wherein the current mirror comprises: A bias circuit, including the third node, is configured to generate the bias voltage in response to the reference current and the first control signal; and a current source circuit configured to generate the supply current in response to the bias voltage, wherein the third node outputs the bias voltage to the current source circuit.

7. The digitally controlled oscillator as claimed in claim 6, wherein the current source circuit is further configured to generate the supply current in response to a second control signal.

8. The digitally controlled oscillator as claimed in claim 1, wherein each of the variable resistor and the calibration current source has a temperature-to-absolute (PTAT) characteristic.

9. The digitally controlled oscillator as claimed in claim 1, wherein the calibration current source is further configured to generate the calibration current in response to a second control signal.

10. A digitally controlled oscillator (DCO), comprising: A current mirror, including a third node, is configured to generate a supply current in response to matching the bias voltage with the reference current; A variable resistor is connected to the current mirror via a first node that outputs the reference current and is configured to provide variable resistance; an oscillating circuit is connected to the current mirror via a second node that outputs the supply current and is configured to receive the supply current; an amplifier includes a first input terminal, a second input terminal, and an output terminal, the first input terminal being connected to the first node to receive a voltage at the first node, the second input terminal being connected to the second node to receive a voltage at the second node, and the output terminal being connected to the third node, wherein the amplifier is configured to generate feedback in response to the difference between the voltage at the first node and the voltage at the second node, and to provide the feedback to the third node; A calibration current source is connected in parallel with the variable resistor between the first node and ground, wherein the calibration current source is configured to adjust the voltage at the first node.

11. The digitally controlled oscillator as claimed in claim 10, wherein the voltage at the third node corresponds to the bias voltage.

12. The digitally controlled oscillator as claimed in claim 10, wherein the current mirror comprises: A bias circuit is configured to generate the bias voltage in response to the reference current; and a current source circuit configured to generate the supply current in response to the bias voltage, wherein the third node is connected to the bias circuit and the current source circuit.

13. The digitally controlled oscillator of claim 10, wherein the feedback increases the bias voltage in response to an increase in the voltage at the first node, and decreases the bias voltage in response to a decrease in the voltage at the first node.

14. A digital phase-locked loop (PLL), comprising: A frequency divider is configured to divide a clock signal and output a divided signal. A time-to-digital converter is configured to compare the divided signal with a reference signal and output a comparison signal; a digital loop filter is configured to output a control signal in response to the comparison signal; and a digital controlled oscillator (DCO) is configured to output the clock signal, the frequency of which is adjusted in response to the control signal, wherein the digital controlled oscillator includes: a current mirror including a third node and configured to generate a supply current in response to a bias voltage matching a reference current; a variable resistor connected to the current mirror via a first node outputting the reference current; an oscillation circuit connected to the current mirror via a second node outputting the supply current; an amplifier including a first input terminal connected to the first node, a second input terminal connected to the second node, and an output terminal connected to the third node; and a calibration current source connected in parallel with the variable resistor at the first node.

15. The digital phase-locked loop as claimed in claim 14, wherein the third node outputs the bias voltage, and the amplifier is configured to increase the bias voltage in response to an increase in the voltage at the first node, and to decrease the bias voltage in response to a decrease in the voltage at the first node.

16. The digital phase-locked loop as claimed in claim 14, wherein each of the variable resistor and the calibration current source has a temperature-to-absolute (PTAT) characteristic.

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