Self-assembled monolayer for selective deposition

Abstract

Methods for selective deposition on metal surfaces are disclosed. Some embodiments of this disclosure utilize a hydrocarbon having at least two functional groups selected from alkenes, alkynes, ketones, alcohols, esters, or combinations thereof to form a self-assembled monolayer (SAM) on a metal surface.

Description

Technical Field

[0001] The embodiments of this disclosure are generally related to methods for forming semiconductor structures. More specifically, some embodiments of this disclosure are for methods of selectively depositing self-assembled monolayers on non-metallic surfaces using precursors, wherein the precursors include at least two functional groups selected from alkenes, alkynes, ketones, alcohols, esters, or combinations thereof. Prior Technology

[0002] In general, an integrated circuit (IC) represents a group of electronic components, such as transistors formed on a small wafer of semiconductor material (usually silicon). Typically, an IC includes one or more metallization layers with metal interconnects to allow the IC's electronic components to connect to each other and to external connections. Typically, layers of interlayer dielectric material are placed between the metallization layers of the IC for insulation.

[0003] As IC size decreases, the spacing between metal interconnects also decreases. Typically, planar processes are used to fabricate interconnect structures, which involves aligning and connecting one metallization layer to another.

[0004] Reducing the resistance of the interposer window is crucial for improving the performance of electronic components. This reduction is typically controlled by minimizing the cladding and lowering the resistivity of the interposer window material. Therefore, a method for reducing the interposer window resistance is needed. Summary of the Invention

[0005] One or more embodiments of this disclosure are directed to a method of forming a semiconductor structure. In some embodiments, the method includes selectively depositing a self-assembled monolayer (SAM) on a first surface of a substrate by exposing the substrate to a first precursor, wherein the substrate has at least one feature including the first surface and a second surface, and wherein the first precursor includes at least two functional groups selected from olefins, alkynes, ketones, alcohols, esters, or combinations thereof; selectively depositing a liner on a second surface by exposing the substrate to a second precursor; and removing the self-assembled monolayer. In some embodiments, the first surface includes a metal. In some embodiments, the second surface includes a dielectric material.

[0006] In one or more embodiments, the method includes: exposing a substrate to at least one first precursor to selectively deposit a self-assembled monolayer (SAM) on a first surface of the substrate, the substrate having at least one feature including the first surface and a second surface; exposing the substrate to a second precursor to selectively deposit a liner on the second surface; removing the self-assembled monolayer (SAM); and densifying the liner as appropriate. In some embodiments, the first surface comprises a metal selected from one or more of tungsten (W) and molybdenum (Mo). In some embodiments, the second surface comprises a dielectric material. In some embodiments, the first precursor is selected from the group consisting of structures of formulas (ii), (iii), (iv), (v), (vi), and (vii). R8, R9, R10, R11, R12, R13, R14, R15, R16, R17 and R18 are independently selected from H and C1~C12 alkyl groups. Simple Explanation of the Diagram

[0007] Therefore, the above-described features of this disclosure can be understood in detail by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of this disclosure and should not be considered as limiting the scope of this disclosure, as other equally effective embodiments are permissible.

[0008] Figure 1 illustrates a process flow diagram of a method according to one or more embodiments of this disclosure.

[0009] Figures 2A through 2G depict cross-sectional views of an exemplary substrate during processing, according to one or more embodiments of this disclosure.

[0010] Figure 3 illustrates an exemplary clustering tool according to one or more embodiments of this disclosure. Implementation

[0011] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or process steps described below. This disclosure can have other embodiments and can be practiced or implemented in various ways.

[0012] As used in this specification and the appended claims, the term "substrate" means the surface or part of the surface on which the process is performed. Those skilled in the art will also understand that reference to substrate may also refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, the reference to deposition on a substrate may mean a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0013] As used herein, "substrate" refers to any substrate on which a film treatment is performed during a manufacturing process, or a material surface formed on a substrate. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or baking of the substrate surface. In addition to performing film treatments directly on the substrate surface itself, in this disclosure, any of the disclosed film treatment steps may also be performed on a substrate substrate (as disclosed in more detail below), and the term "substrate surface" is intended to include such substrates, as indicated in the context. Therefore, for example, in the case where a film / layer or part of a film / layer has been deposited on the substrate surface, the exposed surface of the most recently deposited film / layer becomes the substrate surface.

[0014] As used herein, "atomic layer deposition" or "cyclic deposition" means the sequential exposure of two or more reactive compounds to deposit a material layer on a substrate surface. As used in this specification and the appended claims, the terms "reactive compound," "reactive gas," "reactive substance," "precursor," "process gas," and similar terms are used interchangeably to mean a substance having the ability to react with the substrate surface or a material on the substrate surface in a surface reaction (e.g., chemisorption, oxidation, reduction). The substrate or a portion of the substrate is sequentially or substantially sequentially exposed to the precursor (or reactive gas). As used throughout this specification, "substantially sequentially" means that the majority of the duration of precursor exposure does not overlap with exposure to the co-reagent, although some overlap may exist.

[0015] For many applications, metals can be grown by atomic layer deposition. One or more embodiments of this disclosure advantageously provide a process for atomic layer deposition to form metal-containing films. As used in this specification and the appended claims, the term "metal-containing film" means a film comprising metal atoms and having a metal content greater than or equal to about 1 atomic percent, 2 atomic percent, 3 atomic percent, 4 atomic percent, 5 atomic percent, 10 atomic percent, 15 atomic percent, 20 atomic percent, 25 atomic percent, 30 atomic percent, 35 atomic percent, 40 atomic percent, 45 atomic percent, 50 atomic percent, 55 atomic percent, 60 atomic percent, or 65 atomic percent. In some embodiments, the metal-containing film comprises one or more of a metal, a metal nitride, a metal carbide, or a metal oxide. Those skilled in the art will recognize that the use of a molecular formula such as MO (where M is a metal) does not imply a specific stoichiometric relationship between elements, but only indicates the identity of the main components of the film. For example, MO represents a membrane whose main components include metal and oxygen atoms. In some embodiments, the main components of a specified membrane (i.e., the sum of the atomic percentages of specified atoms) are greater than or equal to about 95%, 98%, 99%, or 99.5% of the membrane.

[0016] As used herein, the phrases “metallic material surface” or “non-metallic material surface” refer to the surface of a metallic or non-metallic material, respectively. For the purposes of this disclosure, a non-metallic material is any material that exhibits properties of a poor conductor or a good insulator. Non-metallic materials may include metal atoms (e.g., tantalum nitride, titanium nitride) and are still within the scope of non-metallic materials. In some embodiments, the term “conductive material” is used instead of “metallic material.” In some embodiments, the term “dielectric material” is used instead of “non-metallic material.”

[0017] As used herein, the phrase "selectively deposited on a first surface relative to a second surface" and the like mean depositing a first amount or thickness on a first surface and depositing a second amount or thickness on a second surface, wherein the second amount or thickness is less than the first amount or thickness, or in some embodiments, no amount of deposition is made on the second surface.

[0018] As used herein, the term "relative" does not imply the physical orientation of one surface on top of another, but rather refers to its relationship with the thermodynamic or kinematic properties of the chemical reaction of one surface relative to the other. For example, selectively depositing a film onto a metallic surface relative to a nonmetallic surface means that the film is deposited on the metallic surface with less or no film deposited on the nonmetallic surface; or that forming a film on a metallic surface is thermodynamically or kinematically advantageous relative to forming a film on a nonmetallic surface.

[0019] Reducing the contact resistance (Rc) of semiconductor structures at 3 nm nodes (N3) and above is crucial. Integration schemes using tungsten (W) or molybdenum (Mo) sublayers are ineffective. Therefore, one or more embodiments of this disclosure pertain to a method for selectively forming a self-assembled monolayer (SAM) on a first surface of a substrate relative to a second surface. The substrate includes a metallic material (conductive material) having a first surface and a non-metallic material (dielectric material) having a second surface. In some embodiments, the first surface may be described as a metallic material surface or a conductive material surface. In some embodiments, the first surface includes one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and molybdenum (Mo). In some embodiments, the second surface may be described as a non-metallic material surface or a dielectric material surface. In some embodiments, the method described herein has middle end of line (MEOL) and back end of line (BEOL) applications.

[0020] Referring to Figure 1, which is a process flow diagram, one or more embodiments of this disclosure are directed to a method 100 for forming electronic components. The method illustrated in Figure 1 represents an integrated process.

[0021] Figures 2A through 2G illustrate cross-sectional views of an exemplary element 200 during processing method 100, according to one or more embodiments of this disclosure. Referring to Figure 2A, a substrate 210 is provided having a barrier layer 215, a metal liner 220, a conductive layer 225, an etch stop layer 230, and a dielectric layer 235. In one or more embodiments, the dielectric layer 235 has at least one feature 240. In some embodiments, the substrate 210 is a wafer, for example, a semiconductor substrate. In some embodiments, the substrate 210 is an etch stop layer on a wafer.

[0022] For illustrative purposes, Figure 2A shows a substrate 210 having a single feature 240. However, those skilled in the art will understand that more than one feature may be present. As shown in Figure 2A, feature 240 includes a first surface 245 and a second surface 250. In some embodiments, the first surface 245 is the bottom surface of feature 240. In some embodiments, the second surface 250 is a sidewall of feature 240. The shape of feature 240 may be any suitable shape, including but not limited to trenches, dielectric windows that transfer current between layers when filled with metal, and wiring that transfers current within the same element layer. It will be understood that in one or more embodiments, conductive layer 225 forms a metal wiring that transfers current within the same element layer. In some embodiments, feature 240 defines a gap in dielectric layer 235. As used herein, the term "feature" means any intentional surface irregularity. Suitable examples of features include, but are not limited to, trenches having a top, two sidewalls, and a bottom; and spikes having a top and two sidewalls. Features may have any suitable aspect ratio (the ratio of the feature's depth to its width). In some embodiments, the aspect ratio is greater than or equal to about 1:1, 2:1, 3:1, 4:1, 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1.

[0023] In one or more embodiments, barrier layer 215 is a conformal layer. Barrier layer 215 may comprise any suitable material known to those skilled in the art and may be deposited using any suitable technique known to those skilled in the art. In some embodiments, the barrier layer is selected from titanium nitride (TiN) and tantalum nitride (TaN), or tungsten nitride (WN). In a particular embodiment, barrier layer 215 comprises tantalum nitride (TaN). In some embodiments, barrier layer 215 is formed by ALD. In some embodiments, barrier layer 215 prevents material from diffusing across itself into the underlying layer.

[0024] In one or more embodiments, the metal liner 220 may comprise any suitable metallic material known to those skilled in the art, and may be deposited using any technique known to those skilled in the art. In one or more embodiments, the metal liner 220 comprises one or more of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt). In one or more embodiments, the metal liner 220 comprises one or more of a monolayer of tungsten (W) or a monolayer of molybdenum (Mo). In some embodiments, the metal liner 220 comprises tungsten or molybdenum or is substantially composed of tungsten or molybdenum. As used in this specification and the appended claims, the term "substantially composed of" means that the material is greater than or equal to about 95%, 98%, or 99% of the material on an atomic basis.

[0025] In one or more embodiments, the conductive layer 225 comprises a metal or a metallic material. In some embodiments, the metal or metallic material may be any suitable metallic material. In some embodiments, the metallic material of this disclosure is a conductive material. Suitable metallic materials include, but are not limited to, metals, conductive metal nitrides, conductive metal oxides, metal alloys, silicon, combinations thereof, and other conductive materials.

[0026] As used in this specification and the appended claims, the term "oxide" or the like means that a material contains (a number of) specified elements. The term should not be construed as implying a specific ratio of elements. Therefore, "oxide" or the like may include stoichiometric ratios or non-stoichiometric ratios of elements.

[0027] In one or more embodiments, the metal or metallic material may include any suitable metal known to those skilled in the art. In some embodiments, the metal or metallic material is selected from one or more of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt). In some embodiments, the metal or metallic material is substantially composed of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt). In some embodiments, the metal or metallic material is substantially composed of copper, cobalt, ruthenium, tungsten, or molybdenum. In some embodiments, the metallic material includes tungsten or molybdenum or is substantially composed of tungsten or molybdenum.

[0028] In one or more embodiments, the etch stop layer 230 comprises any suitable material known to those skilled in the art. In one or more embodiments, the etch stop layer 230 comprises one or more of silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), and aluminum nitride (AlN). In some embodiments, the etch stop layer 230 may be deposited using techniques selected from CVD, PVD, and ALD.

[0029] In one or more embodiments, a portion of the metal liner 220 and the etch stop layer 230 is removed, exposing the bottom first surface 245 of at least one feature 240. In some embodiments, the bottom first surface 245 is a portion of the top surface of the conductive material 225, thereby exposing a portion of the conductive material 225.

[0030] In one or more embodiments, dielectric layer 235 may be any suitable material. In some embodiments, dielectric layer 235 insulates adjacent elements and prevents leakage. Suitable dielectric materials include, but are not limited to, silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), silicon carbide (e.g., SiC), and combinations thereof (e.g., SiCON). Suitable dielectric materials further include aluminum oxide, aluminum nitride, and dielectric materials with low dielectric constants. In some embodiments, the dielectric material is substantially composed of silicon dioxide (SiO2). In some embodiments, dielectric layer 235 comprises silicon nitride. In some embodiments, dielectric layer 235 is substantially composed of silicon nitride.

[0031] In one or more embodiments, any suitable deposition technique is used to deposit the dielectric layer 235, such as, but not limited to, chemical vapor deposition ("CVD"), physical vapor deposition ("PVD"), molecular beam epitaxy ("MBE"), metal-organic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), spin coating, or other deposition techniques generally known to those skilled in the art of microelectronic device fabrication.

[0032] In one or more embodiments, during one or more operations of method 100, the substrate 210 is independently maintained under an operating pressure. In some embodiments, the operating pressure is less than or equal to 100 Torr, less than or equal to 80 Torr, less than or equal to 70 Torr, less than or equal to 60 Torr, less than or equal to 50 Torr, less than or equal to 40 Torr, less than or equal to 30 Torr, less than or equal to 20 Torr, less than or equal to 15 Torr, less than or equal to 10 Torr, less than or equal to 5 Torr, less than or equal to 1 Torr, less than or equal to 500 millitors, less than or equal to 200 millitors, less than or equal to 100 millitors, or less than or equal to 20 millitors. In some embodiments, the operating pressure is 10 Torr, 20 Torr, 30 Torr, 40 Torr, or 50 Torr. In some embodiments, during the deposition of the self-assembled monolayer (SAM) 255, the substrate 210 is maintained at a pressure within the following ranges: from 1 mTorr to 100 Torr, from 1 mTorr to 80 Torr, from 1 mTorr to 60 Torr, from 1 mTorr to 40 Torr, from 1 mTorr to 20 Torr, from 1 mTorr to 10 Torr, from 1 mTorr to 5 Torr, from 1 mTorr to 1 Torr, from 1 mTorr to 500 mTorr, from 1 mTorr to 200 mTorr, from 1 mTorr to 100 mTorr, from 1 mTorr to 50 Torr, from 500 mTorr to 100 Torr, from 500 mTorr to 80 Torr, from 500 mTorr to 60 Torr. From 500 mTorr to 40 Torr, from 500 mTorr to 20 Torr, from 500 mTorr to 10 Torr, from 500 mTorr to 5 Torr, from 500 mTorr to 1 Torr, from 1 Torr to 100 Torr, from 1 Torr to 80 Torr, from 1 Torr to 60 Torr, from 1 Torr to 40 Torr, from 1 Torr to 20 Torr, from 1 Torr to 10 Torr, from 1 Torr to 5 Torr, from 10 Torr to 100 Torr, from 10 Torr to 80 Torr, from 10 Torr to 60 Torr, from 10 Torr to 40 Torr, from 10 Torr to 20 Torr, from 20 Torr to 100 Torr, from 20 Torr to 80 Torr, from 20 Torr to 60 Torr, or from 20 Torr to 40 Torr.

[0033] In some embodiments, the temperature of the substrate is controlled during method 100. The substrate temperature may also be referred to as the operating temperature. In some embodiments, the operating temperature is less than or equal to 450°C, less than or equal to 400°C, less than or equal to 350°C, less than or equal to 300°C, less than or equal to 275°C, less than or equal to 250°C, less than or equal to 225°C, less than or equal to 200°C, less than or equal to 150°C, less than or equal to 100°C, or less than or equal to 80°C. In some embodiments, during the deposition of the self-assembled monolayer (SAM) 255, the operating temperature is in the range of 60°C to 450°C, 60°C to 350°C, 60°C to 250°C, 60°C to 150°C, 60°C to 100°C, 100°C to 450°C, 100°C to 350°C, 100°C to 250°C, 100°C to 200°C, 200°C to 450°C, 200°C to 350°C, 200°C to 300°C, 300°C to 450°C, 300°C to 350°C, or 400°C to 450°C.

[0034] Referring to Figure 1, illustrative method 100 begins with an optional pre-cleaning operation 102. The pre-cleaning operation can be any suitable pre-cleaning process known to those skilled in the art. Suitable pre-cleaning operations include, but are not limited to, immersion, removal of native oxides, and the like. In some embodiments, pre-cleaning operation 102 cleans the first surface 245 and the second surface 250. In some embodiments, pre-cleaning operation 102 results in the formation of a substantially oxide-free surface of the substrate 210 (e.g., the first surface 245 and / or the second surface 250). As used herein, the term "substantially oxide-free" means that the surface has less than 10%, less than 5%, less than 4%, less than 3%, less than 2%, or less than 1% oxygen on an atomic basis.

[0035] At operation 104, substrate 210 is exposed to a first precursor to deposit a self-assembled monolayer (SAM) 255. As used herein, the phrase "exposing substrate to..." means that the substrate as a whole (including individual materials and layers thereon) is exposed to the process or conditions. Figure 2B illustrates the self-assembled monolayer (SAM) 255 deposited on a first surface 245 of feature 240. In some embodiments, the self-assembled monolayer (SAM) 255 is selectively deposited on the first surface 245 of feature 240 relative to a second surface 250. In some embodiments, the self-assembled monolayer (SAM) is not deposited on the second surface 250 of feature 240. In one or more embodiments, the self-assembled monolayer (SAM) 255 is deposited on the exposed first surface 245 of conductive layer 225 at the bottom of feature 240. It should be noted that, as described above, (for example) a portion of the metal liner 220 and a portion of the etch stop layer 230 are removed by etching to expose a portion, for example, the first surface 245 of the conductive layer 225 at the bottom of the feature 240. In some embodiments, operation 104 is a dry deposition process.

[0036] In some embodiments, "selectively" means that the target material is formed on the selected surface at a rate greater than or equal to that formed on the non-selected surface at approximately 1.5 times, 2 times, 3 times, 4 times, 5 times, 7 times, 10 times, 15 times, 20 times, 25 times, 30 times, 35 times, 40 times, 45 times, or 50 times. In other words, the process is selective to the selected surface relative to the non-selected surface at a rate greater than or equal to approximately 3:2, 2:1, 3:1, 4:1, 5:1, 7:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, 45:1, or 50:1.

[0037] In one or more embodiments, the first precursor is reversibly bonded to the metal. In some embodiments, the self-assembled monolayer (SAM) 255 formed by the first precursor remains substantially intact during subsequent operations of method 100. As used herein, the term "substantially" means that up to 99%, 98%, 95%, 90%, or 80% of the self-assembled monolayer (SAM) 255 remains intact during subsequent operations of method 100.

[0038] In some embodiments, the first precursor includes at least one, at least two, or at least three functional groups. In some embodiments, the functional groups are designed to allow reverse-selective ALD deposition. In some embodiments, the functional groups include unsaturated hydrocarbons (e.g., alkenes, alkynes, or combinations thereof), ketones, alcohols, esters, or combinations thereof. In some embodiments, the first precursor includes at least one unsaturated group. In some embodiments, the first precursor includes at least one alcohol group. In some embodiments, the first precursor includes at least one ketone group. In some embodiments, the first precursor includes at least one ester group. In some embodiments, the first precursor includes at least two functional groups. In some embodiments, the at least two functional groups are independently selected from unsaturated hydrocarbons (e.g., alkenes, alkynes, or combinations thereof), ketones, alcohols, esters, or derivatives thereof. In some embodiments, each of the at least three functional groups is independently selected from unsaturated hydrocarbons (e.g., alkenes, alkynes, or combinations thereof), ketones, alcohols, esters, or derivatives thereof. In some embodiments, surface engineering modifications with bifunctional groups allow for reverse-selective ALD deposition for resistance at the interlayer window contact interface. In some embodiments, the bifunctional groups act as conjugated systems. In some embodiments, the conjugated systems include lone pair groups.

[0039] Without being bound by theory, it is believed that the d-orbitals of metallic materials begin to share electrons with the sp2 orbitals of unsaturated hydrocarbons. Therefore, in some embodiments, unsaturated hydrocarbons include at least one compound having at least one double bond between two carbon atoms. In some embodiments, unsaturated hydrocarbons include at least one compound having at least one triple bond between two carbon atoms. In other words, in some embodiments, unsaturated hydrocarbons include at least one compound having the general formula -R1=R2- or -R3≡R4-. In some embodiments, R1, R2, R3, and R4 are independently selected from H, -R5OH, -CH(OH)R6, and -COR7. In some embodiments, R5, R6, and R7 are independently selected from H and C1-C12 groups. As used in this regard, "C1-C12 groups" contain 1 to 12 carbon atoms. In some embodiments, C1-C12 groups are straight-chain groups (e.g., straight-chain saturated or unsaturated hydrocarbons). In some embodiments, the C1-C12 groups are branched groups (e.g., branched saturated or unsaturated hydrocarbons). In some embodiments, the C1-C12 groups are cyclic groups (e.g., cyclic saturated or unsaturated hydrocarbons).

[0040] Without being bound by theory, it is believed that the likelihood of polymerization advantageously increases with the increase in the number of unsaturated bonds. During subsequent operations of method 100, polymerization can make the self-assembled monolayer (SAM) 255 more difficult to detach. Furthermore, without being bound by theory, it is believed that the unsaturated hydrocarbon (self-assembled monolayer (SAM) 255) inhibits one or more of the nucleation or growth rates of subsequent films on the first surface 245. Therefore, in some embodiments, the first precursor comprises only one unsaturated bond, wherein the first surface 245 comprises copper, cobalt, ruthenium, or a combination thereof. In some embodiments, the first precursor comprises at least two unsaturated bonds, wherein the first surface 245 comprises tungsten, molybdenum, or a combination thereof.

[0041] In some embodiments, a self-assembled monolayer (SAM) 255 formed on a metal surface 245 having a single alkyne precursor is unstable for subsequent operations of method 100, wherein the metal surface 245 comprises tungsten, molybdenum, or a combination thereof. In some embodiments, a self-assembled monolayer (SAM) 255 formed on a metal surface 245 having a single alkenyl precursor is unstable for subsequent operations of method 100, wherein the metal surface 245 comprises tungsten, molybdenum, or a combination thereof. In some embodiments, having a single alcohol precursor effectively allows reverse selective ALD deposition. In some embodiments, a self-assembled monolayer (SAM) 255 comprising a single alcohol precursor affects the etch stop layer 230 and / or modifies the non-metallic surface 250. Therefore, in one or more embodiments, a bifunctional group having lone pairs and a conjugated system is designed for the metal surface 245 comprising tungsten, molybdenum, or a combination thereof. In other words, in some embodiments, the self-assembled monolayer (SAM) 255 selectively blocks the metal surface 245 and keeps the non-metallic surface 250 intact during subsequent operations of method 100, wherein the metal surface 245 includes tungsten, molybdenum, or a combination thereof.

[0042] In some embodiments, the first precursor comprises a structure according to formula (ii), wherein R8 is selected from H and C1-C12 groups.

[0043] In some embodiments, the first precursor comprises a structure according to formula (iii), wherein each of R9 and R10 is independently selected from H and C1-C12 groups.

[0044] In some embodiments, the first precursor comprises a structure according to formula (iv), wherein each of R11 and R12 is independently selected from H and C1~C12 groups.

[0045] In some embodiments, the first precursor comprises a structure according to formula (v), wherein each of R13 and R14 is independently selected from H and C1-C12 groups.

[0046] In some embodiments, the first precursor comprises a diketone group. In some embodiments, the first precursor comprises a structure according to formula (vi), wherein each of R15 and R16 is independently selected from H and C1-C12 groups.

[0047] In some embodiments, the first precursor comprises an olefinic group. In some embodiments, the first precursor comprises a structure according to formula (vii), wherein each of R17 and R18 is independently selected from H and C1-C12 groups.

[0048] In one or more embodiments, substrate 210 may be exposed to the first precursor at any suitable flow rate to form a self-assembled monolayer (SAM) 255. In some embodiments, substrate 210 is exposed to the first precursor at flow rates ranging from 50 sccm to 2000 sccm, from 100 sccm to 2000 sccm, from 500 sccm to 2000 sccm, from 1000 sccm to 2000 sccm, from 1500 sccm to 2000 sccm, from 50 sccm to 100 sccm, and from 75 sccm to 100 sccm. In some embodiments, the flow rate of the first precursor is less than or equal to 2000 sccm, less than or equal to 1500 sccm, less than or equal to 1000 sccm, less than or equal to 600 sccm, less than or equal to 500 sccm, less than or equal to 400 sccm, less than or equal to 300 sccm, less than or equal to 250 sccm, less than or equal to 200 sccm, less than or equal to 150 sccm, less than or equal to 100 sccm, less than or equal to 75 sccm, or less than or equal to 50 sccm.

[0049] In some embodiments, the substrate 210 is immersed in the vapor of the first precursor. In some embodiments, the immersion period can be any suitable period for forming the self-assembled monolayer (SAM) 255. In some embodiments, the immersion period is greater than or equal to 10 seconds, greater than or equal to 20 seconds, greater than or equal to 30 seconds, greater than or equal to 45 seconds, greater than or equal to 60 seconds, greater than or equal to 80 seconds, greater than or equal to 120 seconds, greater than or equal to 150 seconds, or greater than or equal to 200 seconds.

[0050] In one or more embodiments, the first precursor is a liquid at the operating temperature and / or operating pressure. In one or more embodiments, the first precursor is a solid at the operating temperature and / or operating pressure. In some embodiments, the first precursor is stored in an ampoule or cylinder and is conveyed from the ampoule or cylinder to the substrate 210. In some embodiments, at operating temperature and / or operating pressure, the first precursor has a vapor pressure in the range of: 0.1 Torr to 150 Torr, 0.1 Torr to 100 Torr, 0.1 Torr to 50 Torr, 0.1 Torr to 10 Torr, 0.1 Torr to 1 Torr, 0.1 Torr to 0.5 Torr, 0.5 Torr to 150 Torr, 0.5 Torr to 100 Torr, 0.5 Torr to 50 Torr, 0.5 Torr to 10 Torr, 0.5 Torr to 1 Torr, 1 Torr to 150 Torr, 1 Torr to 100 Torr, 1 Torr to 50 Torr, 1 Torr to 100 Torr, 10 Torr to 50 Torr, 50 Torr to 150 Torr, 50 Torr to 100 Torr, or 100 Torr to 150 Torr. In some embodiments, the first precursor has a vapor pressure greater than or equal to about 0.1 Torr at the operating temperature and / or operating pressure.

[0051] In one or more embodiments, the first precursor further includes a carrier gas. In some embodiments, the carrier gas is a non-reactive gas. In some embodiments, the carrier gas includes an inert gas. In some embodiments, the inert gas includes one or more of helium (He), neon (Ne), or argon (Ar). In some embodiments, the carrier gas includes argon (Ar).

[0052] In some embodiments, the flow of the carrier gas is configured to carry the first precursor from the container to the substrate 210. In some embodiments, the flow rate of the argon (Ar) gas configured to carry the first precursor to the substrate 210 is controlled.

[0053] Referring to Figure 1, at operation 106, substrate 210 is exposed to a second precursor for selective deposition of a liner on second surface 250. Figure 2C illustrates the selective deposition of liner 260 on second surface 250. In some embodiments, liner 260 is formed on second surface 250 and not on first surface 245. In some embodiments, liner 260 is a conformal layer. Liner 260 may comprise any suitable material known to those skilled in the art and may be deposited by any suitable technique known to those skilled in the art. In some embodiments, liner 260 comprises a metal nitride. In some embodiments, liner 260 comprises tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. In some embodiments, liner 260 has the same properties as barrier layer 215. In some embodiments, liner 260 is selectively deposited by atomic layer deposition (ALD). In some embodiments, the self-assembled monolayer (SAM) 255 selectively blocks the metal interface 245 while also keeping the non-metallic surface 250 intact for selective ALD deposition. In some embodiments, the liner 260 is deposited by sequentially exposing the substrate 210 to a metal precursor and a reactant. In some embodiments, the liner 260 is formed without the use of plasma. In some embodiments, the liner 260 has a thickness ranging from about 2 Å to about 20 Å. In some embodiments, the liner 260 is formed in a single ALD cycle. In some embodiments, the liner 260 is formed in 1 to 40 ALD cycles. In one or more embodiments, each of the 1 to 40 ALD cycles is configured to deposit a thickness of about 0.5 Å for the liner 260.

[0054] Referring to Figure 1, at operation 108, the self-assembled monolayer (SAM) 255 is removed. Figure 2D illustrates the self-assembled monolayer (SAM) 255 removed from the first surface 245. The self-assembled monolayer (SAM) 255 is removed by an etching process. In some embodiments, the etching process may include any suitable means, including but not limited to a plasma cleaning process. In one or more embodiments, the self-assembled monolayer (SAM) 255 is removed by plasma treatment. In some embodiments, the plasma includes one or more of hydrogen (H2), nitrogen (N2), or argon (Ar) plasmas. As used herein, a plasma including hydrogen, nitrogen, or argon means a plasma formed in the molecular form of said substances. In some embodiments, the plasma is substantially composed of hydrogen, nitrogen, argon, or combinations thereof. In some embodiments, the self-assembled monolayer (SAM) 255 is removed without substantially causing damage to the liner 260.

[0055] The plasma power can vary depending on the composition, packaging, and / or thickness of the self-assembled monolayer (SAM) and the composition and / or thickness of the surrounding material. In some embodiments, the plasma power is in the range of about 20 W to about 500 W, about 20 W to about 400 W, about 20 W to about 250 W, about 50 W to about 500 W, about 100 W to about 500 W, about 100 W to about 450 W, about 100 W to about 500 W, or about 200 W to about 400 W. In some embodiments, the plasma power is about 50 W, about 200 W, or about 400 W.

[0056] The duration of plasma exposure may vary depending on the composition, packaging, and / or thickness of the self-assembled monolayer (SAM) 255 and the composition and / or thickness of the surrounding materials. In some embodiments, the substrate is exposed to plasma for a period ranging from about 2 seconds to about 60 seconds, from about 3 seconds to about 30 seconds, or from about 5 seconds to about 10 seconds. In some embodiments, the substrate is exposed to plasma for a period of about 3 seconds, about 5 seconds, about 10 seconds, or about 30 seconds.

[0057] Referring to Figure 1, at operation 110, the liner 260 is densified as appropriate by a densification process. Figure 2F illustrates the densified liner 260 extending over a portion of the facing feature 245 of the etch-stop layer 230. In some embodiments, the densification process includes physical vapor deposition (PVD). In some embodiments, physical vapor deposition (PVD) includes doped physical vapor deposition. In some embodiments, after densification, the liner 260 has a thickness ranging from 5 to 20.

[0058] In some embodiments, operations 108 and 110 are performed simultaneously. Therefore, in some embodiments, the removal of the self-assembled monolayer (SAM) 255 and the densification of the liner 260 are performed simultaneously. In some embodiments, the etching of the self-assembled monolayer (SAM) 255 and the densification of the liner 260 are performed simultaneously. In some embodiments, selective nitrogen removal and densification of the liner 260 are performed simultaneously. In some embodiments, operations 108 and 110 are predominantly deposition-based or predominantly etching-based.

[0059] Referring to Figure 1 and Figure 2E, at operation 112, an adhesive layer 265 is deposited on the barrier layer 260 and the first surface 245. Figure 2F illustrates the adhesive layer 265 deposited on the barrier layer 260 and the first surface 245. In some embodiments, the adhesive layer 265 is conformally deposited on the barrier layer 260 and the first surface 245. In some embodiments, the thickness of the adhesive layer 265 on the barrier layer 260 is the same as the thickness of the adhesive layer 265 on the first surface 245. In some embodiments, the thickness of the adhesive layer 265 on the barrier layer 260 is different from the thickness of the adhesive layer 265 on the first surface 245. In some embodiments, the thickness of the adhesive layer 265 on the barrier layer 260 is greater than the thickness of the adhesive layer 265 on the first surface 245. In some embodiments, the adhesive layer 265 comprises any suitable material known to those skilled in the art and can be deposited by any suitable technique known to those skilled in the art. In one or more embodiments, the adhesive layer 265 comprises one or more of cobalt (Co) and ruthenium (Ru). In some embodiments, the adhesive layer 265 comprises a cobalt, ruthenium (Ru), or a ruthenium / cobalt (Ru / Co) binary layer.

[0060] Referring to Figures 1 and 2G, at operation 214, method 100 includes depositing a conductive material 270 in at least one feature 240 by exposing a substrate to a third precursor. In some embodiments, the third precursor comprises a metal. In some embodiments, the third precursor comprises copper. In some embodiments, the conductive material 270 is deposited on an adhesive layer 265 by a gap-filling process. In some embodiments, the gap-filling process includes bottom-up filling or conformal filling. Figure 2G illustrates the formation of interconnects of conductive material 270 within feature 245.

[0061] The conductive material 270 may be any suitable material known to those skilled in the art. In some embodiments, the conductive filler material 270 includes one or more of copper (Cu), tungsten (W), and molybdenum (Mo). In some embodiments, the conductive filler material 270 includes copper (Cu). In a particular embodiment, the conductive material 270 includes copper.

[0062] In some embodiments, feature 240 includes a bottom and a top. In some embodiments, the bottom includes a mesophyll window. In some embodiments, the top includes a trench. In some embodiments, a first conductive filler material is grown in a bottom-up manner to fill the mesophyll window portion constituting the lower part of feature 240. In some embodiments, a second conductive material is deposited in the upper part. In some embodiments, the first conductive material and the second conductive material are the same. In some embodiments, the first conductive material and the second conductive material are different. In some embodiments, the entire feature 240 is filled at once with a single conductive material to fill the lower and upper parts of feature 240 in one process.

[0063] The conductive material 270 can be deposited using any suitable technique known to those skilled in the art. In some embodiments, the conductive material 270 is deposited using one or more of a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process. In some embodiments, the conductive material 270 is deposited to overfill the feature 240 and form an overload on the surface of the substrate 210. The overload is then removed using any suitable technique (e.g., etching, chemical-mechanical planarization (CMP)).

[0064] Without being bound by theory, it is believed that the self-assembled monolayer (SAM) 255 increases the resistance of the conductive filler 270 only slightly compared to the resistance increase typically seen in most barrier layers (e.g., film 260). Therefore, removal of the self-assembled monolayer (SAM) 255 is an optional process that can further reduce the resistance of the conductive filler 270. In some embodiments, removal of the self-assembled monolayer (SAM) 255 reduces the resistance of the metal interconnect 270 by 30%, 20%, 10%, or 5%.

[0065] Additional embodiments of this disclosure pertain to a processing tool 900 used for the formation of the described elements and methods, as shown in Figure 3. A variety of multi-processing platforms can be utilized, including the Centura®, Dual ACP, Producer® GT, and Endura® platforms available from Applied Materials®, as well as other processing systems. In one or more embodiments, the clustering tool 900 includes at least one central transfer station 921, 931 having a plurality of sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and configured to move robot blades and wafers to each of the plurality of sides.

[0066] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918 (also referred to as process stations) connected to a central transfer station. Each processing chamber provides a separate processing area isolated from adjacent process stations. Processing chambers can be any suitable chamber, including but not limited to selective metal deposition chambers; barrier metal deposition chambers; metal deposition chambers; PVD metal deposition chambers; CVD metal deposition chambers; self-assembled monolayer (SAM) deposition chambers; lined metal deposition chambers; plasma chambers; pre-cleaning chambers; etching chambers; (a number of) transfer spaces, wafer orientation / degassing chambers, cryogenic cooling chambers, and the like. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be considered as limiting the scope of this disclosure.

[0067] In one or more embodiments, the clustering tool 900 includes a self-assembly monolayer (SAM) deposition chamber to expose a substrate to planar hydrocarbons and form a self-assembly monolayer (SAM). In one or more embodiments, the clustering tool 900 includes a pre-cleaning chamber connected to a central transfer station.

[0068] In the embodiment shown in Figure 3, the factory interface 950 is connected to the front portion of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front portion 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 on the right, those skilled in the art will understand that this represents only one possible configuration.

[0069] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary depending on, for example, the substrate being processed in the clustering tool 900. In the illustrated embodiment, the size of the loading chamber 954 and the unloading chamber 956 is determined to hold a wafer cassette having a plurality of wafers positioned within it.

[0070] Robot 952 is located within fab interface 950 and can move between loading chamber 954 and unloading chamber 956. Robot 952 is capable of transferring wafers from a cassette in loading chamber 954 to a loading gate chamber 960 via fab interface 950. Robot 952 is also capable of transferring wafers from loading gate chamber 962 to a cassette in unloading chamber 956 via fab interface 950. As will be understood by those skilled in the art, fab interface 950 may have more than one robot 952. For example, fab interface 950 may have a first robot that transfers wafers between loading chamber 954 and loading gate chamber 960, and a second robot that transfers wafers between loading gate 962 and unloading chamber 956.

[0071] The clustering tool 900 shown has a first portion 920 and a second portion 930. The first portion 920 is connected to a factory interface 950 via loading gate chambers 960, 962. The first portion 920 includes a first transfer chamber 921 having at least one robot 925 positioned therein. The robot 925 is also referred to as a robotic wafer transport mechanism. The first transfer chamber 921 is centrally positioned with respect to the loading gate chambers 960, 962, process chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, the robot 925 is a multi-armed robot capable of independently moving more than one wafer at a time. In one or more embodiments, the first transfer chamber 921 includes more than one robotic wafer transport mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers surrounding the first transfer chamber 921. Individual wafers are carried on wafer transport blades located at the far end of the first robotic mechanism.

[0072] After the wafer has been processed in the first section 920, it can be transferred to the second section 930 via a through chamber. For example, chambers 922 and 924 can be unidirectional or bidirectional through chambers. The through chambers 922 and 924 can be used, for example, to cryogenically cool the wafer prior to processing in the second section 930, or to allow wafer cooling or post-processing before being transferred back to the first section 920.

[0073] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 can be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0074] The process can be stored as a general-purpose software program in the memory of the system controller 990. When executed by the processor, the general-purpose software program causes the process chamber to execute the process of this disclosure. The general-purpose software program can also be stored and / or executed by a second processor (not shown), located remotely from the hardware controlled by the processor. Part or all of the methods of this disclosure can also be executed by hardware. Thus, the process can be implemented in software and executed using a computer system, implemented in hardware as (e.g.) dedicated integrated circuits or other types of hardware, or implemented as a combination of software and hardware. When executed by the processor, the general-purpose software program transforms the general-purpose computer into a dedicated computer (controller), which controls the operation of the process chamber to enable the process to execute.

[0075] In one or more embodiments, the processing tool 900 includes central transfer stations 921, 931, which include at least one robot 925, 935 configured to move the wafer; one or more of a selective interlayer window filling station, a reverse selective deposition station, a self-assembled monolayer (SAM) formation station, a CVD station, and a PVD station connected to the central transfer station; an optional pre-cleaning station connected to the central transfer station; and at least one controller connected to one or more of the central transfer station, the selective interlayer window filling station, the reverse selective deposition station, the self-assembled monolayer (SAM) formation station, the CVD station, the PVD station, or the optional pre-cleaning station. In one or more embodiments, the at least one controller has at least one configuration selected from the following: a configuration for moving the wafer between stations using the robot; a configuration for selectively filling the interlayer window; a configuration for exposing the substrate to planar hydrocarbons and forming a self-assembled monolayer (SAM); a configuration for reverse selectively depositing a barrier layer; a configuration for depositing metal; and a configuration for pre-cleaning the wafer.

[0076] In one or more embodiments, a processing tool includes: a pre-cleaning chamber having a substrate support therein; a selective metal deposition chamber; a barrier metal deposition chamber; a metal deposition chamber; a PVD metal deposition chamber; a CVD metal deposition chamber; optionally, a self-assembled monolayer (SAM) deposition chamber with optional pre-cleaning; optionally, a lined metal deposition chamber; optionally, a plasma chamber; optionally, an etching chamber; and a robot configured to access the pre-cleaning chamber, the selective deposition chamber, the optional self-assembled monolayer (SAM) deposition chamber, the barrier metal deposition chamber, the PVD metal deposition chamber, the optional plasma chamber; and optionally, the etching chamber and the optional lined metal deposition chamber. The device includes a pre-cleaning chamber, a selective deposition chamber, a selective self-assembled monolayer (SAM) deposition chamber, a barrier metal deposition chamber, a PVD metal deposition chamber, a selective plasma chamber, a selective etching chamber, a selective liner metal deposition chamber, a CVD metal deposition chamber, and a PVD metal deposition chamber, as well as a robot. The controller has one or more configurations selected from: cleaning the substrate; selectively forming a self-assembled monolayer (SAM); selectively depositing a liner; forming a metal liner as needed; forming a metal layer; etching the substrate as needed; and removing the self-assembled monolayer (SAM) as needed.

[0077] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, phrases such as "in one or more embodiments," "some embodiments," "in one embodiment," or "in one embodiment" appearing throughout this specification do not necessarily represent the same embodiment of this disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0078] Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that the embodiments described are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

[0079] 100: Method 102: Pre-cleaning operation 104: Operation 106: Operation 108: Operation 110: Operation 112: Operation 114: Operation 200: Components 210:Substrate 215: Barrier Layer 220: Metal Liner 225: Conductive layer 230: Etching stop layer 235: Dielectric layer 240: Features 245: First Surface 250: Second surface 255: Self-assembled single layer (SAM) 260: Lining 265: Adhesive layer 270: Conductive materials 900: Cluster Tools 902: Processing Chamber 904: Processing Chamber 906: Processing Chamber 908: Processing Chamber 910: Processing Chamber 912: Processing Chamber 914: Processing Chamber 916: Processing Chamber 918: Processing Chamber 920: Part One 921: Central Transfer Station 922: Buffer Chamber 924: Buffer Chamber 925: Robot 930: Part Two 931: Central Transfer Station 935: Robot 950: Factory Interface 951: Front 952: Robot 954: Loading Chamber 956: Carrying Chamber 960: Loading gate chamber 962: Loading gate chamber 990: System Controller

[0080] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a semiconductor structure, the method comprising the steps of: selectively depositing a self-assembled monolayer (SAM) on a first surface of a substrate by exposing a substrate to a first precursor, wherein the substrate has at least one feature including the first surface and a second surface, and wherein the first precursor is selected from the group consisting of structures of formulas (i), (ii), (iii), (iv), (v), and (vii): wherein R1, R2, R3, and R4 are independently selected from -R5OH, -CH(OH)R6, and -C(O)R7, R5, R6, and R7 are independently selected from H and C1-C12 groups, and R9, R10, R11, R12, R13, R14, R17, and R18 are independently selected from C1-C12 groups; selectively depositing a liner on a second surface by exposing the substrate to a second precursor; and removing the self-assembled monolayer (SAM). The first surface includes a metal, and the second surface includes a dielectric material.

2. The method as described in claim 1, wherein the step of selectively depositing the self-assembled monolayer (SAM) includes the step of forming the SAM on the first surface but not on the second surface.

3. The method as described in claim 1, wherein the step of selectively depositing the liner includes the step of forming the liner on the second surface but not on the first surface.

4. The method as described in claim 1 further includes the step of cleaning the substrate to form a generally oxide-free substrate surface before depositing the self-assembled monolayer (SAM).

5. The method as described in claim 1, wherein the first surface comprises one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and molybdenum (Mo).

6. The method as described in claim 1, further comprising the step of: densifying the lining.

7. The method as described in claim 4, wherein the step of densifying the liner includes physical vapor deposition (PVD).

8. The method as described in claim 1, further comprising the step of depositing an adhesive layer on the first surface and on the liner after removing the self-assembled monolayer (SAM).

9. The method as claimed in claim 1, wherein the at least one feature comprises one or more of a groove and a mesoscopic window.

10. The method of claim 1, further comprising the step of: depositing a conductive material in the at least one feature by exposing the substrate to a third precursor, the third precursor comprising a metal.

11. The method as described in claim 8, wherein the step of depositing the conductive material includes one or more of a bottom-up gap filling and a conformal gap filling.

12. The method as claimed in claim 1, wherein the first precursor has a structure of one of formula (i) or formula (ii): wherein R1, R2, R3 and R4 are independently selected from -R5OH, -CH(OH)R6 and -C(O)R7, and wherein R5, R6 and R7 are independently selected from H and C1 to C12 groups.

13. The method as described in claim 1, wherein the first precursor comprises a diketone or fumarate.

14. The method as claimed in claim 1, wherein the first precursor is selected from the group consisting of structures of formulas (iii), (iv), (v), and (vii): wherein R9, R10, R11, R12, R13, R14, R17, and R18 are independently selected from C1 to C12 groups.

15. The method as claimed in claim 1, wherein the first precursor comprises at least one unsaturated group.

16. The method as described in claim 1, wherein the first precursor comprises at least one alcohol group.

17. The method as described in claim 1, wherein the first precursor comprises at least one ketone group.

18. The method as described in claim 1, wherein the first precursor is a structure of formula (vii).

19. A method of forming a semiconductor structure, the method comprising the steps of: exposing a substrate to at least one first precursor to selectively deposit a self-assembled monolayer (SAM) on a first surface of the substrate, the substrate having at least one feature including the first surface and a second surface; exposing the substrate to a second precursor to selectively deposit a liner on the second surface; removing the self-assembled monolayer (SAM); and, if appropriate, densifying the liner, wherein the first surface comprises a metal selected from one or more of tungsten (W) and molybdenum (Mo), wherein the second surface comprises a dielectric material, and wherein the first precursor is selected from the group consisting of structures of formulas (iii), (iv), (v), and (vii): wherein R9, R10, R11, R12, R13, R14, R17, and R18 are independently selected from C1 to C12 alkyl groups.

20. The method of claim 19 further includes one or more of the following steps: cleaning the substrate to form a substantially oxide-free substrate prior to depositing the self-assembled monolayer (SAM); depositing an adhesive layer on the first surface and on the liner after removing the self-assembled monolayer (SAM); and depositing a conductive material in the at least one feature by exposing the substrate to a third precursor, the third precursor comprising a metal.

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