Frequency-locked loop logic circuit, oscillation system and operating method thereof

Abstract

Disclosed is a frequency-locked loop (FLL) logic circuit, an oscillating system, and a method of operating the FLL logic circuit. The FLL logic circuit includes: a validity signal generator configured to receive an external clock signal and determine whether a fault has occurred in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and the determination result of the validity signal generator; a synchronizer configured to synchronize the phase of the oscillator clock signal with the phase of the reference frequency clock signal; a clock counter configured to count the number of pulses of the oscillator clock signal during a reference time period; and a code limiter configured to determine a range of frequency selection values ​​for calibrating the operating frequency of the oscillator clock signal based on the counted number of pulses.

Description

Technical Field

[0001] The present disclosure relates to an oscillatory system, and more particularly, to an oscillatory system including a frequency-locked loop (FLL) and a method of operating the same. [Cross-Reference to Related Applications]

[0002] This application claims priority based on Korean Patent Application No. 10-2021-0089935, filed on Jul. 8, 2021, with the Korean Intellectual Property Office, and the entire disclosure of the Korean patent application is incorporated herein by reference. Background Art

[0003] In an integrated circuit (IC), an oscillation signal can be used in different ways. For example, the operation of an integrated circuit for processing digital signals can be synchronized with an oscillation signal (or a clock signal). The oscillation signal can also be used for processing analog signals, such as radio frequency (RF) band signals. When a relaxation oscillator is used instead of a phase-locked loop (PLL) as a clock source in many systems, there are advantages such as cost savings and power consumption reduction. However, a relaxation oscillator is vulnerable to temperature changes. The resistance of a resistor, which is a passive component, basically increases or decreases in proportion to temperature, thereby changing the frequency. This may inevitably lead to a fatal problem in the system. Summary of the Invention

[0004] Provided is an oscillatory system for performing frequency calibration based on a discontinuous source.

[0005] In the following description, additional aspects will be partially stated, and these additional aspects will become partially apparent from the present description or may be learned by practicing the provided embodiments.

[0006] According to one aspect of the present disclosure, a frequency-locked loop (FLL) logic circuit includes: a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and the determination result of the validity signal generator; a synchronizer configured to synchronize the phase of an oscillator clock signal with the phase of the reference frequency clock signal; a clock counter configured to count the number of pulses of the oscillator clock signal during a reference period; and a code limiter configured to determine a range of frequency selection values for calibrating the operating frequency of the oscillator clock signal based on the counted number of pulses.

[0007] According to one aspect of the present disclosure, an oscillatory system includes a relaxation oscillator and a frequency-locked loop (FLL) logic circuit. The relaxation oscillator includes a resistive element and a capacitor. The frequency-locked loop (FLL) logic circuit includes: a validity signal generator configured to receive an external clock signal and determine whether a fault exists in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and the determination result of the validity signal generator; a synchronizer configured to synchronize the phase of an oscillator clock signal with the phase of the reference frequency clock signal; a clock counter configured to count the number of pulses of the oscillator clock signal within a reference time; and a code limiter configured to determine a range of frequency selection values for calibrating the operating frequency of the oscillator clock signal based on the counted number of pulses.

[0008] According to one aspect of the present disclosure, a method for operating a frequency-locked loop (FLL) logic circuit includes: receiving an external clock signal; determining whether a glitch occurs in the external clock signal; generating a reference frequency clock signal based on determining that no glitch occurs in the external clock signal; synchronizing the phase of the reference frequency clock signal with the phase of an oscillator clock signal; performing clock counting; determining whether the operating frequency of the oscillator clock signal is the same as a target frequency based on the result of the clock counting; and adjusting a frequency selection value based on the result of the clock counting, where the frequency selection value is used for calibrating the operating frequency of the oscillator clock signal.

[0009] According to one aspect of the present disclosure, an oscillatory system includes a relaxation oscillator and a frequency-locked loop (FLL) logic circuit. The relaxation oscillator is configured to provide an oscillating clock signal. The frequency-locked loop (FLL) logic circuit is configured to: receive an external clock signal; adjust a frequency selection signal based on the external clock signal and the difference between the oscillating frequency and a target frequency during a first time period when the external clock signal is determined to be valid, in response to determining that the oscillating frequency of the oscillating clock signal does not match the target frequency, and provide the frequency selection signal to the relaxation oscillator, wherein the frequency selection signal enables the relaxation oscillator to adjust the oscillating frequency to match the target frequency; and maintain the frequency selection signal at a constant value during a second time period when the external clock signal is determined to be invalid. Brief Description of the Drawings

[0010] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram of an oscillatory system according to an exemplary embodiment. FIG. 2 is a block diagram of a frequency-locked loop (FLL) logic circuit according to an exemplary embodiment. FIG. 3 is a timing diagram of an oscillatory system according to an exemplary embodiment. FIG. 4 is a graph of an internal frequency selection signal versus frequency when a code limit enable signal is disabled according to an exemplary embodiment. FIG. 5 is a graph of an internal frequency selection signal versus frequency when a code limit enable signal is enabled according to an exemplary embodiment. FIG. 6 is a mapping table between temperature and an internal frequency selection signal according to an exemplary embodiment. FIG. 7 is a block diagram of an electronic device according to an exemplary embodiment. Embodiments

[0011] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0012] As a convention in the art, examples of blocks that implement one or more of the functions described may be set forth and illustrated. As shown in the figures, these blocks, which may be referred to herein as units or modules or similar names or may be referred to by names such as circuits, generators, frequency dividers, synchronizers, counters, limiters or similar names, may be physically implemented by analog or digital circuits (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits or similar circuits), and may be driven by firmware and software. For example, the circuits may be implemented in one or more semiconductor wafers or on a substrate support (such as a printed circuit board or similar component). The circuits included in a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware that implements some of the functions of the block and a processor that implements other functions of the block. Each block of the examples may be physically separated into two or more interacting and discrete blocks. Similarly, the blocks of the examples may be physically combined into more complex blocks.

[0013] FIG. 1 is a block diagram of an oscillatory system according to an exemplary embodiment.

[0014] Referring to FIG. 1, the oscillatory system 100 may include a frequency-locked loop (FLL) logic circuit 110 and a relaxation oscillator 120. According to an embodiment, the oscillatory system 100 may be implemented on a wafer of an integrated circuit (IC) including analog components.

[0015] According to an embodiment, the FLL logic circuit 110 may perform frequency calibration, thereby locking the oscillator frequency to a target frequency. The target frequency may be a frequency for internal operation of an electronic device including the oscillatory system 100.

[0016] According to an embodiment, the FLL logic circuit 110 may receive an external clock signal EXT_CLK and an initial frequency selection signal INIT_FSEL, and output an internal frequency selection signal INT_FSEL to the relaxation oscillator 120. The external clock signal EXT_CLK may correspond to a reference frequency of the relaxation oscillator 120.

[0017] The initial frequency selection signal INIT_FSEL may refer to an initial setting value for outputting a target frequency based on an external clock signal EXT_CLK. Even if the external clock signal EXT_CLK is the same, the frequency of the oscillator clock signal OSC_CLK may be different according to the process condition of the oscillator system 100. For example, a wafer including a first oscillator system may be formed in the central region of the wafer, and a wafer including a second oscillator system may be formed in the boundary region of the wafer. In this case, when the value of the internal frequency selection signal INT_FSEL is 100 relative to the external clock signal EXT_CLK, the wafer including the first oscillator system may output the target frequency as the frequency of the oscillator clock signal OSC_CLK, and when the value of the internal frequency selection signal INT_FSEL is 120, the wafer including the second oscillator system may output an oscillator frequency OSC_CLK having the same frequency as the target frequency. In other words, the value of the initial frequency selection signal INIT_FSEL is the initial value of the internal frequency selection signal INT_FSEL, and the oscillator system 100 may use the initial value to output the target frequency based on the external clock signal EXT_CLK.

[0018] According to an embodiment, the external clock signal EXT_CLK may not be input to or may not always be input to the FLL logic circuit 110. The external clock signal EXT_CLK may correspond to a discontinuous clock signal or an intermittent clock signal. For example, other modules (such as a memory and a central processing unit (CPU)) that receive the oscillator clock signal OSC_CLK may not operate during a specific time period, or may enter an idle mode in response to a user input. In this case, when other modules enter the idle mode, the oscillator system 100 may determine not to provide the oscillator clock signal OSC_CLK to other modules to reduce power consumption. According to the related art, the FLL logic circuit may receive a continuous clock signal and perform frequency calibration, but may not be able to perform frequency calibration for a discontinuous clock signal or an intermittent clock signal.

[0019] According to an embodiment, the relaxation oscillator 120 may be a module configured to output the oscillator clock signal OSC_CLK. The oscillator clock signal OSC_CLK may be transmitted to other modules that require a clock signal.

[0020] FIG. 2 is a block diagram of the FLL logic circuit 110 according to an exemplary embodiment.

[0021] Referring to FIG. 2, the FLL logic circuit 110 may include a validity signal generator 210, a clock divider 220, a synchronizer 230, a clock counter 240, and a code limiter 250.

[0022] The validity signal generator 210 may receive an external clock signal EXT_CLK and determine the validity of the external clock signal EXT_CLK. For example, the validity signal generator 210 may determine the validity signal based on whether there is a fault in the external clock signal EXT_CLK. When the magnitude of the external clock signal EXT_CLK exceeds a specific value, the validity signal generator 210 may determine that there is a fault in the external clock signal EXT_CLK. When there is a fault in the external clock signal EXT_CLK, the validity signal generator 210 may not output the validity signal FIN_VALID to the clock divider 220 or output a validity signal FIN_VALID that is at logic low. When the magnitude of the external clock signal EXT_CLK does not exceed a specific value, the validity signal generator 210 may generate a validity signal FIN_VALID (or a validity signal FIN_VALID that is at logic high) and transmit the validity signal FIN_VALID to the clock divider 220.

[0023] The clock divider 220 may receive the external clock signal EXT_CLK and the validity signal FIN_VALID, and output a reference frequency signal FREF based on the external clock signal EXT_CLK and the validity signal FIN_VALID. For example, when the validity signal FIN_VALID is at logic high, the clock divider 220 may output the reference frequency signal FREF by dividing the frequency of the external clock signal EXT_CLK. When the validity signal FIN_VALID is at logic low, since there is a fault in the external clock signal EXT_CLK, the clock divider 220 may bypass the generation of the reference frequency signal FREF. According to an embodiment, the clock divider 220 may receive the external clock signal EXT_CLK and output the reference frequency signal FREF by dividing the frequency of the external clock signal EXT_CLK by 500. For example, the frequency of the external clock signal EXT_CLK may be 100 megahertz, and the frequency of the reference frequency signal FREF output by the clock divider 220 may be 200 kilohertz.

[0024] The synchronizer 230 can receive the oscillator clock signal OSC_CLK from the relaxation oscillator 120 and receive the reference frequency signal FREF from the clock divider 220. The synchronizer 230 can include a D flip-flop and synchronize the phase of the reference frequency signal FREF with the phase of the oscillator clock signal OSC_CLK based on the D flip-flop.

[0025] The clock counter 240 can be a module configured to count the number of pulses of the input clock signal. The clock counter 240 can receive the oscillator clock signal OSC_CLK from the relaxation oscillator 120. The clock counter 240 can be configured to count the pulses of the oscillator clock signal OSC_CLK within a reference time. The reference time can be determined based on the amplitude of the reference frequency window FREF_WIN. The reference time can vary with the performance of a module (such as an oscillator) or similar parameters. For example, the reference time can be 1 millisecond (ms), but is not limited thereto. The clock counter 240 can be configured to input a count value to the code limiter 250. The code limiter 250 can determine the change of the internal frequency selection signal INT_FSEL (as shown in FIG. 3, for example) based on the count value. For example, when the code limit enable signal CODE_LIMIT_EN (as shown in FIG. 3, for example) is enabled, the code limiter 250 can output the change of the internal frequency selection signal INT_FSEL within the range between the upper limit and the lower limit based on the initial frequency selection signal INIT_FSEL.

[0026] FIG. 3 is a timing diagram of an oscillatory system according to an exemplary embodiment.

[0027] Referring to FIG. 3, the inverted reset signal RESET_B can transition to a logic high at time point T1. The FLL logic circuit 110 can receive the initial frequency selection signal INIT_FSEL in response to the transition of the inverted reset signal RESET_B and output the initial frequency selection signal INIT_FSEL to the relaxation oscillator 120. The relaxation oscillator 120 can output the oscillator clock signal OSC_CLK based on the initial frequency selection signal INIT_FSEL. The relaxation oscillator 120 can output the oscillator clock signal OSC_CLK with a target frequency based on the initial frequency selection signal INIT_FSEL. For example, the value of the initial frequency selection signal INIT_FSEL can be 100.

[0028] The external clock signal EXT_CLK can be input to the FLL logic circuit 110 at time point T2. The external clock signal EXT_CLK can be input to the validity signal generator 210 of the FLL logic circuit 110. The validity signal generator 210 can determine the validity of the external clock signal EXT_CLK during the cycle period between time point T2 and time point T3. For example, the validity signal generator 210 can monitor the amplitude of the external clock signal EXT_CLK during the cycle period between time point T2 and time point T3 and determine whether there is a fault in the external clock signal EXT_CLK.

[0029] At time point T3, the validity signal FIN_VALID can change from logic low to logic high. In other words, the validity signal generator 210 may not detect the signal amplitude of the fault in the external clock signal EXT_CLK input from time point T2, and thus can change the validity signal FIN_VALID indicating the validity of the external clock signal EXT_CLK to logic high. When the validity signal FIN_VALID changes to logic high, frequency calibration can be performed by the FLL logic circuit 110. In other words, during the cycle period between time point T3 and time point T4, the FLL logic circuit 110 can change the internal frequency selection signal INT_FSEL, thereby causing the frequency of the oscillator clock signal OSC_CLK to follow the target frequency. Since the temperature does not change during the cycle period between time point T3 and time point T4, and the internal frequency selection signal INT_FSEL may include a small error in the frequency of the oscillator clock signal OSC_CLK, the value of the internal frequency selection signal INT_FSEL can vary between, for example, 101 and 99.

[0030] At time point T4, the frequency of the oscillator clock signal OSC_CLK may decrease. Referring to FIG. 3, the temperature of the oscillatory system 100 can increase from room temperature to a high temperature at time point T4. In an embodiment, the room temperature can be 25 °C, and the high temperature can be 100 °C. The relaxation oscillator 120 can include a resistive element, and the resistance of the resistive element can increase as the temperature increases. As the resistance of the resistive element increases, the frequency at which the relaxation oscillator 120 resonates may decrease.

[0031] When the operating frequency of the oscillator clock signal OSC_CLK rapidly decreases at time point T4, the FLL logic circuit 110 can adjust the value of the internal frequency selection signal INT_FSEL, thereby enabling the operating frequency to follow the target frequency. For example, from time point T4 when the operating frequency of the oscillator clock signal OSC_CLK rapidly decreases until time point T5 when the operating frequency of the oscillator clock signal OSC_CLK is the same as the target frequency, the FLL logic circuit 110 can increase the value of the internal frequency selection signal INT_FSEL so that the operating frequency is the same as the target frequency in each frequency window. For example, at time point T5, the value of the internal frequency selection signal INT_FSEL can be approximately 120. Although the operating frequency of the oscillator clock signal OSC_CLK is the same as the target frequency at time point T5, the frequency calibration can continue until time point T6. In other words, the internal frequency selection signal INT_FSEL can change instantaneously within a range near the value 120.

[0032] The validity signal FIN_VALID can transition to logic low at time point T6. According to an embodiment, the validity signal generator 210 can be configured to generate the validity signal FIN_VALID during a specific time period. Since the external clock signal EXT_CLK may be a non - continuous clock source or an intermittent clock source, it may not be known when the input of the external clock signal EXT_CLK is interrupted. Therefore, the validity signal generator 210 can output the validity signal FIN_VALID only during a specific number of clock periods. When the validity signal FIN_VALID transitions to logic low at time point T6, the internal frequency selection signal INT_FSEL can be maintained at a fixed value. As described above, in order to enable the operating frequency of the oscillator clock signal OSC_CLK, which has rapidly decreased at time point T4, to follow the target frequency, the value of the internal frequency selection signal INT_FSEL can be maintained at approximately 120 from time point T5 to time point T6. At time point T6, when the validity signal FIN_VALID transitions to logic low, the value of the internal frequency selection signal INT_FSEL can be 120.

[0033] The frequency of the oscillator clock signal OSC_CLK can increase at time point T7. The temperature of the oscillatory system 100 can decrease from a high temperature to room temperature at time point T7. Since the operating frequency of the oscillator clock signal OSC_CLK is set to match the target frequency at high temperature during the period between time point T5 and time point T6, the operating frequency of the oscillator clock signal OSC_CLK may increase even if the temperature changes from a high temperature to room temperature. Since the resistance of the resistive element of the relaxation oscillator 120 is proportional to the temperature, the resistance of the resistive element can decrease as the temperature decreases. Since the resistance of the relaxation oscillator 120 is inversely proportional to the resonance frequency of the relaxation oscillator 120, the resonance frequency of the relaxation oscillator 120 can increase as the resistance of the relaxation oscillator 120 decreases.

[0034] The operating frequency of the oscillator clock signal OSC_CLK can increase at time point T8. The temperature of the oscillatory system 100 can decrease from room temperature to a low temperature at time point T8. The description given above regarding time point T7 can be applied to the increase in the operating frequency of the oscillator clock signal OSC_CLK at time point T8, and thus will not be repeated here. During the period between time point T6 and time point T8 when the validity signal FIN_VALID is maintained at logic low, the value of the internal frequency selection signal INT_FSEL for following the target frequency can be fixed even if the operating frequency of the oscillator clock signal OSC_CLK is different from the target frequency.

[0035] The external clock signal EXT_CLK can be input to the FLL logic circuit 110 at time point T9. The validity signal generator 210 of the FLL logic circuit 110 can determine the validity of the external clock signal EXT_CLK during the period between time point T9 and time point T10. The period for determining the validity of the external clock signal EXT_CLK can be the same as the period between time point T2 and time point T3.

[0036] The validity signal FIN_VALID can transition from logic low to logic high at time point T10. When the external clock signal EXT_CLK received during the period between time point T9 and time point T10 is free of faults, the validity signal generator 210 can change the validity signal FIN_VALID to logic high. The FLL logic circuit 110 can start frequency calibration based on the logic high of the validity signal FIN_VALID. Referring back to FIG. 2, based on the transition of the validity signal FIN_VALID to logic high, the clock divider 220 generates a reference frequency signal FREF, compares the operating frequency of the oscillator clock signal OSC_CLK with the frequency of the reference frequency signal FREF, and adjusts the value of the internal frequency selection signal INT_FSEL such that the operating frequency of the oscillator clock signal OSC_CLK follows the target frequency.

[0037] At time point T10 when the validity signal FIN_VALID transitions to logic high, the value of the internal frequency selection signal INT_FSEL can be 120. At time point T10, the operating frequency of the oscillator clock signal OSC_CLK may be higher than the target frequency. This is because the temperature decreased twice at time points T7 and T8 previously, and frequency calibration was not performed. The value of the internal frequency selection signal INT_FSEL can be decreased starting from time point T10 such that the operating frequency of the oscillator clock signal OSC_CLK is the same as the target frequency. For example, the value of the internal frequency selection signal INT_FSEL can be decreased to 80 at time point T11.

[0038] The temperature can increase slowly starting from time point T11. While the temperature increases or decreases rapidly at time points T4, T7, or T8, the temperature can increase slowly and linearly from time point T11 to time point T12. During the period between time point T11 and time point T12, the value of the internal frequency selection signal INT_FSEL can also increase linearly corresponding to the linearly increasing temperature. The operating frequency of the oscillator clock signal OSC_CLK reaches the target frequency at time point T11, and the temperature does not increase rapidly but increases linearly from time point T11 to time point T12, and thus, the operating frequency of the oscillator clock signal OSC_CLK can be the same as the target frequency or within the error margin relative to the target frequency. Since the internal frequency selection signal INT_FSEL increases when the temperature increases slowly from time point T11 to time point T12, the frequency calibration can be regarded as being performed in real time.

[0039] The validity signal FIN_VALID can transition from logic high to logic low at time point T13. Since time point T13, the value of the internal frequency selection signal INT_FSEL can be maintained constant. For example, the value of the internal frequency selection signal INT_FSEL can be 101.

[0040] The code limit enable signal CODE_LIMIT_EN can be enabled at time point T14. The code limit enable signal CODE_LIMIT_EN can limit the range of the value of the internal frequency selection signal INT_FSEL based on the initial frequency selection signal INIT_FSEL. For example, when the code limit enable signal CODE_LIMIT_EN transitions to logic high, based on the value of the initial frequency selection signal INIT_FSEL, the internal frequency selection signal INT_FSEL can be limited to a 10% change, and the value of the initial frequency selection signal INIT_FSEL can be, for example, 100. Thus, when the code limit enable signal CODE_LIMIT_EN is enabled, the value of the internal frequency selection signal INT_FSEL is prevented from changing excessively so that the operating frequency of the oscillator clock signal OSC_CLK can follow the target frequency even when the temperature abnormally increases or decreases, and the swing width of the internal frequency selection signal INT_FSEL is fixed. When the code limit enable signal CODE_LIMIT_EN is enabled and the temperature changes greatly, the operating frequency of the oscillator clock signal OSC_CLK may not follow the target frequency, but the code limit value can be determined in advance, so that the error between the operating frequency and the target frequency is within the error range of the oscillating system 100. In other words, referring to Figure 3, when the internal frequency selection signal INT_FSEL has a 10% change based on the value 100 of the initial frequency selection signal INIT_FSEL, the range of the value of the internal frequency selection signal INT_FSEL can be 90 to 110.

[0041] As the temperature rapidly increases at time point T15, the operating frequency of the oscillator clock signal OSC_CLK may rapidly decrease. The external clock signal EXT_CLK may be newly input at time point T16, and the validity signal FIN_VALID may transition to logic high at time point T17. Frequency calibration may be performed by the FLL logic circuit 110 starting from time point T17. When frequency calibration starts at time point T17, the internal frequency selection signal INT_FSEL starts from the value 101. Since the operating frequency of the oscillator clock signal OSC_CLK is lower than the target frequency at time point T17, the internal frequency selection signal INT_FSEL may start to increase to increase the operating frequency of the oscillator clock signal OSC_CLK. However, since the code limit enable signal CODE_LIMIT_EN has been enabled, the maximum allowable value of the internal frequency selection signal INT_FSEL is 110. When the code limit enable signal CODE_LIMIT_EN is not enabled, the value of the internal frequency selection signal INT_FSEL may increase to 120 so that the operating frequency of the oscillator clock signal OSC_CLK follows the target frequency. However, the maximum value of the internal frequency selection signal INT_FSEL is 110, and thus, the operating frequency of the oscillator clock signal OSC_CLK approaches a value lower than the target frequency.

[0042] The validity signal FIN_VALID may transition to logic low at time point T18, and the internal frequency selection signal INT_FSEL may be maintained at a constant value. Due to the influence of the code limit enable signal CODE_LIMIT_EN, the constant value maintained by the internal frequency selection signal INT_FSEL starting from time point T18 may be 110. Although the operating frequency is lower than the target frequency at the high temperature at time point T18, when the temperature rapidly decreases to a low temperature at time point T19, the oscillator clock signal OSC_CLK operates at a frequency higher than the target frequency. Compared to the error in the operating frequency at the low temperature at time point T8, the error in the operating frequency at the low temperature at time point T19 after the code limit enable signal CODE_LIMIT_EN is enabled is reduced. Similarly, compared to the error in the operating frequency at the high temperature at time point T4 when the code limit enable signal CODE_LIMIT_EN is not enabled, the error in the operating frequency at the high temperature at time point T18 after the code limit enable signal CODE_LIMIT_EN is enabled is reduced.

[0043] FIG. 4 is a graph of the internal frequency selection signal INT_FSEL relative to the frequency when the code limit enable signal CODE_LIMIT_EN is not enabled according to an exemplary embodiment.

[0044] Referring to FIG. 4, the internal frequency selection signal INT_FSEL can be set to the value of the initial frequency selection signal INIT_FSEL. The initial frequency selection signal INIT_FSEL can correspond to a trim value for outputting a target frequency in consideration of component characteristics that may vary according to the chip manufacturing process. The relaxation oscillator 120 can receive the internal frequency selection signal INT_FSEL and output an oscillator clock signal OSC_CLK that operates at the target frequency.

[0045] According to an embodiment, when the temperature rapidly decreases, the operating frequency of the oscillator clock signal OSC_CLK can follow the path to increase. In other words, the path can correspond to a situation where the validity signal FIN_VALID is also logic low even though the temperature has rapidly decreased. Since the validity signal FIN_VALID is logic low, the internal frequency selection signal INT_FSEL can be maintained constant. In other words, the operating frequency of the oscillator clock signal OSC_CLK can increase along the Y-axis to exceed the frequency of the low-temperature graph LOW_TEMP of the same internal frequency selection signal INT_FSEL value.

[0046] According to an embodiment, when an external clock signal EXT_CLK is received after the operating frequency of the oscillator clock signal OSC_CLK has increased along the path frequency calibration can be performed based on the path In other words, when the external clock signal EXT_CLK is received and is determined to be valid due to the absence of a fault in the external clock signal EXT_CLK, the validity signal FIN_VALID can transition to logic high, and frequency calibration can start. In the situation shown in FIG. 4, since there is no code limit on the internal frequency selection signal INT_FSEL, frequency calibration can be performed while changing the value of the internal frequency selection signal INT_FSEL so that the operating frequency of the oscillator clock signal OSC_CLK is the same as the target frequency along the low-temperature graph LOW_TEMP. Referring to FIG. 4, the internal frequency selection signal INT_FSEL can be decreased to a first code value.

[0047] According to an embodiment, the temperature can change from a low temperature to room temperature. The operating frequency of the oscillator clock signal OSC_CLK can follow the path to decrease. In other words, the path This may correspond to a situation where, despite a rapid increase in temperature, the validity signal FIN_VALID is also logic low. Since the validity signal FIN_VALID is logic low, the internal frequency selection signal INT_FSEL can be maintained at the first code value. The operating frequency of the oscillator clock signal OSC_CLK can be reduced along the Y-axis of the first code value to a frequency that crosses the room temperature graph ROOM_TEMP. The reduced frequency may correspond to the first frequency FIRST_FREQ.

[0048] According to an embodiment, when the temperature rapidly increases, the operating frequency of the oscillator clock signal OSC_CLK can follow a path to decrease. In other words, the path may correspond to a situation where, despite a rapid increase in temperature, the validity signal FIN_VALID is also logic low. Since the validity signal FIN_VALID is logic low, the internal frequency selection signal INT_FSEL can be maintained constant. The operating frequency of the oscillator clock signal OSC_CLK can be reduced along the Y-axis to a frequency that crosses the high temperature graph HIGH_TEMP, so that the internal frequency selection signal INT_FSEL is maintained at the same X value.

[0049] According to an embodiment, when an external clock signal EXT_CLK is received after the operating frequency of the oscillator clock signal OSC_CLK follows a path to decrease, frequency calibration can be performed based on the path In other words, when the external clock signal EXT_CLK is received and is determined to be valid due to the absence of a fault in the external clock signal EXT_CLK, the validity signal FIN_VALID can transition to logic high, and frequency calibration can begin. In the situation shown in FIG. 4, since there are no code restrictions on the internal frequency selection signal INT_FSEL, frequency calibration can be performed while changing the value of the internal frequency selection signal INT_FSEL so that the operating frequency of the oscillator clock signal OSC_CLK is the same as the target frequency along the high temperature graph HIGH_TEMP. Referring to FIG. 4, the internal frequency selection signal INT_FSEL can be increased to the second code value.

[0050] According to an embodiment, the temperature can change from a high temperature to room temperature. The operating frequency of the oscillator clock signal OSC_CLK can follow a path to increase. In other words, the path It can correspond to a situation where, despite a rapid temperature decrease, the validity signal FIN_VALID is also logic low. Since the validity signal FIN_VALID is logic low, the internal frequency selection signal INT_FSEL can be maintained at the second code value. The operating frequency of the oscillator clock signal OSC_CLK can increase along the Y-axis of the second code value to exceed the frequency of the room temperature graph ROOM_TEMP. The increased frequency can correspond to the second frequency SECOND_FREQ. In other words, according to the path to the maximum error range MAX FREQ_ERROR of the operating frequency of the oscillator clock signal OSC_CLK can be the difference between the second frequency SECOND_FREQ and the first frequency FIRST_FREQ.

[0051] Figure 5 is a graph of the internal frequency selection signal INT_FSEL versus frequency when the code limit enable signal CODE_LIMIT_EN is enabled according to an exemplary embodiment.

[0052] Referring to Figure 5, when the temperature rapidly decreases, the operating frequency of the oscillator clock signal OSC_CLK can increase along the path increase. In other words, the path can correspond to a situation where, despite a rapid temperature decrease, the validity signal FIN_VALID is also logic low. Since the validity signal FIN_VALID is logic low, the internal frequency selection signal INT_FSEL can be maintained constant. In other words, the operating frequency of the oscillator clock signal OSC_CLK can increase along the Y-axis to exceed the frequency of the low temperature graph LOW_TEMP of the same internal frequency selection signal INT_FSEL value.

[0053] According to an embodiment, when an external clock signal EXT_CLK is received after the operating frequency of the oscillator clock signal OSC_CLK increases along the path increase, frequency calibration can be performed based on the path In other words, when the external clock signal EXT_CLK is received and is determined to be valid due to the absence of a fault in the external clock signal EXT_CLK, the validity signal FIN_VALID can transition to logic high, and frequency calibration can begin.

[0054] When the code limit enabling signal CODE_LIMIT_EN is enabled, the value of the internal frequency selection signal INT_FSEL can be limited. The value of the internal frequency selection signal INT_FSEL can be decreased so that the operating frequency of the oscillator clock signal OSC_CLK follows the target frequency on the low temperature graph LOW_TEMP. At this time, the value of the internal frequency selection signal INT_FSEL can be decreased to the lower limit based on the value of the initial frequency selection signal INIT_FSEL. In other words, even if frequency calibration is performed, the operating frequency of the oscillator clock signal OSC_CLK may not be decreased to the target frequency.

[0055] According to an embodiment, the temperature can change from a low temperature to room temperature. The operating frequency of the oscillator clock signal OSC_CLK can decrease along the path decrease. In other words, the path can correspond to a situation where the validity signal FIN_VALID is also logic low even though the temperature has rapidly increased. Since the validity signal FIN_VALID is logic low, the internal frequency selection signal INT_FSEL can be maintained at the lower limit of the code limit CODE_LIMIT. The operating frequency of the oscillator clock signal OSC_CLK can decrease along the Y-axis of the lower limit of the code limit CODE_LIMIT to cross the frequency of the room temperature graph ROOM_TEMP. The decreased frequency can correspond to the third frequency THIRD_FREQ.

[0056] According to an embodiment, when the temperature rapidly increases, the operating frequency of the oscillator clock signal OSC_CLK can decrease along the path decrease. In other words, the path can correspond to a situation where the validity signal FIN_VALID is also logic low even though the temperature has rapidly increased. Since the validity signal FIN_VALID is logic low, the internal frequency selection signal INT_FSEL can be maintained constant. The operating frequency of the oscillator clock signal OSC_CLK can decrease along the Y-axis to cross the frequency of the high temperature graph HIGH_TEMP so that the internal frequency selection signal INT_FSEL is maintained at the same X value.

[0057] According to an embodiment, when an external clock signal EXT_CLK is received after the operating frequency of the oscillator clock signal OSC_CLK has decreased along the path decrease, it can be based on the path Frequency calibration is performed. In other words, when an external clock signal EXT_CLK is received and is determined to be valid because there is no fault in the external clock signal EXT_CLK, the validity signal FIN_VALID can transition to logic high, and frequency calibration can start.

[0058] When the code limit enable signal CODE_LIMIT_EN is enabled, the value of the internal frequency selection signal INT_FSEL can be limited. The value of the internal frequency selection signal INT_FSEL can be increased so that the operating frequency of the oscillator clock signal OSC_CLK follows the target frequency on the high temperature graph HIGH_TEMP. At this time, the value of the internal frequency selection signal INT_FSEL can be increased to the upper limit based on the value of the initial frequency selection signal INIT_FSEL. In other words, even if frequency calibration is performed, the operating frequency of the oscillator clock signal OSC_CLK may not increase to the target frequency.

[0059] According to an embodiment, the temperature can change from a high temperature to room temperature. The operating frequency of the oscillator clock signal OSC_CLK can increase along the path Increase. In other words, the path can correspond to a situation where the validity signal FIN_VALID is logic low even though the temperature has rapidly decreased. Since the validity signal FIN_VALID is logic low, the internal frequency selection signal INT_FSEL can be maintained at the upper limit of the code limit CODE_LIMIT. The operating frequency of the oscillator clock signal OSC_CLK can increase along the Y-axis of the upper limit of the code limit CODE_LIMIT to exceed the frequency of the room temperature graph ROOM_TEMP. The increased frequency can correspond to the fourth frequency FOURTH_FREQ. In other words, when the code limit enable signal CODE_LIMIT_EN is enabled, the operating frequency of the oscillator clock signal OSC_CLK according to the path to the path The limit error range LIMIT_FREQ_ERROR of the operating frequency can be the difference between the third frequency THIRD_FREQ and the fourth frequency FOURTH_FREQ. Referring to FIGS. 4 and 5, it can be seen that when the code limit enable signal CODE_LIMIT_EN is enabled and the value of the internal frequency selection signal INT_FSEL is limited, the amplitude of the frequency error decreases.

[0060] FIG. 6 is a mapping table between temperature and an internal frequency selection signal INT_FSEL according to an exemplary embodiment.

[0061] Referring to FIG. 6, an electronic device including an oscillatory system 100 can store a mapping table between temperature and an internal frequency selection signal INT_FSEL.

[0062] While the code limit enable signal CODE_LIMIT_EN is not enabled, the mapping table can store the code value of the internal frequency selection signal INT_FSEL according to temperature changes. For example, the mapping table can store 100 as the value of the initial frequency selection signal INIT_FSEL. Thereafter, when the temperature increases to 50 °C, the value of the internal frequency selection signal INT_FSEL can be changed so that the operating frequency of the oscillator clock signal OSC_CLK follows the target frequency. When the operating frequency of the oscillator clock signal OSC_CLK is the same as the target frequency, the electronic device can store the value of the internal frequency selection signal INT_FSEL in the mapping table. The stored value of the internal frequency selection signal INT_FSEL can be 105. Similarly, when the temperature increases to 75 °C, the value of the internal frequency selection signal INT_FSEL when the frequency calibration is completed can be 110. When the temperature increases to 100 °C, the value of the internal frequency selection signal INT_FSEL when the frequency calibration is completed can be 120.

[0063] When the temperature changes and the number of times of completing the frequency calibration increases with the change of temperature, the electronic device can store a representative value in the cumulative value of the internal frequency selection signal INT_FSEL in the mapping table. The representative value can correspond to the maximum value, the minimum value or the average value of the cumulative value of the internal frequency selection signal INT_FSEL, but the embodiment is not limited thereto.

[0064] According to an embodiment, when an external clock signal EXT_CLK is not received, the oscillatory system 100 can receive current temperature information from a temperature sensor and input the value of the internal frequency selection signal INT_FSEL mapped to the current temperature information to the relaxation oscillator 120. Therefore, even if an external clock signal EXT_CLK is not received, the oscillatory system 100 can actively perform frequency calibration.

[0065] According to an embodiment, an oscillating system includes a relaxation oscillator and a frequency-locked loop (FLL) logic circuit. The relaxation oscillator is configured to provide an oscillating clock signal. The frequency-locked loop (FLL) logic circuit is configured to: receive an external clock signal during a first time period when the external clock signal is determined to be valid, based on determining that an oscillation frequency of the oscillating clock signal does not match a target frequency; adjust a frequency selection signal based on the external clock signal and a difference between the oscillation frequency and the target frequency; and provide the frequency selection signal to the relaxation oscillator.

[0066] Wherein the frequency selection signal causes the relaxation oscillator to adjust the oscillation frequency to match the target frequency and maintains the frequency selection signal at a constant value during a second time period when the external clock signal is determined to be invalid.

[0067] According to an embodiment, during the first time period, the FLL logic circuit is further configured to adjust the frequency selection signal within a pre-determined range.

[0068] According to an embodiment, the FLL logic circuit is further configured to: determine a temperature of the oscillating system during the second time period; and select the constant value from a plurality of pre-determined constant values based on the temperature.

[0069] FIG. 7 is a block diagram of an electronic device 2000 according to an exemplary embodiment.

[0070] Referring to FIG. 7, the electronic device 2000 may include a receiver 2012, a transmitter 2016, a communication module 2020, an antenna, an external input / output (I / O) device 2040, and an oscillator system 2042. According to an exemplary embodiment, the receiver 2012 may include an FLL 2100. According to an exemplary embodiment, the FLL 2100 may include a relaxation oscillator 120 and FLL logic circuitry 110. According to an exemplary embodiment, the transmitter 2016 may include an FLL 2100. The receiver 2012 may receive an analog signal from the outside via the antenna, convert the analog signal into a digital signal using the output signal of its FLL 2100, and provide the digital signal to the communication module 2020. The transmitter 2016 may receive a digital signal from the communication module 2020, convert the digital signal into an analog signal using the output signal of its FLL 2100, and output the analog signal via the antenna. The oscillator system 2042 may include a crystal oscillator (XO), a voltage controlled crystal oscillator (VCXO), or a temperature compensated crystal oscillator (TCXO).

[0071] The communication module 2020 may include a modem processor 2022, a reduced instruction set computer (RISC) / digital signal processor (DSP) 2024, a controller / processor 2026, a memory 2028, an I / O device 2030, and an FLL 2100.

[0072] The modem processor 2022 may perform processing operations such as encoding, modulation, demodulation, and decoding to transmit and receive data. The RISC / DSP 2024 may perform general-purpose processing operations or dedicated processing operations in the electronic device 2000.

[0073] The controller / processor 2026 may control blocks of the communication module 2020. The memory 2028 may store data, various instruction codes, and the mapping table shown in FIG. 6. The I / O device 2030 may communicate with the external I / O device 2040. The communication module 2020 (e.g., the modem processor 2022 or the controller / processor 2026) may perform processing operations necessary for communication using the output signal generated by the FLL 2100.

[0074] Although the embodiments have been specifically shown and described, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the following claims for patent.

[0075] 100, 2042: Oscillatory system 110: Frequency Locked Loop (FLL) logic circuit 120: Relaxation oscillator 210: Validity signal generator 220: Clock divider 230: Synchronizer 240: Clock counter 250: Code limiter 2000: Electronic device 2012: Receiver 2016: Transmitter 2020: Communication module 2022: Modem processor 2024: Reduced Instruction Set Computer (RISC) / Digital Signal Processor (DSP) 2026: Controller / Processor 2028: Memory 2030: I / O device 2040: External Input / Output (I / O) device 2100: Frequency Locked Loop (FLL) CODE_LIMIT: Code limit CODE_LIMIT_EN: Code limit enable signal EXT_CLK: External clock signal FIN_VALID: Validity signal FREF: Reference frequency signal FREF_WIN: Reference frequency window HIGH_TEMP: High temperature graph INIT_FSEL: Initial frequency selection signal INT_FSEL: Internal frequency selection signal LIMIT_FREQ_ERROR: Limit error range LOW_TEMP: Low temperature graph MAX FREQ_ERROR: Maximum error range OSC_CLK: Oscillator clock signal RESET_B: Inverted reset signal ROOM_TEMP: Room temperature curve T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19: Time points , , , , , , , , , , , : Path

Claims

1. A frequency-locked loop (FLL) logic circuit, comprising: A validity signal generator is configured to receive an external clock signal and determine whether a fault has occurred in the external clock signal. A clock divider is configured to generate a reference frequency clock signal based on the external clock signal and the determination result of the validity signal generator; A synchronizer is configured to synchronize the phase of the oscillator clock signal with the phase of the reference frequency clock signal; a clock counter is configured to count the number of pulses of the oscillator clock signal during the reference time. And a code limiter, configured to determine a range of frequency selection values ​​for calibrating the operating frequency of the oscillator clock signal based on the number of counted pulses.

2. The frequency-locked loop logic circuit as described in claim 1, wherein the range is a predetermined range determined based on an initial frequency selection value.

3. The frequency-locked loop logic circuit as claimed in claim 1, wherein the validity signal generator is further configured to: monitor the external clock signal for a predetermined time period; generate a validity signal based on determining that the fault has not occurred in the external clock signal and transmit the validity signal to the clock divider, wherein the validity signal indicates that the external clock signal is valid.

4. The frequency-locked loop logic circuit as claimed in claim 3, wherein the clock divider is further configured to generate a clock signal having a target frequency based on the validity signal received from the validity signal generator and to transmit the clock signal to the synchronizer.

5. The frequency-locked loop logic circuit as claimed in claim 4, wherein the clock counter is further configured to: determine whether the operating frequency is the same as the target frequency based on the number of pulses; and output a frequency change value that enables the operating frequency to be the same as the target frequency based on the fact that the operating frequency is different from the target frequency.

6. The frequency-locked loop logic circuit as claimed in claim 1, wherein the validity signal generator is further configured to generate a validity signal and transmit the validity signal to the clock divider based on determining that the fault has occurred in the external clock signal, and wherein the validity signal indicates that the external clock signal is invalid.

7. The frequency-locked loop logic circuit as claimed in claim 6, wherein the clock divider is further configured to determine that the external clock signal is invalid and bypass the generation of the reference frequency clock signal.

8. The frequency lock loop logic circuit as claimed in claim 1, wherein the code limiter is further configured to: pre-store an upper limit and a lower limit of the frequency selection value; and limit the range of frequency variation values ​​to the upper and lower limits based on a control signal indicating the activation of the code limit, wherein the frequency variation values ​​enable the operating frequency to be the same as the target frequency.

9. The frequency-locked loop logic circuit as claimed in claim 1, wherein the external clock signal corresponds to a clock signal that is not continuously input.

10. An oscillating system, comprising: Relaxed oscillators, including resistive elements and capacitors; The circuit also includes a frequency-locked loop (FLL) logic circuit, comprising: a validity signal generator configured to receive an external clock signal and determine whether a fault exists in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and the determination result of the validity signal generator; a synchronizer configured to synchronize the phase of the oscillator clock signal with the phase of the reference frequency clock signal; a clock counter configured to count the number of pulses of the oscillator clock signal within a reference time; and a code limiter configured to determine a range of frequency selection values ​​for calibrating the operating frequency of the oscillator clock signal based on the counted number of pulses.

11. The oscillating system as claimed in claim 10, wherein the range is a predetermined range determined based on an initial frequency selection value.

12. The oscillating system of claim 10, wherein the validity signal generator is further configured to: monitor the external clock signal for a predefined time; and generate a validity signal and transmit the validity signal to the clock divider based on determining that the fault has not occurred in the external clock signal, wherein the validity signal indicates that the external clock signal is valid.

13. The oscillating system as claimed in claim 12, wherein the clock divider is further configured to generate a clock signal having a target frequency based on the validity signal received from the validity signal generator and to transmit the clock signal to the synchronizer.

14. The oscillating system of claim 13, wherein the clock counter is further configured to: determine whether the operating frequency is the same as the target frequency based on the number of pulses; and output a frequency change value that enables the operating frequency to be the same as the target frequency based on the fact that the operating frequency is different from the target frequency.

15. The oscillating system of claim 10, wherein the validity signal generator is further configured to generate a validity signal and transmit the validity signal to the clock divider based on determining that the fault has occurred in the external clock signal, and wherein the validity signal indicates that the external clock signal is invalid.

16. The oscillating system as claimed in claim 15, wherein the clock divider is further configured to determine that the external clock signal is invalid and bypass the generation of the reference frequency clock signal.

17. The oscillating system of claim 10, wherein the code limiter is further configured to: pre-store an upper limit and a lower limit of the frequency selection value; and limit the range of frequency variation values ​​to the upper and lower limits based on a control signal indicating the activation of code restriction, wherein the frequency variation values ​​enable the operating frequency to be the same as the target frequency.

18. The oscillating system as claimed in claim 10, wherein the external clock signal corresponds to an input clock signal that is not continuously input.

19. A method of operating a frequency-locked loop (FLL) logic circuit, the method comprising: Receive external clock signals; Determine whether a fault has occurred in the external clock signal; A reference frequency clock signal is generated based on the determination that no fault has occurred in the external clock signal; the phase of the reference frequency clock signal is synchronized with the phase of the oscillator clock signal; clock counting is performed; based on the result of the clock counting, it is determined whether the operating frequency of the oscillator clock signal is the same as the target frequency; and a frequency selection value is adjusted based on the result of the clock counting, wherein the frequency selection value is used to calibrate the operating frequency of the oscillator clock signal.

20. The method of operation as described in claim 19 further includes receiving an enable control signal for an indication code restriction, wherein the control signal corresponds to a signal that commands a restriction on a range of frequency variation values, the frequency variation values ​​such that the operating frequency is the same as the target frequency.

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