Analog-to-digital conversion

Abstract

A device for analog-to-digital conversion is disclosed. In an exemplary embodiment, the device includes an analog-to-digital converter (ADC). The ADC includes a reference cross-detector having inputs and outputs. The ADC also includes a jump generator coupled between the output and input of the reference cross-detector. The ADC further includes a voltage shifter coupled between the output and input of the reference cross-detector.

Description

Technical Field

[0001] In general, the subject matter of this case concerns signal communication or signal processing using electronic devices; more specifically, it concerns analog-to-digital conversion. Prior Technology

[0002] Electronic devices include traditional computing devices such as desktop computers, laptops, smartphones, wearable devices (e.g., smartwatches), and internet servers. However, electronic devices also include other types of computing devices, such as personal voice assistants (e.g., smart speakers), wireless access points or routers, thermostats and other sensors or automatic controllers, robots, automotive electronics, devices embedded in other machines (e.g., refrigerators and industrial tools), and Internet of Things (IoT) devices. These diverse electronic devices provide services related to productivity, communication, social interaction, security, safety, remote system management, entertainment, transportation, and information dissemination. Therefore, electronic devices play a crucial role in many aspects of modern society.

[0003] In today's interconnected world, many services provided by electronic devices rely at least in part on electronic communications. For example, electronic communications include the exchange of wireless or wired signals between two or more electronic devices via one or more networks (e.g., the Internet, Wi-Fi, or cellular networks). Therefore, electronic communications can include both wireless and wired transmission and reception. To conduct such electronic communications, electronic devices can use transceivers (such as wireless transceivers for wireless communications).

[0004] Electronic communication can be achieved by transmitting signals between two wireless transceivers at two different electronic devices. For example, using a wireless transmitter, a smartphone can send wireless signals to a base station via broadcast media as part of uplink communication to support mobile services. Using a wireless receiver, a smartphone can receive wireless signals transmitted from a base station via broadcast media as part of downlink communication to enable mobile services. Mobile services using a smartphone can include making voice and video calls, engaging in social media interactions, sending messages, watching movies, sharing videos, performing searches, obtaining map information or navigation instructions, finding friends, participating in location-based services, transferring money, and obtaining other services (such as transportation).

[0005] Many of these mobile services rely, at least in part, on the transmission and reception of wireless signals between two or more electronic devices. Therefore, scientists, electrical engineers, and other electronic device designers strive to develop wireless transceivers that can effectively utilize wireless signals to provide these and other mobile services. Summary of the Invention

[0006] To facilitate the transmission and reception of wireless signals, electronic devices can use wireless interface devices including wireless transceivers. The wireless transceiver, along with other components of the electronic device, can include analog-to-digital converters (ADCs). One type of ADC (an asynchronous digital leap ADC) may have characteristics that result in slower ADC operation and / or troublesome residual values ​​in pipelined ADCs. In an exemplary embodiment, an asynchronous digital leap ADC may include a reference cross-detector, a leap generator, and a voltage shifter or offset adjuster. The voltage shifter can shift the voltage of the input signal by a voltage shift amount based on the value of the input signal to reduce the extent of the leap ramp before the digital value is locked. By reducing the leap range, the digital leap ADC can perform faster. The offset adjuster can adjust the output voltage by a voltage offset amount to reduce the magnitude of the voltage "overshoot" from the leap process. By reducing the overshoot magnitude, the residual signal in pipelined ADC applications can be scaled more fully to improve the accuracy of subsequent analog-to-digital conversion stages. An ADC (which includes the analog-to-digital conversion stage of a pipelined ADC) may include a voltage shifter and an offset adjuster.

[0007] In one exemplary embodiment, an apparatus for analog-to-digital conversion is disclosed. The apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference cross-detector, a jump generator, and a voltage shifter. The reference cross-detector includes an input and an output. The jump generator is coupled between the output and the input of the reference cross-detector. The voltage shifter is also coupled between the output and the input of the reference cross-detector.

[0008] In one exemplary embodiment, an apparatus for analog-to-digital conversion is disclosed. The apparatus includes: means for generating a first signal in response to a second signal and based on a reference value. The apparatus also includes: means for shifting a voltage based on the first signal at a first time, the voltage corresponding to the second signal. The apparatus further includes: means for increasing the voltage at a second time in response to at least partially a digital value based on a bit value of the first signal, the bit value corresponding to at least a portion of a digital output signal.

[0009] In one exemplary embodiment, a method for analog-to-digital conversion is disclosed. The method includes: generating a first signal based on a second signal and a reference value. The method also includes: shifting the voltage of the second signal based on the first signal. Additionally, the method further includes: causing the voltage of the second signal to rise in response to a digit value. The method further includes: latching the digit value based on the change in the first signal.

[0010] In one exemplary embodiment, an apparatus for analog-to-digital conversion is disclosed. The apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a plurality of analog-to-digital conversion stages and at least one amplifier coupled between two or more of the plurality of analog-to-digital conversion stages. At least one of the plurality of analog-to-digital conversion stages includes a reference cross-detector, a jump generator, and at least one capacitor. The reference cross-detector includes an input and an output. The jump generator is coupled to the output of the reference cross-detector. The jump generator includes a plurality of buffers connected in series, and a plurality of capacitors. The plurality of capacitors are coupled between the plurality of buffers and the input of the reference cross-detector. The at least one capacitor is coupled between the output of the reference cross-detector and the input of the reference cross-detector.

[0011] In one exemplary embodiment, an apparatus for analog-to-digital conversion is disclosed. The apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference cross-detector, a jump generator, and an offset adjuster. The reference cross-detector includes an input and an output. The jump generator is coupled between the output and the input of the reference cross-detector. The offset adjuster is coupled between the output and the input of the reference cross-detector. Simple Explanation of the Diagram

[0012] Figure 1 illustrates an environment having an exemplary electronic device including a wireless interface device, which includes a transceiver having an analog-to-digital converter (ADC).

[0013] Figure 2 illustrates an exemplary transceiver including an ADC as part of a receive chain.

[0014] Figure 3 illustrates an exemplary pipelined ADC that includes multiple analog-to-digital conversion stages (ADC stages) and at least one amplifier.

[0015] Figure 4 is a schematic diagram of an exemplary ADC including a reference cross detector, a jump generator, and voltage control circuitry (e.g., a voltage shifter and / or offset adjuster).

[0016] Figure 4-1 is a schematic diagram of an exemplary ADC including a reference cross detector, a jump generator, and a voltage shifter.

[0017] Figure 4-2 is a schematic diagram of an exemplary ADC including a reference cross detector, a jump generator, and an offset adjuster.

[0018] Figure 5 is a flowchart illustrating an exemplary process for operating an ADC similar to that in Figure 4, which includes voltage displacement and voltage offset adjustment.

[0019] Figure 6 illustrates two graphs: the lower graph of voltage versus time illustrates an exemplary voltage level at the input / output node of an ADC using a voltage shifter and offset adjuster, and the upper graph illustrates an exemplary voltage value obtained from voltage comparison using a reference cross-detector.

[0020] Figure 7 is a circuit diagram of an exemplary ADC including a reference cross detector, a jump generator, and a voltage shifter or offset adjuster.

[0021] Figure 8 is a circuit diagram of an exemplary jump generator.

[0022] Figure 9 is a circuit diagram of an exemplary voltage shifter.

[0023] Figure 10 is a circuit diagram of an exemplary offset adjuster.

[0024] Figure 11 shows an example of a capacitor array that can be used to implement ADC elements in a differential environment.

[0025] Figure 12-1 is a flowchart illustrating an exemplary calibration process for determining the first stage of the offset voltage adjustment.

[0026] Figure 12-2 is a flowchart illustrating an exemplary calibration process for determining the second stage of the offset voltage adjustment.

[0027] Figure 13 is a flowchart illustrating an exemplary process for analog-to-digital conversion.

[0028] Figure 14 is a block diagram of an exemplary ADC that includes at least a reference cross detector mechanism, a jump generator mechanism, and a voltage shifter mechanism. Implementation

[0029] To facilitate the transmission and reception of wireless signals, electronic devices can use wireless interface devices that include wireless transceivers. These transceivers include several elements to generate, manipulate, regulate, or otherwise process signals for transmission or reception. For example, an analog-to-digital converter (ADC) can be used to convert analog received signals into digital signals, which can then be processed to recover the information carried on the received signal. Asynchronous digital-to-digital ADCs are a type of ADC whose architecture allows for faster speeds and lower power consumption than some other types of ADCs. Asynchronous digital-to-digital ADCs can also be designed to be precise. In some cases, they can be deployed as part of the analog-to-digital conversion stage (ADC stage) of a pipelined ADC.

[0030] Pipeline analog-to-digital converters (or pipelined analog-to-digital converters) have multiple ADC stages. Each ADC stage can be built using any of a variety of ADC architectures. For example, an ADC stage (e.g., with 1-2 bits) can be built using a multiplicative digital-to-analog converter (DAC) (MDAC). While MDACs can be relatively fast, they typically require complex calibration and consume significant power. An ADC stage (e.g., with 3-5 bits) can instead be built using flash memory or a direct conversion ADC. While flash memory ADCs can also perform quickly, typical flash memory ADCs occupy a large area and consume significant power. A third exemplary architecture for ADC stages (e.g., with 5-7 bits) is a successive approximation register (SAR) ADC. SAR ADCs can typically be built to be power efficient, but this same SAR ADC can be slow due to the multiple comparator and DAC setup stages.

[0031] Asynchronous digital leap ADCs are the fourth type of ADC architecture that can be used in pipeline ADC stages. Asynchronous digital leap ADCs can provide multiple bits per ADC stage (e.g., 4-6 bits or other numbers of bits). Asynchronous digital leap ADCs can be calibrated quickly, accurately, and relatively easily for use in ADC stages. However, several issues may arise with asynchronous digital leap ADCs, which will be discussed below.

[0032] Asynchronous digital step-up ADC may include a reference cross-detector (e.g., a zero-crossing detector (ZCD)) and a step-up generator. In exemplary operation, the step-up generator digitally steps up the voltage signal at the input of the reference cross-detector until the signal crosses a reference value (e.g., a zero-voltage reference value). In response to the reference cross-detector detecting such a signal crossing, the step-up generator may lock the digital value that generates the step-up voltage signal. Thus, the voltage signal corresponds to the digital value of the step-up generator, and the step-up generator can provide at least a portion of that digital value as a digital output signal for the ADC. If the asynchronous digital step-up ADC is part of a pipelined ADC, the digitally generated voltage signal resulting from the step-up process can be provided to the next or subsequent ADC stage of the pipelined ADC (including via a residual amplifier).

[0033] Several approaches to asynchronous step-up ADCs can present problems. First, the rise period used to make the voltage signal rise step-up may be longer than acceptable for some applications. For example, the initial voltage level of the signal to be step-up may be too far from the reference value of the reference cross-detector. Therefore, the rise time to reach the reference value may cause a significant delay before the digital value is locked, and this delay slows down the ADC process. For pipelined ADCs, this delay can be particularly impactful in the first ADC stage. As a second problem, the step-up voltage signal may "overshoot" the reference value. Voltage overshoot can be caused by latency due to signal propagation or circuit operation. The additional voltage amplitude (e.g., a positive voltage "bulge" above the zero-volt level) can correspond to errors in the digital value and / or can reduce the available signal range of subsequent stages of the pipelined ADC.

[0034] To address the first problem, in some implementations, the described ADC includes a reference cross-detector, a rise generator, and a voltage shifter. The voltage shifter is coupled between the output and input of the reference cross-detector. The voltage shifter can shift the voltage level of the input signal based on the value of the detected signal generated by the reference cross-detector. Therefore, the voltage shifter can shift the voltage at the input of the reference cross-detector by a voltage amount that depends at least partially on the voltage of the input signal. For example, for a zero-voltage reference and a positive rise process, if the input signal voltage is positive, the voltage shifter can shift the voltage at the input of the reference cross-detector by a larger amount, but if the input signal voltage is "already" negative, the shift will be relatively smaller.

[0035] Subsequently, the rise generator begins to rise the voltage from the offset voltage level; in this positive rise example, the rise increases the voltage level. By shifting the negative input signal voltage by a relatively small amount, the negative input signal rises from a voltage level closer to the zero voltage reference value than in cases where the voltage shift is constant or not tailored to the input signal voltage. Therefore, the rise process can end more quickly, and the digital value of the ADC can be determined more quickly. This means that the ADC can generate a digital output signal representing the analog input signal in a shorter time.

[0036] To address the second problem, in some implementations, the described ADC includes a reference cross-detector, a rise generator, and an offset adjuster. The offset adjuster is coupled between the output and input of the reference cross-detector. After the voltage at the input of the reference cross-detector crosses with a reference value, the reference cross-detector generates a detection signal that can lock the digital value of the rise generator. Due to the latency of signal propagation or circuit operation, the rise signal may exceed or "overshoot" the target reference value. The offset adjuster can reduce the magnitude of the "voltage overshoot" to at least mitigate the effects of latency. For example, the offset adjuster can reduce the absolute value of the voltage at the input of the reference cross-detector to obtain a zero-volt reference value.

[0037] In an exemplary operation, the offset voltage amount or level can be determined as part of a calibration process that analyzes the output of subsequent stages of the pipelined ADC. In response to the timing of the detected signal provided at the output of the reference cross-detector, the offset adjuster can apply an offset voltage amount to reduce voltage overshoot. For a zero-volt reference, the offset adjuster can reduce the voltage amplitude at the input of the reference cross-detector. In pipelined ADC applications, the offset adjuster can shift the voltage close to zero volts to prepare for amplification into a residual signal in the pipelined ADC. This reduction in the residual voltage amplitude at least reduces overshoot error and allows for greater scaling of the residual signal. Greater amplification scalability can improve the accuracy of signal processing through subsequent ADC stages of the pipelined ADC.

[0038] These voltage shift and offset adjustment implementations can also be used together as part of a "standalone" ADC, or as part of the analog-to-digital conversion stage (ADC stage) of a pipelined ADC. Therefore, voltage shifters can reduce the rise period to increase the operating speed of the ADC. Furthermore, offset adjusters can essentially remove the amount of overshoot voltage from the residual signal to be processed by subsequent ADC stages, thereby improving accuracy in the pipelined ADC. This document describes some ADC implementations in the context of wireless interface devices (e.g., wireless transceivers) and / or their receive chains. However, the described ADC implementations can be deployed in different environments or used in alternative applications. For example, asynchronous digital rise ADCs are commonly used in wired communication components, processors, system-on-chips (SoCs), or integrated circuits (ICs).

[0039] Figure 1 illustrates an exemplary environment 100, in which electronic device 102 has a wireless interface device 120, which includes a transceiver 126 having an analog-to-digital converter 130 (ADC 130). This document describes an exemplary implementation of the ADC 130, which may include an asynchronous digital step-up ADC. In environment 100, the exemplary electronic device 102 communicates with a base station 104 via a wireless link 106. In Figure 1, electronic device 102 is illustrated as a smartphone. However, electronic device 102 can be implemented as any suitable computing or other electronic device. Examples of electronic devices 102 include cellular base stations, broadband routers, access points, cellular or mobile phones, gaming devices, navigation devices, media devices, laptops, desktop computers, tablets, server computers, network attached storage (NAS) devices, smart home appliances, in-vehicle communication systems, Internet of Things (IoT) devices, sensors or security devices, asset trackers, fitness management devices, wearable devices (such as smart glasses or smartwatches), wireless power devices (transmitters or receivers), and medical devices.

[0040] Base station 104 communicates with electronic device 102 via wireless link 106, which can be implemented as any suitable type of wireless link carrying communication signals. Although illustrated as a base station tower of a cellular radio network, base station 104 can be represented or implemented as another device, such as a satellite, terrestrial broadcast tower, access point, peer device, mesh network node, fiber optic interface, or other electronic device as described above. Therefore, wireless link 106 extends between electronic device 102 and base station 104.

[0041] Wireless link 106 may include a downlink for transmitting data or control information from base station 104 to electronic device 102. Wireless link 106 may also include an uplink for transmitting other data or control information from electronic device 102 to base station 104. Wireless link 106 may be implemented using any suitable wireless communication protocol or standard. Examples of such protocols and standards include 3GPP Long Term Evolution (LTE) standards, such as fourth-generation (4G) or fifth-generation (5G) cellular standards; IEEE 802.11 standards, such as 802.11g, ac, ax, ad, aj, or ay (e.g., Wi-Fi 6 or WiGig®); IEEE 802.16 standards (e.g., WiMAX®); and Bluetooth® standards. In some implementations, wireless link 106 may be wirelessly powered, and electronic device 102 or base station 104 may contain a power source.

[0042] As shown with respect to some embodiments, electronic device 102 may include at least one application processor 108 and at least one computer-readable storage medium 110 (CRM 110). Application processor 108 may include any type of processor configured to execute processor-executable instructions (e.g., code) stored in CRM 110, such as a central processing unit (CPU) or a multi-core processor. CRM 110 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, and magnetic media (e.g., magnetic disks or magnetic tapes). In the context of this application, CRM 110 is implemented as storing instructions 112, data 114, and other information of electronic device 102; therefore, CRM 110 does not include transient propagation signals or carrier waves.

[0043] Electronic device 102 may also include one or more input / output ports 116 (I / O ports 116) and at least one display 118. I / O ports 116 are capable of exchanging or interacting with other devices, networks, or users. I / O ports 116 may include serial ports (e.g., Universal Serial Bus (USB) ports), parallel ports, audio ports, infrared (IR) ports, and camera or other sensor ports. Display 118 may be implemented as a screen or projection displaying graphical images provided by other components of electronic device 102, such as a user interface (UI) associated with an operating system, program, or application. Alternatively or additionally, display 118 may be implemented as a display port or virtual interface through which the graphical content of electronic device 102 is transmitted or presented.

[0044] Electronic device 102 further includes at least one wireless interface device 120 and at least one antenna 122. The exemplary wireless interface device 120 provides connectivity to various networks and peer devices via a wireless link, which may be configured similarly or differently from wireless link 106. The wireless interface device 120 can facilitate communication via any suitable type of wireless network, such as a wireless local area network (WLAN), a wireless personal area network (PAN) (WPAN), a peer-to-peer (P2P) network, a mesh network, a cellular network, a wireless wide area network (WAN) (WWAN), and / or a navigation network (e.g., North American Global Positioning System (GPS) or other satellite positioning systems (SPS) or Global Navigation Satellite System (GNSS)). In the context of exemplary environment 100, electronic device 102 can bidirectionally transmit various data and control information with base station 104 via the wireless interface device 120. However, electronic device 102 can also communicate directly with other peer devices, alternative to wireless networks, etc.

[0045] As shown, the wireless interface device 120 may include at least one communication processor 124, at least one transceiver 126, and at least one radio frequency (RF) front-end 128 (RFFE 128). These components process data information, control information, and signals associated with transmitting information to the electronic device 102 via the antenna 122. The communication processor 124 may be implemented as at least a part of a system-on-a-chip (SoC), a modem processor, or a baseband radio processor (BBP) that implements a digital communication interface for data, voice, messaging, or other applications of the electronic device 102. The communication processor 124 may include a digital signal processor (DSP) or one or more signal processing blocks (not shown) to encode and modulate data for transmission and demodulate and decode received data. Furthermore, the communication processor 124 may also manage (e.g., control or configure) the states or operations of the transceiver 126, the RF front-end 128, and other components of the wireless interface device 120 to implement various communication protocols or communication technologies.

[0046] In some cases, application processor 108 and communication processor 124 may be combined into a module or integrated circuit (IC), such as a SoC. In any case, application processor 108, communication processor 124, or another processor may be operatively coupled to one or more other components, such as CRM 110 or display 118, to enable control or other interactions with various components of electronic device 102. For example, at least one processor 108 or 124 may present one or more graphic images on the display screen implementation of display 118 based on one or more wireless signals received by components using wireless interface device 120 via at least one antenna 122. Furthermore, application processor 108 or communication processor 124 (including combinations thereof) may be implemented using digital circuitry that implements the logic or functions described herein. Additionally, communication processor 124 may also include memory (not shown separately), such as CRM 110, for storing data and processor-executable instructions (e.g., code).

[0047] As shown, transceiver 126 may include at least the ADC 130 described below. Transceiver 126 may also include circuitry and logic for filtering, switching, amplification, channelization, or frequency conversion. Frequency conversion functionality may include up-conversion or down-conversion of frequencies performed via a single conversion operation (e.g., using a direct conversion architecture) or via multiple conversion operations (e.g., using a superheterodyne architecture). Typically, transceiver 126 may include filters, switches, amplifiers, or mixers for routing and conditioning signals transmitted or received via antenna 122.

[0048] In addition to ADC 130, transceiver 126 may also include a digital-to-analog converter (DAC). In operation, the ADC can convert an analog signal to a digital signal, while the DAC can convert a digital signal to an analog signal. Typically, the ADC or DAC can be implemented as part of the communication processor 124, as part of the transceiver 126, or separately (e.g., as another part of the SoC or as part of the application processor 108).

[0049] The elements or circuitry of transceiver 126 can be implemented in any suitable manner, such as using combined transceiver logic or implementing them separately as respective transmitter and receiver entities. In some cases, transceiver 126 is implemented with multiple or different sections to perform separate transmit and receive operations (e.g., having separate transmit and receive chains as illustrated in Figure 2). Although not shown in Figure 1, transceiver 126 may also include logic that performs in-phase / quadrature (I / Q) operations, such as combining, phase correction, modulation, demodulation, etc.

[0050] RF front-end 128 may include one or more filters, switches, or amplifiers for conditioning signals received via antenna 122 or for conditioning signals to be transmitted via antenna 122. RF front-end 128 may include a phase shifter (PS), a peak detector, a power meter, a gain control block, an antenna tuning circuit, an N-multiplexer, a balun, etc. Configurable elements of RF front-end 128 (e.g., phase shifters or automatic gain controllers (AGC)) may be controlled by communication processor 124 to enable various modes, different frequency bands, or beamforming communications. In some embodiments, antenna 122 is implemented as at least one antenna array comprising multiple antenna elements. Therefore, as used herein, "antenna" may refer to at least one individual or separate antenna, at least one antenna array comprising multiple antenna elements, or a portion of an antenna array (e.g., antenna elements), depending on the context or implementation.

[0051] In Figure 1, the analog-to-digital converter 130 (ADC 130) is illustrated as part of transceiver 126. However, the described implementation of ADC 130 may be used additionally or alternatively in other parts of wireless interface device 120 (e.g., as part of communication processor 124 or RF front end 128), or typically in other parts of electronic device 102 (e.g., for digitizing analog signals or analog sensor information for storage or processing).

[0052] As shown in the figure, ADC 130 may include at least one reference cross-detector 132 (RCD 132), at least one rise generator 134, one or more capacitors 136, and voltage transformation circuitry 138. In some cases, the one or more capacitors 136 may be shared between the rise generator 134 and the voltage transformation circuitry 138, or distributed between them. The voltage transformation circuitry 138 may include a voltage shifter or offset adjuster, a term that may include both voltage shifter and offset adjuster (depending on the optional but permissible inclusive interpretation of the word "or"). An exemplary implementation of such an ADC is described below with reference to Figure 4. An exemplary pipeline ADC 130-1, which may include an analog-to-digital conversion stage with ADC 130, is described below with reference to Figure 3. However, an exemplary transceiver implementation is described below.

[0053] Figure 2 generally illustrates an exemplary transceiver 126 at 200, which includes an ADC 130 as part of a receive chain 202. In addition to transceiver 126, Figure 2 also illustrates an antenna 122, an RF front-end 128, and a communication processor 124. The communication processor 124 transmits one or more data signals to other components (such as the application processor 108 of Figure 1) for further processing at 224 (e.g., processing for application level).

[0054] As shown from left to right, in the exemplary implementation, antenna 122 is coupled to RF front-end 128, and RF front-end 128 is coupled to transceiver 126. Transceiver 126 is coupled to communication processor 124. Exemplary RF front-end 128 includes at least one antenna feed 222. Exemplary transceiver 126 includes at least one receive chain 202 and at least one transmit chain 252. Although only one RF front-end 128, one transceiver 126, and one communication processor 124 are illustrated at 200, electronic device 102 or its wireless interface device 120 may include multiple instances of any or all of these elements. Furthermore, although only certain elements are explicitly illustrated in Figure 2 and shown coupled together in a particular manner, transceiver 126 may include other elements not shown, more or fewer elements, and different coupling arrangements of elements.

[0055] In some embodiments, RF front-end 128 couples antenna 122 to transceiver 126 via antenna feed 222. In operation, antenna feed 222 propagates a signal between antenna 122 and transceiver 126. During or as part of signal propagation, antenna feed 222 modulates the propagated signal. This enables RF front-end 128 to couple radio signal 220 from antenna 122 to transceiver 126 as part of a receiving operation. RF front-end 128 also enables transmission signals to be coupled from transceiver 126 to antenna 122 as part of a transmitting operation of radio signal 220. Although not explicitly shown in Figure 2, RF front-end 128 or its antenna feed 222 may include one or more other elements such as filters, amplifiers (e.g., power amplifiers or low-noise amplifiers), N-multiplexers, or phase shifters.

[0056] In some embodiments, transceiver 126 may include at least one receive chain 202, at least one transmit chain 252, or at least one receive chain 202 and at least one transmit chain 252. Receive chain 202 may include a low-noise amplifier 204 (LNA 204), a filter 206, a mixer 208 for downconversion, and an ADC 130. Transmit chain 252 may include a power amplifier 254 (PA 254), a filter 256, a mixer 258 for upconversion, and a DAC 260. However, receive chain 202 or transmit chain 252 may include other elements electrically disposed at any location along the illustrated receive and transmit chains, such as other amplifiers or filters, multiple mixers, one or more buffers, or at least one local oscillator.

[0057] The receive chain 202 is coupled between the antenna feed 222 of the RF front end 128 and the communication processor 124, for example, via a low-noise amplifier 204 and an ADC 130. The transmit chain 252 is coupled between the antenna feed 222 and the communication processor 124, for example, via a power amplifier 254 and a DAC 260. The transceiver 126 may also include at least one phase-locked loop 232 (PLL 232) coupled to the mixer 208 or 258. For example, the transceiver 126 may include one PLL 232 for each transmit / receive chain pair, one PLL 232 for each transmit chain and one PLL 232 for each receive chain, or multiple PLL 232 per chain.

[0058] As shown in some exemplary implementations of receiver chain 202, antenna 122 is coupled to low-noise amplifier 204 via antenna feed 222, and low-noise amplifier 204 is coupled to filter 206. Filter 206 is coupled to mixer 208, and mixer 208 is coupled to ADC 130. ADC 130 is in turn coupled to communication processor 124. As shown in some exemplary implementations of transmitter chain 252, communication processor 124 is coupled to DAC 260, and DAC 260 is coupled to mixer 258. Mixer 258 is coupled to filter 256, and filter 256 is coupled to power amplifier 254. Power amplifier 254 is coupled to antenna 122 via antenna feed 222. Although only one receiver chain 202 and one transmitter chain 252 are explicitly illustrated, electronics 102 or its transceiver 126 may include multiple instances of any one or both of these elements. Although the ADC 130 and DAC 260 are shown as being coupled to the processor 124 respectively, they may share a bus or other components for communicating with the processor 124.

[0059] As part of an exemplary signal receiving operation, low-noise amplifier 204 provides an amplified signal to filter 206. Filter 206 filters the amplified signal and provides the filtered signal to mixer 208. Mixer 208 performs a frequency conversion operation on the filtered signal to downconvert from one frequency to a lower frequency (e.g., from radio frequency (RF) to intermediate frequency (IF) or to base frequency (BBF)). Mixer 208 may perform the frequency downconversion in a single conversion step or via multiple conversion steps using at least one PLL 232. Mixer 208 may provide the downconverted signal to ADC 130 for conversion and forward it to communication processor 124.

[0060] Typically, ADC 130 receives or otherwise receives an analog input signal 212 from another element, such as mixer 208. ADC 130 performs an analog-to-digital conversion operation on this analog signal to produce a digital signal. For this purpose, ADC 130 may quantize a sampled portion of the analog signal into frequency bands (bins). ADC 130 may further assign digital values ​​corresponding to the frequency bands to represent sampled instances of the signal. Therefore, ADC 130 may generate a digital output signal 214 that spans one or more sampled instances of the analog input signal 212. ADC 130 may provide or forward the digital output signal 214 to another element (e.g., communications processor 124).

[0061] As described with reference to Figure 3, ADC 130 can be implemented as at least one pipelined ADC, or as part of a pipelined ADC. Although ADC 130 is shown as part of the receive chain 202 of transceiver 126, ADC 130 (including pipelined ADC 130) can be implemented in other elements or parts of the electronic device.

[0062] Figure 3 illustrates an exemplary pipelined ADC 130-1, which includes multiple analog-to-digital conversion stages (ADC stages) and at least one amplifier (e.g., residual amplifier 304). The pipelined ADC 130-1 (or pipelined ADC 130-1) accepts an analog input signal 212 and produces a digital output signal 214. For this purpose, the pipelined ADC 130-1 uses two or more ADC stages, which may operate substantially in parallel but at different times on different portions of the analog input signal 212 to produce digital values ​​that form the digital output signal 214.

[0063] In an exemplary implementation, the pipeline ADC 130-1 includes multiple ADC stages 302-1, 302-2, ..., 302-S, where "S" represents an integer greater than one. The pipeline ADC 130-1 also includes multiple residual amplifiers 304-1, 304-2, ..., 304-(S-1) (where the "(S-1)th" amplifier is not explicitly shown). In some cases, the number of residual amplifiers may be one less than the number of ADC stages. Typically, at least one residual amplifier 304 is coupled to two or more of the multiple ADC stages 302-1 to 302-S, and interleaved therebetween. For example, a first residual amplifier 304-1 is coupled between the output of the first ADC stage 302-1 and the input of the second ADC stage 302-2. Similarly, a second residual amplifier 304-2 is coupled between the output of the second ADC stage 302-2 and the input of a third ADC stage 302-3 (not explicitly shown). The pipeline ADC 130-1 also includes at least one register 306, which can be coupled to multiple ADC stages (such as, coupled to each of multiple ADC stages 302-1 to 302S ADC stage 302).

[0064] In an exemplary operation, a respective ADC stage 302 of a plurality of ADC stages 302-1 to 302-S generates a respective digital value 312 of a plurality of digital values ​​312-1 to 312-S. For example, a first ADC stage 302-1 may generate a first digital value 312-1, and a second ADC stage 302-2 may generate a second digital value 312-2. A "Sth" ADC stage 302-S may generate a "Sth" digital value 312-S. Each respective ADC stage 302 provides a corresponding digital value 312 to a register 306. The register 306 accepts or otherwise receives the plurality of digital values ​​312-1 to 312-S, wherein the respective analog-to-digital converter stage 302 of the plurality of analog-to-digital converter stages 302-1 to 302-S receives the corresponding digital value 312 of each of the plurality of digital values ​​312-1 to 312-S. The register 306 combines the plurality of digital values ​​312-1 to 312-S to generate a digital output signal 214 for the pipeline ADC 130-1.

[0065] A given ADC stage 302 generates a digital value 312 as its output signal based on the input signal used for the ADC stage 302. In the case of the first ADC stage 302-1, the stage input signal may correspond to the analog input signal 212. For other ADC stages, the stage input signal may correspond to the corresponding residual input signal 310 from the previous ADC stage. In addition to the digital value 312, a given ADC stage 302 may generate an analog residual signal 308 as another output signal. In some embodiments, the ADC stage 302 provides the analog residual signal 308 to the next residual amplifier 304. The residual amplifier 304 amplifies the analog residual signal 308 to generate the residual input signal 310 for the subsequent ADC stage 302.

[0066] In Figure 3, the pipeline ADC 130-1 is explicitly illustrated as having a first analog residual signal 308-1, a first residual input signal 310-1, a second analog residual signal 308-2, and a second residual input signal 310-2. For example, a first ADC stage 302-1 generates the first analog residual signal 308-1 and forwards it to a first residual amplifier 304-1. The first residual amplifier 304-1 amplifies the first analog residual signal 308-1 to generate the first residual input signal 310-1. By amplifying the first analog residual signal 308-1, the first residual amplifier 304-1 prepares the analog signal for further digital conversion (e.g., for bits of less importance than those already converted). The first residual amplifier 304-1 provides the first residual input signal 310-1 to the second ADC stage 302-2. The second ADC stage 302-2 receives or otherwise receives the first residual input signal 310-1 and generates a second digital value 312-2 based on it and the second analog residual signal 308-2.

[0067] Pipeline operation can continue with additional ADC stages and interleaved residual amplifiers. Although three ADC stages are explicitly shown in Figure 3, the pipeline ADC 130-1 may include two ADC stages (e.g., where "S" equals "2") or more than three ADC stages. In the two-stage case, the pipeline ADC 130-1 may include a single residual amplifier 304-1 coupled between the first ADC stage 302-1 and the second ADC stage 302-2. Typically, each ADC stage 302 can be constructed using the same type of ADC; or, at least some ADC stages may be designed to have different types of ADCs. For example, the first ADC stage 302-1 may include an asynchronous digital step-up ADC, while one or more other ADC stages may include different types of ADCs.

[0068] Figure 4 is a schematic diagram 400 of an exemplary ADC 130 (e.g., Figures 1 through 3), which includes a reference cross-detector 132, a jump generator 134, and a voltage shifting circuit 138 (e.g., a voltage shifter 404 and / or an offset adjuster 406). Schematic diagram 400 also includes ADC control circuitry 402; at least one switch 408, which may be referred to as an input switch 408 or a sampling switch 408; and at least one delay unit 412, such as a first delay unit 412-1 and a second delay unit 412-2. Schematic diagram 400 may correspond to at least a portion of the ADC stage 302 of ADC 130 or pipelined ADC 130-1 (e.g., Figure 3).

[0069] Although the ADC control circuit 402 is illustrated as a single discrete rectangle, it may include logic or elements distributed around the schematic 400 to provide control functions to the various illustrated elements. Therefore, although not explicitly illustrated in schematic 400, the ADC control circuit 402 may include logic or control elements for the jump generator 134, voltage shifter 404, and / or offset adjuster 406. Furthermore, although not illustrated in this manner in Figure 4 for clarity, the ADC control circuit 402 may include at least one delay unit 412. The ADC control circuit 402 may also include other control circuitry, such as logic for signal routing or gating and / or logic for controlling the timing of providing the detection signal 420 to the various elements. For example, the ADC control circuit 402 may coordinate or control the forwarding order or interpretation of the different detection signals generated by the reference cross-detector 132. In addition, the ADC control circuit 402 may include logic such as logic 718 or logic 728 (e.g., Figure 7) as part of another element such as voltage shifter 404 or offset adjuster 406.

[0070] In an exemplary implementation, reference cross-detector 132 includes input 414 and output 416. Switch 408 is coupled to input 414 of reference cross-detector 132 via node 410. Jump generator 134 may be coupled between output 416 and input 414 of reference cross-detector 132. Voltage shifter 404 may be coupled between output 416 and input 414 of reference cross-detector 132. Offset adjuster 406 may also be coupled between output 416 and input 414 of reference cross-detector 132.

[0071] In some configurations, multiple capacitors 136 may be distributed across two or more of the following elements: a rise generator 134, a voltage shifter 404, or an offset adjuster 406. The capacitors 136 may be implemented using, for example, at least one capacitive digital-to-analog converter (DAC) (e.g., at least one capacitive DAC 136 (or capacitive DAC 136)). Each of the multiple capacitors 136 may be coupled to the input 414 of the reference cross-detector 132 via node 410. As described herein, as part of ADC operation, each corresponding element (rise generator 134, voltage shifter 404, or offset adjuster 406) may affect the voltage at node 410 at the input 414 of the reference cross-detector 132.

[0072] In an exemplary operation, the ADC of schematic 400 receives an input signal 418 at node 410 via switch 408. Input signal 418 may correspond to analog input signal 212 (Figures 2 and 3) or residual input signal 310 (Figure 3). In response to switch 408 being closed, input 414 of reference cross-detector 132 is exposed to a voltage of input signal 418. Sampling signal 422 controls the operation of switch 408. Sampling signal 422 may close switch 408 to obtain the sampled signal based on the sampled signal becoming active (e.g., driven to a high or low level depending on the transistor technology of switch 408). When switch 408 is closed in response to sampling signal 422, the voltage of input signal 418 may be stored on one or more capacitors 136.

[0073] The ADC control circuit 402 can generate a sampling signal 422 based on a master clock signal 432. In some cases, the master clock signal 432 at least partially controls the timing of operation of the circuitry including the ADC 130. The ADC control circuit 402 can adjust or modify the timing of the master clock signal 432 to generate the sampling signal 422. For example, the master clock signal 432 can be applied to a first ADC stage 302-1 (e.g., Figure 3), which can then trigger the next element (e.g., a first residual amplifier 304-1), causing element operation to be asynchronously cascaded along the pipeline ADC 130-1 (starting from the first ADC stage 302-1). Alternatively, a corresponding version or derivative of the master clock signal 432 can be applied individually to each element block of the pipeline ADC 130-1 (Figure 3) to synchronously control ADC operation. After a period of time sufficient for the voltage of the input signal 418 to be transmitted to one or more capacitors 136 has elapsed, the ADC control circuit 402 can use the sampling signal 422 to turn on the switch 408.

[0074] Reference cross detector 132 (RCD 132) generates a signal (e.g., detection signal 420) based on a reference value 428 and in response to a voltage 430 at input 414. Therefore, reference cross detector 132 can generate detection signal 420 based on input signal 418 and reference value 428. For example, reference cross detector 132 can set the value of detection signal 420 based on whether the voltage of input signal 418 (or otherwise the voltage 430 at node 410) is greater than or less than reference value 428. For example, reference cross detector 132 can be implemented as an asynchronous comparator that compares voltage 430 at input 414 with reference value 428 (which may correspond to a reference voltage level). In some cases, reference cross detector 132 can be implemented as a zero-crossing detector (ZCD), where the ZCD outputs a signal in response to the input signal crossing approximately zero voltage or ground voltage. In such cases, reference value 428 may correspond to approximately zero voltage or ground voltage. In some implementations, the reference cross-detector 132 can be implemented using an analog amplifier that operates like a digital asynchronous comparator. A positive input voltage at input 414 drives the detection signal 420 at output 416 to the upper voltage rail, which can correspond to a high voltage (or a logic "1" value). A negative input voltage at input 414 drives the detection signal 420 at output 416 to the ground voltage level, which can correspond to a low voltage (or a logic "0" value).

[0075] The detection signal 420 may correspond to any of a plurality of different signals (depending on the ADC's signal destination, context, relative time, or operating phase, which may be controlled by the ADC control circuitry 402 and / or other logic such as one or more delay units 412, logic 718 (e.g., Figures 7 and 9), and / or logic 728 (e.g., Figures 7 and 10) described herein). Exemplary signal versions of the detection signal 420 include a first-time selected voltage shift amount signal 420-1, a second-time locked bit value signal 420-2, and / or a third-time applied voltage offset signal 420-3. Thus, the detection signal 420 may be interpreted or used differently depending on the destination and / or the relative time during each ADC cycle. An example of such timing is described below with reference to Figure 6. As shown, the reference cross detector 132 provides the selected voltage shift amount signal 420-1 to the voltage shifter 404. Reference cross detector 132 provides a locked digital value signal 420-2 to the jump generator 134. Reference cross detector 132 provides an applied voltage offset signal 420-3 to the offset adjuster 406.

[0076] Simultaneously, the ADC control circuit 402 can generate one or more other signals based on the sampled signal 422 via at least one delay unit 412. As shown, the first delay unit 412-1 generates an applied voltage shift signal 424 based on the sampled signal 422. The first delay unit 412-1 can provide the applied voltage shift signal 424 to the voltage shifter 404. The second delay unit 412-2 generates a jump trigger signal 426 based on the applied voltage shift signal 424, which can be based on the sampled signal 422. Alternatively, the second delay unit 412-2 can generate the jump trigger signal 426 "directly" from the sampled signal 422. In this case, the second delay unit 412-2 can use a longer delay period than the delay period of the first delay unit 412-1 to generate the jump trigger signal 426 based on the sampled signal 422, such that the jump trigger signal 426 is emitted after the applied voltage shift signal 424. The second delay unit 412-2 can provide the jump trigger signal 426 to the jump generator 134.

[0077] To influence the voltage 430 at input 414 of node 410 or reference cross detector 132, jump generator 134 can generate a digital jump or jump signal. Jump generator 134 responds to jump trigger signal 426 to cause voltage 430 to rise in a jump manner, and can terminate the jump process in response to lock digital value signal 420-2. Jump generator 134 may include elements at least similar to those of a time-to-digital converter (TDC) coupled to a capacitor array. Exemplary elements of jump generator 134 are described below with reference to Figures 7 and 8. The lock digital value generated by the jump can be output as digital value 312 (e.g., also shown in Figures 3, 7, and 8).

[0078] Voltage shifter 404 shifts the voltage 430 at node 410 or input 414 of reference cross detector 132 based on selected voltage shift amount signal 420-1 and in response to applied voltage shift signal 424. Offset adjuster 406 can respond to applied voltage offset signal 420-3 and adjust the voltage 430 at node 410 or input 414 based on the offset voltage amount. The offset voltage amount can be determined via a calibration process, which will be described below with reference to Figure 12.

[0079] Therefore, in exemplary operation, voltage 430 can be established based on input signal 418 and rise generator 134. Voltage 430 can be further established or modified based on the operation of voltage changing circuit 138 (e.g., operation of voltage shifter 404 or offset adjuster 406). In response to the operation of these components (e.g., two or more of these components), the ADC generates voltage 430 at node 410 or input 414 of reference cross-detector 132, according to one of the sequences described herein. The ADC can generate voltage 430 as another output signal. In a pipelined ADC 130-1 environment, the output signal can be used as an analog residual signal 308 (e.g., Figure 3), which provides a residual voltage to be forwarded as an input signal to subsequent ADC stage 302 or intermediate residual amplifier 304 (Figure 3). Using the pipelined analog-to-digital converter 130-1, the input 414 of the reference cross detector 132 can be used as the input of a given ADC stage 302 at a first time, and the same input 414 can provide the output of the ADC stage 302 at a second time.

[0080] Figure 5 is a flowchart illustrating an exemplary process 500 for operating an ADC 130 similar to that of Figure 4 using voltage offset and voltage offset adjustment. The flowchart of process 500 comprises eleven (11) blocks 502-522. In the exemplary implementation, process 500 illustrates techniques for operating the ADC of Figure 4 in a specific order. However, the operation of the ADC can be performed using more, fewer, and / or different actions or using actions in a different order. Furthermore, such actions can be performed in a fully or partially overlapping manner.

[0081] At block 502, sampling signal 422 closes switch 408 and allows input signal 418 to reach node 410 and input 414 of reference cross detector 132. Therefore, at block 504, the ADC samples input signal 418 to establish an initial voltage level of voltage 430 at node 410.

[0082] At block 506, reference cross-detector 132 determines the voltage shift amount and indicates the selected voltage shift amount using detection signal 420 at the output 416 of reference cross-detector 132. This voltage shift amount determination can be based on voltage 430 and reference value 428. The voltage shift amount is selected from at least two voltage shift amount candidates. The ADC can select this voltage offset to ensure that the voltage of the rise signal will be close to the reference value 428 but not deviate too far from the reference value 428, thus prolonging the rise time. Exemplary voltage shift amount options are described below with reference to Figure 6.

[0083] At block 508, voltage shifter 404 shifts voltage 430 based on a selected voltage shift amount signal 420-1 and in response to an applied voltage shift signal 424. In some cases, a voltage jump can be initiated after the voltage 430 is shifted. At block 510, jump generator 134 initiates a jump signal that changes the voltage 430 at input 414 of reference cross detector 132 in response to a jump trigger signal 426. As described herein, the jump signal can be implemented as a digital jump, which uses an array of capacitors coupled to node 410 to increase voltage 430 in quantized steps.

[0084] At block 512, reference cross detector 132 determines whether voltage 430 exceeds reference value 428. When voltage 430 does not reach reference value 428, the jump signal can continue at block 514 to change (e.g., increase or decrease) voltage 430 (e.g., for positive or negative jumps, respectively). As part of the process loop, reference cross detector 132 can also continue to detect whether voltage 430 exceeds reference value 428 at block 512. In response to voltage 430 crossing reference value 428, reference cross detector 132 detects the crossing and changes the value of detection signal 420, which corresponds to the locked bit value signal 420-2 in this operation phase.

[0085] At block 516, reference cross detector 132 sends a lock bit value signal 420-2 to jump generator 134 and causes jump generator 134 to stop increasing the jump signal. Therefore, voltage 430 can stop increasing at node 410. Furthermore, jump generator 134 can output bit value 312 to register 306 at block 518 (e.g., both in Figure 3). Bit value 312 can represent at least a portion of the ADC's digital output signal 214.

[0086] Due to signal propagation or circuit operation latency, voltage 430 may exceed reference value 428 before the rise signal stops. This voltage overshoot can complicate the operation of subsequent ADC stages by limiting the amplification range of intermediate residual amplifier 304. To reduce voltage overshoot, at block 520, offset adjuster 406 adjusts voltage 430 based on the amount of offset voltage in response to the applied voltage offset signal 420-3. At block 522, the ADC can forward the final level of voltage 430 as a residual signal (e.g., analog residual signal 308 in Figure 3) to downstream elements of pipeline ADC 130-1.

[0087] Figure 4-1 is a schematic diagram 400-1 of an exemplary ADC 130 (e.g., Figures 1-3) including a reference cross-detector 132, a jump generator 134, and a voltage shifter 404. In an exemplary implementation, the device may include the ADC 130 as described herein. The reference cross-detector 132 includes an input 414 and an output 416. The jump generator 134 is coupled between the output 416 of the reference cross-detector 132 and the input 414 of the reference cross-detector 132. The voltage shifter 404 is coupled between the output 416 of the reference cross-detector 132 and the input 414 of the reference cross-detector 132.

[0088] Figure 4-2 is a schematic diagram 400-2 of an exemplary ADC 130 (e.g., Figures 1-3) including a reference cross-detector 132, a boost generator 134, and an offset adjuster 406. In an exemplary implementation, the apparatus may include the ADC 130 as described herein. The reference cross-detector 132 includes an input 414 and an output 416. The boost generator 134 is coupled between the output 416 of the reference cross-detector 132 and the input 414 of the reference cross-detector 132. The offset adjuster 406 is coupled between the output 416 of the reference cross-detector 132 and the input 414 of the reference cross-detector 132.

[0089] Figure 6 generally illustrates two graphs at 600. The lower graph (bottom two-thirds of the figure) illustrates the voltage versus time relationship, illustrating exemplary voltage levels at the input / output nodes of the ADC using voltage shifters and offset adjusters. The upper graph (top third of the figure) shows the voltage versus time relationship, illustrating exemplary voltage values ​​generated by comparing the voltages in the lower graph. The lower graph illustrates the voltage along the vertical axis, where the voltage corresponds to voltage 430 at input 414 of reference cross detector 132. The voltage axis illustrates the reference value 428 and four voltage levels "a" to "d" (which are above reference value 428) and four voltage levels "-a" to "-d" (which are below reference value 428). Time increases by eight (8) or more time units to the right along the horizontal axis from zero (0). The upper graph illustrates the voltage along the vertical axis, where the voltage corresponds to the detection signal 420 at output 416 of reference cross detector 132. First, the diagram below is described in detail, and then the diagram above with detection signal 420 is further described.

[0090] As shown in the illustration, the thick solid lines correspond to initial voltage levels above the reference value 428, while the thick dashed lines correspond to initial voltage levels below the reference value 428. These thick lines represent the voltage 430 across the five stages (Φ1 to Φ5) of operation. The thick solid lines have phases indicated by capital "A" (phases Φ1A to Φ5A), while the thick dashed lines have phases indicated by capital "B" (phases Φ1B to Φ5B).

[0091] In the exemplary implementation, the first phase Φ1 corresponds to the determination of the initial voltage level of the input signal 418 by the reference cross detector 132. The second phase Φ2 corresponds to the voltage displacement performed by the voltage shifter 404 before the voltage rise of the rise generator 134. The third phase Φ3 corresponds to the rise of the voltage 430 by the rise generator 134. The fourth phase Φ4 corresponds to the locking of the digital value and the voltage overshoot of the rise generator 134, together with the determination of the reference cross detector 132. The fifth phase Φ5 corresponds to the voltage offset adjustment of the offset adjuster 406.

[0092] The illustration shows two exemplary voltage offsets: a first voltage amount 602-1 (or a first voltage offset 602-1) and a second voltage amount 602-2 (or a second voltage offset 602-2). As illustrated, one voltage amount differs from the other to illustrate different initial voltage levels of the input signal 418. For example, the first voltage amount 602-1 (or the first amount) used for the initial positive voltage level is greater than the second voltage amount 602-2 (or the second amount) used for the initial negative voltage level. This ensures that the voltage level after offsetting from the initial positive voltage level begins to rise in a stepwise manner at a voltage level below the reference value 428. When the initial voltage level is "already" below the reference value 428, the rise period of multiple voltage levels can also be shortened by reducing the magnitude of the voltage rise before reaching the reference value 428. By reducing the rise period in this way, ADC operation can be completed more quickly.

[0093] In the exemplary operating environment of Figure 600, the rise generator 134 generates a positive rise. Therefore, the voltage 430 increases during the third phase Φ3. However, the techniques described herein can be applied to negative rises, where a digital rise reduces the voltage 430 in the third phase Φ3. In this case, the relative magnitudes of the first voltage quantity 602-1 and the second voltage quantity 602-2 can be reversed such that the smaller of the two is applied to (e.g., added to) the initial positive voltage level of the input signal 418. The voltage levels of Figure 600 will be further described with reference to Figures 6 and 7. For clarity, some exemplary implementations are described using a reference value 428 that is approximately zero volt or a ground level. However, the reference value 428 may correspond to another voltage level, such as a voltage level close to zero volts (e.g., a few millivolts (mV)) or a voltage level relatively far from zero volts (e.g., 100 or 200 mV).

[0094] Figure 7 is a circuit diagram 700 of an exemplary ADC, which includes a reference cross-detector 132, a jump generator 134, and a voltage shifter 404 or an offset adjuster 406. Circuit diagram 700 illustrates additional exemplary circuitry for certain elements of the schematic diagram 400 of Figure 4. Figure 7 also illustrates phases Φ1 to Φ5 of Figure 6 at exemplary related locations. Each of the jump generator 134, voltage shifter 404, and offset adjuster 406 includes at least one corresponding switch. Each of the jump generator 134, voltage shifter 404, and offset adjuster 406 also includes at least one corresponding capacitor, which may be part of the plurality of capacitors 136 (e.g., those in Figures 1 and 4). The illustrated elements may also include logic units that are part of ADC control circuitry 402 (e.g., those in Figure 4). The logic unit may be implemented using circuitry (e.g., passive circuitry, active circuitry such as one or more transistors, logic gates, flip-flops or latches, and delay elements) designed, manufactured, or otherwise implemented to perform the functions described herein.

[0095] In an exemplary embodiment, the jump generator 134 may include a plurality of buffers 702-1...702-N and a plurality of latches 704-1...704-N, where "N" represents a positive integer. Typically, the plurality of buffers 702-1 to 702-N are coupled to the plurality of latches 704-1 to 704-N, respectively. The buffers of the plurality of buffers 702-1 to 702-N may be coupled together in series. The jump generator 134 also includes at least one capacitor (jump capacitor 706 (C.ramp 706)) and at least one switch 708. A first side or first terminal of the jump capacitor 706 is coupled to an input 414 of a reference cross detector 132. A second side or second terminal of the jump capacitor 706 is coupled to at least one voltage rail, which provides at least one voltage increment 710. The voltage jump rail may be maintained at the voltage increment 710, which corresponds to the subtlety of the jump signal used to increase or decrease at node 410. N latches 704-1 to 704-N can be coupled to at least one switch 708 via N lines to control the corresponding states (e.g., open or closed) of one or more switches 708. These N lines can provide digital values ​​312 output by the N latches 704-1 to 704-N. In some cases, the jump generator 134 includes N switches 708 and N jump capacitors 706. An exemplary implementation of the jump generator 134 is described below with reference to Figure 8.

[0096] Voltage shifter 404 may include at least one capacitor (shift capacitor 712) and at least one switch 714. Shift capacitor 712 is coupled between node 410 and switch 714. A first terminal of shift capacitor 712 is coupled to input 414 of reference cross detector 132. At least one switch 714 is coupled between (i) a second terminal of shift capacitor 712 and (ii) a first voltage rail or a second voltage rail. The at least one switch 714 may be implemented as, for example, a single-pole double-throw (SPDT) switch. ADC control circuitry 402 or another element may hold the first voltage rail at a first voltage level 716-1 and the second voltage rail at a second voltage level 716-2. The first voltage level 716-1 may correspond to a first voltage offset 602-1 (Figure 6), and the second voltage level 716-2 may correspond to a second voltage offset 602-2. Each voltage level 716 may be provided using a direct current (DC) voltage. Voltage shifter 404 may also include logic 718 to control the state of switch 714. Logic unit 718 may coordinate or control switch 714 based on applied voltage shift signal 424 and selected voltage shift amount signal 420-1. Therefore, at least one capacitor (e.g., shift capacitor 712), at least one switch (e.g., switch 714), and logic 718 may collectively comprise voltage shifter 404. An exemplary implementation of voltage shifter 404 is described below with reference to Figure 9.

[0097] The offset adjuster 406 may include at least one capacitor (adjustment capacitor 722) and at least one switch 724. Adjustment capacitor 722 is coupled between node 410 and switch 724. A first terminal of adjustment capacitor 722 is coupled to input 414 of reference cross-detector 132. The at least one switch 724 is coupled between a second terminal of adjustment capacitor 722 and at least one voltage rail. ADC control circuitry 402 or another element may maintain the voltage rail at an offset voltage amount 726. The offset voltage amount 726 (or offset voltage level) may correspond to an offset voltage adjustment amount 604 (or offset voltage adjustment level) (in Figure 6). The voltage amount 726 may be provided using a direct current (DC) voltage. The offset adjuster 406 may also include logic 728 to control the state of switch 724. Logic 728 may coordinate or control switch 724 based on the applied voltage offset signal 420-3. Therefore, at least one capacitor (e.g., adjusting capacitor 722), at least one switch (e.g., switch 724), and logic 728 may collectively comprise offset adjuster 406. An exemplary implementation of offset adjuster 406 is described below with reference to Figure 10.

[0098] For clarity, the switches in Figure 7 are shown as open and capable of being closed to connect the corresponding capacitor to the corresponding voltage source or voltage level. For example, at least one switch 708, at least one switch 714, and at least one switch 724 are all shown as "started" in the open state. However, each of these switches may have an initial state of connecting the terminals of the corresponding capacitor to a known voltage level (e.g., DC voltage or ground). For example, switch 724 may disconnect the second terminal of adjusting capacitor 722 from ground and connect the second terminal of adjusting capacitor 722 to an offset voltage amount 726. This is shown more clearly in Figures 8 through 10 and further described below. Each at least one switch may be implemented as a single switch, multiple switches (e.g., as at least two switches, such as a first switch and a second switch), a single-pole multi-throw switch (e.g., as a single-pole double-throw (SPDT) switch), or some combination thereof. Each switch or part thereof may be implemented using at least one transistor (e.g., a field-effect transistor (FET)).

[0099] This document now describes an exemplary operation of circuit diagram 700 with reference to operation phases Φ1 to Φ5, also illustrated in Figure 6. For simplicity, this description is provided in the context of a positive rise process, where reference value 428 is zero volts. However, the relevant principles also apply to negative rise processes or non-zero reference value 428. Before the first phase Φ1 begins or at least completes, sampling signal 422 closes switch 408. Once the voltage of input signal 418 is delivered to node 410, sampling signal 422 can open switch 408, and the first phase Φ1 can begin, complete, or otherwise occur. Node 410 therefore samples the voltage of input signal 418 as a sampling signal and uses it as the initial voltage level of voltage 430. The operation of positive input signal 418 is described first, corresponding to phases Φ1A to Φ5A in Figure 6.

[0100] Reference cross-detector 132 compares the initial voltage with zero voltage (e.g., similar to the operation of a zero-crossing detector (ZCD)). If the initial voltage is positive, reference cross-detector 132 generates a first value for the detection signal 420. In the first phase Φ1A, at the output 416 of reference cross-detector 132, the selected voltage shift amount signal 420-1 is driven to the first value. The logic 718 of voltage shifter 404 receives or otherwise receives the selected voltage shift amount signal 420-1 at the first value. Based on the first value, logic unit 718 sets switch 714 to connect shift capacitor 712 to a first voltage rail on the first voltage shift amount 716-1.

[0101] In the second stage Φ2A, the applied voltage shift signal 424 can be generated as a delayed version of the sampled signal 422 (e.g., after a delay in the first delay unit 412-1). In response to the activation of the applied voltage shift signal 424, logic unit 718 connects the second plate of shift capacitor 712 to the first voltage rail according to a first value of the selected voltage shift amount signal 420-1. This causes the voltage 430 at input 414 of reference cross detector 132 to shift downward (e.g., decrease) by the first voltage shift amount 602-1 in the second stage Φ2A. After the voltage shift, voltage 430 can rise. At least the second delay unit 412-2 generates another delay or a single longer delay. This longer delay results in a rise trigger signal 426, which can also be based on the sampled signal 422. In the third stage Φ3A, ADC control circuitry 402 couples the rise trigger signal 426 to a first or initial buffer of a series of buffers formed by multiple buffers 702-1 to 702-N.

[0102] As a pulse traverses multiple buffers 702-1 to 702-N, a corresponding latch among multiple latches 704-1 to 704-N is activated or supplied with a voltage value corresponding to the pulse. The activation latches of these multiple latches 704-1 to 704-N use a digital value 312 to close a corresponding switch in switch 708. Each closed switch 708 connects another step capacitor 706 to at least one voltage rail maintained at voltage increment 710. Therefore, each closed switch 708 increases the voltage 430 at input 414 of reference cross detector 132. This causes voltage 430 to jump upwards (e.g., increase or climb in this example). Although this jump is shown as a smooth line in Figure 6, the digital jump process can include quantized steps.

[0103] Ultimately, the voltage rise at input 414 of reference cross-detector 132 exceeds the reference value 428 (zero volts in this example). In response to this reference value exceedance, reference cross-detector 132 can change the value of detection signal 420 to generate a latched digital value signal 420-2 in the fourth stage Φ4A. The latched digital value signal 420-2 has the function of latching the respective latches of the plurality of latches 704-1 to 704-N to the value of any value from the respective buffers of the plurality of buffers 702-1 to 702-N currently coupled to. This terminates the voltage rise at node 410 by preventing any further switches 708 from closing.

[0104] As shown in Figure 6, in stages Φ4A and Φ4B, the voltage 430 at input 414 overshoots the reference value 428. Here, the reference value 428 is zero volts, and the voltage 430 at node 410 is above zero voltage. Due to the amplification constraints of the adjacent downstream residual amplifier 304, this reduces the dynamic range used to process the residual signal in subsequent ADC stages. Therefore, the offset adjuster 406 can reduce the absolute value of voltage 430 or generally reduce the magnitude of voltage overshoot relative to the zero-volt reference value 428. In stage Φ5A, logic 728 interprets the detection signal 420 set by exceeding the reference value 428 as an applied voltage offset signal 420-3. In response to receiving or otherwise receiving the applied voltage offset signal 420-3 from the reference cross detector 132, logic unit 728 closes switch 724, thereby coupling the second terminal of adjustment capacitor 722 to at least one voltage rail with an offset voltage amount 726. This reduces the voltage 430 at node 410 by a voltage adjustment amount 604 (as shown in Figure 6), bringing the voltage 430 close to zero volts.

[0105] As previously described, the ADC operation for the first to fifth stages Φ1B to Φ5B of the negative input signal 418 is similar to the operation for the first to fifth stages Φ1A to Φ5A of the positive input signal 418. However, the first stage Φ1B and the second stage Φ2B differ from the first stage Φ1A and the second Φ2A. In the first stage Φ1B, the reference cross-detector 132 determines that the initial voltage level of the voltage 430 is negative. If the downward voltage shift is small compared to a larger amount, the positive jump process targeting the zero-volt reference value 428 can be completed more quickly (assuming a constant ramp rate). To enable this different voltage shift amount, based on the initial voltage being negative (or more generally, less than the reference value 428), the reference cross-detector 132 generates a second value for the detection signal 420. In the first stage Φ1B, at the output 416 of the reference cross-detector 132, the selected voltage shift amount signal 420-1 is driven to the second value.

[0106] The logic unit 718 of the voltage shifter 404 receives a selected voltage shift amount signal 420-1 at a second value. Based on the second value, the logic 718 sets the switch 714 to connect the shift capacitor 712 to at least one second voltage rail on the second voltage shift amount 716-2. In the second phase Φ2B, the applied voltage shift signal 424 can be generated as a delayed version of the sampled signal 422 (e.g., after the delay of the first delay unit 412-1). In response to the activation of the applied voltage shift signal 424, the logic 718 connects the second plate of the shift capacitor 712 to the second voltage rail. This causes the voltage 430 at the input 414 of the reference cross detector 132 to shift downward (e.g., decrease) by a second voltage offset amount 602-2 at the second phase Φ2B. After the voltage shift, the voltage 430 can jump at the third phase Φ3B. The reference cross detector 132 detects a signal overshoot in the fourth phase Φ4B and terminates the jump with a locked bit value signal 420-2. In the fifth stage Φ5B, offset adjuster 406 uses offset adjustment amount 726 to correct voltage overshoot.

[0107] The upper graph in Figure 6 illustrates an example of the relationship between the detection signal 420 and time, which is related to the exemplary voltage in the lower figure. In the exemplary implementation, the detection signal 420 is a function of voltage 430 and reference value 428. For example, reference cross-detector 132 may generate the detection signal 420 based on a comparison of voltage 430 with respect to reference value 428. As shown in the upper graph of this example, reference cross-detector 132 outputs a higher voltage level ("+1") in response to voltage 430 being higher than reference value 428, and outputs a relatively lower voltage level ("0") in response to voltage 430 being lower than reference value 428.

[0108] As an example, the detection signal 420 in the above figure tracks the voltage when the sampled signal 122 is above the reference value 428, but the signal analysis is similar when the sampled signal 122 is below the reference value 428. During the first phase Φ1A, the detection signal 420 corresponds to the selected voltage shift signal 420-1 and has a relatively high voltage value. The selected voltage shift signal 420-1 responds to the applied voltage shift signal 424 and at least partially controls the voltage shifter 404, as explained above and further described below with respect to Figure 9. During the second phase Φ2A, the detection signal 420 is illustrated as having a relatively low voltage value during period 606, but the ADC 130 is not controlled by the detection signal 420 during this period 606. Period 606 extends to the third phase Φ3A until the jump signal crosses the reference value 428. At this time 612, the voltage 430 exceeds the reference value 428, and the detection signal 420 climbs to a higher voltage value at the end of period 606.

[0109] As shown in the figure above, this rising edge of the detection signal 420 corresponds to the lock bit value signal 420-2 and the applied voltage offset signal 420-3. The lock bit value signal 420-2 at least partially controls the jump generator 134, as explained above and further described below with reference to Figure 8. As described below with reference to Figure 8, the rising edge of the detection signal 420 can cause the lock bit value signal 420-2 to be gated relative to a plurality of latches 704-1 to 704-N of the jump generator 134 to prevent subsequent changes in the detection signal 420 from unlocking the latches. The applied voltage offset signal 420-3 at least partially controls the offset adjuster 406, as explained above and further described below with reference to Figure 10.

[0110] During period 608, via the fourth stage Φ4A, the detection signal 420 remains at a relatively high voltage level until the offset adjuster 406 returns the voltage 430 to the reference value 428. During the fifth stage Φ5A, the voltage 430 is approximately equal to the reference value 428. In an ideal circuit, the detection signal 420 would have a determinable value (e.g., a zero-volt input would produce a zero-volt output, or the voltage would be at the midpoint of 0.5 * the voltage rail's voltage level). However, for a physical circuit, the value of the detection signal 420 during period 610 may be undefined. As previously mentioned, the latched digit value signal 420-2 can be gated from multiple latches 704-1 to 704-N before the start of period 610, keeping the digit value 312 latched. Sometime after the start of the fifth stage Φ5A, the current ADC cycle can be completed, and a new cycle can be started using the sampling signal 422.

[0111] Figure 8 is a circuit diagram 800 of an exemplary jump generator 134 (e.g., Figures 4 and 7). In an exemplary implementation, the jump capacitor 706 can be implemented as a capacitor bank 806 or a capacitor array 806. The capacitor array 806 includes a first jump capacitor 706-1 (C.ramp1 706-1), a second jump capacitor 706-2 (C.ramp2 706-2), a third jump capacitor 706-3 (C.ramp3 706-3), ..., an "Nth" jump capacitor 706-N (C.rampN 706-N). Each jump capacitor 706 of the capacitor array 806 is coupled to node 410. The switch 708 can be implemented as a switch bank 808 or a switch array 808. The switch array 808 includes a first step switch 708-1, a second step switch 708-2, a third step switch 708-3, ..., an "Nth" step switch 708-N.

[0112] As shown in the figure, each of the plurality of step capacitors 706-1 to 706-N has a corresponding step capacitor 706 coupled between a plurality of step switches 708-1 to 708-N and node 410. Each step switch 708 may be coupled between a corresponding step capacitor 706 and at least one voltage rail corresponding to a voltage level (e.g., the amount of voltage increment (VI) used to increase the step at each step). The corresponding step capacitor 706 may also be coupled to ground voltage (GND), which will be described below. The plurality of step capacitors 706-1 to 706-N may be encoded in any of a variety of different ways (e.g., using thermometer encoding).

[0113] The plurality of buffers 702-1 to 702-N are shown as being serially coupled together as a first buffer 702-1 (buffer 1), a second buffer 702-2 (buffer 2), a third buffer 702-3 (buffer 3), ..., "Nth" buffer 702-N (buffer N). Buffers such as the initial buffer or the first buffer 702-1 receive a jump trigger signal 426 from the ADC control circuit 402 (e.g., using at least one delay unit 412) in the third stage Φ3. The pulse travels through the serially connected buffers from the first buffer 702-1 to the "Nth" buffer 702-N. In some cases, differential circuitry can be used to implement each buffer 702. Using two parallel buffer chains for differential signals, latch control signals for the plurality of latches 704-1 to 704-N can be extracted from the plurality of buffers 702-1 to 702-N in alternating buffer chains, such that each buffer 702 can be formed by an inverter for each positive buffer chain and each negative buffer chain.

[0114] The plurality of latches 704-1 to 704-N are shown as having a first latch 704-1 (latch 1), a second latch 704-2 (latch 2), a third latch 702-3 (latch 3), ..., an "Nth" latch 704-N (latch N). Each corresponding latch 704 may include two inputs and one output. The first input of each corresponding latch 704 of the plurality of latches 704-1 to 704-N is coupled to the output of the corresponding buffer 702 of the plurality of buffers 702-1 to 702-N. Thus, the plurality of latches 704-1 to 704-N can track the process of pulses propagating through the plurality of buffers 702-1 to 702-N. The second input of each of the plurality of latches 704-1 to 704-N is coupled to receive a locked digital value signal 420-2. In response to the activation of the latch value signal 420-2, in the fourth stage Φ4, each of the plurality of latches 704-1 to 704-N latches the output signal of the corresponding buffer 702 among the plurality of buffers 702-1 to 702-N. In some cases, the plurality of buffers 702-1 to 702-N and the plurality of latches 704-1 to 704-N may be coupled together in a manner similar to that of the time-to-digital converter 802 (TDC 802).

[0115] As described above with reference to Figure 6, at the end of time period 606, the latch value signal 420-2 goes high at time 612. This relatively high voltage can cause multiple latches 704-1 to 704-N to latch. However, the latch value signal 420-2 may drop to a relatively low voltage or an undefined level during time period 610. To prevent such a change in the latch value signal 420-2 from affecting the latching time (and thus potentially affecting the digit value 312), a gate control circuit 810 (GC 810) can be coupled between the reference cross detector 132 (e.g., Figure 4) and the respective second inputs of the multiple latches 704-1 to 704-N. The gate control circuit 810 can selectively determine when or whether the multiple latches 704-1 to 704-N are sensitive to or affected by the latch value signal 420-2. For example, the gate control circuit 810 can respond to the lock bit value signal 420-2 going high and, after some lock-allowed delay time, decouple multiple latches 704-1 to 704-N from the lock bit value signal 420-2 for the remainder of the ADC cycle.

[0116] As shown in Figure 8, each of the plurality of switches 708-1 to 708-N has its corresponding switch 708 coupled between its corresponding latch 704 in the plurality of latches 704-1 to 704-N and its corresponding step capacitor 706 in the plurality of step capacitors 706-1 to 706-N. For example, the output of each of the plurality of latches 704-1 to 704-N can be coupled to the control input of each of the plurality of switches 708-1 to 708-N. The output of each of the N latches 704-1 to 704-N corresponds to the corresponding bit 804 of the N bit values ​​804-1 to 804-N. Therefore, the first latch 704-1 can output a first digit value bit 804-1, the second latch 704-2 can output a second digit value bit 804-2, the third latch 704-3 can output a third digit value bit 804-3, ..., and the Nth latch 704-N can output a Nth digit value bit 804-N. The digit value 312 can include at least a portion of the "N" digit value bits 804-1, 804-2, 804-3, ..., 804-N. Therefore, the digit value bit 804 output from each latch 704 can control whether the corresponding switch 708 is open or closed (for example, an open or closed state can be established for the corresponding switch 708).

[0117] As the trigger pulse propagates through multiple buffers 702-1 to 702-N, corresponding latches among multiple latches 704-1 to 704-N close corresponding switches among multiple switches 708-1 to 708-N. When each switch 708 is closed, the second terminal of the corresponding step capacitor 706 is coupled to a voltage level. Therefore, the first terminal of the corresponding step capacitor 706 can increase the voltage 430 on node 410 (for a positive step) to cause the voltage 430 at input 414 of the reference cross detector 132 to step.

[0118] In some cases, at least one switch 708 initially couples the corresponding step capacitor 706 to ground (GND) or another DC voltage (as an "initial" voltage level). When a pulse passes through a portion of the plurality of latches 704-1 to 704-N, at least one switch 708 disconnects the step capacitor 706 from ground (GND) and couples the step capacitor 706 to a voltage increment (VI). This changes the voltage "applied" to node 410 by the corresponding step capacitor 706. Here, the at least one switch 708 may include an open first switch (e.g., a closed first transistor) to disconnect the second terminal of the step capacitor 706 from ground, and a closed second switch (e.g., a closed second transistor) to connect the second terminal of the step capacitor 706 to the voltage increment. However, switch 708 may be implemented in an alternative manner.

[0119] Therefore, the time-to-digital converter 802 of the rise generator 134 can encode a digital value 312 (e.g., Figure 3) representing at least a portion of the digital output signal 214 of the analog-to-digital converter 130 in various states of the various latches 704-1 to 704-N, various states of the various switches 708-1 to 708-N, or combinations thereof. The various capacitors 706-1 to 706-N can convert the digital value 312 to an analog version to cause a voltage rise 430 at node 410. The rise generator 134 is described with reference to Figure 8, which employs a TDC-type circuit. However, the rise generator 134 can be implemented differently. For example, the rise generator 134 can be implemented using a binary weighted capacitor array, an operational amplifier-based analog integrator, or a fixed current source coupled to a capacitor.

[0120] Figure 9 is a circuit diagram 900 of an exemplary voltage shifter 404 (e.g., Figures 4 and 7). Circuit diagram 900 illustrates an exemplary implementation of logic 718. As shown, logic 718 may include at least one flip-flop 902. In this example, flip-flop 902 is implemented as a "D" flip-flop (DFF). A data input (e.g., a "D" input) is coupled to the output 416 of a reference cross-detector 132 to receive or otherwise receive a selected voltage shift amount signal 420-1 at a first stage Φ1. The clock input "<" of the "D" flip-flop 902 is coupled to circuitry (such as a first delay unit 412-1) that provides the applied voltage shift signal 424. The output of the "D" flip-flop 902 is coupled to the control terminal of switch 714.

[0121] In exemplary operation, the reference cross-detector 132 selects the position of switch 714 (for a first voltage level or a second voltage level) using a selected voltage shift signal 420-1 in the first stage Φ1. This establishes the voltage shift for the second stage Φ2. In response to the activation of the applied voltage shift signal 424 (e.g., with a rising or falling edge), the "D" flip-flop 902 transmits the value on the "D" input to the flip-flop output. Therefore, logic 718 can control the state of switch 714 to select between at least two voltage offsets. In response to a signal received from logic 718, switch 714 can selectively change the second terminal of shift capacitor 712 from being coupled to ground voltage to being coupled to either a first voltage amount 716-1 or a second voltage amount 716-2. In operation, at the beginning of each ADC cycle, ADC control circuitry 402 (Figure 4) can reset flip-flop 902 and position at least one switch 714 to connect the second terminal of shift capacitor 712 to ground.

[0122] In an alternative implementation, the reference cross-detector 132 and voltage shifter 404 can assign the initial voltage level of the input signal 418 to more than two categories or ranges. For example, the voltage shifter 404 can have three or four voltage shift amounts, assigned based on how far (above or below) the initial voltage level is relative to the reference value 428. This reduces the amount of time consumed during the rise process in the third stage Φ3 so that the reference value 428 is reached after the voltage shift in the second stage Φ2. In this case, the logic 718 can be modified to handle a finer classification of the initial voltage level (e.g., beyond two categories corresponding to positive and negative values, or beyond less than or greater than zero volts). Therefore, in this case, the selected voltage shift amount signal 420-1 can have more than two bits to distinguish more than two voltage shift amounts.

[0123] Figure 10 is a circuit diagram 1000 of an exemplary offset adjuster 406. Circuit diagram 1000 illustrates an exemplary implementation of logic 728. As shown, logic 728 may include at least one flip-flop 1002. In this case, flip-flop 1002 is implemented as a "D" flip-flop (DFF). The "D" input is coupled to a fixed value, such as a power supply voltage. The output of the "D" flip-flop 1002 is coupled to the control terminal of switch 724. Referring to Figures 6 and 7, after the rise process terminates at the fourth stage Φ4 of operation, switch 724 will close at the fifth stage Φ5. Therefore, the clock input "<" of flip-flop 1002 will be triggered at the fifth stage Φ5 in response to the applied voltage offset signal 420-3. In this case, at least one switch 724 is closed to connect the second terminal of the adjusting capacitor 722 to the offset voltage amount 726. Based on the signal received from the flip-flop 1002, at least one switch 724 (e.g., using a first switch and a second switch implemented with a first transistor and a second transistor) can also be turned on to disconnect the second terminal of the adjusting capacitor 722 from ground.

[0124] However, the purpose or meaning of the detection signal 420 output by the cross-detector 132 changes at different stages of ADC operation. As shown in Figures 7 and 10, the detection signal 420 is associated with the first stage Φ1, the fourth stage Φ4, and the fifth stage Φ5. Logic 728 includes circuitry such as a signal disambiguator 1004 to ensure that the relevant transitions of the detection signal 420 are applied to the clock input of the flip-flop 1002. In exemplary operation, the signal disambiguator 1004 therefore gates the selection voltage shift signal 420-1 in the first stage Φ1.

[0125] In contrast, signal disambiguator 1004 transmits the applied voltage offset signal 420-3 to the clock input in the fifth stage Φ5. For this purpose, for example, after the rise trigger signal 426 is initiated in the third stage Φ3, signal disambiguator 1004 can transmit the detection signal 420 as the applied voltage offset signal 420-3 to the clock input of flip-flop 1002. In this case, the rise trigger signal 426 can be routed to signal disambiguator 1004. As an alternative timing method, after the detection signal 420 is transformed into the locked digital value signal 420-2 in the fourth stage Φ4, signal disambiguator 1004 can introduce a delay period (e.g., using another delay unit 412). After the delay period, signal disambiguator 1004 can provide the detection signal 420 as the applied voltage offset signal 420-3 to the clock input of flip-flop 1002 in the fifth stage Φ5. In operation, at the beginning of each ADC cycle, the ADC control circuit 402 (Figure 4) can reset the flip-flop 1002 of logic 728. This reset can change the output of flip-flop 1002 from "1" to "0", thereby changing at least one switch 724 from connecting the second terminal of adjustment capacitor 722 to offset voltage amount 726 to connecting the second terminal of adjustment capacitor 722 to ground. If adjustment capacitor 722 is coupled to ground or another DC voltage, applying voltage offset signal 420-3 can apply a calibrated voltage offset amount in the next cycle.

[0126] Figure 11 generally illustrates an example of a capacitor array 1102 at 1100, which can be used as capacitors (e.g., one or more of capacitors 136 in Figures 1 and 4) to implement ADC elements in a differential environment. The capacitor array 1102 can be used to implement a step capacitor 706, a shift capacitor 712, or a regulating capacitor 722 (e.g., each in Figure 7). The voltages to which these capacitors may be coupled (such as offset voltage amount 726 or first voltage shift amount 716-1 and second voltage shift amount 716-2) may not be implemented using voltage rails directly connected to the power rails or power management integrated circuit (PMIC). Instead, in some implementations, the voltages for these voltage rails can be established or generated in different ways. For example, a DAC with a capacitor array can generate these voltages using, for example, a positive reference voltage V.refp from a positive voltage rail and a negative reference voltage V.refm from a negative voltage rail, as described with reference to Figure 11.

[0127] Figure 11 is primarily described based on voltage shifter 404, but its principles apply to other components (including those described below). In a differential environment, reference cross-detector 132 may include positive and negative inputs for input 414. In this case, voltage 430 may correspond to positive voltage signal V+ and negative voltage signal V- (as shown in Figure 11), and node 410 may correspond to positive node 410+ and negative node 410- (also as shown in Figure 11). Capacitor array 1102 is shown as having six capacitors C0, C1, C2, C6, C7, and C8, but the array may contain more or fewer capacitors. In the lower half of Figure 11, the first group of capacitors includes capacitors C0, C1, and C2. These three capacitors are coupled between the positive node 410+ with positive voltage signal V+ and the differential portion of the applied voltage shift signal 424. Each corresponding capacitor C0, C1, and C2 is coupled with a corresponding inverse OR gate between a line used to apply the voltage shift signal bar 424b (SHIFTb). Each inverse OR gate has two inputs: a first input coupled to the applied voltage shift signal bar 424b and a second input coupled to the control bit_bar signal. The control bit_bar signal includes CNTL0b, CNTL1b, and CNTL2b bits for capacitors C0, C1, and C2, respectively.

[0128] In the upper half of Figure 11, the second group of capacitors includes capacitors C6, C7, and C8. These three capacitors are coupled between a negative node 410- with a negative voltage signal V- and the differential portion of the applied voltage shift signal 424. A corresponding inverse gate is coupled between each of the respective capacitors C6, C7, and C8 and the line used to apply the voltage shift signal 424 (SHIFT). Each inverse gate has two inputs: a first input coupled to the applied voltage shift signal 424 and a second input coupled to a control bit signal. The control bit signal includes CNTL0, CNTL1, and CNTL2 bits for capacitors C6, C7, and C8, respectively.

[0129] At least one corresponding switch is coupled between each corresponding capacitor and each corresponding logic gate (e.g., an inverse gate or an inverse OR gate). As shown, each corresponding switch can be implemented as a single-pole double-throw (SPDT) switch. The pole is coupled to the second terminal of each capacitor. Each of the two throws is coupled to a corresponding differential voltage: a positive reference voltage V.refp or a negative reference voltage V.refm. The output of the corresponding logic gate controls the state of the SPDT switch. In some cases, the SPDT switch can be implemented with two transistors, such as an n-type FET (nFET) coupled to V.refm and a p-type FET (pFET) coupled to V.refp (not shown). In some such cases, a single signal from the output of the corresponding logic gate can turn on one FET and turn off the other FET. However, each of the at least one switch can be implemented differently. In Figure 11, these switches are shown pre-positioned to generate a negative voltage offset. Thus, the "down" (as shown) switch coupled to the positive node 410+ via capacitors C0, C1, and C2 initially connects these capacitors to the positive reference voltage V.refp. The "up" switch, coupled to the negative node 410- via capacitors C6, C7 and C8, initially connects these capacitors to the negative reference voltage V.refm.

[0130] Although Figure 11 is described primarily around voltage shifter 404, the exemplary binary capacitor DAC shown can be used to at least implement shift capacitor 712 or adjustment capacitor 722. At the start of the ADC cycle, applying voltage shift signal 424 can provide the following values: SHIFT = 0 / SHIFTb = 1. This equal value causes the capacitor connected to the negative voltage signal V– to be connected to V.refm, while the capacitor connected to the positive voltage signal V+ is connected to V.refp. In response to the transition of the SHIFT / SHIFTb signal (e.g., applying voltage shift signal 424 at the second stage Φ2 or the fifth stage Φ5), logic 718 of voltage shifter 404 can cause one or more capacitors on V+ to change V.refp to V.refm, and one or more capacitors on V– to change from V.refm to V.refp. Using this exemplary configuration, these connection changes result in a negative differential voltage shift, as shown in Figure 6.

[0131] The amplitude of the voltage shift bits can be controlled via the CNTL# and CNTL#b bits. For example, if CNTL=010 and CNTLb=101, in response to the SHIFT signal changing from 0 to 1 (0=>1), the connection of capacitor C7 is changed. The connections of the other capacitors remain unchanged because the other inverting gates have a "0" input. Similarly, when the SHIFTb signal changes from 1 to 0 (1=>0), logic 718 can change the connection of capacitor C1, but the connections of the other capacitors remain unchanged because the other inverting gates have a "1" input.

[0132] Regarding voltage shifter 404, a first voltage shift amount 716-1 can be generated when CNTL = 001. A second voltage shift amount 716-2 can be generated when CNTL = 111. The output of reference cross detector 132 can be mapped to this code using digital logic, for example, as part of ADC control circuit 402 or its logic 718. Regarding offset adjuster 406, the circuit of Figure 11 can also be used to implement adjustment capacitor 722. In this case, CNTL bits can correspond to a calibration code. An exemplary method for generating the calibration code will be described next.

[0133] In some differential implementations, for voltage shifter 404 or offset adjuster 406, at least one switch 714 or 724 may each comprise a plurality of switches. Furthermore, the capacitors (e.g., shift capacitor 712 or adjustment capacitor 722, respectively) can be implemented using a capacitor differential array such as capacitor array 1102. The capacitor differential array may include a first set of capacitors (e.g., capacitors C0, C1, and C2) and a second set of capacitors (e.g., capacitors C6, C7, and C8). The first voltage rail may include a positive voltage rail (e.g., held to a positive reference voltage V.refp), and the second voltage rail may include a negative voltage rail (e.g., held to a negative reference voltage V.refm). Each of the first set of capacitors includes a first terminal coupled to the positive input of the reference cross detector 132 (e.g., V+ corresponding to the positive node 410+) and a second terminal selectively coupled to the positive or negative voltage rail via a corresponding first positive switch or first negative switch among the plurality of switches. Here, at least two switches can be used to implement the illustrated SPDT switch, one for each voltage rail. Each corresponding capacitor in the second group of capacitors includes a first terminal coupled to the negative input of the reference cross detector 132 (e.g., V- corresponding to the negative node 410-) and a second terminal selectively coupled to the positive or negative voltage rail via a corresponding second positive or second negative switch among a plurality of switches. The SPDT switch shown can be implemented using at least two switches, such as a positive switch for the positive voltage rail and a negative switch for the negative voltage rail.

[0134] Figures 12-1 and 12-2 include corresponding flowcharts illustrating the respective first and second stages of an exemplary calibration procedure. Figure 12-1 is a flowchart illustrating an exemplary calibration process 1200-1 for determining the first stage of the offset voltage amount 726. Process 1200-1 includes six (6) blocks 1202-1212. In the exemplary implementation, processes 1200-1 and 1200-2 illustrate techniques for determining the voltage adjustment amount 604, as shown for the first stage Φ5 in Figure 6. However, the calibration procedure can be performed using more, fewer, and / or different actions or in a different order. Furthermore, these actions can be performed in a fully or partially overlapping manner. Calibration can be performed in response to turning on the electronic device or each time the ADC is powered on.

[0135] At block 1202, a calibrated ADC is identified or obtained. For example, a subsequent or second ADC stage 302-2 of pipeline ADC 130-1 can be calibrated. The calibrated second ADC stage 302-2 can be used to calibrate the offset voltage amount 726 of another previous ADC stage. Alternatively, any currently unused or unparticipated ADC separate from ADC 130 can be used for calibration. For example, a maintenance or hold ADC or a one-bit ADC (e.g., implemented as a comparator) can be used. At block 1204, the ADC (e.g., its ADC control circuitry 402) uses another ADC, another ADC stage, an amplifier, or other circuitry within the ADC that connects V+ and V- to the same common-mode voltage to apply a zero-volt (0V) input signal 418 to the undercalibrated or first ADC stage 302-1. ADC stage 302-1 operates on the zero-volt input signal 418 using a certain "current" offset voltage adjustment code. Initially, the offset voltage adjustment code can be a preset code, such as a minimum code increased for calibration or a maximum code decreased for calibration. This example is described using a zero initial offset voltage adjustment code. This offset adjustment code can correspond to the control bit (CNTL) of the capacitor array 1102 implemented with the adjustment capacitor 722 in Figure 11.

[0136] At block 1206, the ADC control circuit 402 measures the residual of the first ADC stage 302-1 based on the digital value 312-2 generated by the second ADC stage 302-2. This application and measurement can be repeated multiple times (e.g., six iterations) to determine the average residual value. At block 1208, the ADC control circuit 402 determines whether the residual (e.g., the average residual value) is equal to zero volts (within some achievable measurement range). If the digital value 312-2 from the second ADC stage 302-2 is greater than zero, the residual or voltage overshoot is still too large.

[0137] Therefore, if the residual voltage is not equal to zero volts, the ADC control circuit 402 changes the current offset voltage adjustment code at block 1210. In this example, the current offset voltage adjustment code is increased to increase the amount of offset voltage adjustment applied by the adjustment capacitor 722 of the offset adjuster 406 in the fifth stage Φ5. After the current offset voltage adjustment code is changed at block 1210, the procedure can continue at block 1204.

[0138] Multiple iterations of the zero-volt input signal (in block 1204) and the residual measurement (in block 1206) in the next round result in a reduction in the absolute magnitude of the voltage overshoot. After one or more rounds of changing the offset voltage adjustment code (in block 1210), the analog residual signal 308-1 of the first ADC stage 302-1 (represented by the digital value 312-2 of the second ADC stage 302-2) becomes zero within a given measurement error, based on the voltage step size of the digital circuit. At block 1212, the first ADC stage 302-1 can use the current offset voltage adjustment code to establish a calibrated offset voltage amount 726, thereby providing a calibrated offset voltage adjustment amount 604 for the fifth stage Φ5 of the ADC operation (which is performed by the offset adjuster 406). Alternatively, the current offset voltage adjustment code can be considered as the first-level offset voltage adjustment code of the first stage of the determination procedure for calibrating the offset voltage adjustment amount. A second stage can be used to refine the offset voltage adjustment code, which will be described below.

[0139] Figure 12-2 is a flowchart illustrating an exemplary calibration process 1200-2 for determining the second stage of the offset voltage amount 726. Process 1200-2 comprises seven (7) blocks 1222-1234. If the input signal is zero volt, the offset voltage adjustment code determined in the first stage of calibration process 1200-1 is used to provide an offset adjustment amount so that the output residual is at zero volt. However, the intersection of these two values ​​may not be an intermediate voltage level. To determine the intermediate voltage level of the curve, the input signal can be adjusted over multiple input signals near zero volt, for example, by adjusting a few millivolts (mV). In some circuits, obtaining an input signal that can be finely adjusted may be difficult.

[0140] To accommodate this situation, the voltage 430 at node 410 can be adjusted using a capacitor DAC instead of changing the input signal. At block 1222, the calibration controller (e.g., the calibration controller of the ADC control circuit 402 in Figure 4) can use a capacitor DAC to simulate the deviation of the input signal. Alternatively, the "existing" circuitry of the ADC stage 302 can be used. For example, the shift capacitor 712 of the voltage shifter 404 can be used to change the initial value of voltage 430 using a first voltage quantity 716-1 or a second voltage quantity 716-2 (which includes changing the initial value of voltage 430 by using both and one or more switches 714).

[0141] At block 1224, the first undercalibrated ADC stage operates in response to the analog deviation input signal. In some cases, the input signal deviation is 1-5 mV, but other values ​​can also be used. At block 1226, the residual of the first ADC stage 302-1 is measured based on the digital value 312-2 output by the second ADC stage 302-2. At block 1228, the controller determines whether the target number of input signal deviations has been measured. Any number of input signal deviations can be measured. For example, three values ​​above zero volts and three values ​​below zero volts can be measured. If the target number of input signal deviations has not been measured, the analog deviation of the input signal is changed (e.g., increased or decreased) at block 1230. The actions of blocks 1224 to 1228 can be repeated until the target number of data points are obtained.

[0142] At block 1232, the midpoint of the output residual between the minimum and maximum measurement residual values ​​is calculated. At block 1234, the controller adds the calculated residual midpoint to the first-stage calibration offset voltage adjustment (from the first stage in Figure 12-1) to determine the operational calibration offset voltage amount 726 to be applied to node 410 after the rise termination. Therefore, this sum can establish a calibrated offset voltage amount 726 to provide a calibrated offset voltage adjustment amount 604 (Figure 6) for the fifth stage Φ5 of the ADC operation performed by the offset adjuster 406. The calibration controller (e.g., the calibration controller of the ADC control circuit 402 in Figure 4) can also adjust a calibrated version of the offset voltage amount based on the digital value generated by the rise generator to address mismatches in the components of the time-to-digital converter. For example, a checklist can be used to apply the correction based on each ADC output code.

[0143] Figure 13 is a flowchart illustrating an exemplary process 1300 for analog-to-digital conversion. Process 1300 is described in the form of a set of blocks 1302-1308, which specify the operations that can be performed. However, the operations are not necessarily limited to the order shown in Figure 13 or described herein, as these operations can be implemented in an alternative order or in a fully or partially overlapping manner. Furthermore, more, fewer, and / or different operations can be implemented to perform process 1300 or alternative processes. The operations represented by the blocks of process 1300 can be performed by ADC 130 or a portion thereof.

[0144] At block 1302, the ADC generates a first signal based on a second signal and a reference value. For example, reference cross-detector 132 can generate the first signal (e.g., at output 416) based on the second signal (e.g., present at input 414) and reference value 428. For example, reference cross-detector 132 can use detection signal 420 to indicate whether the voltage 430 at input 414 of reference cross-detector 132 is greater than or less than reference value 428. The second signal can be obtained by sampling the analog input signal 418 using at least one switch 408 of the ADC.

[0145] In some implementations, generating block 1302 may include asynchronously comparing a second signal (e.g., present at input 414 of reference cross detector 132) with a reference value 428, wherein the reference value 428 corresponds to at least one of ground voltage or near-zero voltage. In this case, reference cross detector 132 may operate as a zero-crossing detector. Generating block 1302 may also include providing a voltage value for the first signal (e.g., at output 416 of reference cross detector 132) based on whether the second signal is less than or greater than the reference value 428.

[0146] At block 1304, the ADC shifts the voltage of the second signal based on the first signal. For example, voltage shifter 404 can shift the voltage 430 of the second signal at input 414 based on the first signal at output 416. In some cases, the amount of voltage shift 716 can depend on the value of voltage 430 relative to reference value 428 before voltage shifter 404 shifts the voltage.

[0147] At block 1306, the ADC responds to a digital value, causing a voltage jump in the second signal. For example, jump generator 134 can respond to a digital value 312, causing a voltage jump of 430 in the second signal at input 414, which is at least partially based on the first signal from output 416. To this end, jump generator 134 can allow digital value 312 to increase, and thus voltage 430 to rise or fall until the first signal from output 416 (e.g., locked digital value signal 420-2) changes to indicate that voltage 430 has exceeded reference value 428. Jump generator 134 can respond to jump trigger 426 to initiate the voltage jump of 430, jump trigger 426 being output based on sampled signal 422.

[0148] At block 1308, the ADC latches a digital value based on a change in the first signal. For example, the jump generator 134 can latch the digital value 312 based on a change in the first signal provided by the reference cross-detector 132 via output 416. Here, the jump generator 134 can respond to the latched digital value signal 420-2 by using multiple latches 704-1 to 704-N to latch the digital value 312 to prevent its change. This latching may include triggering multiple latches 704-1 to 704-N using the first signal in response to a second signal exceeding a reference value.

[0149] In some implementations, process 1300 may further include adjusting the voltage of the second signal (e.g., present at input 414 of reference cross detector 132) based on the offset voltage amount 726 (or offset voltage level) in response to latching. Process 1300 may also include calibrating the offset voltage amount 726 based on the output of an analog-to-digital converter (ADC), such as a "split" ADC or a subsequent ADC stage 302 of pipelined analog-to-digital converter (ADC) 130-1.

[0150] Figure 14 is a block diagram 1400 of an exemplary ADC 130 (e.g., Figures 1 through 3), which includes at least a reference cross-detector mechanism, a voltage shifter mechanism, and a jump generator mechanism. An apparatus may include ADC 130. ADC 130 may include, at 1402, a component for generating a first signal in response to a second signal and based on a reference value. ADC 130 may also include, at 1404, a component for shifting a voltage based on the first signal at a first time, wherein the voltage corresponds to the second signal. ADC 130 may further include, at 1406, a component for causing a voltage jump at a second time in response to at least partially based on a digital value of the first signal, wherein the digital value corresponds to at least a portion of a digital output signal. Generally, the described actions or method steps and / or the described circuitry or mechanisms can be implemented using various components for performing the actions and / or providing features. For example, method steps may be embodied in corresponding components for performing those steps. Similarly, circuit elements can be embodied in corresponding components used to provide the corresponding structure and / or operation.

[0151] This section describes some examples of exemplary implementations and / or exemplary configurations related to the apparatus and / or processes provided above.

[0152] Example 1: An apparatus comprising: Analog-to-digital converters (ADCs) include: Includes a reference cross detector for both inputs and outputs; A jump generator coupled between the output and the input of the reference cross detector; and A voltage shifter coupled between the output of the reference cross detector and the input of the reference cross detector.

[0153] Exemplary State 2: The apparatus according to Exemplary State 1, wherein the voltage shifter includes: A capacitor coupled to the input of the reference cross detector via at least one terminal.

[0154] Exemplary State 3: An apparatus according to Exemplary State 2, wherein: The first terminal of the capacitor is coupled to the input of the reference cross detector; and The voltage shifter includes at least one switch coupled between the following: The second terminal of the capacitor; and First voltage rail and second voltage rail.

[0155] Exemplary State 4: The apparatus according to Exemplary State 3, wherein the voltage shifter includes: A logic unit coupled between the output of the reference cross detector and the at least one switch.

[0156] Exemplary State 5: An apparatus according to Exemplary State 4, wherein the logic unit includes: A flip-flop, which includes a data input coupled to the output of the reference cross detector.

[0157] Example 6: An apparatus according to Example 4 or 5, wherein the logic unit is configured as follows: Based on the signal received from the output of the reference cross detector, the at least one switch is controlled to selectively connect the second terminal of the capacitor to the first voltage rail or the second voltage rail.

[0158] Exemplary State 7: An apparatus according to Exemplary State 6, wherein: The at least one switch includes a first switch and a second switch; and The capacitor is configured to selectively perform the following operations: In response to the first switch, the capacitor is connected to the first voltage rail, and the voltage at the input of the reference cross detector is adjusted by a first voltage amount; or In response to the second switch, the capacitor is connected to the second voltage rail, and the voltage at the input of the reference cross detector is adjusted to a second voltage amount.

[0159] Exemplary Sample 8: An apparatus according to any one of Exemplary Samples 3 or 4-7, wherein: The at least one switch includes multiple switches; The capacitor includes a differential array of capacitors, which comprises a first group of capacitors and a second group of capacitors; The first voltage rail includes a positive voltage rail; The second voltage rail includes a negative voltage rail; Each of the first group of capacitors includes a first terminal coupled to the positive input of the reference cross detector and a second terminal selectively coupled to the positive or negative voltage rail via a corresponding first positive or first negative switch among the plurality of switches; and Each of the second group of capacitors includes a first terminal coupled to the negative input of the reference cross detector and a second terminal selectively coupled to the positive or negative voltage rail via a corresponding second positive or second negative switch among the plurality of switches.

[0160] Exemplary State 9: The apparatus according to any of the foregoing exemplary states, wherein the voltage shifter is configured to: The voltage at the input of the reference cross detector is adjusted based on the signal generated at the output of the reference cross detector.

[0161] Exemplary State 10: The apparatus according to Exemplary State 9, wherein the voltage shifter is configured as follows: The voltage at the input of the reference cross detector is adjusted based on the voltage level of the sampled signal coupled to the input of the reference cross detector.

[0162] Exemplary State 11: The apparatus according to Exemplary State 10, wherein the voltage shifter is configured as follows: The voltage at the input of the reference cross detector will be selectively adjusted by the following amounts: A first voltage amount that responds to the voltage level of the sampled signal being higher than the reference voltage level; or The voltage level of the sampled signal is lower than the reference voltage level by a second voltage quantity, which is different from the first voltage quantity.

[0163] Example 12: An apparatus according to any of the foregoing example examples, wherein the reference cross detector is configured as follows: Based on the signal at the input of the reference cross detector and the reference voltage level, the signal at the output of the reference cross detector is changed.

[0164] Exemplary State 13: An apparatus according to Exemplary State 12, wherein: The reference crossover detector includes a zero-crossing detector; and The zero-crossing detector is configured to change the voltage at its output based on the voltage at its input and at least one of a ground voltage or a near-zero voltage.

[0165] Exemplary Form 14: An apparatus according to any of the foregoing exemplary forms, wherein the jump generator comprises: A capacitor coupled to the input of the reference cross detector via at least one terminal; and A time-to-digital converter coupled between the output of the reference cross detector and the capacitor.

[0166] Exemplary Version 15: An apparatus according to Exemplary Version 14, wherein the capacitor includes: A capacitor array comprising a plurality of capacitors, wherein each of the plurality of capacitors is coupled to the input of the reference cross detector via the at least one terminal.

[0167] Exemplary State 16: An apparatus according to Exemplary State 15, wherein: The time-to-digital converter includes multiple buffers serially coupled together; and The corresponding buffer in the plurality of buffers is coupled to the corresponding capacitor in the plurality of capacitors.

[0168] Exemplary Version 17: An apparatus according to Exemplary Version 16, wherein the time-to-digital converter includes: Multiple latches, wherein the respective latches of the multiple latches are coupled between the respective buffers of the multiple buffers and the respective capacitors of the multiple capacitors.

[0169] Example 18: The apparatus according to Example 17, wherein the respective latch of the plurality of latches is configured as follows: In response to the signal received from the output of the reference cross detector, the corresponding value of the corresponding buffer from the plurality of buffers is latched.

[0170] Exemplary form 19: An apparatus according to exemplary form 16 or 17, wherein the jump generator includes: Multiple switches, wherein a corresponding switch of the multiple switches is coupled between a corresponding buffer of the multiple buffers and a corresponding capacitor of the multiple capacitors.

[0171] Exemplary State 20: An apparatus according to Exemplary State 19, wherein: The corresponding output of the corresponding buffer of the plurality of buffers is configured to control the corresponding state of the corresponding switch among the plurality of switches.

[0172] Example 21: The apparatus according to Example 20, wherein the time-to-digital converter is configured to: At least a portion of the digital output signal of the analog-to-digital converter, representing the corresponding state of the corresponding switch among the plurality of switches, is encoded.

[0173] Example 22: An apparatus according to any of the foregoing example examples, wherein the analog-to-digital converter comprises: An offset adjuster coupled between the output of the reference cross detector and the input of the reference cross detector.

[0174] Example 23: The apparatus according to Example 22, wherein the offset adjuster includes: A capacitor coupled to the input of the reference cross detector via at least one terminal.

[0175] Exemplary State 24: An apparatus according to Exemplary State 23, wherein: The first terminal of the capacitor is coupled to the input of the reference cross detector; and The offset adjuster includes at least one switch coupled between the following: The second terminal of the capacitor; and Voltage rail.

[0176] Exemplary State 25: An apparatus according to Exemplary State 24, wherein: The offset adjuster includes a logic unit coupled between the output of the reference cross detector and the at least one switch; and The logic unit is configured to control at least one state of the at least one switch based on a signal received from the output of the reference cross detector.

[0177] Exemplary State 26: An apparatus according to Exemplary State 25, wherein: The at least one switch includes a first switch coupled between the second terminal of the capacitor and the voltage rail; The at least one switch includes a second switch coupled between the second terminal of the capacitor and a node configured to maintain a direct current (DC) voltage. The logic unit is configured to, in response to a change in the signal received from the output of the reference cross detector, use a second switch to disconnect the second terminal of the capacitor from the node, and use a first switch to connect the second terminal of the capacitor to the voltage rail; and The capacitor is configured to connect the second terminal of the capacitor to the voltage rail in response to the at least one switch, thereby reducing the absolute value of the voltage at the input of the reference cross detector.

[0178] Example 27: A device according to Example 24 or 25, wherein the analog-to-digital converter is configured to: Maintain the voltage rail at the offset voltage amount.

[0179] Example 28: The apparatus according to Example 27, wherein the analog-to-digital converter is configured to: The offset voltage is calibrated based on the output of the subsequent analog-to-digital conversion stage of the pipeline analog-to-digital converter.

[0180] Example 29: The apparatus according to Example 28, wherein the analog-to-digital converter is configured to: Based on the digital value generated by the jump generator, a calibrated version of the offset voltage is tuned.

[0181] Exemplary Version 30: The apparatus according to any of the foregoing exemplary versions further includes: Pipeline analog-to-digital converters, including: Multiple analog-to-digital conversion levels; and At least one amplifier coupled to two or more analog-to-digital converter stages and interleaved between the two or more analog-to-digital converter stages. The analog-to-digital conversion level among the plurality of analog-to-digital conversion levels includes the analog-to-digital converter.

[0182] Example 31: The apparatus according to Example 30, wherein the pipeline analog-to-digital converter is configured to: Using this input of the reference cross-detector, input is provided to the analog-to-digital converter stage at the first moment; and Using this input from the reference cross detector, the output is provided to the analog-to-digital converter stage at a second time.

[0183] Example 32: The apparatus according to any of the foregoing example examples further includes: Wireless interface devices The wireless interface device includes the analog-to-digital converter.

[0184] Exemplary form 33: The apparatus according to exemplary form 32 further includes: Display screen; and At least one processor operatively coupled to at least a portion of the display screen and the wireless interface device, the at least one processor being configured to present one or more graphic images on the display screen based on one or more wireless signals received by the analog-to-digital converter using the wireless interface device.

[0185] Exemplary Form 34: An apparatus according to any of the foregoing exemplary forms, wherein the analog-to-digital converter includes an asynchronous digital step-up analog-to-digital converter.

[0186] Exemplary Form 35: An apparatus according to any of the foregoing exemplary forms, wherein: The reference cross detector is configured to generate a detection signal at the output based on the analog voltage provided at the input. The voltage shifter is configured to shift the analog voltage based on the value of the detected signal at a first time, so as to generate a shift voltage at the output of the reference cross detector; and The jump generator is configured to cause the shifted voltage to jump, thereby generating a jump voltage at the output of the reference cross detector, and at a second time to generate a digital value in response to another value of the detection signal.

[0187] Example 36: The apparatus according to Example 35 further includes: An offset adjuster, coupled between the output and the input of the reference cross detector, wherein: The offset adjuster is configured to adjust the jump voltage so that, at the second time, in response to the other value of the detected signal, an adjusted voltage is generated at the output of the reference cross detector; and The analog-to-digital converter is configured to provide the adjusted voltage as an analog residual signal to subsequent analog-to-digital conversion stages.

[0188] Example 37: An apparatus for analog-to-digital conversion, the apparatus comprising: A component used to respond to a second signal and generate a first signal based on a reference value; A component for shifting a voltage based on the first signal at a first time, the voltage corresponding to the second signal; and For use at a second time, in response to a voltage jump based at least in part on a digital value corresponding to at least a portion of a digital output signal.

[0189] Exemplary form 38: The apparatus according to exemplary form 37, wherein the component for lifting includes: A capacitor component used to convert the digital value to an analog version of the voltage.

[0190] Exemplary form 39: The apparatus according to exemplary form 37 or 38, wherein the component for displacement includes: A component for adjusting the voltage by an amount at that first moment, the amount of which depends at least in part on the first signal.

[0191] Exemplary Sample 40: The apparatus according to any one of Exemplary Samples 37-39 further includes: A component used to offset the voltage based on the first signal at a third time.

[0192] Exemplary form 41: The apparatus according to exemplary form 40, wherein the component for offset includes: The component used to adjust the voltage in response to the third time, wherein the third time depends at least in part on the change of the first signal after the voltage jump begins.

[0193] Example 42: The apparatus according to Example 40 or 41 further includes: A component for calibrating a voltage quantity, wherein the component for offset adjusts the voltage quantity at the third time.

[0194] Example 43: A method for analog digit conversion, the method comprising: The first signal is generated based on the second signal and the reference value; Based on the first signal, the voltage of the second signal is shifted; In response to a digital value, the voltage of the second signal increases; and Based on the change in the first signal, the digital value is latched.

[0195] Example 44: The method according to Example 43 further includes: In response to the latch, the voltage of the second signal is adjusted based on the offset voltage.

[0196] Example 45: The method according to Example 44 further includes: The offset voltage is calibrated based on the output of the analog-to-digital converter (ADC).

[0197] Exemplary Sample 46: The method according to any one of Exemplary Samples 43-45, wherein the generation includes: The second signal is compared asynchronously with the reference value, which corresponds to at least one of ground voltage or near-zero voltage; and The voltage value is provided to the first signal based on whether the second signal is less than or greater than the reference value.

[0198] Example 47: The method according to any one of Example 43-46, wherein the shift includes selectively performing the following operations: In response to the second signal being greater than the reference value, the voltage of the second signal is adjusted by a first amount; or In response to the second signal being less than the reference value, the voltage of the second signal is adjusted by a second amount.

[0199] Exemplary State 48: The method according to any one of Exemplary States 43-47, wherein the jump includes: Change the state of the corresponding switch among the corresponding switches of the corresponding capacitors coupled to multiple capacitors; and Based on the change in the corresponding state of the corresponding switch, the voltage of the second signal is adjusted using the multiple capacitors.

[0200] Example 49: The method according to any one of Example 43-48 further includes: The second signal is obtained by sampling an analog input signal, wherein the jump includes: In response to the sampling, the signal is propagated through multiple buffers; and The respective outputs of the corresponding buffers of the multiple buffers are coupled to the respective latches of the multiple latches.

[0201] Example 50: The method according to Example 49, wherein the latch includes: In response to the second signal crossing the reference value, the first signal is used to trigger the plurality of latches.

[0202] Example 51: An apparatus comprising: Pipeline analog-to-digital converters, including: A plurality of analog digit conversion levels, wherein at least one of the plurality of analog digit conversion levels includes: Includes a reference cross detector for both inputs and outputs; A jump generator, coupled to the output of the reference cross detector, the jump generator comprising: Multiple buffers serially arranged; and Multiple capacitors coupled between the plurality of buffers and the input of the reference cross detector; and At least one capacitor coupled between the output and the input of the reference cross detector; and At least one amplifier coupled between two or more of the plurality of analog-to-digital conversion stages.

[0203] Exemplary State 52: An apparatus according to Exemplary State 51, wherein: The at least one capacitor is configured to adjust the voltage corresponding to the input of the reference cross detector based on the signal provided at the output of the reference cross detector.

[0204] Example 53: The apparatus according to Example 52, wherein the at least one analog-to-digital conversion stage among the plurality of analog-to-digital conversion stages includes: The logic coupled between the output of the reference cross detector and the at least one capacitor is configured to: in response to a change in the signal received from the output of the reference cross detector, cause the at least one capacitor to adjust the voltage corresponding to the input of the reference cross detector.

[0205] Exemplary State 54: An apparatus according to Exemplary State 53, wherein: The at least one capacitor and the logic unit together include an offset adjuster configured to adjust the voltage corresponding to the input of the reference cross detector in response to the termination of the voltage rise by the rise generator.

[0206] Exemplary Sample 55: An apparatus according to any one of Exemplary Samples 52-54, wherein: The at least one capacitor is configured to adjust the voltage corresponding to the input of the reference cross detector so that the voltage is closer to at least one of ground voltage or near-zero voltage.

[0207] Exemplary form 56: An apparatus according to exemplary form 55, wherein: The at least one amplifier includes at least one residual amplifier configured to amplify the voltage after the at least one capacitor brings the voltage closer to at least one of the ground voltage or the near-zero voltage.

[0208] Example 57: The apparatus according to any one of Example 52-56, wherein the at least one analog-to-digital conversion stage among the plurality of analog-to-digital conversion stages includes: The logic coupled between the output of the reference cross detector and the at least one capacitor is configured to, based on the voltage value of the signal received from the output of the reference cross detector, cause the at least one capacitor to selectively offset the voltage corresponding to the input of the reference cross detector by at least one of two amounts.

[0209] Exemplary State 58: An apparatus according to Exemplary State 57, wherein: The at least one capacitor and the logic unit together include a voltage shifter configured to selectively adjust the voltage corresponding to the input of the reference cross detector before the voltage rises due to the rise generator.

[0210] Exemplary Sample 59: An apparatus according to any one of Exemplary Samples 51-58, wherein the pipeline analog-to-digital converter includes: At least one register coupled to the jump generator of the at least one analog-to-digital converter in the plurality of analog-to-digital converter stages, the at least one register being configured to: Receive a plurality of digital values, each of which is received from a corresponding analog-to-digital converter level in the plurality of analog-to-digital converter levels; and These multiple digital values ​​are combined to form the digital output signal of the pipeline analog-to-digital converter.

[0211] Example 60: An apparatus comprising: Analog-to-digital converters (ADCs) include: Includes a reference cross detector for both inputs and outputs; A jump generator coupled between the output and the input of the reference cross detector; and An offset adjuster coupled between the output of the reference cross detector and the input of the reference cross detector.

[0212] Example 61: The apparatus according to Example 60, wherein the offset adjuster includes: A capacitor coupled to the input of the reference cross detector via at least one terminal.

[0213] Exemplary form 62: An apparatus according to exemplary form 61, wherein: The first terminal of the capacitor is coupled to the input of the reference cross detector; and The offset adjuster includes at least one switch coupled between the following: The second terminal of the capacitor; and Voltage rail.

[0214] Exemplary form 63: An apparatus according to exemplary form 62, wherein: The offset adjuster includes logic coupled between the output of the reference cross detector and the at least one switch; and The logic unit is configured to control at least one state of the at least one switch based on a signal received from the output of the reference cross detector.

[0215] Exemplary form 64: An apparatus according to exemplary form 63, wherein: The at least one switch includes a first switch coupled between the second terminal of the capacitor and the voltage rail; The at least one switch includes a second switch coupled between the second terminal of the capacitor and a node configured to maintain a direct current (DC) voltage. The logic unit is configured to: in response to a change in the signal received from the output of the reference cross detector, use a second switch to disconnect the second terminal of the capacitor from the node, and use a first switch to connect the second terminal of the capacitor to the voltage rail; and The capacitor is configured to reduce the absolute value of the voltage at the input of the reference cross detector in response to the at least one switch connecting the second terminal of the capacitor to the voltage rail.

[0216] Example 65: An apparatus according to Example 62, wherein the analog-to-digital converter is configured to: Maintain the voltage rail at the offset voltage amount.

[0217] Example 66: The apparatus according to Example 65, wherein the analog-to-digital converter is configured to: The offset voltage is calibrated based on the output of the subsequent analog-to-digital conversion stage of the pipeline analog-to-digital converter.

[0218] Example 67: An apparatus according to Example 66, wherein the analog-to-digital converter is configured to: Based on the digital value generated by the jump generator, a calibrated version of the offset voltage is tuned.

[0219] As used herein, the terms "coupled," "coupled to," or "coupled" refer to a relationship between two or more elements that are operable to communicate with each other to achieve certain features or capabilities described herein. For example, coupling can be achieved using a physical line such as a metal trace or wire. Coupling can include direct coupling or indirect coupling. Direct coupling refers to connecting individual circuit elements via the same node without intermediate elements. Indirect coupling refers to connecting individual circuit elements via one or more other devices or other individual circuit elements (which include two or more different nodes).

[0220] In this document, the terms "first," "second," "third," and other number-related indicators are used to identify or distinguish similar or related items in a given context (e.g., a specific implementation, a single drawing, a given element, or a request item). Therefore, the first item in one context may differ from the first item in another context. For example, an item identified as "first switch" in one context may be identified as "second switch" in another. Similarly, "first capacitor array" in one request item may be described as "second capacitor array" in a different request item.

[0221] Unless the context otherwise indicates, the use of the word "or" herein can be interpreted as the use of "inclusive or," or as allowing the inclusion or application of one or more items linked by the word "or" (e.g., the phrase "A or B" can be interpreted as allowing only "A," only "B," or both "A" and "B"). As used herein, the phrase "at least one" in a list of items means any combination of such items, including a single member. For example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, and any combination having multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c). Furthermore, items represented in the figures and terminology discussed herein may indicate one or more items or terms, and therefore reference may be made interchangeably to the single or plural forms of items and terms in this written description. Finally, although the subject matter of the invention has been described in language specific to structural features or methodological operations, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations described above, and includes, but is not necessarily limited to, the organization of arrangement features or the order of performing operations.

[0222] 100: Environment 102: Electronic Equipment 104:Base station 106: Wireless Link 108: Application Processor 110: Computer-readable storage media 112: Store command 114: Data 116: Electronic equipment 118: Monitor 120: Wireless Interface Device 122: Antenna 124: Communication Processor 126: Transceiver 128: Radio Frequency (RF) Front End 130: Analog-to-Digital Converter 130-1: Pipeline ADC 132: Reference Cross Detector 134: Jump Generator 136: Capacitor 138: Voltage Transformation Circuit 200: Figure 202: Receive Chain 204: Low-noise amplifier 206: Filter 208: Mixer 212: Analog Input Signal 214: Digital output signal 220: Wireless signal 222: Antenna feeder 224: Processing 232: Phase-locked loop 252: Launch Chain 254: Power Amplifier 256: Filter 258: Mixer 260:DAC 304-1: Residual Amplifier 304-2: Residual Amplifier 306: Temporary Register 308-1: First-order residual signal 308-2: Second-order analog residual signal 310-1: First residual input signal 310-2: Second residual input signal 312-1: Place value 312-2: Place value 312-S: Place value 400: Schematic diagram 400-1: Schematic diagram 400-2: Schematic diagram 402: ADC control circuit 404: Voltage displacement device 406: Offset Adjuster 408: Switch 410: Node 412-1: First Delay Unit 412-2: Second Delay Unit 416: Output 418: Input signal 420: Detection signal 420-1: Select voltage shift signal 420-2: Locking the digital value signal 420-3: Apply voltage offset signal 422: Sampling signal 424: Apply voltage shift signal 424b: Apply voltage shift signal bar 426: Ascension Trigger 428: Reference value 430: Voltage 432: Master clock signal 500: Process 502: Operation 504: Operation 506: Operation 508: Operation 510: Operation 512: Operation 514: Operation 516: Operation 518: Operation 520: Operation 522: Operation 600: Chart 602-1: First voltage offset 602-2: Second voltage offset 604: Voltage displacement device 606: Time Period 608: Time Period 610: Time Period 612: Time 700: Circuit Diagram 702-1: Buffer 702-2: Buffer 702-3: Buffer 702-N: Buffer 704-1: Latch 704-2: Latch 704-3: Latch 704-N: Latch 706: Jump Capacitor 706-1: First-stage leap capacitor 706-2: Second-stage capacitor 706-3: Third-stage leap capacitor 706-N: "Nth" step-up capacitor 708: Switch 708-1: Jump-type switch 708-2: Jump-type switch 708-3: Jump-type switch 708-N: Jump Switch 710: Voltage increment 712: Capacitor 714: Switch 716-1: First voltage quantity 716-2: Second voltage quantity 718: Logic 722: Capacitor 724: Switch 726: Offset voltage 728: Logic 802: Time-to-Digital Converter 804-1: First digit value bit 804-2: Second digit value 804-3: Third digit value 804-N: The Nth bit value 806: Capacitor Bank / Capacitor Array 808: Switch Group / Switch Array 810: Gate control circuit 900: Circuit Diagram 902: Flip-Flipper 1000: Circuit Diagram 1002: Flipper 1004: Signal Disambiguator 1100: Image 1102: Capacitor Array 1200-1: Calibration Process 1200-2: Calibration Process 1202: Operation 1204: Operation 1206: Operation 1208: Operation 1210: Operation 1212: Operation 1222: Operation 1224: Operation 1226: Operation 1228: Operation 1230: Operation 1232: Operation 1234: Operation 1300: Process 1302: Operation 1304: Operation 1306: Operation 1308: Operation 1400: Block Diagram 1402: Operation 1404: Operation 1406: Operation C0: Capacitor C1: Capacitor C2: Capacitor C6: Capacitor C7: Capacitor C8: Capacitor CNTL0: bit CNTL0b: Bit CNTL1: bit CNTL1b: bits CNTL2: bits CNTL2b: bits GND: Grounding voltage VI: Voltage Increment Φ1: First stage Φ1B: Phase Φ2: Second stage Φ2A: Second stage Φ2B: Phase Φ3: Third stage Φ3A: Third stage Φ3B: Phase Φ4: Fourth Stage Φ4A: Fourth stage Φ4B: Phase Φ5: Fifth Stage Φ5A: Fifth stage Φ5B: Phase

[0223] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A signal processing apparatus, comprising: An analog-to-digital converter (ADC) includes: a reference cross-detector including an input and an output; a rise generator coupled between the output and the input of the reference cross-detector; and a voltage shifter coupled between the output and the input of the reference cross-detector, wherein the voltage shifter includes a capacitor coupled to the input of the reference cross-detector via at least one terminal, wherein a first terminal of the capacitor is coupled to the input of the reference cross-detector; and the voltage shifter includes at least one switch coupled between: a second terminal of the capacitor; and a first voltage rail and a second voltage rail.

2. The apparatus as claimed in claim 1, wherein the voltage shifter comprises: A logic unit coupled between the output of the reference cross detector and the at least one switch.

3. The apparatus as described in claim 2, wherein the logic unit comprises: A flip-flop that includes a data input coupled to the output of the reference cross detector.

4. The apparatus as claimed in claim 2, wherein the logic unit is configured to: control the at least one switch to selectively connect the second terminal of the capacitor to the first voltage rail or the second voltage rail based on a signal received from the output of the reference cross detector.

5. The apparatus as described in claim 4, wherein: The at least one switch includes a first switch and a second switch; and the capacitor is configured to selectively perform the following operations: in response to the first switch connecting the capacitor to the first voltage rail, adjusting a voltage at the input of the reference cross detector by a first voltage amount; or in response to the second switch connecting the capacitor to the second voltage rail, adjusting the voltage at the input of the reference cross detector by a second voltage amount.

6. The apparatus as described in claim 1, wherein: The at least one switch includes a plurality of switches; the capacitor includes a differential array of capacitors, the differential array of capacitors including a first group of capacitors and a second group of capacitors; the first voltage rail includes a positive voltage rail; the second voltage rail includes a negative voltage rail; each of the first group of capacitors includes a first terminal coupled to a positive input of the reference cross detector and a second terminal selectively coupled to the positive voltage rail or the negative voltage rail via a corresponding first positive switch or a first negative switch of the plurality of switches; and each of the second group of capacitors includes a first terminal coupled to a negative input of the reference cross detector and a second terminal selectively coupled to the positive voltage rail or the negative voltage rail via a corresponding second positive switch or a second negative switch of the plurality of switches.

7. The apparatus as claimed in claim 1, wherein the voltage shifter is configured to: adjust a voltage at the input of the reference cross detector based on a signal generated at the output of the reference cross detector.

8. The apparatus as claimed in claim 7, wherein the voltage shifter is configured to: adjust the voltage at the input of the reference cross detector based on a voltage level of a sampled signal coupled to the input of the reference cross detector.

9. The apparatus of claim 8, wherein the voltage shifter is configured to: selectively adjust the voltage at the input of the reference cross detector by: a first voltage amount in response to the voltage level of the sampled signal being higher than a reference voltage level; or a second voltage amount in response to the voltage level of the sampled signal being lower than a reference voltage level, the first voltage amount being different from the second voltage amount.

10. The apparatus of claim 1, wherein the reference cross detector is configured to: change a signal at the output of the reference cross detector based on a signal at the input of the reference cross detector and a reference voltage level.

11. The apparatus as claimed in claim 10, wherein: The reference cross detector includes a zero-crossing detector; and the zero-crossing detector is configured to change a voltage at the output of the zero-crossing detector based on a voltage at the input of the zero-crossing detector and at least one of a ground voltage or a near-zero voltage.

12. The apparatus as claimed in claim 1, wherein the jump generator comprises: A capacitor coupled to the input of the reference cross detector via at least one terminal; and a time-to-digital converter coupled between the output of the reference cross detector and the capacitor.

13. The apparatus as claimed in claim 12, wherein the capacitor comprises: A capacitor array comprising a plurality of capacitors, each of the plurality of capacitors being coupled to the input of the reference cross detector via at least one terminal.

14. The apparatus as claimed in claim 13, wherein: The time-to-digital converter includes multiple buffers serially coupled together; and a corresponding buffer in the multiple buffers is coupled to a corresponding capacitor in the multiple capacitors.

15. The apparatus as claimed in claim 14, wherein the time-to-digital converter comprises: Multiple latches, wherein the respective latches of the multiple latches are coupled between the respective buffers of the multiple buffers and the respective capacitors of the multiple capacitors.

16. The apparatus of claim 15, wherein a respective latch of the plurality of latches is configured to latch a respective value from the respective buffer of the plurality of buffers in response to a signal received from the output of the reference cross detector.

17. The apparatus as claimed in claim 14, wherein the jump generator comprises: Multiple switches, wherein a corresponding switch of the multiple switches is coupled between a corresponding buffer of the multiple buffers and a corresponding capacitor of the multiple capacitors.

18. The apparatus as claimed in claim 17, wherein: The corresponding output of the corresponding buffer of the plurality of buffers is configured to control the corresponding state of the corresponding switch among the plurality of switches.

19. The apparatus of claim 18, wherein the time-to-digital converter is configured to: encode a digital value of at least a portion of a digital output signal of the analog-to-digital converter representing the corresponding state of the respective switch among the plurality of switches.

20. The apparatus of claim 1, wherein the analog-to-digital converter comprises: An offset adjuster coupled between the output and the input of the reference cross detector.

21. The apparatus as claimed in claim 20, wherein the offset adjuster comprises: A capacitor coupled to the input of the reference cross detector via at least one terminal.

22. The apparatus as claimed in claim 21, wherein: A first terminal of the capacitor is coupled to the input of the reference cross detector; and the offset adjuster includes at least one switch coupled between: a second terminal of the capacitor; and a voltage rail.

23. The apparatus as described in claim 22, wherein: The offset adjuster includes a logic unit coupled between the output of the reference cross detector and the at least one switch; and the logic unit is configured to control at least one state of the at least one switch based on a signal received from the output of the reference cross detector.

24. The apparatus as described in claim 23, wherein: The at least one switch includes a first switch coupled between the second terminal of the capacitor and the voltage rail; the at least one switch includes a second switch coupled between the second terminal of the capacitor and a node configured to maintain a DC voltage; the logic unit is configured to, in response to a change in the signal received from the output of the reference cross detector, use the second switch to disconnect the second terminal of the capacitor from the node and use the first switch to connect the second terminal of the capacitor to the voltage rail; and the capacitor is configured to, in response to the at least one switch connecting the second terminal of the capacitor to the voltage rail, reduce an absolute value of a voltage at the input of the reference cross detector.

25. The apparatus as claimed in claim 22, wherein the analog-to-digital converter is configured to: maintain the voltage rail at an offset voltage amount.

26. The apparatus of claim 25, wherein the analog-to-digital converter is configured to: calibrate the offset voltage amount based on an output of a subsequent analog-to-digital conversion stage of a pipelined analog-to-digital converter.

27. The apparatus as claimed in claim 26, wherein the analog-to-digital converter is configured to: tune a calibrated version of the offset voltage quantity based on a digital value generated by the rise generator.

28. The apparatus as described in claim 1, further comprising: A pipelined analog-to-digital converter includes: a plurality of analog-to-digital conversion stages; and at least one amplifier coupled to and interleaved between two or more of the plurality of analog-to-digital conversion stages, wherein one of the plurality of analog-to-digital conversion stages includes the analog-to-digital converter.

29. The apparatus of claim 28, wherein the pipelined analog-to-digital converter is configured to: use the input of the reference cross-detector to provide an input to the analog-to-digital conversion stage at a first time; and use the input of the reference cross-detector to provide an output to the analog-to-digital conversion stage at a second time.

30. The apparatus as described in claim 1, further comprising: A wireless interface device, wherein the wireless interface device includes the analog-to-digital converter.

31. The apparatus as described in claim 30, further comprising: One display screen; and at least one processor operatively coupled to at least a portion of the display screen and the wireless interface device, the at least one processor being configured to display one or more graphic images on the display screen based on one or more wireless signals received by the analog-to-digital converter using the wireless interface device.

32. The apparatus as claimed in claim 1, wherein the analog-to-digital converter includes an asynchronous digital-step analog-to-digital converter.

33. The apparatus as claimed in claim 1, wherein: The reference cross detector is configured to generate a detection signal at the output based on an analog voltage provided at the input; the voltage shifter is configured to shift the analog voltage based on a value of the detection signal at a first time to generate a shifted voltage at the output of the reference cross detector; and the jump generator is configured to jump the shifted voltage to generate a jump voltage at the output of the reference cross detector, and to generate a digital value in response to another value of the detection signal at a second time.

34. The apparatus as described in claim 33, further comprising: An offset adjuster coupled between the output and the input of the reference cross detector, wherein: the offset adjuster is configured to adjust the step voltage to generate an adjusted voltage at the output of the reference cross detector in response to another value of the detection signal at the second time; and the analog-to-digital converter is configured to provide the adjusted voltage as an analog residual signal to a subsequent analog-to-digital conversion stage.

35. A method for analog-to-digital conversion, the method comprising the steps of: generating a first signal based on a second signal and a reference value via a reference cross-detector; shifting a voltage of the second signal based on the first signal via a voltage shifter, wherein the voltage shifter includes a capacitor coupled to the input of the reference cross-detector via at least one terminal, wherein a first terminal of the capacitor is coupled to the input of the reference cross-detector, and the voltage shifter includes at least one switch coupled to a second terminal of the capacitor and between a first voltage rail and a second voltage rail; increasing the voltage of the second signal in response to a digital value; and latching the digital value based on a change in the first signal.

36. The method as described in claim 35 further includes the step of: adjusting the voltage of the second signal based on an offset voltage amount in response to the latching step.

37. The method as described in claim 36 further includes the step of: calibrating the offset voltage amount based on an output of an analog-to-digital converter (ADC).

38. The method as claimed in claim 35, wherein the generating step comprises the following steps: asynchronously comparing the second signal with the reference value, the reference value corresponding to at least one of a ground voltage or a near-zero voltage; and providing a voltage value to the first signal based on whether the second signal is less than or greater than the reference value.

39. The method as described in claim 35, wherein the shifting step includes selectively performing the following operations: adjusting the voltage of the second signal by a first amount in response to the second signal being greater than the reference value; or adjusting the voltage of the second signal by a second amount in response to the second signal being less than the reference value.

40. The method as claimed in claim 35, wherein the step of the jump includes the steps of: changing a corresponding state of a corresponding switch of a plurality of switches of a corresponding capacitor coupled to a plurality of capacitors; and using the plurality of capacitors to adjust the voltage of the second signal based on the change in the corresponding state of the corresponding switch.

41. The method as described in claim 35 further includes the steps of: sampling an analog input signal to obtain the second signal, wherein the step of the step includes the steps of: propagating a signal through a plurality of buffers in response to the sampling step; and coupling the respective outputs of the respective buffers of the plurality of buffers to the respective latches of the plurality of latches.

42. The method as described in claim 41, wherein the latching step includes the following steps: in response to the second signal crossing the reference value, using the first signal to trigger the plurality of latches.

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