Integrated passive devices

Abstract

This invention discloses an element and techniques for manufacturing the element. The element may include a top substrate including a plurality of top vias coupled to a first top metal layer forming a top winding portion of a first inductor. The element also includes an intermediate substrate including one or more intermediate metal layers. The top substrate is disposed on the intermediate substrate. The one or more intermediate metal layers form an intermediate winding portion of the first inductor. The element further includes a bottom substrate electrically coupled to the intermediate substrate opposite to the top substrate, wherein a first bottom metal layer of the bottom substrate forms a bottom winding portion of the first inductor.

Description

[Technical Field]

[0001] The various aspects of this case generally relate to elements, such as integrated circuits and semiconductor elements, and more specifically to integrated passive elements comprising passive elements on or embedded in an insulating material. [Previous Technology]

[0002] Integrated circuit (IC) technology has made significant progress in improving computing power through the miniaturization of active components. Passive components have also been miniaturized. As frequencies and data rates become increasingly higher, there is a need for further miniaturization of integrated passive components (e.g., filters in IC components that include inductors (L) and capacitors (C)) and increased functional combinations. Additionally, to improve the quality of received signals, certain components of a mobile device can be formed on an insulating substrate (e.g., a glass substrate). For example, circuit elements can be formed on a glass substrate to "isolate" the element, thereby reducing the impact of noise from other components of the mobile device.

[0003] In some applications, integrated passive components (IPD), including inductor and capacitor elements, suffer from lower inductor density and a reduced Q factor (i.e., a dimensionless parameter that associates the inductor with an ideal inductor). Accordingly, there is a need for systems, apparatuses, and methods (including those provided herein in the following disclosure) to overcome the shortcomings of conventional IC component designs with integrated passive components. [Summary of the Invention]

[0004] The following provides a simplified overview of one or more variations and / or examples associated with the various apparatuses and methods disclosed herein. Thus, this overview should not be considered an exhaustive overview of all contemplated variations and / or examples, nor should it be considered to identify key or defining elements or illustrations associated with all contemplated variations and / or examples and to define the scope of any particular variation and / or example. Accordingly, the following overview serves only to present, in a simplified form, certain concepts related to one or more variations and / or examples of the apparatuses and methods disclosed herein before the detailed descriptions provided below.

[0005] According to the various embodiments disclosed herein, at least one embodiment includes a device comprising an element. The element may include a top substrate including a plurality of top vias coupled to a first top metal layer forming a top winding portion of a first inductor. The element also includes an intermediate substrate including one or more intermediate metal layers. The top substrate is disposed on the intermediate substrate. The one or more intermediate metal layers form an intermediate winding portion of the first inductor. The element also includes a bottom substrate electrically coupled to the intermediate substrate opposite to the top substrate, wherein a first bottom metal layer of the bottom substrate forms a bottom winding portion of the first inductor.

[0006] According to the various embodiments disclosed herein, at least one embodiment includes a method for manufacturing a component. The method also includes the steps of: forming a top substrate including a plurality of top vias coupled to a first top metal layer, the first top metal layer forming a top winding portion of a first inductor. The method also includes the steps of: forming an intermediate substrate including one or more intermediate metal layers, wherein the top substrate is disposed on the intermediate substrate, and wherein the one or more intermediate metal layers form an intermediate winding portion of the first inductor. The method also includes the steps of: forming a bottom substrate electrically coupled to the intermediate substrate relative to the top substrate, wherein a first bottom metal layer of the bottom substrate forms a bottom winding portion.

[0007] Other features and advantages associated with the various apparatuses and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.

Implementation Method

[0022] Various embodiments of this case are illustrated in the following description and related drawings with respect to specific embodiments. Alternative embodiments or examples may be designed without departing from the scope of this teaching. Additionally, well-known elements of the illustrative embodiments herein will not be described in detail or will be omitted so as not to obscure the relevant details of the teachings herein.

[0023] In some of the exemplary implementations described herein, examples are identified in which various parts of the component structures and operations are available from known prior art and are subsequently arranged according to one or more exemplary embodiments. In such examples, internal details of known, generally known component structures and / or operations may be omitted to help avoid potential confusion with the concepts illustrated in the illustrative embodiments disclosed herein.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "some," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprising," "having," "including," and / or "containing," as used herein, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] FIG1A illustrates a portion of an apparatus 100 including an element 101 (e.g., a semiconductor element, integrated circuit, IPD, etc.) according to at least one embodiment of the present invention. Element 101 may include a top substrate 110, an intermediate substrate 120, and a bottom substrate 140. The bottom substrate 140 may be a laminate, a semiconductor die, or any substrate having at least one metal layer for forming a bottom winding portion, as discussed herein. The top substrate may include a plurality of top vias 115 coupled to a first top metal layer M1a, which forms a top winding portion 112 of a first inductor 105. It will be appreciated that the first inductor 105 is illustrated in cross-section so that the interconnections of the windings are not shown, but will be readily understood by those skilled in the art. The top substrate 110 is disposed on the intermediate substrate 120. The intermediate substrate 120 may include a plurality of intermediate vias 125 and one or more intermediate metal layers (e.g., M1(b), M2(b), M3(b), and M4(b)). The plurality of intermediate vias 125 and the one or more intermediate metal layers (M1(b)–M4(b)) form the intermediate winding portion 122 of the first inductor 105. It will be appreciated that other components may be coupled to one or more of the plurality of intermediate vias 125 and the one or more intermediate metal layers (M1(b)–M4(b)). Furthermore, it will be appreciated that in some embodiments, the plurality of intermediate vias 125 and the one or more intermediate metal layers may have more or fewer metal layers and vias than illustrated. For example, the one or more intermediate metal layers may consist only of a top metal layer and a bottom metal layer (e.g., top metal layer M1(b) and bottom metal layer M2(b)), wherein the plurality of vias 125 connect the top metal layer and the bottom metal layer. In a further embodiment, the intermediate substrate 120 may include only one metal layer for forming the intermediate winding portion 122. In yet another embodiment, the intermediate layer may include a dielectric material between the two metal layers to form a metal-insulator-metal (MIM) capacitor (discussed further below). Thus, the embodiments are not limited to having an intermediate via 125 in all disclosed embodiments. As further illustrated, the bottom substrate 140 is electrically coupled to the intermediate substrate 120 relative to the top substrate 110. The first bottom metal layer M1(c) of the bottom substrate 140 forms the bottom winding portion 142 of the first inductor 105.

[0026] A plurality of connectors 130 may be used to electrically couple the intermediate substrate 120 to the bottom substrate 140. In some embodiments, each of the plurality of connectors 130 may include a conductive post 132 (e.g., copper (Cu) or other highly conductive material) and a solder portion 134. The conductive post is coupled to the intermediate substrate 120, and the solder portion is coupled to the bottom substrate 140. A molded portion 150 may be deposited on the component 101 to at least encapsulate the top substrate 110 and the intermediate substrate 120.

[0027] In some embodiments, the first top metal layer M1(a) is the top metal layer of the top substrate 110. However, in other embodiments, it may be a different metal layer in the top substrate 110. In some embodiments, the first bottom metal layer M1(c) is the top metal layer of the bottom substrate 140. However, in other embodiments, it may be a different metal layer in the bottom substrate 140. Therefore, it will be understood that the various embodiments disclosed herein are not limited to the illustrated configurations, but are provided merely as examples to aid in the illustration of the various embodiments.

[0028] FIG1B illustrates the current flow in a portion of a device 100 according to at least one embodiment of the present invention. In this illustration, the flow of current 160 is indicated by arrows passing through a portion of the winding of the first inductor 105. For example, current 160 may enter at the first connector of the plurality of connectors 130 and flow through a first portion of the intermediate winding portion 122 to a first top through-hole in the top through-hole 115 and the top winding portion 112 of the first inductor 105. Current 160 may exit the top winding portion 112 and flow through a second top through-hole in the top through-hole 115, a second portion of the intermediate winding portion 122, a second connector of the plurality of connectors 130, and through the bottom winding portion 142 of the first inductor 105, thereby completing one turn of winding. Current 160 may exit this portion of winding and proceed to another winding or port of the first inductor.

[0029] As described above, it will be appreciated that by using portions of the top substrate 110, the intermediate substrate 120, and the bottom substrate 140, the length of the winding can be significantly increased compared to forming the winding in a single substrate. For example, in some embodiments, the top substrate 110 may have a height of about 100 micrometers (μm) to 300 μm, the intermediate substrate 120 may have a height of about 30 μm to 70 μm, and the connector 130 may have a height of about 60 μm to 140 μm. Therefore, even using the top metal layer (e.g., M1(c)) in the bottom substrate, the combined height is about 220 μm, which is significantly greater than any individual substrate or connector. The longer winding allows for a larger inductance value to be formed in a given portion of the component. Additionally, the longer winding results in fewer turns, and it reduces the number of corners for a given inductance, and fewer turns / corners per unit inductance improves the Q factor of the inductor. In some embodiments, the Q factor can be increased by more than 25% compared to conventional designs.

[0030] FIG. 2A illustrates a portion of an apparatus 200 including an element 201 (e.g., a semiconductor element, integrated circuit, IPD, etc.) and a die 260 according to at least one embodiment of the present invention. Element 201 has some features similar to element 101, therefore a detailed repetition of all similar embodiments will not be provided. Element 201 may include a top substrate 210, an intermediate substrate 220, and a bottom substrate 240. The top substrate 210 may include a plurality of top vias 215 coupled to a first top metal layer, which forms a top winding portion 212 of a first inductor 205. The top substrate 210 is disposed on the intermediate substrate 220. The intermediate substrate 220 may include a plurality of intermediate vias 225 and a plurality of intermediate metal layers. The plurality of intermediate vias 225 and the plurality of intermediate metal layers form an intermediate winding portion 222 of the first inductor 205. As will be understood, other components may be coupled to one or more of the plurality of intermediate vias 225 and the plurality of intermediate metal layers. The bottom substrate 240 is electrically coupled to the intermediate substrate 220 relative to the top substrate 210. A first bottom metal layer M1(c) of the bottom substrate 240 forms the bottom winding portion 242 of the first inductor 205. Additionally, a second portion 244 of the bottom metal layer M1(c) is configured to electrically couple a die 260 to element 201, which, in some cases, may be a radio frequency (RF) filter. In some cases, the die 260 may be a power amplifier (PA), and element 201 may be configured as a transmit (Tx) filter. In some cases, the die 260 may be a low-noise amplifier (LNA), and element 201 may be configured as a receive (Rx) filter.

[0031] A plurality of connectors 230 may be used to electrically couple intermediate substrate 220 to bottom substrate 240. In some embodiments, each of the plurality of connectors 230 may include a conductive post 232 (e.g., copper or other highly conductive material) and a solder portion 234. The conductive post is coupled to intermediate substrate 220, and the solder portion is coupled to bottom substrate 240. A molded portion 250 may be deposited on component 201 to at least encapsulate top substrate 210 and intermediate substrate 220. It will be understood that die 260 is coupled to component 201 via bottom substrate and the plurality of connectors.

[0032] FIG. 2B illustrates a portion of an apparatus 200 including element 201 according to at least one embodiment of the present invention. From the scaling of the top substrate 210, intermediate substrate 220, connector 230, and bottom substrate 240 (which is not at any particular scale), it will be understood that the various substrates may have different heights. Furthermore, it will be understood that the bottom substrate may have additional metal layers besides the top metal layer M1(c), as discussed herein. Although, as illustrated, the bottom winding portion 242 of the first inductor 205 is in the top metal layer M1(c), in some embodiments, the bottom winding portion may be in other lower metal layers (e.g., below M1(c)). Furthermore, the additional metal layers may be used for signal routing between the die (not shown) and element 201, to other elements coupled to the bottom substrate (if any), and / or to external elements. The number and configuration of vias in the additional metal layers and interconnecting metal layers in the bottom substrate may vary. Therefore, it will be understood that the various states disclosed herein are not limited to the configurations illustrated, but are provided merely as examples to help illustrate the various states.

[0033] FIG3 illustrates a portion of an apparatus 300 comprising an element 301 (e.g., a semiconductor element, integrated circuit, IPD, etc.) and a die 360 ​​according to at least one embodiment of the present invention. Element 301 has some features similar to element 101, therefore a detailed repetition of all similar embodiments will not be provided. Element 301 may include a top substrate 310, an intermediate substrate 320, and a bottom substrate 340. Top substrate 310 may include a plurality of top vias 315 coupled to a top winding portion 312 of a first inductor 305 formed in a first top metal layer (e.g., M1(a)). Top substrate 310 is disposed on intermediate substrate 320. Intermediate substrate 320 may include a plurality of intermediate vias 325 and a plurality of intermediate metal layers (e.g., M1(b), M2(b), M3(b), and M4(b)). A plurality of intermediate vias 325 and a plurality of intermediate metal layers form the intermediate winding portion 322 of the first inductor 305. It will be understood that other components may be coupled to one or more of the plurality of intermediate vias 325 and the plurality of intermediate metal layers (e.g., M1(b)–M4(b)). A bottom substrate 340 is electrically coupled to an intermediate substrate 320 relative to a top substrate 310. A first bottom metal layer M1(c) of the bottom substrate 340 forms the bottom winding portion 342 of the first inductor 305. In some embodiments of this invention, a die 360 ​​may be physically and electrically coupled to the intermediate substrate 320 of the element 301. A plurality of die connectors 362 (e.g., solder balls, bumps, etc.) may be used to couple the die 360 ​​to the intermediate substrate 320. In some embodiments, the die 360 ​​may be a power amplifier (PA), and the element 301 may be configured as a transmission (Tx) filter. In some cases, die 360 ​​can be a low-noise amplifier (LNA), and element 301 can be configured as a receive (Rx) filter.

[0034] A plurality of connectors 330 may be used to electrically couple an intermediate substrate 320 to a bottom substrate 340. In some embodiments, each of the plurality of connectors 330 may include a conductive post 332 (e.g., copper or other highly conductive material). The conductive post 332 is coupled between the intermediate substrate 320 and the bottom substrate 340. In some embodiments, solder portions may be used to bond the conductive post 332 to the bottom substrate 340 (e.g., bottom winding in a package substrate). In other embodiments, metal-to-metal (e.g., Cu-to-Cu) direct bonding may also be used (e.g., bottom winding in wafer form). Molded portions 350 may be deposited on the connectors 330 and the die 360 ​​to encapsulate at least a portion of the connectors 330 and the die 360.

[0035] It will be understood that the die 360 ​​is coupled to the element 301 via an intermediate substrate 320 and a plurality of die connectors 362. Since the bottom substrate is not used to route signals and / or power from the die to the element, the complexity of routing in the bottom substrate 340 is reduced. Furthermore, since the die is coupled to the intermediate substrate 320, the number of connectors 370 (e.g., solder balls, pins, etc.) can be reduced and / or used for other signal or power connections. Depending on the disclosed various states, a reduction in overall height and / or xy-size can be achieved. It will be understood that inductance is proportional to the total length of the inductor traces, therefore height affects the achievable inductance in a given design (e.g., 1-10 nH in most sub-6 GHz applications). Therefore, the disclosed various states can be used to maintain a certain height for a given inductor and / or reduce the number of turns and xy-size. To further improve space utilization, in some states, the semiconductor die can be placed within the inductor envelope to provide increased functionality without affecting the overall height.

[0036] FIG3 additionally illustrates the protruding portion 302 shown in a perspective view, which illustrates some elements that are not easily seen from a cross-sectional view. As can be seen in the illustrated example, the first inductor 305 can be formed as a multi-turn 3D inductor, which includes a top winding portion 312 in a top substrate 310 and a bottom winding portion 342 in a bottom substrate 340. The top winding portion 312 is coupled to the bottom winding portion 342 via pillars, which can be formed by a top through-hole 315, an intermediate winding portion 322, and a connector 330. Although represented as pillars, it will be appreciated that the various configurations are not limited to this configuration, and any shape can be used to electrically couple the top winding portion 312 and the bottom winding portion 342. From the illustrated exemplary configuration, it will be appreciated that the first inductor 305 can surround at least a portion of the intermediate substrate 320.

[0037] The intermediate substrate 320 may include one or more metal-insulator-metal (MIM) capacitors 326 and one or more additional inductors 328. It will be appreciated that the MIM capacitors 326 and inductors 328 may be part of an integrated passive device (IPD) formed in the intermediate substrate 320 using a plurality of intermediate vias 325 and a plurality of intermediate metal layers M1(b)–M4(b), as known in the art. The plurality of intermediate metal layers may be unequally spaced to facilitate the fabrication of the individual components. For example, the first two metal layers M1(b) and M2(b) may be closer together to facilitate the formation and connection of the MIM capacitors 326. The spacing between metal layers M2(b), M3(b), and M4(b) may be greater than the spacing between the first two metal layers M1(b) and M2(b) to facilitate the formation of the inductor 328. Inductor 328 can be formed as a 2D, 2.5D, or 3D inductor in an intermediate substrate by using one or more of various metal layers M1(b)–M4(b) and vias 325. It will be understood that MIM capacitor 326 and inductor 328 can be coupled to one or more of a plurality of intermediate vias 325 and a plurality of intermediate metal layers M1(b)–M4(b) forming part of the first inductor 305. Furthermore, it will be understood that the disclosed various configurations include configurations having more than one inductor formed via a top substrate 310, an intermediate substrate 320, and a bottom substrate 340, as discussed with respect to the first inductor 305. Therefore, it will be understood that the various configurations disclosed herein are not limited to the illustrated configurations, but are merely provided as examples to aid in the illustration of the various configurations.

[0038] FIG4 illustrates a portion of an apparatus 400 comprising a first element 401 (e.g., a semiconductor element, integrated circuit, IPD, etc.), a first die 461, a second element 402 (e.g., a semiconductor element, integrated circuit, IPD, etc.), and a second die 462, according to at least one embodiment of the present invention. The first element 401 and the second element 402 have some features similar to those of elements 101, 201, and 301 discussed above, and therefore a detailed repetition of all similar embodiments will not be provided. The first element 401 may include a top substrate 411, an intermediate substrate 421, and a bottom substrate 441. The top substrate 411 is disposed on the intermediate substrate 421. The bottom substrate 441 is electrically coupled to the intermediate substrate 421 via a connector 431 on the side of the intermediate substrate 421 opposite to the top substrate 411. The first element 401 may include a first inductor 451 formed in portions of the top substrate 411, the intermediate substrate 421, and the bottom substrate 441, as discussed herein. A first die 461 is coupled to an intermediate substrate 421 and disposed within a first inductor 451. A plurality of first interconnects 471 may be used to couple the first element 401 to other elements. In the illustrated configuration, the first element 401 is coupled to a second element 402 via a plurality of first interconnects 471.

[0039] The second element 402 may include a top substrate 412, an intermediate substrate 422, and a bottom substrate 442. The top substrate 412 is disposed on the intermediate substrate 422. The bottom substrate 442 is electrically coupled to the intermediate substrate 422 via a connector 432 on the side of the intermediate substrate 422 opposite to the top substrate 412. The second element 402 may include a second inductor 452 formed in portions of the top substrate 412, the intermediate substrate 422, and the bottom substrate 442, as discussed herein. A second die 462 is coupled to the intermediate substrate 422 and disposed within the second inductor 452. A plurality of second interconnects 472 may be used to couple the second element 402 to other elements. As illustrated, it will be understood that the first element 401 and the second element 402 can be packaged in a single package, wherein a plurality of second interconnects 472 provide connectivity to external elements and a plurality of first interconnects 471 provide signal and / or power connectivity between the first element 401 and the second element 402, thereby allowing signals and / or power to be coupled to the first die 461 and the second die 462, respectively.

[0040] In some embodiments, the first element 401 and the second element 402 may each be configured as a radio frequency (RF) filter. In some embodiments, the second die 462 may be a power amplifier (PA), and the second element 402 may be configured as a transmit (Tx) filter. In some embodiments, the first die 462 may be a low-noise amplifier (LNA), and the first element 401 may be configured as a receive (Rx) filter. Therefore, in some embodiments, the device 400 may be a radio frequency front-end (RFFE) module and is similar to a stacked package (POP) element, including both transmit and receive elements in a compact stacked configuration.

[0041] To fully illustrate the various forms of the design in this case, a manufacturing method is proposed. Other manufacturing methods are also possible, and the manufacturing methods discussed are only used to help understand the concepts revealed herein.

[0042] Figures 5A-D illustrate portions of a manufacturing process for device 500 according to one or more embodiments of the present invention. The process may begin with Figure 5A, wherein through-holes 515 are formed in a top substrate 510 to a first top metal layer M1(a). The substrate 510 may comprise glass (e.g., prepreg), silicon, ceramic, or epoxy molding compound (EMC), such as a through-hole type substrate. In some embodiments, the substrate 510 may be purchased or provided with pre-formed through-holes 515. The process may continue in Figure 5B, wherein the top substrate 510 has a plurality of through-holes 515 coupled to the first top metal layer M1(a). In this portion of the process, an adhesive 507 may be used to attach a carrier 506 to the top substrate 510.

[0043] This process can continue as shown in FIG. 5C, wherein the top substrate 510 has a plurality of vias 515 coupled to the first top metal layer M1(a), which are attached to the carrier 506 via adhesive 507. In this part of the process, the intermediate substrate 520 and connector 530 can be fabricated using known techniques. Therefore, details of each fabrication part will not be discussed herein. In some embodiments, the first metal layer M1(b) can be formed as a metal layer via a semi-additive process (SAP), damascene plating, or other suitable metal layer fabrication process. One or more dielectric layers can be deposited on the first metal layer M1(b). The one or more dielectric layers may include silicon nitride (SiN) and / or dielectrics such as silicon nitride (Si3N4), silicon oxide (SiO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), and similar materials for MIM capacitors (not shown). The procedure can continue using SAP or other suitable metal layer fabrication processes to form a second metal layer M2(b). The second metal layer M2(b) can be used in part as the top electrode of the MIM capacitor. Vias (e.g., 525) can be formed in the intermediate substrate 520 to couple each metal layer using known techniques; therefore, further details will not be provided.

[0044] The process may continue with the deposition, patterning, and curing of the first interlayer dielectric. The first interlayer dielectric may include polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), or other suitable dielectrics. It will be understood that if the design does not include MIM capacitors, the process may include depositing the interlayer dielectric on the first metal layer M1(b). The process may continue using SAP or other suitable metal layer fabrication processes to form a third metal layer M3(b). The third metal layer M3(b) may be used in part to form one or more inductors and / or for routing / interconnection. The process may continue with the deposition, patterning, and curing of the second interlayer dielectric. The second interlayer dielectric may include polyimide (PI) or other suitable dielectrics. The process may continue using SAP or other suitable metal layer fabrication processes to form a fourth metal layer M4(b). The fourth metal layer M4(b) may be used in part to form one or more inductors and / or for routing / interconnection. The process can proceed to the deposition, patterning, and curing of the third interlayer dielectric. The second interlayer dielectric may include polyimide (PI) or other suitable dielectrics, and in the illustrated state, may be the final passivation dielectric. The process can proceed to conventional under-bump metallization (UBM) fabrication to form a UBM (not shown) for connector 530. Solder portions 534 can be formed to form connector 530 via forming conductive (e.g., Cu) pillars 532 and solder plating and reflow processes.

[0045] The procedure can continue in FIG. 5D, where the carrier 506 and adhesive 507 are removed, and the previous individual components 501 from the wafer are diced, forming part of the device 500 including component 501. Component 501 has some features similar to those of the aforementioned components 101, 201, and 301, therefore a detailed repetition of all similar forms will not be provided. Component 501 may include a top substrate 510 and an intermediate substrate 520. The bottom substrate is not explicitly shown, but may simply be a metal layer to complete the bottom winding portion of the first inductor 505. The top substrate 510 may include a plurality of top vias 515 coupled to the top winding portion 512 of the first inductor 505 formed in the first top metal layer (e.g., M1(a)). It will be understood that during the manufacturing process (e.g., electroplating, etc.), various metal traces can be formed on each metal layer, and such layers are coupled to connector 530 via vias (e.g., 515 and 525) to form a first inductor 505.

[0046] A top substrate 510 is disposed on an intermediate substrate 320. The intermediate substrate 520 may include a plurality of intermediate vias 525 and a plurality of intermediate metal layers (e.g., M1(b), M2(b), M3(b), and M4(b)). The plurality of intermediate vias 525 and the plurality of intermediate metal layers form an intermediate winding portion 522 of the first inductor 305. It will be appreciated that other components (such as MIM capacitors and inductors) may be coupled to one or more of the plurality of intermediate vias 525 and the plurality of intermediate metal layers (e.g., M1(b)–M4(b)). A plurality of connectors 530 may each include a conductive post 532 and a solder portion 534, which may be used to connect to a metal layer (not shown) that may form a bottom winding portion of the inductor 505. The bottom winding portion may be formed in a third substrate, which may be a laminated substrate having one or more metal layers, as discussed herein.

[0047] Figures 6A-K illustrate portions of a manufacturing process for device 600 according to one or more embodiments of the present invention. The process may begin with Figure 6A, wherein through-holes 615 are formed in a top substrate 610 to a first top metal layer M1(a). The substrate 610 may comprise glass (e.g., prepreg), silicon, or ceramic. In some embodiments, the substrate 610 may be purchased or provided with pre-formed through-holes 615. The process may continue in Figure 6B, wherein the top substrate 610 has a plurality of through-holes 615 coupled to the first top metal layer M1(a). In this portion of the process, an adhesive 607 may be used to attach a carrier 606 to the top substrate 610.

[0048] This process can continue as shown in FIG. 6C, wherein the top substrate 610 has a plurality of vias 615 coupled to the first top metal layer M1(a), which are attached to the carrier 606 via adhesive 607. In this part of the process, the intermediate substrate 620 and the connector 630 can be manufactured using known techniques. Therefore, details of each manufacturing part will not be discussed herein. Furthermore, it will be appreciated that the manufacturing of the intermediate substrate 620 is similar to the manufacturing of the substrate 520 discussed above with respect to FIG. 5C, and therefore only a summary of the process will be described to avoid redundancy. In some cases, the first metal layer M1(b), the second metal layer M2(b), the third metal layer M3(b), and the fourth metal layer M4(b) are formed as metal layers via a semi-additive process (SAP) electroplating or other suitable metal layer manufacturing process, as discussed above. Furthermore, as discussed above, one or more dielectric layers may be deposited on the first metal layer. Vias (e.g., 625) can be formed in the intermediate substrate 620 to couple each metal layer using conventional techniques, therefore further details will not be provided. Conventional UBM manufacturing processes can be used to form the UBM (not shown) for connector 630. Connector 630 can be formed by forming conductive (e.g., Cu) pillars 632, in which no solder portion is added. Similarly, in a process different from the aforementioned process, pads 628 are formed to facilitate connection to the die.

[0049] This process can continue in FIG. 6D, wherein the top substrate 610 is attached to the carrier 606 via adhesive 607. An intermediate substrate 620 is formed on the top substrate 610, and a connector 630 is formed on the intermediate substrate. In this part of the process, the die 660 is attached to the intermediate substrate 620. In some embodiments, a plurality of die connectors 662 (e.g., solder balls, bumps, etc.) may be used to couple the die 660 to pads 628 in the intermediate substrate 620 to provide electrical and physical connections from the die 660 to the intermediate substrate 620.

[0050] This process can continue as shown in FIG. 6E, wherein the top substrate 610 is attached to the carrier 606 via adhesive 607. An intermediate substrate 620 is formed on the top substrate 610, and a connector 630 is formed on the intermediate substrate. A die 660 is attached to the intermediate substrate 620. In this part of the process, the die 660 and the conductive pillar 632 are embedded in a molding portion 650, which can be formed by depositing a molding compound on the conductive pillar 632 and the die 660.

[0051] The process can continue as shown in FIG. 6F, wherein the top substrate 610 is attached to the carrier 606 via adhesive 607. An intermediate substrate 620 is formed on the top substrate 610, and a connector 630 is formed on the intermediate substrate. A die 660 is attached to the intermediate substrate 620, and a molded portion 650 is deposited on the connector 630 and the die 660. In this part of the process, the molded portion 650 is ground away to planarize the bottom surface and expose the connector 630 (e.g., pillar 632).

[0052] The process can continue in FIG. 6G, wherein the top substrate 610 is attached to the carrier 606 via adhesive 607. An intermediate substrate 620 is formed on the top substrate 610, and a connector 630 is formed on the intermediate substrate. A die 660 is attached to the intermediate substrate 620, and a molded portion 650 is deposited on the connector 630 and the die 660. In this part of the process, a first bottom metal layer M1(c) can be formed, and a portion of M1(c) can be used to form the bottom portion 642 of the inductor 605.

[0053] The process can continue as shown in FIG. 6H, wherein the top substrate 610 is attached to the carrier 606 via adhesive 607. An intermediate substrate 620 is formed on the top substrate 610, and a connector 630 is formed on the intermediate substrate. A die 660 is attached to the intermediate substrate 620, and a molding portion 650 is deposited over the connector 630 and the die 660. Additionally, a bottom portion 642 of the inductor 605 is formed. In this part of the process, a bottom passivation layer 652 (e.g., an interlayer dielectric) can be deposited over the bottom portion 642 of the inductor 605 and any exposed portions of the molding 650. The bottom passivation layer 652 may comprise polyimide (PI) or other suitable dielectric, and in the illustrated pattern, may be a final passivation dielectric. The bottom passivation layer 652 may be patterned to form a cavity for connection to a first bottom metal layer M1(c) including the bottom portion 642 of the inductor 605. In some embodiments, a first bottom metal layer M1(c) and a bottom passivation layer 652 may form a bottom substrate 640. It will be appreciated that in some embodiments, more than one bottom metal layer may be included together with a corresponding interlayer dielectric layer for separating and insulating the bottom metal layers. Furthermore, in some embodiments, the bottom portion 642 may be formed in a layer of a multilayer laminate (e.g., using a conventional redistribution layer (RDL) process) or any suitable substrate having at least one metal layer.

[0054] This process can continue as shown in FIG. 6I, wherein the top substrate 610 is attached to the carrier 606 via adhesive 607. An intermediate substrate 620 is formed on the top substrate 610, and a connector 630 is formed on the intermediate substrate. A die 660 is attached to the intermediate substrate 620, and a molded portion 650 is deposited on the connector 630 and the die 660. Additionally, a bottom portion 642 of the inductor 605 is formed together with a bottom passivation layer 652. In this part of the process, a ball grid array (BGA) can be formed on the bottom of the component 601 via a solder ball placement / reflow process 670.

[0055] The process can continue as shown in FIG. 6J, wherein an intermediate substrate 620 is formed on a top substrate 610, and a connector 630 is formed on the intermediate substrate. A die 660 is attached to the intermediate substrate 620, and a molded portion 650 is deposited on the connector 630 and the die 660. Additionally, a bottom portion 642 of the inductor 605 is formed together with a bottom passivation layer 652 and solder balls 670. In this part of the process, the carrier 606 and adhesive 607 are removed, and a dicing is performed on a previous individual element 601 from the wafer, similar to the previous element discussed in the previous description, which forms part of the device 600 including element 601.

[0056] Figure 7 illustrates a flowchart of a method 700 for manufacturing an element according to one or more of the present invention. It will be apparent from the foregoing disclosure that additional procedures for manufacturing the various forms disclosed herein will be obvious to those skilled in the art, and a literal reproduction of the procedures described above will not be provided or illustrated in the included figures. It will be understood that the sequence of manufacturing procedures is not necessarily in any particular order, and later procedures may be discussed earlier to provide examples of the breadth of the various forms disclosed.

[0057] Referring to FIG7, a simplified procedure is provided to outline a wide range of procedures / actions to be performed according to one or more of the disclosed states. The procedure may begin at 702 at forming a top substrate (e.g., 110, 210, 310, etc.) including a plurality of top vias (e.g., 115, 215, 315, etc.) coupled to a first top metal layer, which forms the top winding portion (e.g., 112, 212, 312, etc.) of a first inductor (e.g., 105, 205, 305, etc.). The process continues at 704, wherein an intermediate substrate (e.g., 120, 220, 320, etc.) comprising one or more intermediate metal layers is formed, wherein a top substrate (e.g., 115, 215, 315, etc.) is disposed on the intermediate substrate (e.g., 120, 220, 320, etc.), and wherein the one or more intermediate metal layers form an intermediate winding portion (e.g., 122, 222, 322, etc.) of the first inductor. The process continues at 706, wherein a bottom substrate (e.g., 140, 240, 340, etc.) is formed relative to the top substrate (e.g., 110, 210, 310, etc.) and electrically coupled to the intermediate substrate (e.g., 120, 220, 320, etc.), wherein a first bottom metal layer of the bottom substrate (e.g., 140, 240, 340, etc.) forms the bottom winding portion (e.g., 142, 242, 342, etc.) of the first inductor (e.g., 105, 205, 305, etc.).

[0058] It should be understood that the aforementioned manufacturing process is provided only as a general description of the various forms of this application and is not intended to limit this application or the appended claims. Furthermore, many details of the manufacturing process known to those skilled in the art can be omitted or combined in the various summary procedure sections to facilitate understanding of the disclosed forms without presenting every detail and / or all possible process variations in detail.

[0059] Figure 8 illustrates the components of one or more embodiments of the device 800 according to this invention. Regardless of the various configurations of the components discussed above (e.g., 101, 201, 301, etc.), it will be understood that component 801 may be configured to be coupled to a printed circuit board (PCB) 890. PCB 890 is also coupled to a power supply 880 (e.g., a power management integrated circuit (PMIC)), which allows the component to be electrically coupled to PMIC 880. Specifically, one or more power (VDD) lines 891 and one or more ground (GND) lines 892 may be coupled to PMIC 880 to distribute power to PCB 890, to component 801 via VDD BGA pin 825 and GND BGA pin 827, and to die 860 via component 801. VDD line 891 and GND line 892 may each be formed by traces, shapes, or patterns in one or more metal layers (e.g., layers 1-6) of PCB 890, coupled by one or more vias through insulating layers that separate metal layers 1-6 in PCB 890. PCB 890 may have one or more PCB capacitors (PCB caps) 895, which can be used to condition power signals, as is known to those skilled in the art. Additional connections and components may be coupled to component 801 and / or through PCB 890 to component 801 via one or more additional BGA pins (not shown). It will be understood that the illustrated configurations and descriptions are provided merely to aid in illustrating the various forms disclosed herein. For example, PCB 890 may have more or fewer metal layers and insulating layers, may have multiple lines supplying power to various components, etc. Accordingly, the above illustrative examples and associated figures should not be construed as limiting the various forms disclosed and claimed herein.

[0060] FIG9 illustrates an exemplary mobile device according to some embodiments of this case. Referring now to FIG9, a block diagram of a mobile device configured according to an exemplary configuration is illustrated and generally designated as mobile device 900. In some configurations, mobile device 900 may be configured as a wireless communication device. As shown, mobile device 900 includes a processor 901. Processor 901 may be communicatively coupled to memory 932 over a link, which may be a die-to-die or chip-to-chip link. Mobile device 900 also includes a display 928 and a display controller 926, wherein display controller 926 is coupled to processor 901 and display 928.

[0061] In some embodiments, FIG9 may include: a decoder / decoder (CODEC) 934 (e.g., an audio and / or voice CODEC) coupled to processor 901; a speaker 936 and a microphone 938 coupled to CODEC 934; and a wireless circuit 940 (which may include a modem, RF circuitry, filters, etc., which may be implemented using one or more elements as disclosed herein (e.g., 101, 201, 301, etc.)) coupled to wireless antenna 942 and processor 901.

[0062] In a particular configuration, with one or more of the aforementioned blocks present, the processor 901, display controller 926, memory 932, CODEC 1234, and wireless circuitry 940 may be included in a system-in-package or system-on-a-chip 922, which may be implemented in part using the elements disclosed herein. Input devices 930 (e.g., physical or virtual keyboards), power supply 944 (e.g., battery), display 928, speaker 936, microphone 938, wireless antenna 942, and power supply 944 may be located external to the system-on-a-chip 922 and may be coupled to elements of the system-on-a-chip 922 (such as interfaces or controllers).

[0063] It should be noted that although Figure 9 illustrates a mobile device 900, the processor 901 and memory 932 may also be integrated into a set-top box, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, laptop, tablet computer, communication device, mobile phone or other similar device.

[0064] FIG10 illustrates various electronic devices that can be integrated with any of the aforementioned integrated elements or components according to various embodiments of the present invention. For example, mobile phone device 1002, laptop computer device 1004, and fixed location terminal device 1006 can each generally be regarded as user equipment (UE) and may include element 1000 as described herein. Element 1000 can be any of, for example, integrated circuit, die, integrated element, integrated element package, integrated circuit element, component package, integrated circuit (IC) package, and stacked package element as described herein. Devices 1002, 1004, and 1006 illustrated in FIG10 are merely exemplary. Other electronic devices may also be characterized by element 1000, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0065] The devices and functionalities disclosed above can be designed and configured in computer files (e.g., register transfer stage (RTL), geometric data stream (GDS) Gerber, etc.) stored on a computer-readable medium. Some or all of these files can be provided to a manufacturing processor that manufactures components based on such files. The resulting products may include semiconductor wafers, which are subsequently diced into semiconductor dies and packaged into semiconductor packages, integrated devices, system-on-a-chip devices, etc., which can then be used in the various devices described herein.

[0066] It will be understood that the various embodiments disclosed herein can be described as functional equivalents of structures, materials, and / or components as described and / or known to those skilled in the art. For example, in one embodiment, the apparatus may include various functional components for performing the foregoing. It will be understood that the foregoing embodiments are provided by way of example only, and the embodiments claimed are not limited to the specific references and / or illustrations cited as examples.

[0067] One or more of the elements, programs, features and / or functions illustrated in Figures 1-10 may be rearranged and / or combined into a single element, program, feature or function, or incorporated into several elements, programs or functions. Additional elements, components, programs, and / or functions may also be added without departing from this invention. It should also be noted that Figures 1-10 and their corresponding descriptions in this invention are not limited to dies and / or ICs. In some implementations, Figures 1-10 and their corresponding descriptions may be used to manufacture, build, provide, and / or produce integrated components. In some implementations, components may include dies, integrated components, die packages, integrated circuits (ICs), component packages, integrated circuit (IC) packages, wafers, devices, system-in-package (SiP), system-on-a-chip (SoC), or stacked package (PoP) components, etc.

[0068] As used herein, the terms "user equipment" (or "UE"), "user device," "user terminal," "client device," "communication device," "wireless device," "wireless communication device," "handheld device," "mobile device," "mobile terminal," "mobile station," "handheld device," "access terminal," "user equipment," "user terminal," "user station," "terminal," and variations thereof may interchangeably represent any suitable mobile or stationary device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, in-vehicle equipment in motor vehicles, and / or other types of portable electronic devices that are typically carried by an individual and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device capable of receiving wireless communications and / or navigation signals (such as via short-range wireless, infrared, wired connections, or other connections), regardless of whether satellite signal reception, auxiliary data reception, and / or positioning-related processing occur on the device or on the other device. The UE can be implemented via any of several types of devices, including but not limited to printed circuit (PC) cards, CF memory devices, external or internal modems, wireless or wired telephones, smartphones, tablets, consumer tracking devices, asset tags, etc.

[0069] Wireless communication between electronic devices can be based on various technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi) and IEEE 802.15.4 (Zigbee / Thread), or other protocols that can be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE and Bluetooth Smart).

[0070] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" is not to be construed as superior to other instances. Similarly, the term "instance" does not mean that all instances include the features, advantages, or modes of operation discussed. Furthermore, a particular feature and / or structure may be combined with one or more other features and / or structures. In addition, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0071] It should be noted that the terms “connection”, “coupling” or any variation thereof mean any direct or indirect connection or coupling between elements, and may cover the presence of an intermediate element between two elements that are “connected” or “coupled” together via the intermediate element, unless the connection is explicitly disclosed as a direct connection.

[0072] Any reference to elements using designations such as "first," "second," etc., herein does not limit the number and / or order of those elements. Rather, such designations are used as a convenient way to distinguish two or more elements and / or examples of elements. Similarly, unless otherwise stated, a set of elements may include one or more elements.

[0073] Those skilled in this art will understand that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0074] Nothing described or illustrated in this case is intended to designate any element, action, feature, benefit, advantage, or equivalent to be offered to the public, whether or not such element, action, feature, benefit, advantage, or equivalent is described in the claim.

[0075] Furthermore, those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic actions described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative elements, blocks, modules, circuits, and actions described above are generalized in their functional form. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as deviating from the scope of this work.

[0076] Although some states have been described in conjunction with the device, it is undeniable that these states also constitute a description of the corresponding method, and therefore the blocks or elements of the device should also be understood as corresponding method actions or features of method actions. Similarly, the states combined with or described as method actions also constitute a description of the corresponding blocks, details, or features of the corresponding device. Some or all of the method actions can be performed by hardware devices (or using hardware devices), such as, for example, microprocessors, programmable computers, or electronic circuits. In some instances, some or more of the most important method actions can be performed by such devices.

[0077] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various forms of this case may include fewer features than those of the individual exemplary clauses disclosed. Therefore, the appended clauses should thus be considered as being incorporated into this description, where each clause may be a separate instance. Although each subordinate clause may refer in its respective clause to a specific combination with one of the other clauses, the form(s) of that subordinate clause is not limited to that specific combination. It will be appreciated that other exemplary clauses may also include combinations of the form(s) of subordinate clauses with the subject matter of any other subordinate or independent clause, or any feature combined with other subordinate and independent clauses. The various forms disclosed herein expressly include such combinations unless explicitly stated or readily inferred that a particular combination is not intended (e.g., contradictory forms, such as defining an element as both an insulator and a conductor). Furthermore, it is intended that various forms of clauses may be included in any other independent clause, even if that clause is not directly subordinate to that independent clause.

[0078] Implementation examples are described in the following numbered clauses.

[0079] Clause 1. An apparatus including an element, wherein the element comprises: a top substrate including a plurality of top through-holes coupled to a first top metal layer, the first top metal layer forming a top winding portion of a first inductor; an intermediate substrate including one or more intermediate metal layers, wherein the top substrate is disposed on the intermediate substrate, and wherein the one or more intermediate metal layers form an intermediate winding portion of the first inductor; and a bottom substrate electrically coupled to the intermediate substrate opposite to the top substrate, wherein a first bottom metal layer of the bottom substrate forms a bottom winding portion of the first inductor.

[0080] Clause 2. The apparatus of Clause 1 further includes: a plurality of connectors configured to electrically couple the intermediate substrate to the bottom substrate.

[0081] Clause 3. The apparatus of Clause 2, wherein each of the plurality of connectors includes: a conductive post; and a solder portion, wherein the conductive post is coupled to the intermediate substrate and the solder portion is coupled to the bottom substrate.

[0082] Clause 4. The device of any one of Clauses 1 to 3, wherein the first top metal layer is the top metal layer of the top substrate.

[0083] Clause 5. The device of any one of Clauses 1 to 4, wherein the first bottom metal layer is the top metal layer of the bottom substrate.

[0084] Clause 6. The apparatus of any one of Clauses 1 to 5 further includes: a molded portion configured to at least enclose the top substrate and the intermediate substrate.

[0085] Clause 7. The apparatus of any one of Clauses 1 to 6 further includes: a die coupled to the bottom substrate.

[0086] Clause 8. The apparatus of Clause 7, wherein the die is a power amplifier and the element is a transmission filter.

[0087] Clause 9. An apparatus as described in any of Clauses 7 to 8, wherein the die is a low-noise amplifier and the element is a receiver filter.

[0088] Clause 10. The apparatus of any one of Clauses 1 to 9 further includes: a die coupled to the intermediate substrate.

[0089] Clause 11. The apparatus of Clause 10, wherein the first inductor is arranged around the die.

[0090] Clause 12. An apparatus as described in any of Clauses 10 to 11, wherein the die is a power amplifier and the element is a transmission filter.

[0091] Clause 13. An apparatus as described in any of Clauses 10 to 12, wherein the die is a low-noise amplifier and the element is a receiver filter.

[0092] Clause 14. The apparatus of any one of Clauses 1 to 13, wherein the intermediate substrate further comprises: one or more metal-insulator-metal (MIM) capacitors; and one or more inductors.

[0093] Clause 15. The apparatus of Clause 14, wherein the one or more MIM capacitors are formed or connected using a first intermediate metal layer and a second intermediate metal layer of one or more intermediate metal layers, wherein the one or more inductors are formed using a third intermediate metal layer of one or more intermediate metal layers, and wherein the spacing between the first intermediate metal layer and the second intermediate metal layer is less than the spacing between the second intermediate metal layer and the third intermediate metal layer.

[0094] Clause 16. The device of any of Clauses 14 to 15, wherein the one or more inductors are at least one of a two-dimensional (2D) inductor, a 2.5D inductor or a 3D inductor.

[0095] Clause 17. The apparatus of any one of Clauses 1 to 16 further includes a second element, wherein the second element includes: a second top substrate including a plurality of second top vias coupled to a second top metal layer, the second top metal layer forming a second top winding portion of the second inductor; a second intermediate substrate including a plurality of second intermediate vias and a plurality of second intermediate metal layers, wherein the second top substrate is disposed on the second intermediate substrate, and wherein the plurality of second intermediate vias and the plurality of second intermediate metal layers form a second intermediate winding portion of the second inductor; and a second bottom substrate electrically coupled to the second intermediate substrate relative to the second top substrate, wherein a first bottom metal layer of the second bottom substrate forms a second bottom winding portion of the second inductor.

[0096] Clause 18. The apparatus of Clause 17, wherein the element is stacked vertically on the second element.

[0097] Clause 19. The apparatus of Clause 18 further includes: a first plurality of interconnects configured to couple a bottom metal layer in the bottom substrate to a second top metal layer in the second top substrate; and a second plurality of interconnects configured to couple the bottom metal layer in the second bottom substrate to an external element.

[0098] Clause 20. The apparatus of any one of Clauses 17 to 19 further includes: a first die coupled to the intermediate substrate; and a second die coupled to the second intermediate substrate.

[0099] Clause 21. The apparatus of Clause 20, wherein the first die is a low-noise power amplifier and the element is a transmission filter, and wherein the second die is a power amplifier and the second element is a transmission filter.

[0100] Clause 22. The apparatus of any of Clauses 1 to 21, wherein the first inductor is a three-dimensional (3D) inductor having a serpentine winding.

[0101] Clause 23. The apparatus of any of Clauses 1 to 22, wherein the top substrate further comprises at least one of glass, prepreg, silicon, ceramic or epoxy molding compound.

[0102] Clause 24. The apparatus of any one of Clauses 1 to 23, wherein the intermediate substrate further comprises a plurality of dielectric layers.

[0103] Clause 25. The apparatus of any one of Clauses 1 to 24, wherein the bottom substrate further comprises a laminated substrate having a plurality of metal layers.

[0104] Article 26. Any device as described in any of Articles 1 to 25, wherein the device is selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, access points, fixed-location terminals, tablet computers, computers, wearable devices, Internet of Things (IoT) devices, laptops, servers, base stations, and devices in motor vehicles.

[0105] Clause 27. A method for forming an element, comprising the steps of: forming a top substrate including a plurality of top vias coupled to a first top metal layer, the first top metal layer forming a top winding portion of a first inductor; forming an intermediate substrate including one or more intermediate metal layers, wherein the top substrate is disposed on the intermediate substrate, and wherein the one or more intermediate metal layers form an intermediate winding portion of the first inductor; and forming a bottom substrate electrically coupled to the intermediate substrate relative to the top substrate, wherein a first bottom metal layer of the bottom substrate forms a bottom winding portion of the first inductor.

[0106] Clause 28. The method of Clause 27 further includes the step of: forming a plurality of connectors that electrically couple the intermediate substrate to the bottom substrate.

[0107] Clause 29. The method of any one of Clauses 27 to 28 further includes the step of: depositing a molded portion to at least encapsulate the top substrate and the intermediate substrate.

[0108] Clause 30. The method of any one of Clauses 27 to 29 further includes the step of coupling the die to the bottom substrate.

[0109] Clause 31. The method of any one of Clauses 27 to 30 further includes the step of coupling the die to the intermediate substrate.

[0110] Clause 32. The method of Clause 31, wherein the first inductor is arranged around the die.

[0111] Clause 33. The method of any one of Clauses 27 to 32, wherein forming the intermediate substrate further comprises: forming one or more metal-insulator-metal (MIM) capacitors; and forming one or more inductors.

[0112] Clause 34. The method of any one of Clauses 27 to 33 further includes forming a second element, wherein forming the second element includes: forming a second top substrate, the second top substrate including a plurality of second top vias coupled to a second top metal layer, the second top metal layer forming a second top winding portion of the second inductor; forming a second intermediate substrate, the second intermediate substrate including a plurality of second intermediate vias and a plurality of second intermediate metal layers, wherein the second top substrate is disposed on the second intermediate substrate, and wherein the plurality of second intermediate vias and the plurality of second intermediate metal layers form a second intermediate winding portion of the second inductor; and forming a second bottom substrate electrically coupled to the second intermediate substrate relative to the second top substrate, wherein a first bottom metal layer of the second bottom substrate forms a second bottom winding portion of the second inductor.

[0113] Clause 35. The method of Clause 34, wherein the element is stacked vertically on the second element.

[0114] Clause 36. The method of Clause 35 further includes the steps of: forming a first plurality of interconnects configured to couple a bottom metal layer in the bottom substrate to a second top metal layer in the second top substrate; and forming a second plurality of interconnects configured to couple the bottom metal layer in the second bottom substrate to an external element.

[0115] Clause 37. The method of any one of Clauses 34 to 36 further includes the steps of: coupling a first die coupled to the intermediate substrate; and coupling a second die coupled to the second intermediate substrate.

[0116] Clause 38. The method of Clause 37, wherein the first die is a low-noise power amplifier and the element is a transmission filter, and wherein the second die is a power amplifier and the second element is a transmission filter.

[0117] Clause 39. The method of any one of Clauses 27 to 38, wherein the first inductor is a three-dimensional (3D) inductor having a serpentine winding.

[0118] It should also be noted that the methods, systems and apparatus disclosed in this description or claim may be implemented by a device including components for performing corresponding actions and / or functions of the disclosed methods.

[0119] Furthermore, in some instances, an individual action may be subdivided into a plurality of sub-actions or may contain a plurality of sub-actions. Such sub-actions may be included in the disclosure of the individual action and may be part of the disclosure of the individual action.

[0120] Although the foregoing disclosure presents illustrative examples of this case, it should be noted that various changes and modifications may be made without departing from the scope of this case as defined in the appended claims. The functions and / or actions in the method claims of the various examples of this case described herein need not necessarily be performed in any particular order. Furthermore, well-known elements will not be described in detail or may be omitted to avoid obscuring the relevant details of the various forms and examples disclosed herein. Moreover, although elements of this case may be described or claimed in the singular, pluralism is also contemplated unless explicitly stated to be limited to the singular. [Simplified Explanation of the Diagram]

[0008] A more complete understanding of the various aspects of this case and its many accompanying advantages will be readily available when considered in conjunction with the following detailed description, which is provided for illustrative purposes only and does not constitute any limitation on this case.

[0009] Figure 1A illustrates a portion of an apparatus including elements according to at least one aspect of the present invention.

[0010] Figure 1B illustrates the current flow in a portion of an apparatus according to at least one of the present invention.

[0011] Figure 2A illustrates a portion of an apparatus including elements and a die according to at least one state of the present invention.

[0012] Figure 2B illustrates a portion of an apparatus including elements according to at least one of the present invention.

[0013] Figure 3 illustrates a portion of an apparatus including elements and a die according to at least one state of the present invention.

[0014] Figure 4 illustrates a portion of an apparatus comprising a first element, a first die, a second element, and a second die according to at least one embodiment of the present invention.

[0015] Figures 5A-5D illustrate various parts of the manufacturing process for the device according to one or more versions of this invention.

[0016] Figures 6A-6J illustrate various parts of the manufacturing process for the device according to one or more versions of this invention.

[0017] Figure 7 illustrates a flowchart of a method for manufacturing an element according to one or more of the present invention.

[0018] Figure 8 illustrates one or more integrated elements according to this case.

[0019] Figure 9 illustrates an exemplary mobile device according to one or more states of this case.

[0020] Figure 10 illustrates various electronic devices that can be integrated with any of the aforementioned elements according to one or more forms of this invention.

[0021] By convention, the features illustrated in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the illustrated features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not show all elements of a particular device or method. Furthermore, similar element symbols are used throughout the specification and accompanying drawings to indicate similar features. [Biomaterial Storage]

[0122] Domestic storage information (please note in order of storage institution, date, and number) None Foreign storage information (please note in order of storage country, institution, date, and number) None

Claims

1. An apparatus including an element, wherein the element comprises: A top substrate including a plurality of top vias coupled to a first top metal layer forming a top winding portion of a first inductor; an intermediate substrate including one or more intermediate metal layers, wherein the top substrate is disposed on the intermediate substrate, and wherein the one or more intermediate metal layers form an intermediate winding portion of the first inductor; and a bottom substrate electrically coupled to the intermediate substrate opposite to the top substrate, wherein a first bottom metal layer of the bottom substrate forms a bottom winding portion of the first inductor, and wherein the device includes a first die coupled to the intermediate substrate.

2. The apparatus of claim 1, further comprising: A plurality of connectors configured to electrically couple the intermediate substrate to the bottom substrate.

3. The apparatus of claim 2, wherein each of the plurality of connectors comprises: A conductive pillar; and a solder portion, wherein the conductive post is coupled to the intermediate substrate and the solder portion is coupled to the bottom substrate.

4. The apparatus of claim 1, wherein the first top metal layer is a top metal layer of the top substrate.

5. The apparatus of claim 1, wherein the first bottom metal layer is a top metal layer of the bottom substrate.

6. The apparatus of claim 1, further comprising: A molded part is configured to at least enclose the top substrate and the intermediate substrate.

7. The apparatus of claim 1, wherein the first inductor is arranged around the first die.

8. The apparatus of claim 1, wherein the first die is a power amplifier and the element is a transmission filter.

9. The apparatus of claim 1, wherein the first die is a low-noise amplifier and the element is a receiver filter.

10. The apparatus of claim 1, wherein the intermediate substrate further comprises: One or more metal-insulator-metal (MIM) capacitors; and one or more inductors.

11. The apparatus of claim 10, wherein the one or more MIM capacitors are formed or connected using a first intermediate metal layer and a second intermediate metal layer of the one or more intermediate metal layers, wherein the one or more inductors are formed using a third intermediate metal layer of the one or more intermediate metal layers, and wherein a gap between the first intermediate metal layer and the second intermediate metal layer is smaller than a gap between the second intermediate metal layer and the third intermediate metal layer.

12. The apparatus of claim 10, wherein the one or more inductors are at least one of a two-dimensional (2D) inductor, a 2.5D inductor, or a 3D inductor.

13. The apparatus of claim 1, further comprising a second element, wherein the second element includes: A second top substrate including a plurality of second top vias coupled to a second top metal layer, the second top metal layer forming a second top winding portion of a second inductor; a second intermediate substrate including one or more second intermediate metal layers, wherein the second top substrate is disposed on the second intermediate substrate, and wherein the one or more second intermediate metal layers form a second intermediate winding portion of the second inductor; and a second bottom substrate electrically coupled to the second intermediate substrate relative to the second top substrate, wherein a first bottom metal layer of the second bottom substrate forms a second bottom winding portion of the second inductor.

14. The apparatus of claim 13, wherein the element is stacked vertically on the second element.

15. The apparatus of claim 14, further comprising: A first plurality of interconnects configured to couple a bottom metal layer in the bottom substrate to a second top metal layer in the second top substrate; and a second plurality of interconnects configured to couple a bottom metal layer in the second bottom substrate to an external element.

16. The apparatus of claim 13, further comprising: A second grain coupled to the second intermediate substrate.

17. The apparatus of claim 16, wherein the first die is a low-noise power amplifier and the element is a transmission filter, and wherein the second die is a power amplifier and the second element is a transmission filter.

18. The apparatus of claim 1, wherein the first inductor is a three-dimensional (3D) inductor having a serpentine winding.

19. The apparatus of claim 1, wherein the top substrate further comprises at least one of glass, prepreg, silicon, ceramic or epoxy molding compound.

20. The apparatus of claim 1, wherein the intermediate substrate further comprises a plurality of dielectric layers.

21. The apparatus of claim 1, wherein the bottom substrate further comprises a laminate having a plurality of metal layers.

22. The device as claimed in claim 1, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a digital assistant, an access point, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, a base station, and a device in a motor vehicle.

23. A method for forming a component, comprising the steps of: forming a top substrate including a plurality of top vias coupled to a first top metal layer, the first top metal layer forming a top winding portion of a first inductor; forming an intermediate substrate including one or more intermediate metal layers, wherein the top substrate is disposed on the intermediate substrate, and wherein the one or more intermediate metal layers form an intermediate winding portion of the first inductor; coupling a first die to the intermediate substrate; and forming a bottom substrate electrically coupled to the intermediate substrate opposite to the top substrate, wherein a first bottom metal layer of the bottom substrate forms a bottom winding portion of the first inductor.

24. The method of claim 23 further includes the step of: forming a plurality of connectors that electrically couple the intermediate substrate to the bottom substrate.

25. The method of claim 23 further includes the step of: depositing a molded portion to at least encapsulate the top substrate and the intermediate substrate.

26. The method of claim 23, wherein the first inductor is arranged around the first die.

27. The method of claim 23, wherein the step of forming the intermediate substrate further comprises the steps of: forming one or more metal-insulator-metal (MIM) capacitors; and forming one or more inductors.

28. The method of claim 23 further includes the steps of: forming a second element, wherein forming the second element includes the steps of: forming a second top substrate, the second top substrate including a plurality of second top vias coupled to a second top metal layer, the second top metal layer forming a second top winding portion of a second inductor; forming a second intermediate substrate including one or more second intermediate metal layers, wherein the second top substrate is disposed on the second intermediate substrate, and wherein the one or more second intermediate metal layers form a second intermediate winding portion of the second inductor; and forming a second bottom substrate electrically coupled to the second intermediate substrate relative to the second top substrate, wherein a first bottom metal layer of the second bottom substrate forms a second bottom winding portion of the second inductor.

29. The method of claim 28, wherein the element is stacked vertically on the second element.

30. The method of claim 29 further includes the steps of: forming a first plurality of interconnects configured to couple a bottom metal layer in the bottom substrate to a second top metal layer in the second top substrate; and forming a second plurality of interconnects configured to couple a bottom metal layer in the second bottom substrate to an external element.

31. The method of claim 28 further includes the step of: coupling a second die to the second intermediate substrate.

32. The method of claim 31, wherein the first die is a low-noise power amplifier and the element is a transmission filter, and wherein the second die is a power amplifier and the second element is a transmission filter.

33. The method of claim 23, wherein the first inductor is a three-dimensional (3D) inductor having a serpentine winding.

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